From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chao Peng Subject: [PATCH v8 07/13] x86: add scheduling support for Intel CAT Date: Thu, 21 May 2015 16:41:38 +0800 Message-ID: <1432197704-20816-8-git-send-email-chao.p.peng@linux.intel.com> References: <1432197704-20816-1-git-send-email-chao.p.peng@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1432197704-20816-1-git-send-email-chao.p.peng@linux.intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org Cc: keir@xen.org, Ian.Campbell@citrix.com, stefano.stabellini@eu.citrix.com, andrew.cooper3@citrix.com, dario.faggioli@citrix.com, Ian.Jackson@eu.citrix.com, will.auld@intel.com, JBeulich@suse.com, wei.liu2@citrix.com, dgdegra@tycho.nsa.gov List-Id: xen-devel@lists.xenproject.org On context switch, write the the domain's Class of Service(COS) to MSR IA32_PQR_ASSOC, to notify hardware to use the new COS. For performance reason, the COS mask for current cpu is also cached in the local per-CPU variable. Signed-off-by: Chao Peng Acked-by: Jan Beulich --- Changes in v5: * Remove the need to cache socket. Changes in v2: * merge common scheduling changes into scheduling improvement patch. * use readable expr for psra->cos_mask. --- xen/arch/x86/psr.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index 7af84b1..0e75c77 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -35,6 +35,7 @@ struct psr_cat_socket_info { struct psr_assoc { uint64_t val; + uint64_t cos_mask; }; struct psr_cmt *__read_mostly psr_cmt; @@ -200,7 +201,16 @@ static inline void psr_assoc_init(void) { struct psr_assoc *psra = &this_cpu(psr_assoc); - if ( psr_cmt_enabled() ) + if ( cat_socket_info ) + { + unsigned int socket = cpu_to_socket(smp_processor_id()); + + if ( test_bit(socket, cat_socket_enable) ) + psra->cos_mask = ((1ull << get_count_order( + cat_socket_info[socket].cos_max)) - 1) << 32; + } + + if ( psr_cmt_enabled() || psra->cos_mask ) rdmsrl(MSR_IA32_PSR_ASSOC, psra->val); } @@ -209,6 +219,12 @@ static inline void psr_assoc_rmid(uint64_t *reg, unsigned int rmid) *reg = (*reg & ~rmid_mask) | (rmid & rmid_mask); } +static inline void psr_assoc_cos(uint64_t *reg, unsigned int cos, + uint64_t cos_mask) +{ + *reg = (*reg & ~cos_mask) | (((uint64_t)cos << 32) & cos_mask); +} + void psr_ctxt_switch_to(struct domain *d) { struct psr_assoc *psra = &this_cpu(psr_assoc); @@ -217,6 +233,11 @@ void psr_ctxt_switch_to(struct domain *d) if ( psr_cmt_enabled() ) psr_assoc_rmid(®, d->arch.psr_rmid); + if ( psra->cos_mask ) + psr_assoc_cos(®, d->arch.psr_cos_ids ? + d->arch.psr_cos_ids[cpu_to_socket(smp_processor_id())] : + 0, psra->cos_mask); + if ( reg != psra->val ) { wrmsrl(MSR_IA32_PSR_ASSOC, reg); -- 1.9.1