From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37715) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3PY6-0003xf-K0 for qemu-devel@nongnu.org; Fri, 12 Jun 2015 10:03:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z3PY4-0000xw-W6 for qemu-devel@nongnu.org; Fri, 12 Jun 2015 10:03:10 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:19160) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3PY4-0000xc-L2 for qemu-devel@nongnu.org; Fri, 12 Jun 2015 10:03:08 -0400 From: Yongbok Kim Date: Fri, 12 Jun 2015 15:02:22 +0100 Message-ID: <1434117743-53520-13-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1434117743-53520-1-git-send-email-yongbok.kim@imgtec.com> References: <1434117743-53520-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 12/13] target-mips: microMIPS32 R6 POOL16{A, C} instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: leon.alrae@imgtec.com, aurelien@aurel32.net microMIPS32 Release 6 POOL16A/ POOL16C instructions Signed-off-by: Yongbok Kim --- target-mips/translate.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 105 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 3ac9632..936fb3e 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12929,6 +12929,101 @@ static void gen_pool16c_insn(DisasContext *ctx) } } +static void gen_pool16c_r6_insn(DisasContext *ctx) +{ + int rt = mmreg((ctx->opcode >> 7) & 0x7); + int rs = mmreg((ctx->opcode >> 4) & 0x7); + + switch (ctx->opcode & 0xf) { + case R6_NOT16: + gen_logic(ctx, OPC_NOR, rt, rs, 0); + break; + case R6_AND16: + gen_logic(ctx, OPC_AND, rt, rt, rs); + break; + case R6_LWM16: + { + static const int lwm_convert[] = { 0x11, 0x12, 0x13, 0x14 }; + int offset = ZIMM(ctx->opcode, 4, 4); + gen_ldst_multiple(ctx, LWM32, lwm_convert[(ctx->opcode >> 8) & 0x3], + 29, offset << 2); + } + break; + case R6_JRC16: + switch (ctx->opcode >> 4 & 1) { + case 0: + /* JRC16 */ + { + int reg = (ctx->opcode >> 5) & 0x1f; + gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 0); + } + break; + case 1: + /* JRCADDIUSP */ + { + int imm = ZIMM(ctx->opcode, 5, 5); + gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0); + gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2); + } + break; + } + break; + case MOVEP ... MOVEP_07: + case MOVEP_0C ... MOVEP_0F: + { + int enc_dest = uMIPS_RD(ctx->opcode); + int enc_rt = uMIPS_RS2(ctx->opcode); + int enc_rs = (ctx->opcode & 3) | ((ctx->opcode >> 1) & 4); + int rd, rs, re, rt; + static const int rd_enc[] = { 5, 5, 6, 4, 4, 4, 4, 4 }; + static const int re_enc[] = { 6, 7, 7, 21, 22, 5, 6, 7 }; + static const int rs_rt_enc[] = { 0, 17, 2, 3, 16, 18, 19, 20 }; + rd = rd_enc[enc_dest]; + re = re_enc[enc_dest]; + rs = rs_rt_enc[enc_rs]; + rt = rs_rt_enc[enc_rt]; + gen_arith(ctx, OPC_ADDU, rd, rs, 0); + gen_arith(ctx, OPC_ADDU, re, rt, 0); + } + break; + case R6_XOR16: + gen_logic(ctx, OPC_XOR, rt, rt, rs); + break; + case R6_OR16: + gen_logic(ctx, OPC_OR, rt, rt, rs); + break; + case R6_SWM16: + { + static const int swm_convert[] = { 0x11, 0x12, 0x13, 0x14 }; + int offset = ZIMM(ctx->opcode, 4, 4); + gen_ldst_multiple(ctx, SWM32, swm_convert[(ctx->opcode >> 8) & 0x3], + 29, offset << 2); + } + break; + case JALRC16: + switch (ctx->opcode >> 4 & 3) { + case 0: + case 2: + /* JALRC16 */ + gen_compute_branch(ctx, OPC_JALR, 2, (ctx->opcode >> 5) & 0x1f, + 31, 0, 0); + break; + case 1: + /* BREAK16 */ + generate_exception(ctx, EXCP_BREAK); + break; + case 3: + /* SDBBP16 */ + generate_exception(ctx, EXCP_DBp); + break; + } + break; + default: + generate_exception(ctx, EXCP_RI); + break; + } +} + static void gen_ldxs (DisasContext *ctx, int base, int index, int rd) { TCGv t0 = tcg_temp_new(); @@ -14942,7 +15037,11 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) int rs1 = mmreg(uMIPS_RS1(ctx->opcode)); int rs2 = mmreg(uMIPS_RS2(ctx->opcode)); uint32_t opc = 0; - + if (ctx->insn_flags & ISA_MIPS32R6) { + rd = mmreg(uMIPS_RS1(ctx->opcode)); + rs1 = mmreg(uMIPS_RD(ctx->opcode)); + rs2 = mmreg(uMIPS_RS2(ctx->opcode)); + } switch (ctx->opcode & 0x1) { case ADDU16: opc = OPC_ADDU; @@ -14976,7 +15075,11 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) } break; case POOL16C: - gen_pool16c_insn(ctx); + if (ctx->insn_flags & ISA_MIPS32R6) { + gen_pool16c_r6_insn(ctx); + } else { + gen_pool16c_insn(ctx); + } break; case LWGP16: { -- 1.7.5.4