From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39235) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4gB9-0001ap-Ul for qemu-devel@nongnu.org; Mon, 15 Jun 2015 22:01:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z4gAh-0005cq-Mv for qemu-devel@nongnu.org; Mon, 15 Jun 2015 22:00:43 -0400 Received: from mail-ob0-x236.google.com ([2607:f8b0:4003:c01::236]:33600) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4gAh-0005by-H6 for qemu-devel@nongnu.org; Mon, 15 Jun 2015 22:00:15 -0400 Received: by obcej4 with SMTP id ej4so2143499obc.0 for ; Mon, 15 Jun 2015 19:00:15 -0700 (PDT) From: "Edgar E. Iglesias" Date: Tue, 16 Jun 2015 11:51:54 +1000 Message-Id: <1434419515-3572-6-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1434419515-3572-1-git-send-email-edgar.iglesias@gmail.com> References: <1434419515-3572-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v5 5/6] hw/arm/virt: Replace magic IRQ constants with macros List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Replace magic constants with macros from hw/arm/virt.h and hw/intc/arm_gic_common.h. Reviewed-by: Peter Maydell Signed-off-by: Edgar E. Iglesias --- hw/arm/virt.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 1b1cc71..f822ea0 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -47,6 +47,7 @@ #include "hw/arm/virt-acpi-build.h" #include "hw/arm/sysbus-fdt.h" #include "hw/platform-bus.h" +#include "hw/intc/arm_gic_common.h" /* Number of external interrupt lines to configure the GIC with */ #define NUM_IRQS 256 @@ -395,15 +396,17 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic) */ for (i = 0; i < smp_cpus; i++) { DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); - int ppibase = NUM_IRQS + i * 32; + int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; /* physical timer; we wire it up to the non-secure timer's ID, * since a real A15 always has TrustZone but QEMU doesn't. */ qdev_connect_gpio_out(cpudev, 0, - qdev_get_gpio_in(gicdev, ppibase + 30)); + qdev_get_gpio_in(gicdev, + ppibase + ARCH_TIMER_NS_EL1_IRQ)); /* virtual timer */ qdev_connect_gpio_out(cpudev, 1, - qdev_get_gpio_in(gicdev, ppibase + 27)); + qdev_get_gpio_in(gicdev, + ppibase + ARCH_TIMER_VIRT_IRQ)); sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); sysbus_connect_irq(gicbusdev, i + smp_cpus, -- 1.9.1