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From: Arun Siluvery <arun.siluvery@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v5 3/6] drm/i915/gen8: Add WaDisableCtxRestoreArbitration workaround
Date: Thu, 18 Jun 2015 18:33:26 +0100	[thread overview]
Message-ID: <1434648809-24168-3-git-send-email-arun.siluvery@linux.intel.com> (raw)
In-Reply-To: <1434648809-24168-1-git-send-email-arun.siluvery@linux.intel.com>

In Indirect and Per context w/a batch buffer,
+WaDisableCtxRestoreArbitration

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 62486cd..c4b3493 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1110,8 +1110,8 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
 
 	index = offset;
 
-	/* FIXME: Replace me with WA */
-	wa_ctx_emit(batch, MI_NOOP);
+	/* WaDisableCtxRestoreArbitration:bdw,chv */
+	wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_DISABLE);
 
 	/* Pad to end of cacheline */
 	while (index % CACHELINE_DWORDS)
@@ -1144,6 +1144,9 @@ static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
 
 	index = offset;
 
+	/* WaDisableCtxRestoreArbitration:bdw,chv */
+	wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_ENABLE);
+
 	wa_ctx_emit(batch, MI_BATCH_BUFFER_END);
 
 	*num_dwords = index - offset;
-- 
2.3.0

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  parent reply	other threads:[~2015-06-18 17:33 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-18 13:07 [PATCH v5 0/6] Add Per-context WA using WA batch buffers Arun Siluvery
2015-06-18 13:07 ` [PATCH v5 1/6] drm/i915/gen8: Add infrastructure to initialize " Arun Siluvery
2015-06-18 16:06   ` Chris Wilson
2015-06-18 13:07 ` [PATCH v5 2/6] drm/i915/gen8: Re-order init pipe_control in lrc mode Arun Siluvery
2015-06-18 13:07 ` [PATCH v5 3/6] drm/i915/gen8: Add WaDisableCtxRestoreArbitration workaround Arun Siluvery
2015-06-18 13:07 ` [PATCH v5 4/6] drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround Arun Siluvery
2015-06-18 13:07 ` [PATCH v5 5/6] drm/i915/gen8: Add WaClearSlmSpaceAtContextSwitch workaround Arun Siluvery
2015-06-18 13:07 ` [PATCH v5 6/6] drm/i915/gen8: Add WaRsRestoreWithPerCtxtBb workaround Arun Siluvery
2015-06-18 17:33 ` [PATCH v5 1/6] drm/i915/gen8: Add infrastructure to initialize WA batch buffers Arun Siluvery
2015-06-18 17:33   ` [PATCH v5 2/6] drm/i915/gen8: Re-order init pipe_control in lrc mode Arun Siluvery
2015-06-18 17:33   ` Arun Siluvery [this message]
2015-06-18 17:33   ` [PATCH v5 4/6] drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround Arun Siluvery
2015-06-18 17:33   ` [PATCH v5 5/6] drm/i915/gen8: Add WaClearSlmSpaceAtContextSwitch workaround Arun Siluvery
2015-06-19  9:29     ` Chris Wilson
2015-06-18 17:33   ` [PATCH v5 6/6] drm/i915/gen8: Add WaRsRestoreWithPerCtxtBb workaround Arun Siluvery
2015-06-19  9:35     ` Chris Wilson
2015-06-19  9:27   ` [PATCH v5 1/6] drm/i915/gen8: Add infrastructure to initialize WA batch buffers Chris Wilson
2015-06-19  9:48     ` Siluvery, Arun
2015-06-19  9:55       ` Chris Wilson

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