[RFC 11/14] drm/i915: Enable MIPI display self refresh mode

From: Gaurav K Singh <gaurav.k.singh@intel.com>
To: intel-gfx <intel-gfx@lists.freedesktop.org>
Cc: Shobhit Kumar <shobhit.kumar@intel.com>
Subject: [RFC 11/14] drm/i915: Enable MIPI display self refresh mode
Date: Fri, 19 Jun 2015 03:26:45 +0530	[thread overview]
Message-ID: <1434664605-20419-1-git-send-email-gaurav.k.singh@intel.com> (raw)
In-Reply-To: <558056E7.3050105@intel.com>

During enable sequence for MIPI encoder in command mode, enable
MIPI display self-refresh mode bit in Pipe Ctrl reg.

v2: Use crtc state flag instead of loop over encoders (Daniel)

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dd518d6..c53f66d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2158,6 +2158,11 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
 		return;
 	}
 
+	if (crtc->config->dsi_self_refresh) {
+		val = val | PIPECONF_MIPI_DSR_ENABLE;
+		I915_WRITE(reg, val);
+	}
+
 	I915_WRITE(reg, val | PIPECONF_ENABLE);
 	POSTING_READ(reg);
 }
-- 
1.7.9.5

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