From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33075) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5z7f-00063O-DZ for qemu-devel@nongnu.org; Fri, 19 Jun 2015 12:26:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z5z7Z-00027d-UN for qemu-devel@nongnu.org; Fri, 19 Jun 2015 12:26:31 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:50483) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5z7Z-00027K-On for qemu-devel@nongnu.org; Fri, 19 Jun 2015 12:26:25 -0400 From: Yongbok Kim Date: Fri, 19 Jun 2015 17:25:23 +0100 Message-ID: <1434731138-4918-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 00/15] target-mips: add microMIPS32 R6 Instruction Set support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: leon.alrae@imgtec.com, aurelien@aurel32.net The patchset implements the latest microMIPS32 Release 6 Instruction Set. However LLX, LLXE, SCX and SCXE aren't included in the patchset. For more information, microMIPS R6 Instruction Set document is available: MIPS Architecture for Programmers Volume II-B: microMIPS32 Instruction Set Revision 6.01 http://www.imgtec.com/mips/architectures/mips32.asp --- v2: * Updated for review comment (Leon, Aurelien) * Added signal RI exception when FIR.PS = 0 (Leon) * Removed an unused argument from decode_micromips32_opc() * Reused gen_pcrel() for pc relative instructions (Leon) Yongbok Kim (15): target-mips: fix {RD,WR}PGPR in microMIPS target-mips: add microMIPS TLBINV, TLBINVF target-mips: remove an unused argument target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP target-mips: rearrange gen_compute_compact_branch target-mips: raise RI exceptions when FIR.PS = 0 target-mips: signal RI for removed instructions in microMIPS R6 target-mips: add microMIPS32 R6 opcode enum target-mips: microMIPS32 R6 branches and jumps target-mips: microMIPS32 R6 POOL32A{XF} instructions target-mips: microMIPS32 R6 POOL32F instructions target-mips: microMIPS32 R6 POOL32{I,C} instructions target-mips: microMIPS32 R6 Major instructions target-mips: microMIPS32 R6 POOL16{A,C} instructions target-mips: add mips32r6-generic CPU definition target-mips/translate.c | 2088 ++++++++++++++++++++++++++++-------------- target-mips/translate_init.c | 37 + 2 files changed, 1452 insertions(+), 673 deletions(-) -- 1.7.5.4