From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33236) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5z7q-0006Oo-42 for qemu-devel@nongnu.org; Fri, 19 Jun 2015 12:26:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z5z7l-0002Df-1m for qemu-devel@nongnu.org; Fri, 19 Jun 2015 12:26:41 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:63045) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5z7k-0002DL-QN for qemu-devel@nongnu.org; Fri, 19 Jun 2015 12:26:36 -0400 From: Yongbok Kim Date: Fri, 19 Jun 2015 17:25:33 +0100 Message-ID: <1434731138-4918-11-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1434731138-4918-1-git-send-email-yongbok.kim@imgtec.com> References: <1434731138-4918-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 10/15] target-mips: microMIPS32 R6 POOL32A{XF} instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: leon.alrae@imgtec.com, aurelien@aurel32.net add new microMIPS32 Release 6 pool32a/pool32axf instructions. Signed-off-by: Yongbok Kim Reviewed-by: Leon Alrae --- target-mips/translate.c | 80 ++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 69 insertions(+), 11 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index c0db5ec..6a29796 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -13333,6 +13333,10 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) break; case 0x2c: switch (minor) { + case BITSWAP: + check_insn(ctx, ISA_MIPS32R6); + gen_bitswap(ctx, OPC_BITSWAP, rs, rt); + break; case SEB: gen_bshfl(ctx, OPC_SEB, rs, rt); break; @@ -13530,8 +13534,8 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) break; case SDBBP: check_insn(ctx, ISA_MIPS32); - if (!(ctx->hflags & MIPS_HFLAG_DM)) { - generate_exception(ctx, EXCP_DBp); + if (ctx->hflags & MIPS_HFLAG_SBRI) { + generate_exception(ctx, EXCP_RI); } else { generate_exception(ctx, EXCP_DBp); } @@ -13893,6 +13897,14 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) do_shifti: gen_shift_imm(ctx, mips32_op, rt, rs, rd); break; + case SELEQZ: + check_insn(ctx, ISA_MIPS32R6); + gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt); + break; + case SELNEZ: + check_insn(ctx, ISA_MIPS32R6); + gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt); + break; default: goto pool32a_invalid; } @@ -13966,16 +13978,52 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) minor = (ctx->opcode >> 6) & 0xf; switch (minor) { /* Conditional moves */ - case MOVN: - mips32_op = OPC_MOVN; - goto do_cmov; - case MOVZ: - mips32_op = OPC_MOVZ; - do_cmov: - gen_cond_move(ctx, mips32_op, rd, rs, rt); + case MOVN: /* MUL */ + if (ctx->insn_flags & ISA_MIPS32R6) { + /* MUL */ + gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt); + } else { + /* MOVN */ + gen_cond_move(ctx, OPC_MOVN, rd, rs, rt); + } + break; + case MOVZ: /* MUH */ + if (ctx->insn_flags & ISA_MIPS32R6) { + /* MUH */ + gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt); + } else { + /* MOVZ */ + gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt); + } break; - case LWXS: - gen_ldxs(ctx, rs, rt, rd); + case MULU: + check_insn(ctx, ISA_MIPS32R6); + gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt); + break; + case MUHU: + check_insn(ctx, ISA_MIPS32R6); + gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt); + break; + case LWXS: /* DIV */ + if (ctx->insn_flags & ISA_MIPS32R6) { + /* DIV */ + gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt); + } else { + /* LWXS */ + gen_ldxs(ctx, rs, rt, rd); + } + break; + case MOD: + check_insn(ctx, ISA_MIPS32R6); + gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt); + break; + case R6_DIVU: + check_insn(ctx, ISA_MIPS32R6); + gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt); + break; + case MODU: + check_insn(ctx, ISA_MIPS32R6); + gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt); break; default: goto pool32a_invalid; @@ -13984,6 +14032,16 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) case INS: gen_bitops(ctx, OPC_INS, rt, rs, rr, rd); return; + case LSA: + check_insn(ctx, ISA_MIPS32R6); + gen_lsa(ctx, OPC_LSA, rd, rs, rt, + extract32(ctx->opcode, 9, 2)); + break; + case ALIGN: + check_insn(ctx, ISA_MIPS32R6); + gen_align(ctx, OPC_ALIGN, rd, rs, rt, + extract32(ctx->opcode, 9, 2)); + break; case EXT: gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd); return; -- 1.7.5.4