From: Yongbok Kim <yongbok.kim@imgtec.com>
To: qemu-devel@nongnu.org
Cc: leon.alrae@imgtec.com, aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v2 11/15] target-mips: microMIPS32 R6 POOL32F instructions
Date: Fri, 19 Jun 2015 17:25:34 +0100 [thread overview]
Message-ID: <1434731138-4918-12-git-send-email-yongbok.kim@imgtec.com> (raw)
In-Reply-To: <1434731138-4918-1-git-send-email-yongbok.kim@imgtec.com>
add new microMIPS32 Release 6 POOL32F instructions
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
---
target-mips/translate.c | 231 ++++++++++++++++++++++++++++++++++++++++-------
1 files changed, 199 insertions(+), 32 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 6a29796..5f6ae43 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -14195,6 +14195,14 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
goto pool32f_invalid;
}
break;
+ case CMP_CONDN_S:
+ check_insn(ctx, ISA_MIPS32R6);
+ gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
+ break;
+ case CMP_CONDN_D:
+ check_insn(ctx, ISA_MIPS32R6);
+ gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
+ break;
case POOL32FXF:
gen_pool32fxf(ctx, rt, rs);
break;
@@ -14223,6 +14231,19 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
goto pool32f_invalid;
}
break;
+ case MIN_FMT:
+ check_insn(ctx, ISA_MIPS32R6);
+ switch ((ctx->opcode >> 9) & 0x3) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);
+ break;
+ default:
+ goto pool32f_invalid;
+ }
+ break;
case 0x08:
/* [LS][WDU]XC1 */
switch ((ctx->opcode >> 6) & 0x7) {
@@ -14256,6 +14277,19 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
goto pool32f_invalid;
}
break;
+ case MAX_FMT:
+ check_insn(ctx, ISA_MIPS32R6);
+ switch ((ctx->opcode >> 9) & 0x3) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);
+ break;
+ default:
+ goto pool32f_invalid;
+ }
+ break;
case 0x18:
/* 3D insns */
check_insn_opc_removed(ctx, ISA_MIPS32R6);
@@ -14304,40 +14338,70 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case 0x20:
- /* MOV[FT].fmt and PREFX */
+ /* MOV[FT].fmt, PREFX, RINT.fmt, CLASS.fmt*/
cc = (ctx->opcode >> 13) & 0x7;
fmt = (ctx->opcode >> 9) & 0x3;
switch ((ctx->opcode >> 6) & 0x7) {
- case MOVF_FMT:
- switch (fmt) {
- case FMT_SDPS_S:
- gen_movcf_s(ctx, rs, rt, cc, 0);
- break;
- case FMT_SDPS_D:
- gen_movcf_d(ctx, rs, rt, cc, 0);
- break;
- case FMT_SDPS_PS:
- check_ps(ctx);
- gen_movcf_ps(ctx, rs, rt, cc, 0);
- break;
- default:
- goto pool32f_invalid;
+ case MOVF_FMT: /* RINT_FMT */
+ if (ctx->insn_flags & ISA_MIPS32R6) {
+ /* RINT_FMT */
+ switch (fmt) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);
+ break;
+ default:
+ goto pool32f_invalid;
+ }
+ } else {
+ /* MOVF_FMT */
+ switch (fmt) {
+ case FMT_SDPS_S:
+ gen_movcf_s(ctx, rs, rt, cc, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_movcf_d(ctx, rs, rt, cc, 0);
+ break;
+ case FMT_SDPS_PS:
+ check_ps(ctx);
+ gen_movcf_ps(ctx, rs, rt, cc, 0);
+ break;
+ default:
+ goto pool32f_invalid;
+ }
}
break;
- case MOVT_FMT:
- switch (fmt) {
- case FMT_SDPS_S:
- gen_movcf_s(ctx, rs, rt, cc, 1);
- break;
- case FMT_SDPS_D:
- gen_movcf_d(ctx, rs, rt, cc, 1);
- break;
- case FMT_SDPS_PS:
- check_ps(ctx);
- gen_movcf_ps(ctx, rs, rt, cc, 1);
- break;
- default:
- goto pool32f_invalid;
+ case MOVT_FMT: /* CLASS_FMT */
+ if (ctx->insn_flags & ISA_MIPS32R6) {
+ /* CLASS_FMT */
+ switch (fmt) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);
+ break;
+ default:
+ goto pool32f_invalid;
+ }
+ } else {
+ /* MOVT_FMT */
+ switch (fmt) {
+ case FMT_SDPS_S:
+ gen_movcf_s(ctx, rs, rt, cc, 1);
+ break;
+ case FMT_SDPS_D:
+ gen_movcf_d(ctx, rs, rt, cc, 1);
+ break;
+ case FMT_SDPS_PS:
+ check_ps(ctx);
+ gen_movcf_ps(ctx, rs, rt, cc, 1);
+ break;
+ default:
+ goto pool32f_invalid;
+ }
}
break;
case PREFX:
@@ -14362,6 +14426,32 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
default: \
goto pool32f_invalid; \
}
+ case MINA_FMT:
+ check_insn(ctx, ISA_MIPS32R6);
+ switch ((ctx->opcode >> 9) & 0x3) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);
+ break;
+ default:
+ goto pool32f_invalid;
+ }
+ break;
+ case MAXA_FMT:
+ check_insn(ctx, ISA_MIPS32R6);
+ switch ((ctx->opcode >> 9) & 0x3) {
+ case FMT_SDPS_S:
+ gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
+ break;
+ case FMT_SDPS_D:
+ gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);
+ break;
+ default:
+ goto pool32f_invalid;
+ }
+ break;
case 0x30:
/* regular FP ops */
switch ((ctx->opcode >> 6) & 0x3) {
@@ -14390,13 +14480,90 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case 0x38:
/* cmovs */
- switch ((ctx->opcode >> 6) & 0x3) {
- case MOVN_FMT:
+ switch ((ctx->opcode >> 6) & 0x7) {
+ case MOVN_FMT: /* SELNEZ_FMT */
+ if (ctx->insn_flags & ISA_MIPS32R6) {
+ /* SELNEZ_FMT */
+ switch ((ctx->opcode >> 9) & 0x3) {
+ case FMT_SDPS_S:
+ gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
+ break;
+ case FMT_SDPS_D:
+ gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
+ break;
+ default:
+ goto pool32f_invalid;
+ }
+ } else {
+ /* MOVN_FMT */
+ FINSN_3ARG_SDPS(MOVN);
+ }
+ break;
+ case MOVN_FMT_04:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
FINSN_3ARG_SDPS(MOVN);
break;
- case MOVZ_FMT:
+ case MOVZ_FMT: /* SELEQZ_FMT */
+ if (ctx->insn_flags & ISA_MIPS32R6) {
+ /* SELEQZ_FMT */
+ switch ((ctx->opcode >> 9) & 0x3) {
+ case FMT_SDPS_S:
+ gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
+ break;
+ case FMT_SDPS_D:
+ gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
+ break;
+ default:
+ goto pool32f_invalid;
+ }
+ } else {
+ /* MOVZ_FMT */
+ FINSN_3ARG_SDPS(MOVZ);
+ }
+ break;
+ case MOVZ_FMT_05:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
FINSN_3ARG_SDPS(MOVZ);
break;
+ case SEL_FMT:
+ check_insn(ctx, ISA_MIPS32R6);
+ switch ((ctx->opcode >> 9) & 0x3) {
+ case FMT_SDPS_S:
+ gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
+ break;
+ case FMT_SDPS_D:
+ gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);
+ break;
+ default:
+ goto pool32f_invalid;
+ }
+ break;
+ case MADDF_FMT:
+ check_insn(ctx, ISA_MIPS32R6);
+ switch ((ctx->opcode >> 9) & 0x3) {
+ case FMT_SDPS_S:
+ mips32_op = OPC_MADDF_S;
+ goto do_fpop;
+ case FMT_SDPS_D:
+ mips32_op = OPC_MADDF_D;
+ goto do_fpop;
+ default:
+ goto pool32f_invalid;
+ }
+ break;
+ case MSUBF_FMT:
+ check_insn(ctx, ISA_MIPS32R6);
+ switch ((ctx->opcode >> 9) & 0x3) {
+ case FMT_SDPS_S:
+ mips32_op = OPC_MSUBF_S;
+ goto do_fpop;
+ case FMT_SDPS_D:
+ mips32_op = OPC_MSUBF_D;
+ goto do_fpop;
+ default:
+ goto pool32f_invalid;
+ }
+ break;
default:
goto pool32f_invalid;
}
--
1.7.5.4
next prev parent reply other threads:[~2015-06-19 16:26 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-19 16:25 [Qemu-devel] [PATCH v2 00/15] target-mips: add microMIPS32 R6 Instruction Set support Yongbok Kim
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 01/15] target-mips: fix {RD, WR}PGPR in microMIPS Yongbok Kim
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 02/15] target-mips: add microMIPS TLBINV, TLBINVF Yongbok Kim
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 03/15] target-mips: remove an unused argument Yongbok Kim
2015-06-22 8:16 ` Leon Alrae
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 04/15] target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP Yongbok Kim
2015-06-22 8:36 ` Leon Alrae
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 05/15] target-mips: rearrange gen_compute_compact_branch Yongbok Kim
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 06/15] target-mips: raise RI exceptions when FIR.PS = 0 Yongbok Kim
2015-06-22 9:41 ` Leon Alrae
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 07/15] target-mips: signal RI for removed instructions in microMIPS R6 Yongbok Kim
2015-06-22 9:41 ` Leon Alrae
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 08/15] target-mips: add microMIPS32 R6 opcode enum Yongbok Kim
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 09/15] target-mips: microMIPS32 R6 branches and jumps Yongbok Kim
2015-06-23 10:40 ` Leon Alrae
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 10/15] target-mips: microMIPS32 R6 POOL32A{XF} instructions Yongbok Kim
2015-06-19 16:25 ` Yongbok Kim [this message]
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 12/15] target-mips: microMIPS32 R6 POOL32{I, C} instructions Yongbok Kim
2015-06-23 14:23 ` Leon Alrae
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 13/15] target-mips: microMIPS32 R6 Major instructions Yongbok Kim
2015-06-22 12:19 ` Leon Alrae
2015-06-23 9:08 ` Yongbok Kim
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 14/15] target-mips: microMIPS32 R6 POOL16{A, C} instructions Yongbok Kim
2015-06-23 11:18 ` Leon Alrae
2015-06-19 16:25 ` [Qemu-devel] [PATCH v2 15/15] target-mips: add mips32r6-generic CPU definition Yongbok Kim
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