From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFOFO-0004wW-Aw for qemu-devel@nongnu.org; Wed, 15 Jul 2015 11:05:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZFOFN-0008MY-AD for qemu-devel@nongnu.org; Wed, 15 Jul 2015 11:05:22 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:49147) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFOFM-0008MS-T6 for qemu-devel@nongnu.org; Wed, 15 Jul 2015 11:05:21 -0400 From: Aurelien Jarno Date: Wed, 15 Jul 2015 17:05:09 +0200 Message-Id: <1436972709-5860-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH v2] target-mips: simplify LWL/LDL mask generation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Leon Alrae , Aurelien Jarno The LWL/LDL instructions mask the GPR with a mask depending on the address alignement. It is currently computed by doing: mask = 0x7fffffffffffffffull >> (t1 ^ 63) It's simpler to generate it by doing: mask = ~(-1 << t1) It uses one TCG instruction less, and it avoids a 32/64-bit constant loading which can take a few instructions on RISC hosts. Cc: Leon Alrae Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) Changes v1 -> v2: - Use ~(-1 << t1) instead of (1 << t1) - 1 as suggested by Paolo Bonzini. diff --git a/target-mips/translate.c b/target-mips/translate.c index 0ac3bd8..950ca2c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -2153,11 +2153,10 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_andi_tl(t0, t0, ~7); tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ); tcg_gen_shl_tl(t0, t0, t1); - tcg_gen_xori_tl(t1, t1, 63); - t2 = tcg_const_tl(0x7fffffffffffffffull); - tcg_gen_shr_tl(t2, t2, t1); + t2 = tcg_const_tl(-1); + tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); - tcg_gen_and_tl(t1, t1, t2); + tcg_gen_andc_tl(t1, t1, t2); tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); tcg_temp_free(t1); @@ -2246,11 +2245,10 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_andi_tl(t0, t0, ~3); tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL); tcg_gen_shl_tl(t0, t0, t1); - tcg_gen_xori_tl(t1, t1, 31); - t2 = tcg_const_tl(0x7fffffffull); - tcg_gen_shr_tl(t2, t2, t1); + t2 = tcg_const_tl(-1); + tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); - tcg_gen_and_tl(t1, t1, t2); + tcg_gen_andc_tl(t1, t1, t2); tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); tcg_temp_free(t1); -- 2.1.4