From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFOdl-0002Ph-J8 for qemu-devel@nongnu.org; Wed, 15 Jul 2015 11:30:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZFOaQ-0008Lg-Ql for qemu-devel@nongnu.org; Wed, 15 Jul 2015 11:27:10 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34481) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFOaQ-0008LY-Lz for qemu-devel@nongnu.org; Wed, 15 Jul 2015 11:27:06 -0400 From: Paolo Bonzini Date: Wed, 15 Jul 2015 17:26:59 +0200 Message-Id: <1436974021-28978-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 0/2] tcg: aarch64: use 32-bit offset for 32-bit user-mode emulation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: claudio.fontana@huawei.com, aurelien@aurel32.net, rth@twiddle.net The register allocator may sometimes pass a 64-bit value to a 32-bit operation if truncations are considered no-ops by the backend. When this happens, user-mode emulation may use an incorrect offset for loads and stores. This affects aarch64 and x86, because other architectures already zero-extend the offset before using it for a load or store. To fix this for aarch64, use the uxtw modifier on load and store instructions. Paolo Paolo Bonzini (2): tcg: aarch64: add ext argument to tcg_out_insn_3310 tcg: aarch64: use 32-bit offset for 32-bit user-mode emulation tcg/aarch64/tcg-target.c | 63 +++++++++++++++++++++++++++--------------------- 1 file changed, 36 insertions(+), 27 deletions(-) -- 2.4.3