From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52294) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFOdj-00022l-6P for qemu-devel@nongnu.org; Wed, 15 Jul 2015 11:30:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZFOaU-0008MJ-Gj for qemu-devel@nongnu.org; Wed, 15 Jul 2015 11:27:11 -0400 Received: from mx1.redhat.com ([209.132.183.28]:57384) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZFOaU-0008MD-9o for qemu-devel@nongnu.org; Wed, 15 Jul 2015 11:27:10 -0400 From: Paolo Bonzini Date: Wed, 15 Jul 2015 17:27:01 +0200 Message-Id: <1436974021-28978-3-git-send-email-pbonzini@redhat.com> In-Reply-To: <1436974021-28978-1-git-send-email-pbonzini@redhat.com> References: <1436974021-28978-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 2/2] tcg: aarch64: use 32-bit offset for 32-bit user-mode emulation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: claudio.fontana@huawei.com, aurelien@aurel32.net, rth@twiddle.net Thanks to the previous patch, it is now easy for tcg_out_qemu_ld and tcg_out_qemu_st to use a 32-bit zero extended offset. However, the guest base register x28 must be the base and addr_reg must be the index. Reported-by: Leon Alrae Signed-off-by: Paolo Bonzini --- tcg/aarch64/tcg-target.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 5395202..4aca883 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -1109,10 +1109,10 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp s_bits, #endif /* CONFIG_SOFTMMU */ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext, - TCGReg data_r, TCGReg addr_r, TCGReg off_r) + TCGReg data_r, TCGReg addr_r, + TCGType otype, TCGReg off_r) { const TCGMemOp bswap = memop & MO_BSWAP; - const TCGType otype = TCG_TYPE_I64; switch (memop & MO_SSIZE) { case MO_UB: @@ -1165,10 +1165,10 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType ext, } static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop, - TCGReg data_r, TCGReg addr_r, TCGReg off_r) + TCGReg data_r, TCGReg addr_r, + TCGType otype, TCGReg off_r) { const TCGMemOp bswap = memop & MO_BSWAP; - const TCGType otype = TCG_TYPE_I64; switch (memop & MO_SIZE) { case MO_8: @@ -1210,12 +1210,15 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, tcg_insn_unit *label_ptr; tcg_out_tlb_read(s, addr_reg, s_bits, &label_ptr, mem_index, 1); - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, addr_reg, TCG_REG_X1); + tcg_out_qemu_ld_direct(s, memop, ext, data_reg, addr_reg, + TCG_TYPE_I64, TCG_REG_X1); add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, addr_reg, - GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR); + const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + tcg_out_qemu_ld_direct(s, memop, ext, data_reg, + GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR, + otype, addr_reg); #endif /* CONFIG_SOFTMMU */ } @@ -1229,12 +1232,15 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, tcg_insn_unit *label_ptr; tcg_out_tlb_read(s, addr_reg, s_bits, &label_ptr, mem_index, 0); - tcg_out_qemu_st_direct(s, memop, data_reg, addr_reg, TCG_REG_X1); + tcg_out_qemu_st_direct(s, memop, data_reg, addr_reg, + TCG_TYPE_I64, TCG_REG_X1); add_qemu_ldst_label(s, false, oi, s_bits == MO_64, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ - tcg_out_qemu_st_direct(s, memop, data_reg, addr_reg, - GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR); + const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + tcg_out_qemu_st_direct(s, memop, data_reg, + GUEST_BASE ? TCG_REG_GUEST_BASE : TCG_REG_XZR, + otype, addr_reg); #endif /* CONFIG_SOFTMMU */ } -- 2.4.3