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From: "Jonathan (Zhixiong) Zhang" <zjzhang@codeaurora.org>
To: catalin.marinas@arm.com, will.deacon@arm.com, fu.wei@linaro.org,
	al.stone@linaro.org,
	"bp @ alien8 . de Matt Fleming" <matt.fleming@intel.com>,
	rjw@rjwysocki.net, ard.biesheuvel@linaro.org,
	leif.lindholm@linaro.org, hanjun.guo@linaro.org
Cc: "Jonathan (Zhixiong) Zhang" <zjzhang@codeaurora.org>,
	linux-kernel@vger.kernel.org, linaro-acpi@lists.linaro.org,
	timur@codeaurora.org
Subject: [PATCH V8 3/5] arm64: mm: add PROT_DEVICE_nGnRnE and PROT_NORMAL_WT
Date: Fri, 24 Jul 2015 16:51:07 -0700	[thread overview]
Message-ID: <1437781869-29721-4-git-send-email-zjzhang@codeaurora.org> (raw)
In-Reply-To: <1437781869-29721-1-git-send-email-zjzhang@codeaurora.org>

From: "Jonathan (Zhixiong) Zhang" <zjzhang@codeaurora.org>

UEFI spec 2.5 section 2.3.6.1 defines that EFI_MEMORY_[UC|WC|WT|WB] are
possible EFI memory types for AArch64. Each of those EFI memory types
is mapped to a corresponding AArch64 memory type. So we need to define
PROT_DEVICE_nGnRnE and PROT_NORMWL_WT additionaly.

MT_NORMAL_WT is defined, and its encoding is added to MAIR_EL1 when
initializing cpu.

Change-Id: I20ac71ddf74c17e41769ecbb5f8c60eeefbb398a
Signed-off-by: Jonathan (Zhixiong) Zhang <zjzhang@codeaurora.org>
---
 arch/arm64/include/asm/memory.h  | 1 +
 arch/arm64/include/asm/pgtable.h | 2 ++
 arch/arm64/mm/proc.S             | 4 +++-
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index f800d45ea226..4112b3d7468e 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -100,6 +100,7 @@
 #define MT_DEVICE_GRE		2
 #define MT_NORMAL_NC		3
 #define MT_NORMAL		4
+#define MT_NORMAL_WT		5
 
 /*
  * Memory types for Stage-2 translation
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 800ec0e87ed9..5c108ad13558 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -61,8 +61,10 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
 #define PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_SECT_AF)
 #endif
 
+#define PROT_DEVICE_nGnRnE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
 #define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
 #define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC))
+#define PROT_NORMAL_WT		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_WT))
 #define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL))
 
 #define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 838266f5b056..dfcc05804665 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -303,12 +303,14 @@ ENTRY(__cpu_setup)
 	 *   DEVICE_GRE		010	00001100
 	 *   NORMAL_NC		011	01000100
 	 *   NORMAL		100	11111111
+	 *   NORMAL_WT		101	10111011
 	 */
 	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
 		     MAIR(0x04, MT_DEVICE_nGnRE) | \
 		     MAIR(0x0c, MT_DEVICE_GRE) | \
 		     MAIR(0x44, MT_NORMAL_NC) | \
-		     MAIR(0xff, MT_NORMAL)
+		     MAIR(0xff, MT_NORMAL) | \
+		     MAIR(0xbb, MT_NORMAL_WT)
 	msr	mair_el1, x5
 	/*
 	 * Prepare SCTLR
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


  parent reply	other threads:[~2015-07-24 23:51 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-24 23:51 [PATCH V8 0/5] map GHES memory region according to EFI memory map Jonathan (Zhixiong) Zhang
2015-07-24 23:51 ` Jonathan (Zhixiong) Zhang
2015-07-24 23:51 ` [PATCH V8 1/5] efi: x86: rearrange efi_mem_attributes() Jonathan (Zhixiong) Zhang
2015-07-24 23:51 ` [PATCH V8 2/5] x86: acpi: implement arch_apei_get_mem_attributes() Jonathan (Zhixiong) Zhang
2015-07-24 23:51 ` Jonathan (Zhixiong) Zhang [this message]
2015-07-27  9:19   ` [PATCH V8 3/5] arm64: mm: add PROT_DEVICE_nGnRnE and PROT_NORMAL_WT Catalin Marinas
2015-07-29  0:20     ` Zhang, Jonathan Zhixiong
2015-07-24 23:51 ` [PATCH V8 4/5] arm64: apei: implement arch_apei_get_mem_attributes() Jonathan (Zhixiong) Zhang
2015-07-27 10:03   ` Catalin Marinas
2015-07-29  0:24     ` Zhang, Jonathan Zhixiong
2015-07-24 23:51 ` [PATCH V8 5/5] acpi, apei: use appropriate pgprot_t to map GHES memory Jonathan (Zhixiong) Zhang

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