From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH V3 4/6] libxc: expose xsaves/xgetbv1/xsavec to hvm guest Date: Wed, 5 Aug 2015 09:37:22 +0100 Message-ID: <1438763842.9747.13.camel@citrix.com> References: <1438739842-31658-1-git-send-email-shuai.ruan@linux.intel.com> <1438739842-31658-5-git-send-email-shuai.ruan@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1438739842-31658-5-git-send-email-shuai.ruan@linux.intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Shuai Ruan , xen-devel@lists.xen.org Cc: kevin.tian@intel.com, wei.liu2@citrix.com, jbeulich@suse.com, stefano.stabellini@eu.citrix.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, eddie.dong@intel.com, jun.nakajima@intel.com, keir@xen.org List-Id: xen-devel@lists.xenproject.org On Wed, 2015-08-05 at 09:57 +0800, Shuai Ruan wrote: > This patch exposes xsaves/xgetbv1/xsavec to hvm guest. > The reserved bits of eax/ebx/ecx/edx must be cleaned up > when call cpuid(0dh) with leaf 1 or 2..63. > > According to the spec the following bits must be reseved: "reserved" > For leaf 1, bits 03-04/08-31 of ecx is reserved. Edx is reserved. > For leaf 2...63, bits 01-31 of ecx is reserved. Edx is reserved. > > Signed-off-by: Shuai Ruan Although this is toolstack code I think this really ought to be acked by the hypervisor x86 maintainers, if they are happy with it then I am too, and in that case you may add: Acked-by: Ian Campbell > --- > tools/libxc/xc_cpuid_x86.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c > index c97f91a..b69676a 100644 > --- a/tools/libxc/xc_cpuid_x86.c > +++ b/tools/libxc/xc_cpuid_x86.c > @@ -211,6 +211,9 @@ static void intel_xc_cpuid_policy( > } > > #define XSAVEOPT (1 << 0) > +#define XSAVEC (1 << 1) > +#define XGETBV1 (1 << 2) > +#define XSAVES (1 << 3) > /* Configure extended state enumeration leaves (0x0000000D for xsave) */ > static void xc_cpuid_config_xsave( > xc_interface *xch, domid_t domid, uint64_t xfeature_mask, > @@ -247,8 +250,9 @@ static void xc_cpuid_config_xsave( > regs[1] = 512 + 64; /* FP/SSE + XSAVE.HEADER */ > break; > case 1: /* leaf 1 */ > - regs[0] &= XSAVEOPT; > - regs[1] = regs[2] = regs[3] = 0; > + regs[0] &= (XSAVEOPT | XSAVEC | XGETBV1 | XSAVES); > + regs[2] &= 0xe7; > + regs[3] = 0; > break; > case 2 ... 63: /* sub-leaves */ > if ( !(xfeature_mask & (1ULL << input[1])) ) > @@ -256,8 +260,9 @@ static void xc_cpuid_config_xsave( > regs[0] = regs[1] = regs[2] = regs[3] = 0; > break; > } > - /* Don't touch EAX, EBX. Also cleanup ECX and EDX */ > - regs[2] = regs[3] = 0; > + /* Don't touch EAX, EBX. Also cleanup EDX. Cleanup bits 01-32 of > ECX*/ > + regs[2] &= 0x1; > + regs[3] = 0; > break; > } > }