From mboxrd@z Thu Jan 1 00:00:00 1970 From: Geert Uytterhoeven Date: Wed, 05 Aug 2015 08:58:06 +0000 Subject: [PATCH v4 2/6] ARM: shmobile: r8a7740 dtsi: Add L1 cache information to CPU node Message-Id: <1438765090-823-3-git-send-email-geert+renesas@glider.be> List-Id: References: <1438765090-823-1-git-send-email-geert+renesas@glider.be> In-Reply-To: <1438765090-823-1-git-send-email-geert+renesas@glider.be> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linux-arm-kernel@lists.infradead.org Describe the L1 cache in the CPU node: - L1 instruction cache: 32 KiB (8 KiB x 4 ways), - L1 data cache: 32 KiB (8 KiB x 4 ways). Add a link to the L2 cache. Signed-off-by: Geert Uytterhoeven --- v4: - No changes, v3: - No changes, v2: - New. --- arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index ddef5b1c68fa06b3..3aaab195132bfc2c 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -26,6 +26,15 @@ reg = <0x0>; clock-frequency = <800000000>; power-domains = <&pd_a3sm>; + i-cache-size = <0x8000>; + i-cache-sets = <256>; + i-cache-block-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <256>; + d-cache-block-size = <32>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; }; }; -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Geert Uytterhoeven Subject: [PATCH v4 2/6] ARM: shmobile: r8a7740 dtsi: Add L1 cache information to CPU node Date: Wed, 5 Aug 2015 10:58:06 +0200 Message-ID: <1438765090-823-3-git-send-email-geert+renesas@glider.be> References: <1438765090-823-1-git-send-email-geert+renesas@glider.be> Return-path: In-Reply-To: <1438765090-823-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Simon Horman , Magnus Damm Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-sh-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Geert Uytterhoeven List-Id: devicetree@vger.kernel.org Describe the L1 cache in the CPU node: - L1 instruction cache: 32 KiB (8 KiB x 4 ways), - L1 data cache: 32 KiB (8 KiB x 4 ways). Add a link to the L2 cache. Signed-off-by: Geert Uytterhoeven --- v4: - No changes, v3: - No changes, v2: - New. --- arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index ddef5b1c68fa06b3..3aaab195132bfc2c 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -26,6 +26,15 @@ reg = <0x0>; clock-frequency = <800000000>; power-domains = <&pd_a3sm>; + i-cache-size = <0x8000>; + i-cache-sets = <256>; + i-cache-block-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <256>; + d-cache-block-size = <32>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; }; }; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: geert+renesas@glider.be (Geert Uytterhoeven) Date: Wed, 5 Aug 2015 10:58:06 +0200 Subject: [PATCH v4 2/6] ARM: shmobile: r8a7740 dtsi: Add L1 cache information to CPU node In-Reply-To: <1438765090-823-1-git-send-email-geert+renesas@glider.be> References: <1438765090-823-1-git-send-email-geert+renesas@glider.be> Message-ID: <1438765090-823-3-git-send-email-geert+renesas@glider.be> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Describe the L1 cache in the CPU node: - L1 instruction cache: 32 KiB (8 KiB x 4 ways), - L1 data cache: 32 KiB (8 KiB x 4 ways). Add a link to the L2 cache. Signed-off-by: Geert Uytterhoeven --- v4: - No changes, v3: - No changes, v2: - New. --- arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index ddef5b1c68fa06b3..3aaab195132bfc2c 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -26,6 +26,15 @@ reg = <0x0>; clock-frequency = <800000000>; power-domains = <&pd_a3sm>; + i-cache-size = <0x8000>; + i-cache-sets = <256>; + i-cache-block-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <256>; + d-cache-block-size = <32>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; }; }; -- 1.9.1