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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	patches@linaro.org
Subject: [Qemu-devel] [PATCH 2/6] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
Date: Fri,  7 Aug 2015 13:33:26 +0100	[thread overview]
Message-ID: <1438950810-28618-3-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1438950810-28618-1-git-send-email-peter.maydell@linaro.org>

Move the two regdefs for TLBI ALLE1 and TLBI ALLE1IS down so that the
whole set of AArch64 TLBI regdefs is arranged in numeric order.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 01f0d0d..d5052c2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2434,14 +2434,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
       .access = PL1_W, .type = ARM_CP_NOP },
     /* TLBI operations */
-    { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
-      .writefn = tlbiall_write },
-    { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
-      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
-      .writefn = tlbiall_is_write },
     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NO_RAW,
@@ -2490,6 +2482,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
       .access = PL1_W, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vaa_write },
+    { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
+      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
+      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .writefn = tlbiall_is_write },
+    { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
+      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
+      .access = PL2_W, .type = ARM_CP_NO_RAW,
+      .writefn = tlbiall_write },
 #ifndef CONFIG_USER_ONLY
     /* 64 bit address translation operations */
     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
-- 
1.9.1

  parent reply	other threads:[~2015-08-07 12:51 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-07 12:33 [Qemu-devel] [PATCH 0/6] flush TLBs for one MMUidx only, missing AArch64 TLB ops Peter Maydell
2015-08-07 12:33 ` [Qemu-devel] [PATCH 1/6] cputlb: Add functions for flushing TLB for a single MMU index Peter Maydell
2015-08-14 10:24   ` Peter Maydell
2015-08-07 12:33 ` Peter Maydell [this message]
2015-08-07 12:33 ` [Qemu-devel] [PATCH 3/6] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch Peter Maydell
2015-08-07 12:33 ` [Qemu-devel] [PATCH 4/6] target-arm: Implement missing EL2 TLBI operations Peter Maydell
2015-08-07 12:33 ` [Qemu-devel] [PATCH 5/6] target-arm: Implement missing EL3 TLB invalidate operations Peter Maydell
2015-08-07 12:33 ` [Qemu-devel] [PATCH 6/6] target-arm: Implement AArch64 TLBI operations on IPAs Peter Maydell
2015-08-13 10:40 ` [Qemu-devel] [PATCH 0/6] flush TLBs for one MMUidx only, missing AArch64 TLB ops Edgar E. Iglesias

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