From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
	id S1753577AbbHTPDb (ORCPT <rfc822;w@1wt.eu>);
	Thu, 20 Aug 2015 11:03:31 -0400
Received: from mga09.intel.com ([134.134.136.24]:56437 "EHLO mga09.intel.com"
	rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP
	id S1752307AbbHTPDa (ORCPT <rfc822;linux-kernel@vger.kernel.org>);
	Thu, 20 Aug 2015 11:03:30 -0400
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="5.15,714,1432623600"; 
   d="scan'208";a="787577439"
Message-ID: <1440082994.7611.3.camel@schen9-mobl2>
Subject: Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions
 implementations
From: Tim Chen <tim.c.chen@linux.intel.com>
To: Borislav Petkov <bp@suse.de>
Cc: Thomas Gleixner <tglx@linutronix.de>, Dave Hansen <dave.hansen@intel.com>,
        Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
        Herbert Xu <herbert@gondor.apana.org.au>,
        Chandramouli Narayanan <mouli@linux.intel.com>, x86@kernel.org,
        linux-kernel@vger.kernel.org, mouli_7982@yahoo.com
Date: Thu, 20 Aug 2015 08:03:14 -0700
In-Reply-To: <20150820040818.GA23184@nazgul.tnic>
References: <1439844283.21627.5.camel@schen9-desk2.jf.intel.com>
	 <55D24FEA.1000803@intel.com>
	 <1439850820.21627.11.camel@schen9-desk2.jf.intel.com>
	 <alpine.DEB.2.11.1508181846160.3873@nanos>
	 <1440002998.13451.1.camel@schen9-mobl2>
	 <20150820040818.GA23184@nazgul.tnic>
Content-Type: text/plain; charset="UTF-8"
X-Mailer: Evolution 3.10.4 (3.10.4-4.fc20) 
Mime-Version: 1.0
Content-Transfer-Encoding: 7bit
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Thu, 2015-08-20 at 06:08 +0200, Borislav Petkov wrote:
> On Wed, Aug 19, 2015 at 09:49:58AM -0700, Tim Chen wrote:

> > Mouli did the patch originally but he left the company.  So
> > I'm picking it up.
> 
> So the SOB chain should be:
> 
> From: you
> 
> <commit message>
> 
> Originally-by: Mouli
> Signed-off-by: you
> 

Thanks.  Revised patch embedded below.

Tim

--->8---
From: Tim Chen <tim.c.chen@linux.intel.com>
Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations

The Intel Secure Hash Algorithm Extensions are designed to improve the performance
of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit.

This will allow the feature to be shown in the /proc/cpuinfo.

The SHA extension programming guide is found in chapter 8 of the Intel
Architecture Instruction Set Extensions Programming reference:
https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf

Originally-by: Chandramouli Narayanan <mouli@linux.intel.com>
Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
---
 arch/x86/include/asm/cpufeature.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 3d6606f..a94f83d 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -239,6 +239,7 @@
 #define X86_FEATURE_AVX512PF	( 9*32+26) /* AVX-512 Prefetch */
 #define X86_FEATURE_AVX512ER	( 9*32+27) /* AVX-512 Exponential and Reciprocal */
 #define X86_FEATURE_AVX512CD	( 9*32+28) /* AVX-512 Conflict Detection */
+#define X86_FEATURE_SHA_NI	( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
 
 /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
 #define X86_FEATURE_XSAVEOPT	(10*32+ 0) /* XSAVEOPT */
-- 
1.8.3.1