From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752830AbbHZQfe (ORCPT ); Wed, 26 Aug 2015 12:35:34 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:56978 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755977AbbHZQfC (ORCPT ); Wed, 26 Aug 2015 12:35:02 -0400 Message-ID: <1440606875.3190.103.camel@pengutronix.de> Subject: Re: [RFC][PATCH 1/2] dt-bindings: drm/mediatek: Add Mediatek DRM dts binding From: Philipp Zabel To: CK Hu Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , David Airlie , Matthias Brugger , devicetree@vger.kernel.org, Jitao Shi , srv_heupstream@mediatek.com, Graeme Gregory , Rob Herring , Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Cawa Cheng , YT Shen , Ashwin Chaugule , linux-mediatek@lists.infradead.org, Sascha Hauer , linux-api@vger.kernel.org, Grant Likely , linux-arm-kernel@lists.infradead.org Date: Wed, 26 Aug 2015 18:34:35 +0200 In-Reply-To: <1431530626-31493-2-git-send-email-ck.hu@mediatek.com> References: <1431530626-31493-1-git-send-email-ck.hu@mediatek.com> <1431530626-31493-2-git-send-email-ck.hu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:100:96de:80ff:fec2:9969 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, overall it looks to me like this binding is modeled after the Linux DRM abstractions. Instead, the device nodes should be modeled after the hardware. Describing each function block as a separate device node is probably not the best choice, as would be combining all devices in the mmsys range into a single device node. So a somewhat arbitrary decision has to be made what to group together. See my comments below: Am Mittwoch, den 13.05.2015, 23:23 +0800 schrieb CK Hu: > This patch includes > 1. Mediatek DRM Device binding > 2. Mediatek DSI Device binding > 3. Mediatek CRTC Main Device binding > 4. Mediatek DDP Device binding > > Signed-off-by: CK Hu > --- > .../bindings/drm/mediatek/mediatek,crtc-main.txt | 38 ++++++++++++++++++++++ > .../bindings/drm/mediatek/mediatek,ddp.txt | 22 +++++++++++++ > .../bindings/drm/mediatek/mediatek,drm.txt | 27 +++++++++++++++ > .../bindings/drm/mediatek/mediatek,dsi.txt | 20 ++++++++++++ > 4 files changed, 107 insertions(+) > create mode 100644 Documentation/devicetree/bindings/drm/mediatek/mediatek,crtc-main.txt > create mode 100644 Documentation/devicetree/bindings/drm/mediatek/mediatek,ddp.txt > create mode 100644 Documentation/devicetree/bindings/drm/mediatek/mediatek,drm.txt > create mode 100644 Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt > > diff --git a/Documentation/devicetree/bindings/drm/mediatek/mediatek,crtc-main.txt b/Documentation/devicetree/bindings/drm/mediatek/mediatek,crtc-main.txt > new file mode 100644 > index 0000000..5c6c420 > --- /dev/null > +++ b/Documentation/devicetree/bindings/drm/mediatek/mediatek,crtc-main.txt > @@ -0,0 +1,38 @@ > +Mediatek CRTC Main Device > +================================ > + > +The Mediatek CRTC Main device is a crtc device of DRM system. "crtc" does not belong in the device tree. There is no crtc hardware. What this node describes is a useful, but fixed configuration of a part of the DISP subsystem function blocks. In my opinion, it would be better to not describe the separate display pipes in the device tree at all if they are dynamically configurable. What for example if you model two separate fixed pipelines in the device tree and then in the future you want to support the MERGE or SPLIT blocks (I'm not sure what MERGE does, SPLIT seems to be needed for 8-lane DSI)? As far as I currently understand, there are five source function blocks that can read from memory (OVL0, OVL1, RDMA0, RDMA1, RDMA2) and three sink function blocks (DSI0, DSI1, DPI0) that can be connected to panels, or encoder bridges. How these map to the crtcs doesn't necessarily have to be described in the device tree. How about a single node that contains all of the DISP functional blocks that don't need their own node (like DSI, which has to be connectable to bridges or panels): disp: disp@0x1400c000 { compatible = "mediatek,mt8173-disp"; interrupts = , /* OVL0 */ ; /* OVL1 */ interrupt-names = "ovl0", "ovl1"; reg = <0 0x1400c000 0 0x1000>, /* OVL0 */ <0 0x1400d000 0 0x1000>, /* OVL1 */ <0 0x1400e000 0 0x1000>, /* RDMA0 */ <0 0x1400f000 0 0x1000>, /* RDMA1 */ <0 0x14010000 0 0x1000>, /* RDMA2 */ <0 0x14013000 0 0x1000>, /* COLOR0 */ <0 0x14014000 0 0x1000>, /* COLOR1 */ <0 0x14015000 0 0x1000>, /* AAL */ <0 0x14016000 0 0x1000>, /* GAMMA */ <0 0x14017000 0 0x1000>, /* MERGE */ <0 0x14018000 0 0x1000>, /* SPLIT0 */ <0 0x14019000 0 0x1000>, /* SPLIT1 */ <0 0x1401a000 0 0x1000>, /* UFOE */ <0 0x14020000 0 0x1000>; /* MUTEX */ <0 0x14023000 0 0x1000>; /* OD */ reg-names = "ovl0", "ovl1", "rdma0", "rdma1", "rdma2", "color0", "color1", "aal", "gamma", "merge", "split0", "split1", "ufoe", "mutex", "od"; clocks = <&mmsys CLK_MM_DISP_OVL0>, <&mmsys CLK_MM_DISP_OVL1>, <&mmsys CLK_MM_DISP_RDMA0>, <&mmsys CLK_MM_DISP_RDMA1>, <&mmsys CLK_MM_DISP_RDMA2>, <&mmsys CLK_MM_DISP_COLOR0>, <&mmsys CLK_MM_DISP_COLOR1>, <&mmsys CLK_MM_DISP_AAL>, <&mmsys CLK_MM_DISP_GAMMA>, <&mmsys CLK_MM_DISP_MERGE>, <&mmsys CLK_MM_DISP_SPLIT0>, <&mmsys CLK_MM_DISP_SPLIT1>, <&mmsys CLK_MM_DISP_UFOE>, <&mmsys CLK_MM_MUTEX_32K>, <&mmsys CLK_MM_DISP_OD>; clock-names = "ovl0", "ovl1", "rdma0", "rdma1", "rdma2", "color0", "color1", "aal", "gamma", "merge", "split0", "split1", "ufoe", "mutex", "od"; power-domains = <&scpsys MT8173_POWER_DOMAIN_DIS>; config = <&mmsys>; /* syscon */ }; How the muxes in the config area are set up to connect those blocks could be determined by the driver. > +Required properties: > +- compatible: "mediatek,-crtc-main" > +- interrupts: The interrupt signal from the CRTC Main block. > +- reg: Physical base address and length of the controller's registers > +- clocks: device clocks > + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. > +- ddp: phandle of ddp device which control display data path. > + > +Example: > + > +crtc_main: crtc@1400c000 { > + compatible = "mediatek,mt8173-crtc-main"; > + interrupts = ; Should it be mentioned that this is the interrupt of the source of the pipeline (OVL0/1)? > + reg = <0 0x1400c000 0 0x1000>, /* OVL0 */ > + <0 0x1400e000 0 0x1000>, /* RDMA0 */ > + <0 0x14013000 0 0x1000>, /* COLOR0 */ > + <0 0x14015000 0 0x1000>, /* AAL */ > + <0 0x1401a000 0 0x1000>, /* UFOE */ > + <0 0x14023000 0 0x1000>; /* OD */ With the amount of register ranges and given the symmetry with the clocks, better use reg-names instead of position to determine the register space for each function block. reg-names = "ovl0", "rdma0", "color0", "aal", "ufoe", "od"; > + clocks = <&mmsys MM_DISP_OVL0>, > + <&mmsys MM_DISP_RDMA0>, > + <&mmsys MM_DISP_COLOR0>, > + <&mmsys MM_DISP_AAL>, > + <&mmsys MM_DISP_UFOE>, > + <&mmsys MM_DISP_OD>; > + clock-names = "ovl0_disp", > + "rdma0_disp", > + "color0_disp", > + "aal_disp", > + "ufoe_disp", > + "od_disp"; I'd drop the disp suffix from the clock input names. clock-names = "ovl0", "rdma0", "color0", "aal", "ufoe", "od"; > + ddp = <&ddp>; > +}; > \ No newline at end of file > diff --git a/Documentation/devicetree/bindings/drm/mediatek/mediatek,ddp.txt b/Documentation/devicetree/bindings/drm/mediatek/mediatek,ddp.txt > new file mode 100644 > index 0000000..77cf630 > --- /dev/null > +++ b/Documentation/devicetree/bindings/drm/mediatek/mediatek,ddp.txt > @@ -0,0 +1,22 @@ > +Mediatek DDP Device > +================================ > + > +The Mediatek DDP device control the display data path. This is not a real device either. There is nothing wrong with having a ddp driver, but I don't think it is right to describe this driver in the device tree. What we really have here is the mutex function block and some registers in the mmsys config region, which already can be accessed via the mmsys syscon. With a single disp device node including the mutex and power domain phandle this node would not be necessary. > +Required properties: > +- compatible: "mediatek,-ddp" > +- reg: Physical base address and length of the controller's registers > +- power-domains: a phandle to DDP power domain node. > +- clocks: device clocks > + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. > + > +Example: > + > +ddp: ddp@14000000 { > + compatible = "mediatek,mt8173-ddp"; > + reg = <0 0x14000000 0 0x100>, /* CONFIG */ This remaps part of the mmsys register space, which is already a syscon. Why not use syscon to access it? > + <0 0x14020000 0 0x1000>; /* MUTEX */ > + power-domains = <&scpsys MT8173_POWER_DOMAIN_DIS>; > + clocks = <&mmsys MM_MUTEX_32K>; > + clock-names = "mutex_disp"; > +}; > \ No newline at end of file > diff --git a/Documentation/devicetree/bindings/drm/mediatek/mediatek,drm.txt b/Documentation/devicetree/bindings/drm/mediatek/mediatek,drm.txt > new file mode 100644 > index 0000000..c4a5702 > --- /dev/null > +++ b/Documentation/devicetree/bindings/drm/mediatek/mediatek,drm.txt > @@ -0,0 +1,27 @@ > +Mediatek DRM Device > +================================ > + > +The Mediatek DRM device is a device needed to list all > +display component nodes that comprise the display subsystem. > +And it list the memory-related interface. "drm" does not belong in the device tree. There is no "drm" hardware. Other SoCs use the "display-subsystem" name for this node, it would be better to follow that. > +Required properties: > +- compatible: "mediatek,-drm" > +- larb: Should contain a list of phandles pointing to larb device. > + larb definitions as defined in > + Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt > +- iommus: required a iommu node > +- connectors: Should contain a list of phandles pointing to connector device. > + connector device should be one component of this master. > +- crtcs: Should contain a list of phandles pointing to crtc device. > + crtc device should be one component of this master. "connectors" and "crtcs" as used here are DRM concepts, not hardware devices that should exist in the device tree. Ideally you would use something recognizable from the datasheet, like "sinks" or from the device tree, like "ports" if of-graph bindings are used, or just "components" if this also were to include things like the ddp. Another possibility would be to even merge the > + > +Example: > + > +drm0: drm { > + compatible = "mediatek,mt8173-drm"; > + larb = <&larb0>; > + iommus = <&iommu M4U_PORT_DISP_OVL0>; > + connectors = <&dsi>; > + crtcs = <&crtc_main>; > +}; > \ No newline at end of file > diff --git a/Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt > new file mode 100644 > index 0000000..16e3eb3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt > @@ -0,0 +1,20 @@ > +Mediatek DSI Device > +================================ > + > +The Mediatek DSI device is a connector device of DRM system. > + > +Required properties: > +- compatible: "mediatek,-dsi" > +- reg: Physical base address and length of the controller's registers > +- clocks: device clocks > + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. Will this use the Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt bindings to connect panels controlled via the DSI command channel or the Documentation/devicetree/bindings/graph.txt bindings to connect panels controlled via I2C or other control buses? If so, this should be documented here. > +Example: > + > +dsi: dsi@10215000 { > + compatible = "mediatek,mt8173-dsi"; > + reg = <0 0x1401B000 0 0x1000>, /* DSI0 */ > + <0 0x10215000 0 0x1000>; /* MIPITX */ > + clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>; > + clock-names = "dsi0_engine_disp_ck", "dsi0_digital_disp_ck"; Maybe shorten the clock names to "engine" and "digital" ? And add an example of panel or bridge connected to the DSI sink. What about DSI1 and the DPI sink? best regards Philipp From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philipp Zabel Subject: Re: [RFC][PATCH 1/2] dt-bindings: drm/mediatek: Add Mediatek DRM dts binding Date: Wed, 26 Aug 2015 18:34:35 +0200 Message-ID: <1440606875.3190.103.camel@pengutronix.de> References: <1431530626-31493-1-git-send-email-ck.hu@mediatek.com> <1431530626-31493-2-git-send-email-ck.hu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1431530626-31493-2-git-send-email-ck.hu@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: CK Hu Cc: Mark Rutland , Catalin Marinas , Will Deacon , dri-devel@lists.freedesktop.org, Rob Herring , Cawa Cheng , YT Shen , devicetree@vger.kernel.org, Jitao Shi , Pawel Moll , Ian Campbell , Grant Likely , Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org, Graeme Gregory , srv_heupstream@mediatek.com, linux-api@vger.kernel.org, linux-kernel@vger.kernel.org, Ashwin Chaugule , Sascha Hauer , Kumar Gala List-Id: devicetree@vger.kernel.org SGksCgpvdmVyYWxsIGl0IGxvb2tzIHRvIG1lIGxpa2UgdGhpcyBiaW5kaW5nIGlzIG1vZGVsZWQg YWZ0ZXIgdGhlIExpbnV4IERSTQphYnN0cmFjdGlvbnMuIEluc3RlYWQsIHRoZSBkZXZpY2Ugbm9k ZXMgc2hvdWxkIGJlIG1vZGVsZWQgYWZ0ZXIgdGhlCmhhcmR3YXJlLgoKRGVzY3JpYmluZyBlYWNo IGZ1bmN0aW9uIGJsb2NrIGFzIGEgc2VwYXJhdGUgZGV2aWNlIG5vZGUgaXMgcHJvYmFibHkgbm90 CnRoZSBiZXN0IGNob2ljZSwgYXMgd291bGQgYmUgY29tYmluaW5nIGFsbCBkZXZpY2VzIGluIHRo ZSBtbXN5cyByYW5nZQppbnRvIGEgc2luZ2xlIGRldmljZSBub2RlLiBTbyBhIHNvbWV3aGF0IGFy Yml0cmFyeSBkZWNpc2lvbiBoYXMgdG8gYmUKbWFkZSB3aGF0IHRvIGdyb3VwIHRvZ2V0aGVyLiBT ZWUgbXkgY29tbWVudHMgYmVsb3c6CgpBbSBNaXR0d29jaCwgZGVuIDEzLjA1LjIwMTUsIDIzOjIz ICswODAwIHNjaHJpZWIgQ0sgSHU6Cj4gVGhpcyBwYXRjaCBpbmNsdWRlcwo+IDEuIE1lZGlhdGVr IERSTSBEZXZpY2UgYmluZGluZwo+IDIuIE1lZGlhdGVrIERTSSBEZXZpY2UgYmluZGluZwo+IDMu IE1lZGlhdGVrIENSVEMgTWFpbiBEZXZpY2UgYmluZGluZwo+IDQuIE1lZGlhdGVrIEREUCBEZXZp Y2UgYmluZGluZwo+IAo+IFNpZ25lZC1vZmYtYnk6IENLIEh1IDxjay5odUBtZWRpYXRlay5jb20+ Cj4gLS0tCj4gIC4uLi9iaW5kaW5ncy9kcm0vbWVkaWF0ZWsvbWVkaWF0ZWssY3J0Yy1tYWluLnR4 dCAgIHwgMzggKysrKysrKysrKysrKysrKysrKysrKwo+ICAuLi4vYmluZGluZ3MvZHJtL21lZGlh dGVrL21lZGlhdGVrLGRkcC50eHQgICAgICAgICB8IDIyICsrKysrKysrKysrKysKPiAgLi4uL2Jp bmRpbmdzL2RybS9tZWRpYXRlay9tZWRpYXRlayxkcm0udHh0ICAgICAgICAgfCAyNyArKysrKysr KysrKysrKysKPiAgLi4uL2JpbmRpbmdzL2RybS9tZWRpYXRlay9tZWRpYXRlayxkc2kudHh0ICAg ICAgICAgfCAyMCArKysrKysrKysrKysKPiAgNCBmaWxlcyBjaGFuZ2VkLCAxMDcgaW5zZXJ0aW9u cygrKQo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRp bmdzL2RybS9tZWRpYXRlay9tZWRpYXRlayxjcnRjLW1haW4udHh0Cj4gIGNyZWF0ZSBtb2RlIDEw MDY0NCBEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZHJtL21lZGlhdGVrL21lZGlh dGVrLGRkcC50eHQKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IERvY3VtZW50YXRpb24vZGV2aWNldHJl ZS9iaW5kaW5ncy9kcm0vbWVkaWF0ZWsvbWVkaWF0ZWssZHJtLnR4dAo+ICBjcmVhdGUgbW9kZSAx MDA2NDQgRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2RybS9tZWRpYXRlay9tZWRp YXRlayxkc2kudHh0Cj4gCj4gZGlmZiAtLWdpdCBhL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9i aW5kaW5ncy9kcm0vbWVkaWF0ZWsvbWVkaWF0ZWssY3J0Yy1tYWluLnR4dCBiL0RvY3VtZW50YXRp b24vZGV2aWNldHJlZS9iaW5kaW5ncy9kcm0vbWVkaWF0ZWsvbWVkaWF0ZWssY3J0Yy1tYWluLnR4 dAo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAwMC4uNWM2YzQyMAo+IC0tLSAv ZGV2L251bGwKPiArKysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZHJtL21l ZGlhdGVrL21lZGlhdGVrLGNydGMtbWFpbi50eHQKPiBAQCAtMCwwICsxLDM4IEBACj4gK01lZGlh dGVrIENSVEMgTWFpbiBEZXZpY2UKPiArPT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0K PiArCj4gK1RoZSBNZWRpYXRlayBDUlRDIE1haW4gZGV2aWNlIGlzIGEgY3J0YyBkZXZpY2Ugb2Yg RFJNIHN5c3RlbS4KCiJjcnRjIiBkb2VzIG5vdCBiZWxvbmcgaW4gdGhlIGRldmljZSB0cmVlLiBU aGVyZSBpcyBubyBjcnRjIGhhcmR3YXJlLgpXaGF0IHRoaXMgbm9kZSBkZXNjcmliZXMgaXMgYSB1 c2VmdWwsIGJ1dCBmaXhlZCBjb25maWd1cmF0aW9uIG9mIGEgcGFydApvZiB0aGUgRElTUCBzdWJz eXN0ZW0gZnVuY3Rpb24gYmxvY2tzLgoKSW4gbXkgb3BpbmlvbiwgaXQgd291bGQgYmUgYmV0dGVy IHRvIG5vdCBkZXNjcmliZSB0aGUgc2VwYXJhdGUgZGlzcGxheQpwaXBlcyBpbiB0aGUgZGV2aWNl IHRyZWUgYXQgYWxsIGlmIHRoZXkgYXJlIGR5bmFtaWNhbGx5IGNvbmZpZ3VyYWJsZS4KV2hhdCBm b3IgZXhhbXBsZSBpZiB5b3UgbW9kZWwgdHdvIHNlcGFyYXRlIGZpeGVkIHBpcGVsaW5lcyBpbiB0 aGUgZGV2aWNlCnRyZWUgYW5kIHRoZW4gaW4gdGhlIGZ1dHVyZSB5b3Ugd2FudCB0byBzdXBwb3J0 IHRoZSBNRVJHRSBvciBTUExJVApibG9ja3MgKEknbSBub3Qgc3VyZSB3aGF0IE1FUkdFIGRvZXMs IFNQTElUIHNlZW1zIHRvIGJlIG5lZWRlZCBmb3IKOC1sYW5lIERTSSk/CgpBcyBmYXIgYXMgSSBj dXJyZW50bHkgdW5kZXJzdGFuZCwgdGhlcmUgYXJlIGZpdmUgc291cmNlIGZ1bmN0aW9uIGJsb2Nr cwp0aGF0IGNhbiByZWFkIGZyb20gbWVtb3J5IChPVkwwLCBPVkwxLCBSRE1BMCwgUkRNQTEsIFJE TUEyKSBhbmQgdGhyZWUKc2luayBmdW5jdGlvbiBibG9ja3MgKERTSTAsIERTSTEsIERQSTApIHRo YXQgY2FuIGJlIGNvbm5lY3RlZCB0byBwYW5lbHMsCm9yIGVuY29kZXIgYnJpZGdlcy4gSG93IHRo ZXNlIG1hcCB0byB0aGUgY3J0Y3MgZG9lc24ndCBuZWNlc3NhcmlseSBoYXZlCnRvIGJlIGRlc2Ny aWJlZCBpbiB0aGUgZGV2aWNlIHRyZWUuCgpIb3cgYWJvdXQgYSBzaW5nbGUgbm9kZSB0aGF0IGNv bnRhaW5zIGFsbCBvZiB0aGUgRElTUCBmdW5jdGlvbmFsIGJsb2Nrcwp0aGF0IGRvbid0IG5lZWQg dGhlaXIgb3duIG5vZGUgKGxpa2UgRFNJLCB3aGljaCBoYXMgdG8gYmUgY29ubmVjdGFibGUgdG8K YnJpZGdlcyBvciBwYW5lbHMpOgoKZGlzcDogZGlzcEAweDE0MDBjMDAwIHsKICAgICAgICBjb21w YXRpYmxlID0gIm1lZGlhdGVrLG10ODE3My1kaXNwIjsKICAgICAgICBpbnRlcnJ1cHRzID0gPEdJ Q19TUEkgMTgwIElSUV9UWVBFX0xFVkVMX0xPVz4sIC8qIE9WTDAgKi8KICAgICAgICAgICAgICAg ICAgICAgPEdJQ19TUEkgMTgxIElSUV9UWVBFX0xFVkVMX0xPVz47IC8qIE9WTDEgKi8KCWludGVy cnVwdC1uYW1lcyA9ICJvdmwwIiwgIm92bDEiOwogICAgICAgIHJlZyA9IDwwIDB4MTQwMGMwMDAg MCAweDEwMDA+LCAgLyogT1ZMMCAqLwogICAgICAgICAgICAgIDwwIDB4MTQwMGQwMDAgMCAweDEw MDA+LCAgLyogT1ZMMSAqLwogICAgICAgICAgICAgIDwwIDB4MTQwMGUwMDAgMCAweDEwMDA+LCAg LyogUkRNQTAgKi8KICAgICAgICAgICAgICA8MCAweDE0MDBmMDAwIDAgMHgxMDAwPiwgIC8qIFJE TUExICovCiAgICAgICAgICAgICAgPDAgMHgxNDAxMDAwMCAwIDB4MTAwMD4sICAvKiBSRE1BMiAq LwogICAgICAgICAgICAgIDwwIDB4MTQwMTMwMDAgMCAweDEwMDA+LCAgLyogQ09MT1IwICovCiAg ICAgICAgICAgICAgPDAgMHgxNDAxNDAwMCAwIDB4MTAwMD4sICAvKiBDT0xPUjEgKi8KICAgICAg ICAgICAgICA8MCAweDE0MDE1MDAwIDAgMHgxMDAwPiwgIC8qIEFBTCAqLwogICAgICAgICAgICAg IDwwIDB4MTQwMTYwMDAgMCAweDEwMDA+LCAgLyogR0FNTUEgKi8KICAgICAgICAgICAgICA8MCAw eDE0MDE3MDAwIDAgMHgxMDAwPiwgIC8qIE1FUkdFICovCiAgICAgICAgICAgICAgPDAgMHgxNDAx ODAwMCAwIDB4MTAwMD4sICAvKiBTUExJVDAgKi8KICAgICAgICAgICAgICA8MCAweDE0MDE5MDAw IDAgMHgxMDAwPiwgIC8qIFNQTElUMSAqLwogICAgICAgICAgICAgIDwwIDB4MTQwMWEwMDAgMCAw eDEwMDA+LCAgLyogVUZPRSAqLwogICAgICAgICAgICAgIDwwIDB4MTQwMjAwMDAgMCAweDEwMDA+ OyAgLyogTVVURVggKi8KICAgICAgICAgICAgICA8MCAweDE0MDIzMDAwIDAgMHgxMDAwPjsgIC8q IE9EICovCglyZWctbmFtZXMgPSAib3ZsMCIsICJvdmwxIiwgInJkbWEwIiwgInJkbWExIiwgInJk bWEyIiwKCQkiY29sb3IwIiwgImNvbG9yMSIsICJhYWwiLCAiZ2FtbWEiLCAibWVyZ2UiLAoJCSJz cGxpdDAiLCAic3BsaXQxIiwgInVmb2UiLCAibXV0ZXgiLCAib2QiOwogICAgICAgIGNsb2NrcyA9 IDwmbW1zeXMgQ0xLX01NX0RJU1BfT1ZMMD4sCgkJIDwmbW1zeXMgQ0xLX01NX0RJU1BfT1ZMMT4s CiAgICAgICAgICAgICAgICAgPCZtbXN5cyBDTEtfTU1fRElTUF9SRE1BMD4sCiAgICAgICAgICAg ICAgICAgPCZtbXN5cyBDTEtfTU1fRElTUF9SRE1BMT4sCiAgICAgICAgICAgICAgICAgPCZtbXN5 cyBDTEtfTU1fRElTUF9SRE1BMj4sCiAgICAgICAgICAgICAgICAgPCZtbXN5cyBDTEtfTU1fRElT UF9DT0xPUjA+LAogICAgICAgICAgICAgICAgIDwmbW1zeXMgQ0xLX01NX0RJU1BfQ09MT1IxPiwK ICAgICAgICAgICAgICAgICA8Jm1tc3lzIENMS19NTV9ESVNQX0FBTD4sCiAgICAgICAgICAgICAg ICAgPCZtbXN5cyBDTEtfTU1fRElTUF9HQU1NQT4sCiAgICAgICAgICAgICAgICAgPCZtbXN5cyBD TEtfTU1fRElTUF9NRVJHRT4sCiAgICAgICAgICAgICAgICAgPCZtbXN5cyBDTEtfTU1fRElTUF9T UExJVDA+LAogICAgICAgICAgICAgICAgIDwmbW1zeXMgQ0xLX01NX0RJU1BfU1BMSVQxPiwKICAg ICAgICAgICAgICAgICA8Jm1tc3lzIENMS19NTV9ESVNQX1VGT0U+LAogICAgICAgICAgICAgICAg IDwmbW1zeXMgQ0xLX01NX01VVEVYXzMySz4sCiAgICAgICAgICAgICAgICAgPCZtbXN5cyBDTEtf TU1fRElTUF9PRD47CgljbG9jay1uYW1lcyA9ICJvdmwwIiwgIm92bDEiLCAicmRtYTAiLCAicmRt YTEiLCAicmRtYTIiLAoJCSJjb2xvcjAiLCAiY29sb3IxIiwgImFhbCIsICJnYW1tYSIsICJtZXJn ZSIsCgkJInNwbGl0MCIsICJzcGxpdDEiLCAidWZvZSIsICJtdXRleCIsICJvZCI7CiAgICAgICAg cG93ZXItZG9tYWlucyA9IDwmc2Nwc3lzIE1UODE3M19QT1dFUl9ET01BSU5fRElTPjsKICAgICAg ICBjb25maWcgPSA8Jm1tc3lzPjsgLyogc3lzY29uICovCn07CgpIb3cgdGhlIG11eGVzIGluIHRo ZSBjb25maWcgYXJlYSBhcmUgc2V0IHVwIHRvIGNvbm5lY3QgdGhvc2UgYmxvY2tzCmNvdWxkIGJl IGRldGVybWluZWQgYnkgdGhlIGRyaXZlci4KCj4gK1JlcXVpcmVkIHByb3BlcnRpZXM6Cj4gKy0g Y29tcGF0aWJsZTogIm1lZGlhdGVrLDxjaGlwPi1jcnRjLW1haW4iCj4gKy0gaW50ZXJydXB0czog VGhlIGludGVycnVwdCBzaWduYWwgZnJvbSB0aGUgQ1JUQyBNYWluIGJsb2NrLgo+ICstIHJlZzog UGh5c2ljYWwgYmFzZSBhZGRyZXNzIGFuZCBsZW5ndGggb2YgdGhlIGNvbnRyb2xsZXIncyByZWdp c3RlcnMKPiArLSBjbG9ja3M6IGRldmljZSBjbG9ja3MKPiArICBTZWUgRG9jdW1lbnRhdGlvbi9k ZXZpY2V0cmVlL2JpbmRpbmdzL2Nsb2NrL2Nsb2NrLWJpbmRpbmdzLnR4dCBmb3IgZGV0YWlscy4K PiArLSBkZHA6IHBoYW5kbGUgb2YgZGRwIGRldmljZSB3aGljaCBjb250cm9sIGRpc3BsYXkgZGF0 YSBwYXRoLgo+ICsKPiArRXhhbXBsZToKPiArCj4gK2NydGNfbWFpbjogY3J0Y0AxNDAwYzAwMCB7 Cj4gKwljb21wYXRpYmxlID0gIm1lZGlhdGVrLG10ODE3My1jcnRjLW1haW4iOwo+ICsJaW50ZXJy dXB0cyA9IDxHSUNfU1BJIDE5NiBJUlFfVFlQRV9MRVZFTF9MT1c+OwoKU2hvdWxkIGl0IGJlIG1l bnRpb25lZCB0aGF0IHRoaXMgaXMgdGhlIGludGVycnVwdCBvZiB0aGUgc291cmNlIG9mIHRoZQpw aXBlbGluZSAoT1ZMMC8xKT8KCj4gKwlyZWcgPSA8MCAweDE0MDBjMDAwIDAgMHgxMDAwPiwJLyog T1ZMMCAqLwo+ICsJICAgICAgPDAgMHgxNDAwZTAwMCAwIDB4MTAwMD4sCS8qIFJETUEwICovCj4g KwkgICAgICA8MCAweDE0MDEzMDAwIDAgMHgxMDAwPiwJLyogQ09MT1IwICovCj4gKwkgICAgICA8 MCAweDE0MDE1MDAwIDAgMHgxMDAwPiwJLyogQUFMICovCj4gKwkgICAgICA8MCAweDE0MDFhMDAw IDAgMHgxMDAwPiwJLyogVUZPRSAqLwo+ICsJICAgICAgPDAgMHgxNDAyMzAwMCAwIDB4MTAwMD47 CS8qIE9EICovCgpXaXRoIHRoZSBhbW91bnQgb2YgcmVnaXN0ZXIgcmFuZ2VzIGFuZCBnaXZlbiB0 aGUgc3ltbWV0cnkgd2l0aCB0aGUKY2xvY2tzLCBiZXR0ZXIgdXNlIHJlZy1uYW1lcyBpbnN0ZWFk IG9mIHBvc2l0aW9uIHRvIGRldGVybWluZSB0aGUKcmVnaXN0ZXIgc3BhY2UgZm9yIGVhY2ggZnVu Y3Rpb24gYmxvY2suCgoJcmVnLW5hbWVzID0gIm92bDAiLCAicmRtYTAiLCAiY29sb3IwIiwgImFh bCIsICJ1Zm9lIiwgIm9kIjsKCj4gKwljbG9ja3MgPSA8Jm1tc3lzIE1NX0RJU1BfT1ZMMD4sCj4g KwkJIDwmbW1zeXMgTU1fRElTUF9SRE1BMD4sCj4gKwkJIDwmbW1zeXMgTU1fRElTUF9DT0xPUjA+ LAo+ICsJCSA8Jm1tc3lzIE1NX0RJU1BfQUFMPiwKPiArCQkgPCZtbXN5cyBNTV9ESVNQX1VGT0U+ LAo+ICsJCSA8Jm1tc3lzIE1NX0RJU1BfT0Q+Owo+ICsJY2xvY2stbmFtZXMgPSAib3ZsMF9kaXNw IiwKPiArCQkgICAgICAicmRtYTBfZGlzcCIsCj4gKwkJICAgICAgImNvbG9yMF9kaXNwIiwKPiAr CQkgICAgICAiYWFsX2Rpc3AiLAo+ICsJCSAgICAgICJ1Zm9lX2Rpc3AiLAo+ICsJCSAgICAgICJv ZF9kaXNwIjsKCkknZCBkcm9wIHRoZSBkaXNwIHN1ZmZpeCBmcm9tIHRoZSBjbG9jayBpbnB1dCBu YW1lcy4KCgljbG9jay1uYW1lcyA9ICJvdmwwIiwgInJkbWEwIiwgImNvbG9yMCIsICJhYWwiLCAi dWZvZSIsICJvZCI7Cgo+ICsJZGRwID0gPCZkZHA+Owo+ICt9Owo+IFwgTm8gbmV3bGluZSBhdCBl bmQgb2YgZmlsZQo+IGRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGlu Z3MvZHJtL21lZGlhdGVrL21lZGlhdGVrLGRkcC50eHQgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRy ZWUvYmluZGluZ3MvZHJtL21lZGlhdGVrL21lZGlhdGVrLGRkcC50eHQKPiBuZXcgZmlsZSBtb2Rl IDEwMDY0NAo+IGluZGV4IDAwMDAwMDAuLjc3Y2Y2MzAKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIv RG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2RybS9tZWRpYXRlay9tZWRpYXRlayxk ZHAudHh0Cj4gQEAgLTAsMCArMSwyMiBAQAo+ICtNZWRpYXRlayBERFAgRGV2aWNlCj4gKz09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09Cj4gKwo+ICtUaGUgTWVkaWF0ZWsgRERQIGRldmlj ZSBjb250cm9sIHRoZSBkaXNwbGF5IGRhdGEgcGF0aC4KClRoaXMgaXMgbm90IGEgcmVhbCBkZXZp Y2UgZWl0aGVyLiBUaGVyZSBpcyBub3RoaW5nIHdyb25nIHdpdGggaGF2aW5nIGEKZGRwIGRyaXZl ciwgYnV0IEkgZG9uJ3QgdGhpbmsgaXQgaXMgcmlnaHQgdG8gZGVzY3JpYmUgdGhpcyBkcml2ZXIg aW4gdGhlCmRldmljZSB0cmVlLiBXaGF0IHdlIHJlYWxseSBoYXZlIGhlcmUgaXMgdGhlIG11dGV4 IGZ1bmN0aW9uIGJsb2NrIGFuZApzb21lIHJlZ2lzdGVycyBpbiB0aGUgbW1zeXMgY29uZmlnIHJl Z2lvbiwgd2hpY2ggYWxyZWFkeSBjYW4gYmUgYWNjZXNzZWQKdmlhIHRoZSBtbXN5cyBzeXNjb24u CldpdGggYSBzaW5nbGUgZGlzcCBkZXZpY2Ugbm9kZSBpbmNsdWRpbmcgdGhlIG11dGV4IGFuZCBw b3dlciBkb21haW4KcGhhbmRsZSB0aGlzIG5vZGUgd291bGQgbm90IGJlIG5lY2Vzc2FyeS4KCj4g K1JlcXVpcmVkIHByb3BlcnRpZXM6Cj4gKy0gY29tcGF0aWJsZTogIm1lZGlhdGVrLDxjaGlwPi1k ZHAiCj4gKy0gcmVnOiBQaHlzaWNhbCBiYXNlIGFkZHJlc3MgYW5kIGxlbmd0aCBvZiB0aGUgY29u dHJvbGxlcidzIHJlZ2lzdGVycwo+ICstIHBvd2VyLWRvbWFpbnM6IGEgcGhhbmRsZSB0byBERFAg cG93ZXIgZG9tYWluIG5vZGUuCj4gKy0gY2xvY2tzOiBkZXZpY2UgY2xvY2tzCj4gKyAgU2VlIERv Y3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9jbG9jay9jbG9jay1iaW5kaW5ncy50eHQg Zm9yIGRldGFpbHMuCj4gKwo+ICtFeGFtcGxlOgo+ICsKPiArZGRwOiBkZHBAMTQwMDAwMDAgewo+ ICsJY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDgxNzMtZGRwIjsKPiArCXJlZyA9IDwwIDB4MTQw MDAwMDAgMCAweDEwMD4sCS8qIENPTkZJRyAqLwoKVGhpcyByZW1hcHMgcGFydCBvZiB0aGUgbW1z eXMgcmVnaXN0ZXIgc3BhY2UsIHdoaWNoIGlzIGFscmVhZHkgYSBzeXNjb24uCldoeSBub3QgdXNl IHN5c2NvbiB0byBhY2Nlc3MgaXQ/Cgo+ICsJICAgICAgPDAgMHgxNDAyMDAwMCAwIDB4MTAwMD47 CS8qIE1VVEVYICovCj4gKwlwb3dlci1kb21haW5zID0gPCZzY3BzeXMgTVQ4MTczX1BPV0VSX0RP TUFJTl9ESVM+Owo+ICsJY2xvY2tzID0gPCZtbXN5cyBNTV9NVVRFWF8zMks+Owo+ICsJY2xvY2st bmFtZXMgPSAibXV0ZXhfZGlzcCI7Cj4gK307Cj4gXCBObyBuZXdsaW5lIGF0IGVuZCBvZiBmaWxl Cj4gZGlmZiAtLWdpdCBhL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kcm0vbWVk aWF0ZWsvbWVkaWF0ZWssZHJtLnR4dCBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5n cy9kcm0vbWVkaWF0ZWsvbWVkaWF0ZWssZHJtLnR4dAo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4g aW5kZXggMDAwMDAwMC4uYzRhNTcwMgo+IC0tLSAvZGV2L251bGwKPiArKysgYi9Eb2N1bWVudGF0 aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZHJtL21lZGlhdGVrL21lZGlhdGVrLGRybS50eHQKPiBA QCAtMCwwICsxLDI3IEBACj4gK01lZGlhdGVrIERSTSBEZXZpY2UKPiArPT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT0KPiArCj4gK1RoZSBNZWRpYXRlayBEUk0gZGV2aWNlIGlzIGEgZGV2 aWNlIG5lZWRlZCB0byBsaXN0IGFsbAo+ICtkaXNwbGF5IGNvbXBvbmVudCBub2RlcyB0aGF0IGNv bXByaXNlIHRoZSBkaXNwbGF5IHN1YnN5c3RlbS4KPiArQW5kIGl0IGxpc3QgdGhlIG1lbW9yeS1y ZWxhdGVkIGludGVyZmFjZS4KCiJkcm0iIGRvZXMgbm90IGJlbG9uZyBpbiB0aGUgZGV2aWNlIHRy ZWUuIFRoZXJlIGlzIG5vICJkcm0iIGhhcmR3YXJlLgpPdGhlciBTb0NzIHVzZSB0aGUgImRpc3Bs YXktc3Vic3lzdGVtIiBuYW1lIGZvciB0aGlzIG5vZGUsIGl0IHdvdWxkIGJlCmJldHRlciB0byBm b2xsb3cgdGhhdC4KCj4gK1JlcXVpcmVkIHByb3BlcnRpZXM6Cj4gKy0gY29tcGF0aWJsZTogIm1l ZGlhdGVrLDxjaGlwPi1kcm0iCj4gKy0gbGFyYjogU2hvdWxkIGNvbnRhaW4gYSBsaXN0IG9mIHBo YW5kbGVzIHBvaW50aW5nIHRvIGxhcmIgZGV2aWNlLgo+ICsgIGxhcmIgZGVmaW5pdGlvbnMgYXMg ZGVmaW5lZCBpbgo+ICsgIERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9zb2MvbWVk aWF0ZWsvbWVkaWF0ZWssc21pLWxhcmIudHh0Cj4gKy0gaW9tbXVzOiByZXF1aXJlZCBhIGlvbW11 IG5vZGUKPiArLSBjb25uZWN0b3JzOiBTaG91bGQgY29udGFpbiBhIGxpc3Qgb2YgcGhhbmRsZXMg cG9pbnRpbmcgdG8gY29ubmVjdG9yIGRldmljZS4KPiArICBjb25uZWN0b3IgZGV2aWNlIHNob3Vs ZCBiZSBvbmUgY29tcG9uZW50IG9mIHRoaXMgbWFzdGVyLgo+ICstIGNydGNzOiBTaG91bGQgY29u dGFpbiBhIGxpc3Qgb2YgcGhhbmRsZXMgcG9pbnRpbmcgdG8gY3J0YyBkZXZpY2UuCj4gKyAgY3J0 YyBkZXZpY2Ugc2hvdWxkIGJlIG9uZSBjb21wb25lbnQgb2YgdGhpcyBtYXN0ZXIuCgoiY29ubmVj dG9ycyIgYW5kICJjcnRjcyIgYXMgdXNlZCBoZXJlIGFyZSBEUk0gY29uY2VwdHMsIG5vdCBoYXJk d2FyZQpkZXZpY2VzIHRoYXQgc2hvdWxkIGV4aXN0IGluIHRoZSBkZXZpY2UgdHJlZS4gSWRlYWxs eSB5b3Ugd291bGQgdXNlCnNvbWV0aGluZyByZWNvZ25pemFibGUgZnJvbSB0aGUgZGF0YXNoZWV0 LCBsaWtlICJzaW5rcyIgb3IgZnJvbSB0aGUKZGV2aWNlIHRyZWUsIGxpa2UgInBvcnRzIiBpZiBv Zi1ncmFwaCBiaW5kaW5ncyBhcmUgdXNlZCwgb3IganVzdAoiY29tcG9uZW50cyIgaWYgdGhpcyBh bHNvIHdlcmUgdG8gaW5jbHVkZSB0aGluZ3MgbGlrZSB0aGUgZGRwLgoKQW5vdGhlciBwb3NzaWJp bGl0eSB3b3VsZCBiZSB0byBldmVuIG1lcmdlIHRoZSAKCj4gKwo+ICtFeGFtcGxlOgo+ICsKPiAr ZHJtMDogZHJtIHsKPiArCWNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ4MTczLWRybSI7Cj4gKwls YXJiID0gPCZsYXJiMD47Cj4gKwlpb21tdXMgPSA8JmlvbW11IE00VV9QT1JUX0RJU1BfT1ZMMD47 Cj4gKwljb25uZWN0b3JzID0gPCZkc2k+Owo+ICsJY3J0Y3MgPSA8JmNydGNfbWFpbj47Cj4gK307 Cj4gXCBObyBuZXdsaW5lIGF0IGVuZCBvZiBmaWxlCj4gZGlmZiAtLWdpdCBhL0RvY3VtZW50YXRp b24vZGV2aWNldHJlZS9iaW5kaW5ncy9kcm0vbWVkaWF0ZWsvbWVkaWF0ZWssZHNpLnR4dCBiL0Rv Y3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kcm0vbWVkaWF0ZWsvbWVkaWF0ZWssZHNp LnR4dAo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAwMC4uMTZlM2ViMwo+IC0t LSAvZGV2L251bGwKPiArKysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZHJt L21lZGlhdGVrL21lZGlhdGVrLGRzaS50eHQKPiBAQCAtMCwwICsxLDIwIEBACj4gK01lZGlhdGVr IERTSSBEZXZpY2UKPiArPT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KPiArCj4gK1Ro ZSBNZWRpYXRlayBEU0kgZGV2aWNlIGlzIGEgY29ubmVjdG9yIGRldmljZSBvZiBEUk0gc3lzdGVt Lgo+ICsKPiArUmVxdWlyZWQgcHJvcGVydGllczoKPiArLSBjb21wYXRpYmxlOiAibWVkaWF0ZWss PGNoaXA+LWRzaSIKPiArLSByZWc6IFBoeXNpY2FsIGJhc2UgYWRkcmVzcyBhbmQgbGVuZ3RoIG9m IHRoZSBjb250cm9sbGVyJ3MgcmVnaXN0ZXJzCj4gKy0gY2xvY2tzOiBkZXZpY2UgY2xvY2tzCj4g KyAgU2VlIERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9jbG9jay9jbG9jay1iaW5k aW5ncy50eHQgZm9yIGRldGFpbHMuCgpXaWxsIHRoaXMgdXNlIHRoZQpEb2N1bWVudGF0aW9uL2Rl dmljZXRyZWUvYmluZGluZ3MvbWlwaS9kc2kvbWlwaS1kc2ktYnVzLnR4dApiaW5kaW5ncyB0byBj b25uZWN0IHBhbmVscyBjb250cm9sbGVkIHZpYSB0aGUgRFNJIGNvbW1hbmQgY2hhbm5lbApvciB0 aGUKRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2dyYXBoLnR4dApiaW5kaW5ncyB0 byBjb25uZWN0IHBhbmVscyBjb250cm9sbGVkIHZpYSBJMkMgb3Igb3RoZXIgY29udHJvbCBidXNl cz8KSWYgc28sIHRoaXMgc2hvdWxkIGJlIGRvY3VtZW50ZWQgaGVyZS4KCj4gK0V4YW1wbGU6Cj4g Kwo+ICtkc2k6IGRzaUAxMDIxNTAwMCB7Cj4gKwljb21wYXRpYmxlID0gIm1lZGlhdGVrLG10ODE3 My1kc2kiOwo+ICsJcmVnID0gPDAgMHgxNDAxQjAwMCAwIDB4MTAwMD4sCS8qIERTSTAgKi8KPiAr CSAgICAgIDwwIDB4MTAyMTUwMDAgMCAweDEwMDA+OyAgLyogTUlQSVRYICovCj4gKwljbG9ja3Mg PSA8Jm1tc3lzIE1NX0RTSTBfRU5HSU5FPiwJPCZtbXN5cyBNTV9EU0kwX0RJR0lUQUw+Owo+ICsJ Y2xvY2stbmFtZXMgPSAiZHNpMF9lbmdpbmVfZGlzcF9jayIsICJkc2kwX2RpZ2l0YWxfZGlzcF9j ayI7CgpNYXliZSBzaG9ydGVuIHRoZSBjbG9jayBuYW1lcyB0byAiZW5naW5lIiBhbmQgImRpZ2l0 YWwiID8KQW5kIGFkZCBhbiBleGFtcGxlIG9mIHBhbmVsIG9yIGJyaWRnZSBjb25uZWN0ZWQgdG8g dGhlIERTSSBzaW5rLgoKV2hhdCBhYm91dCBEU0kxIGFuZCB0aGUgRFBJIHNpbms/CgpiZXN0IHJl Z2FyZHMKUGhpbGlwcAoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Au b3JnCmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2 ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: p.zabel@pengutronix.de (Philipp Zabel) Date: Wed, 26 Aug 2015 18:34:35 +0200 Subject: [RFC][PATCH 1/2] dt-bindings: drm/mediatek: Add Mediatek DRM dts binding In-Reply-To: <1431530626-31493-2-git-send-email-ck.hu@mediatek.com> References: <1431530626-31493-1-git-send-email-ck.hu@mediatek.com> <1431530626-31493-2-git-send-email-ck.hu@mediatek.com> Message-ID: <1440606875.3190.103.camel@pengutronix.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, overall it looks to me like this binding is modeled after the Linux DRM abstractions. Instead, the device nodes should be modeled after the hardware. Describing each function block as a separate device node is probably not the best choice, as would be combining all devices in the mmsys range into a single device node. So a somewhat arbitrary decision has to be made what to group together. See my comments below: Am Mittwoch, den 13.05.2015, 23:23 +0800 schrieb CK Hu: > This patch includes > 1. Mediatek DRM Device binding > 2. Mediatek DSI Device binding > 3. Mediatek CRTC Main Device binding > 4. Mediatek DDP Device binding > > Signed-off-by: CK Hu > --- > .../bindings/drm/mediatek/mediatek,crtc-main.txt | 38 ++++++++++++++++++++++ > .../bindings/drm/mediatek/mediatek,ddp.txt | 22 +++++++++++++ > .../bindings/drm/mediatek/mediatek,drm.txt | 27 +++++++++++++++ > .../bindings/drm/mediatek/mediatek,dsi.txt | 20 ++++++++++++ > 4 files changed, 107 insertions(+) > create mode 100644 Documentation/devicetree/bindings/drm/mediatek/mediatek,crtc-main.txt > create mode 100644 Documentation/devicetree/bindings/drm/mediatek/mediatek,ddp.txt > create mode 100644 Documentation/devicetree/bindings/drm/mediatek/mediatek,drm.txt > create mode 100644 Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt > > diff --git a/Documentation/devicetree/bindings/drm/mediatek/mediatek,crtc-main.txt b/Documentation/devicetree/bindings/drm/mediatek/mediatek,crtc-main.txt > new file mode 100644 > index 0000000..5c6c420 > --- /dev/null > +++ b/Documentation/devicetree/bindings/drm/mediatek/mediatek,crtc-main.txt > @@ -0,0 +1,38 @@ > +Mediatek CRTC Main Device > +================================ > + > +The Mediatek CRTC Main device is a crtc device of DRM system. "crtc" does not belong in the device tree. There is no crtc hardware. What this node describes is a useful, but fixed configuration of a part of the DISP subsystem function blocks. In my opinion, it would be better to not describe the separate display pipes in the device tree at all if they are dynamically configurable. What for example if you model two separate fixed pipelines in the device tree and then in the future you want to support the MERGE or SPLIT blocks (I'm not sure what MERGE does, SPLIT seems to be needed for 8-lane DSI)? As far as I currently understand, there are five source function blocks that can read from memory (OVL0, OVL1, RDMA0, RDMA1, RDMA2) and three sink function blocks (DSI0, DSI1, DPI0) that can be connected to panels, or encoder bridges. How these map to the crtcs doesn't necessarily have to be described in the device tree. How about a single node that contains all of the DISP functional blocks that don't need their own node (like DSI, which has to be connectable to bridges or panels): disp: disp at 0x1400c000 { compatible = "mediatek,mt8173-disp"; interrupts = , /* OVL0 */ ; /* OVL1 */ interrupt-names = "ovl0", "ovl1"; reg = <0 0x1400c000 0 0x1000>, /* OVL0 */ <0 0x1400d000 0 0x1000>, /* OVL1 */ <0 0x1400e000 0 0x1000>, /* RDMA0 */ <0 0x1400f000 0 0x1000>, /* RDMA1 */ <0 0x14010000 0 0x1000>, /* RDMA2 */ <0 0x14013000 0 0x1000>, /* COLOR0 */ <0 0x14014000 0 0x1000>, /* COLOR1 */ <0 0x14015000 0 0x1000>, /* AAL */ <0 0x14016000 0 0x1000>, /* GAMMA */ <0 0x14017000 0 0x1000>, /* MERGE */ <0 0x14018000 0 0x1000>, /* SPLIT0 */ <0 0x14019000 0 0x1000>, /* SPLIT1 */ <0 0x1401a000 0 0x1000>, /* UFOE */ <0 0x14020000 0 0x1000>; /* MUTEX */ <0 0x14023000 0 0x1000>; /* OD */ reg-names = "ovl0", "ovl1", "rdma0", "rdma1", "rdma2", "color0", "color1", "aal", "gamma", "merge", "split0", "split1", "ufoe", "mutex", "od"; clocks = <&mmsys CLK_MM_DISP_OVL0>, <&mmsys CLK_MM_DISP_OVL1>, <&mmsys CLK_MM_DISP_RDMA0>, <&mmsys CLK_MM_DISP_RDMA1>, <&mmsys CLK_MM_DISP_RDMA2>, <&mmsys CLK_MM_DISP_COLOR0>, <&mmsys CLK_MM_DISP_COLOR1>, <&mmsys CLK_MM_DISP_AAL>, <&mmsys CLK_MM_DISP_GAMMA>, <&mmsys CLK_MM_DISP_MERGE>, <&mmsys CLK_MM_DISP_SPLIT0>, <&mmsys CLK_MM_DISP_SPLIT1>, <&mmsys CLK_MM_DISP_UFOE>, <&mmsys CLK_MM_MUTEX_32K>, <&mmsys CLK_MM_DISP_OD>; clock-names = "ovl0", "ovl1", "rdma0", "rdma1", "rdma2", "color0", "color1", "aal", "gamma", "merge", "split0", "split1", "ufoe", "mutex", "od"; power-domains = <&scpsys MT8173_POWER_DOMAIN_DIS>; config = <&mmsys>; /* syscon */ }; How the muxes in the config area are set up to connect those blocks could be determined by the driver. > +Required properties: > +- compatible: "mediatek,-crtc-main" > +- interrupts: The interrupt signal from the CRTC Main block. > +- reg: Physical base address and length of the controller's registers > +- clocks: device clocks > + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. > +- ddp: phandle of ddp device which control display data path. > + > +Example: > + > +crtc_main: crtc at 1400c000 { > + compatible = "mediatek,mt8173-crtc-main"; > + interrupts = ; Should it be mentioned that this is the interrupt of the source of the pipeline (OVL0/1)? > + reg = <0 0x1400c000 0 0x1000>, /* OVL0 */ > + <0 0x1400e000 0 0x1000>, /* RDMA0 */ > + <0 0x14013000 0 0x1000>, /* COLOR0 */ > + <0 0x14015000 0 0x1000>, /* AAL */ > + <0 0x1401a000 0 0x1000>, /* UFOE */ > + <0 0x14023000 0 0x1000>; /* OD */ With the amount of register ranges and given the symmetry with the clocks, better use reg-names instead of position to determine the register space for each function block. reg-names = "ovl0", "rdma0", "color0", "aal", "ufoe", "od"; > + clocks = <&mmsys MM_DISP_OVL0>, > + <&mmsys MM_DISP_RDMA0>, > + <&mmsys MM_DISP_COLOR0>, > + <&mmsys MM_DISP_AAL>, > + <&mmsys MM_DISP_UFOE>, > + <&mmsys MM_DISP_OD>; > + clock-names = "ovl0_disp", > + "rdma0_disp", > + "color0_disp", > + "aal_disp", > + "ufoe_disp", > + "od_disp"; I'd drop the disp suffix from the clock input names. clock-names = "ovl0", "rdma0", "color0", "aal", "ufoe", "od"; > + ddp = <&ddp>; > +}; > \ No newline at end of file > diff --git a/Documentation/devicetree/bindings/drm/mediatek/mediatek,ddp.txt b/Documentation/devicetree/bindings/drm/mediatek/mediatek,ddp.txt > new file mode 100644 > index 0000000..77cf630 > --- /dev/null > +++ b/Documentation/devicetree/bindings/drm/mediatek/mediatek,ddp.txt > @@ -0,0 +1,22 @@ > +Mediatek DDP Device > +================================ > + > +The Mediatek DDP device control the display data path. This is not a real device either. There is nothing wrong with having a ddp driver, but I don't think it is right to describe this driver in the device tree. What we really have here is the mutex function block and some registers in the mmsys config region, which already can be accessed via the mmsys syscon. With a single disp device node including the mutex and power domain phandle this node would not be necessary. > +Required properties: > +- compatible: "mediatek,-ddp" > +- reg: Physical base address and length of the controller's registers > +- power-domains: a phandle to DDP power domain node. > +- clocks: device clocks > + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. > + > +Example: > + > +ddp: ddp at 14000000 { > + compatible = "mediatek,mt8173-ddp"; > + reg = <0 0x14000000 0 0x100>, /* CONFIG */ This remaps part of the mmsys register space, which is already a syscon. Why not use syscon to access it? > + <0 0x14020000 0 0x1000>; /* MUTEX */ > + power-domains = <&scpsys MT8173_POWER_DOMAIN_DIS>; > + clocks = <&mmsys MM_MUTEX_32K>; > + clock-names = "mutex_disp"; > +}; > \ No newline at end of file > diff --git a/Documentation/devicetree/bindings/drm/mediatek/mediatek,drm.txt b/Documentation/devicetree/bindings/drm/mediatek/mediatek,drm.txt > new file mode 100644 > index 0000000..c4a5702 > --- /dev/null > +++ b/Documentation/devicetree/bindings/drm/mediatek/mediatek,drm.txt > @@ -0,0 +1,27 @@ > +Mediatek DRM Device > +================================ > + > +The Mediatek DRM device is a device needed to list all > +display component nodes that comprise the display subsystem. > +And it list the memory-related interface. "drm" does not belong in the device tree. There is no "drm" hardware. Other SoCs use the "display-subsystem" name for this node, it would be better to follow that. > +Required properties: > +- compatible: "mediatek,-drm" > +- larb: Should contain a list of phandles pointing to larb device. > + larb definitions as defined in > + Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt > +- iommus: required a iommu node > +- connectors: Should contain a list of phandles pointing to connector device. > + connector device should be one component of this master. > +- crtcs: Should contain a list of phandles pointing to crtc device. > + crtc device should be one component of this master. "connectors" and "crtcs" as used here are DRM concepts, not hardware devices that should exist in the device tree. Ideally you would use something recognizable from the datasheet, like "sinks" or from the device tree, like "ports" if of-graph bindings are used, or just "components" if this also were to include things like the ddp. Another possibility would be to even merge the > + > +Example: > + > +drm0: drm { > + compatible = "mediatek,mt8173-drm"; > + larb = <&larb0>; > + iommus = <&iommu M4U_PORT_DISP_OVL0>; > + connectors = <&dsi>; > + crtcs = <&crtc_main>; > +}; > \ No newline at end of file > diff --git a/Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt > new file mode 100644 > index 0000000..16e3eb3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/drm/mediatek/mediatek,dsi.txt > @@ -0,0 +1,20 @@ > +Mediatek DSI Device > +================================ > + > +The Mediatek DSI device is a connector device of DRM system. > + > +Required properties: > +- compatible: "mediatek,-dsi" > +- reg: Physical base address and length of the controller's registers > +- clocks: device clocks > + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. Will this use the Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt bindings to connect panels controlled via the DSI command channel or the Documentation/devicetree/bindings/graph.txt bindings to connect panels controlled via I2C or other control buses? If so, this should be documented here. > +Example: > + > +dsi: dsi at 10215000 { > + compatible = "mediatek,mt8173-dsi"; > + reg = <0 0x1401B000 0 0x1000>, /* DSI0 */ > + <0 0x10215000 0 0x1000>; /* MIPITX */ > + clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>; > + clock-names = "dsi0_engine_disp_ck", "dsi0_digital_disp_ck"; Maybe shorten the clock names to "engine" and "digital" ? And add an example of panel or bridge connected to the DSI sink. What about DSI1 and the DPI sink? best regards Philipp