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* [PATCH v4 0/16] Add Analogix Core Display Port Driver
@ 2015-09-01  5:46 ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:46 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Hi all,

   The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
controller, so I decide to name dp core driver with "analogix" which I
find in rk3288 eDP TRM ;)

Beyond that, there are three light registers setting differents bewteen
exynos and rk3288.
1. RK3288 have five special pll resigters which not indicata in exynos
   dp controller.
2. The address of DP_PHY_PD(dp phy power manager register) are different
   between rk3288 and exynos.
3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
   register).

I have verified this series on two kinds of rockchip platform board, one
is rk3288 sdk board which connect with a 2K display port monitor, the other
is google jerry chromebook which connect with a eDP screen "cnm,n116bgeea2",
both of them works rightlly.

I haven't verified the dp function on samsung platform, cause I haven't got
exynos boards. I can only ensure that there are no build error on samsung
platform, wish some samsung guys help to test. ;)

Besides, The v4 version have been rebased on linux-next master branch
(git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git), tag name is
next-20150828 (latest is next-2015-0831). So I think if someone try to apply
this series, there would be no conflict  ;)

Thanks,
- Yakir

Changes in v4:
- Take Romain suggest, rebase on linux-next branch.
- Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
- Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
- Take Archit suggest, create a separate folder for analogix code in bridge/
- Take Jingoo Han suggest, update commit message more readable.
- Adjust the order from 05 to 04
- Take Krzysztof suggest, provide backword compatibility with samsung.
- Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.
- Take Krzysztof suggest, split all DTS changes, and provide backward compatibility.
  Mark old properties as deprecated but still support them.
- Take Rob suggest, update "analogix,hpd-gpio" to "hpd-gpios" prop name.
- Take Thierry suggest, deprecated some properties which could parsed from Edid/Mode/DPCD.
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"
- Take Krzysztof suggest, separate all DTS changes to a separate patch.
- Remove some deprecated DT properties in rockchip dp document.
- Take Kishon suggest, add commit message, and remove the redundant
  rockchip_dp_phy_init() function, move those code to probe() method.
  And remove driver .owner number.
- Take Thierry suggest, seprate the link-rate and lane-count limit
  out with the device_type flag.
- Take Jingoo suggest, add commit messages.
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Take Thierry Reding suggest, move exynos's video_timing code
  to analogix_dp-exynos platform driver, add get_modes method
  to struct analogix_dp_plat_data.
- Take Heiko suggest, rename some "samsung*" dts propery to "analogix*".
- Take Thierry Reding suggest, link_rate and lane_count shouldn't config to
  the DT property value directly, but we can take those as hardware limite.
  For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lane,
  so DT property would like "link-rate = 0x0a" "lane-count = 4".
- Take Thierry Reding suggest, dynamic parse video timing info from
  struct drm_display_mode and struct drm_display_info.
- Take Heiko suggest, add devicetree binding documents.
- Take Thierry Reding suggest, remove sync pol & colorimetry properies
  from the new analogix dp driver devicetree binding.
- Update the exist exynos dtsi file with the latest DP DT properies.
- Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
  dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
  core driver which name to "dp", and leave "pclk_edp" to rockchip dp platform
  driver which name to "pclk".
- Take Heiko suggest, add devicetree binding document.
- Take Heiko suggest, remove "rockchip,panel" DT property, take use of remote
  point to get panel node.
- Add the new function point analogix_dp_platdata.get_modes init.
- Take Heiko suggest, add rockchip dp phy driver,
  collect the phy clocks and power control.
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.
- move dp hpd detect to connector detect function.
- Add edid modes parse support

Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
  avoid using some uncommon style like bellow:
  -  retval = exynos_dp_read_bytes_from_i2c(...
				...)
  +  retval =
  +  exynos_dp_read_bytes_from_i2c(......);
- Take Jingoo Han suggest, just remove my name from author list.
- Take Jingoo Han suggest, remove new copyright
- Fix compiled failed dut to analogix_dp_device misspell
- Take Heiko suggest, get panel node with remote-endpoint method,
  and create devicetree binding for driver.
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.
- Add GNU license v2 declared and samsung copyright
- Fix compile failed dut to phy_pd_addr variable misspell error

Mark Yao (1):
  drm: rockchip: add bpc and color mode setting

Yakir Yang (15):
  drm: exynos/dp: fix code style
  drm: exynos/dp: convert to drm bridge mode
  drm: bridge: analogix/dp: split exynos dp driver to bridge dir
  drm: bridge: analogix/dp: remove duplicate configuration of link rate
    and link count
  drm: bridge: analogix/dp: dynamic parse sync_pol & interlace &
    colorimetry
  Documentation: drm/bridge: add document for analogix_dp
  ARM: dts: exynos/dp: remove some properties that deprecated by
    analogix_dp driver
  drm: rockchip/dp: add rockchip platform dp driver
  phy: Add driver for rockchip Display Port PHY
  drm: bridge: analogix/dp: add platform device type support
  drm: bridge: analogix/dp: add some rk3288 special registers setting
  drm: bridge: analogix/dp: add max link rate and lane count limit for
    RK3288
  drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  drm: bridge: analogix/dp: move hpd detect to connector detect function
  drm: bridge: analogix/dp: add edid modes parse in get_modes method

 .../devicetree/bindings/drm/bridge/analogix_dp.txt |   52 +
 .../devicetree/bindings/phy/rockchip-dp-phy.txt    |   26 +
 .../bindings/video/analogix_dp-rockchip.txt        |   75 +
 .../devicetree/bindings/video/exynos_dp.txt        |   64 +-
 arch/arm/boot/dts/exynos5250-arndale.dts           |    2 -
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 -
 arch/arm/boot/dts/exynos5250-snow.dts              |    4 +-
 arch/arm/boot/dts/exynos5250-spring.dts            |    4 +-
 arch/arm/boot/dts/exynos5420-peach-pit.dts         |    4 +-
 arch/arm/boot/dts/exynos5420-smdk5420.dts          |    2 -
 arch/arm/boot/dts/exynos5800-peach-pi.dts          |    4 +-
 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1409 +++++++++++++++++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  286 ++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1294 ++++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  270 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  355 +++++
 drivers/gpu/drm/exynos/exynos_dp_core.c            | 1427 --------------------
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  281 ----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 -----------------
 drivers/gpu/drm/rockchip/Kconfig                   |    9 +
 drivers/gpu/drm/rockchip/Makefile                  |    1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    |  416 ++++++
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c        |    2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h        |    2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c        |   33 +-
 drivers/phy/Kconfig                                |    7 +
 drivers/phy/Makefile                               |    1 +
 drivers/phy/phy-rockchip-dp.c                      |  166 +++
 include/drm/bridge/analogix_dp.h                   |   40 +
 35 files changed, 4347 insertions(+), 3167 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (62%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 create mode 100644 drivers/phy/phy-rockchip-dp.c
 create mode 100644 include/drm/bridge/analogix_dp.h

-- 
2.1.2



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 0/16] Add Analogix Core Display Port Driver
@ 2015-09-01  5:46 ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:46 UTC (permalink / raw)
  To: linux-arm-kernel

Hi all,

   The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
controller, so I decide to name dp core driver with "analogix" which I
find in rk3288 eDP TRM ;)

Beyond that, there are three light registers setting differents bewteen
exynos and rk3288.
1. RK3288 have five special pll resigters which not indicata in exynos
   dp controller.
2. The address of DP_PHY_PD(dp phy power manager register) are different
   between rk3288 and exynos.
3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
   register).

I have verified this series on two kinds of rockchip platform board, one
is rk3288 sdk board which connect with a 2K display port monitor, the other
is google jerry chromebook which connect with a eDP screen "cnm,n116bgeea2",
both of them works rightlly.

I haven't verified the dp function on samsung platform, cause I haven't got
exynos boards. I can only ensure that there are no build error on samsung
platform, wish some samsung guys help to test. ;)

Besides, The v4 version have been rebased on linux-next master branch
(git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git), tag name is
next-20150828 (latest is next-2015-0831). So I think if someone try to apply
this series, there would be no conflict  ;)

Thanks,
- Yakir

Changes in v4:
- Take Romain suggest, rebase on linux-next branch.
- Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
- Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
- Take Archit suggest, create a separate folder for analogix code in bridge/
- Take Jingoo Han suggest, update commit message more readable.
- Adjust the order from 05 to 04
- Take Krzysztof suggest, provide backword compatibility with samsung.
- Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.
- Take Krzysztof suggest, split all DTS changes, and provide backward compatibility.
  Mark old properties as deprecated but still support them.
- Take Rob suggest, update "analogix,hpd-gpio" to "hpd-gpios" prop name.
- Take Thierry suggest, deprecated some properties which could parsed from Edid/Mode/DPCD.
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"
- Take Krzysztof suggest, separate all DTS changes to a separate patch.
- Remove some deprecated DT properties in rockchip dp document.
- Take Kishon suggest, add commit message, and remove the redundant
  rockchip_dp_phy_init() function, move those code to probe() method.
  And remove driver .owner number.
- Take Thierry suggest, seprate the link-rate and lane-count limit
  out with the device_type flag.
- Take Jingoo suggest, add commit messages.
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Take Thierry Reding suggest, move exynos's video_timing code
  to analogix_dp-exynos platform driver, add get_modes method
  to struct analogix_dp_plat_data.
- Take Heiko suggest, rename some "samsung*" dts propery to "analogix*".
- Take Thierry Reding suggest, link_rate and lane_count shouldn't config to
  the DT property value directly, but we can take those as hardware limite.
  For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lane,
  so DT property would like "link-rate = 0x0a" "lane-count = 4".
- Take Thierry Reding suggest, dynamic parse video timing info from
  struct drm_display_mode and struct drm_display_info.
- Take Heiko suggest, add devicetree binding documents.
- Take Thierry Reding suggest, remove sync pol & colorimetry properies
  from the new analogix dp driver devicetree binding.
- Update the exist exynos dtsi file with the latest DP DT properies.
- Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
  dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
  core driver which name to "dp", and leave "pclk_edp" to rockchip dp platform
  driver which name to "pclk".
- Take Heiko suggest, add devicetree binding document.
- Take Heiko suggest, remove "rockchip,panel" DT property, take use of remote
  point to get panel node.
- Add the new function point analogix_dp_platdata.get_modes init.
- Take Heiko suggest, add rockchip dp phy driver,
  collect the phy clocks and power control.
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.
- move dp hpd detect to connector detect function.
- Add edid modes parse support

Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
  avoid using some uncommon style like bellow:
  -  retval = exynos_dp_read_bytes_from_i2c(...
				...)
  +  retval =
  +  exynos_dp_read_bytes_from_i2c(......);
- Take Jingoo Han suggest, just remove my name from author list.
- Take Jingoo Han suggest, remove new copyright
- Fix compiled failed dut to analogix_dp_device misspell
- Take Heiko suggest, get panel node with remote-endpoint method,
  and create devicetree binding for driver.
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.
- Add GNU license v2 declared and samsung copyright
- Fix compile failed dut to phy_pd_addr variable misspell error

Mark Yao (1):
  drm: rockchip: add bpc and color mode setting

Yakir Yang (15):
  drm: exynos/dp: fix code style
  drm: exynos/dp: convert to drm bridge mode
  drm: bridge: analogix/dp: split exynos dp driver to bridge dir
  drm: bridge: analogix/dp: remove duplicate configuration of link rate
    and link count
  drm: bridge: analogix/dp: dynamic parse sync_pol & interlace &
    colorimetry
  Documentation: drm/bridge: add document for analogix_dp
  ARM: dts: exynos/dp: remove some properties that deprecated by
    analogix_dp driver
  drm: rockchip/dp: add rockchip platform dp driver
  phy: Add driver for rockchip Display Port PHY
  drm: bridge: analogix/dp: add platform device type support
  drm: bridge: analogix/dp: add some rk3288 special registers setting
  drm: bridge: analogix/dp: add max link rate and lane count limit for
    RK3288
  drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  drm: bridge: analogix/dp: move hpd detect to connector detect function
  drm: bridge: analogix/dp: add edid modes parse in get_modes method

 .../devicetree/bindings/drm/bridge/analogix_dp.txt |   52 +
 .../devicetree/bindings/phy/rockchip-dp-phy.txt    |   26 +
 .../bindings/video/analogix_dp-rockchip.txt        |   75 +
 .../devicetree/bindings/video/exynos_dp.txt        |   64 +-
 arch/arm/boot/dts/exynos5250-arndale.dts           |    2 -
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 -
 arch/arm/boot/dts/exynos5250-snow.dts              |    4 +-
 arch/arm/boot/dts/exynos5250-spring.dts            |    4 +-
 arch/arm/boot/dts/exynos5420-peach-pit.dts         |    4 +-
 arch/arm/boot/dts/exynos5420-smdk5420.dts          |    2 -
 arch/arm/boot/dts/exynos5800-peach-pi.dts          |    4 +-
 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1409 +++++++++++++++++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  286 ++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1294 ++++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  270 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  355 +++++
 drivers/gpu/drm/exynos/exynos_dp_core.c            | 1427 --------------------
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  281 ----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 -----------------
 drivers/gpu/drm/rockchip/Kconfig                   |    9 +
 drivers/gpu/drm/rockchip/Makefile                  |    1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    |  416 ++++++
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c        |    2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h        |    2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c        |   33 +-
 drivers/phy/Kconfig                                |    7 +
 drivers/phy/Makefile                               |    1 +
 drivers/phy/phy-rockchip-dp.c                      |  166 +++
 include/drm/bridge/analogix_dp.h                   |   40 +
 35 files changed, 4347 insertions(+), 3167 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (62%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 create mode 100644 drivers/phy/phy-rockchip-dp.c
 create mode 100644 include/drm/bridge/analogix_dp.h

-- 
2.1.2

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 01/16] drm: exynos/dp: fix code style
  2015-09-01  5:46 ` Yakir Yang
@ 2015-09-01  5:46   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:46 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.

- Take Romain suggest, rebase on linux-next branch

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
  avoid using some uncommon style like bellow:
  -  retval = exynos_dp_read_bytes_from_i2c(...
				...)
  +  retval =
  +  exynos_dp_read_bytes_from_i2c(......);

 drivers/gpu/drm/exynos/exynos_dp_core.c | 226 ++++++++++++++++----------------
 drivers/gpu/drm/exynos/exynos_dp_core.h |  54 ++++----
 drivers/gpu/drm/exynos/exynos_dp_reg.c  | 106 +++++++--------
 3 files changed, 188 insertions(+), 198 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index d66ade0..266f7f7 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -115,8 +115,8 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
 	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-				EDID_EXTENSION_FLAG,
-				&extend_block);
+					      EDID_EXTENSION_FLAG,
+					      &extend_block);
 	if (retval)
 		return retval;
 
@@ -124,10 +124,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-						EDID_HEADER_PATTERN,
-						EDID_BLOCK_LENGTH,
-						&edid[EDID_HEADER_PATTERN]);
+		retval = exynos_dp_read_bytes_from_i2c(
+					dp, I2C_EDID_DEVICE_ADDR,
+					EDID_HEADER_PATTERN,
+					EDID_BLOCK_LENGTH,
+					&edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -139,11 +140,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_BLOCK_LENGTH,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_BLOCK_LENGTH]);
+		retval = exynos_dp_read_bytes_from_i2c(
+					dp, I2C_EDID_DEVICE_ADDR,
+					EDID_BLOCK_LENGTH,
+					EDID_BLOCK_LENGTH,
+					&edid[EDID_BLOCK_LENGTH]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		}
 
 		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					&test_vector);
+					      &test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
+			exynos_dp_write_byte_to_dpcd(
+				dp, DP_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
+			exynos_dp_write_byte_to_dpcd(
+				dp, DP_TEST_RESPONSE,
 				DP_TEST_EDID_CHECKSUM_WRITE);
 		}
 	} else {
 		dev_info(dp->dev, "EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_HEADER_PATTERN,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_HEADER_PATTERN]);
+		retval = exynos_dp_read_bytes_from_i2c(
+				dp, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
+				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -183,16 +182,15 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp,
-			DP_TEST_REQUEST,
-			&test_vector);
+		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+					      &test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
+			exynos_dp_write_byte_to_dpcd(
+					dp, DP_TEST_EDID_CHECKSUM,
+					edid[EDID_CHECKSUM]);
+			exynos_dp_write_byte_to_dpcd(
+					dp, DP_TEST_RESPONSE,
+					DP_TEST_EDID_CHECKSUM_WRITE);
 		}
 	}
 
@@ -207,8 +205,7 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
-				12, buf);
+	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
 	if (retval)
 		return retval;
 
@@ -223,7 +220,7 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 }
 
 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
-						bool enable)
+						 bool enable)
 {
 	u8 data;
 
@@ -231,11 +228,11 @@ static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
 
 	if (enable)
 		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DP_LANE_COUNT_ENHANCED_FRAME_EN |
-			DPCD_LANE_COUNT_SET(data));
+					     DP_LANE_COUNT_ENHANCED_FRAME_EN |
+					     DPCD_LANE_COUNT_SET(data));
 	else
 		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DPCD_LANE_COUNT_SET(data));
+					     DPCD_LANE_COUNT_SET(data));
 }
 
 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
@@ -262,13 +259,12 @@ static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
 {
 	exynos_dp_set_training_pattern(dp, DP_NONE);
 
-	exynos_dp_write_byte_to_dpcd(dp,
-		DP_TRAINING_PATTERN_SET,
-		DP_TRAINING_PATTERN_DISABLE);
+	exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+				     DP_TRAINING_PATTERN_DISABLE);
 }
 
 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
-					int pre_emphasis, int lane)
+						 int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -308,15 +304,14 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
-				2, buf);
+	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
 	if (retval)
 		return retval;
 
 	/* Set TX pre-emphasis to minimum */
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_lane_pre_emphasis(dp,
-			PRE_EMPHASIS_LEVEL_0, lane);
+		exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0,
+						     lane);
 
 	/* Wait for PLL lock */
 	pll_tries = 0;
@@ -334,9 +329,9 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
 
 	/* Set RX training pattern */
-	retval = exynos_dp_write_byte_to_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
+	retval = exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+					      DP_LINK_SCRAMBLING_DISABLE |
+					      DP_TRAINING_PATTERN_1);
 	if (retval)
 		return retval;
 
@@ -345,7 +340,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
 	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, buf);
+					       lane_count, buf);
 
 	return retval;
 }
@@ -353,7 +348,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = link_status[lane>>1];
+	u8 link_value = link_status[lane >> 1];
 
 	return (link_value >> shift) & 0xf;
 }
@@ -372,7 +367,7 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 }
 
 static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				int lane_count)
+				   int lane_count)
 {
 	int lane;
 	u8 lane_status;
@@ -391,10 +386,10 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 }
 
 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							int lane)
+							  int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return (link_value >> shift) & 0x3;
 }
@@ -404,13 +399,13 @@ static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 					int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
-					u8 training_lane_set, int lane)
+					     u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -430,9 +425,8 @@ static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
 	}
 }
 
-static unsigned int exynos_dp_get_lane_link_training(
-				struct exynos_dp_device *dp,
-				int lane)
+static unsigned int
+exynos_dp_get_lane_link_training(struct exynos_dp_device *dp, int lane)
 {
 	u32 reg;
 
@@ -466,7 +460,7 @@ static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
 }
 
 static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
-					u8 adjust_request[2])
+					       u8 adjust_request[2])
 {
 	int lane, lane_count;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -499,13 +493,13 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
-			DP_LANE0_1_STATUS, 2, link_status);
+	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
+						 2, link_status);
 	if (retval)
 		return retval;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
-			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
+	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
+						 2, adjust_request);
 	if (retval)
 		return retval;
 
@@ -513,8 +507,8 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 		/* set training pattern 2 for EQ */
 		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
 
-		retval = exynos_dp_write_byte_to_dpcd(dp,
-				DP_TRAINING_PATTERN_SET,
+		retval = exynos_dp_write_byte_to_dpcd(
+				dp, DP_TRAINING_PATTERN_SET,
 				DP_LINK_SCRAMBLING_DISABLE |
 				DP_TRAINING_PATTERN_2);
 		if (retval)
@@ -552,11 +546,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 	exynos_dp_get_adjust_training_lane(dp, adjust_request);
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
-			dp->link_train.training_lane[lane], lane);
+		exynos_dp_set_lane_link_training(
+				dp, dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp,
-			DP_TRAINING_LANE0_SET, lane_count,
+	retval = exynos_dp_write_bytes_to_dpcd(
+			dp, DP_TRAINING_LANE0_SET, lane_count,
 			dp->link_train.training_lane);
 	if (retval)
 		return retval;
@@ -574,8 +568,8 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
-			DP_LANE0_1_STATUS, 2, link_status);
+	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
+						2, link_status);
 	if (retval)
 		return retval;
 
@@ -584,13 +578,13 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 		return -EIO;
 	}
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
-			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
+	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
+						2, adjust_request);
 	if (retval)
 		return retval;
 
-	retval = exynos_dp_read_byte_from_dpcd(dp,
-			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
+	retval = exynos_dp_read_byte_from_dpcd(dp, DP_LANE_ALIGN_STATUS_UPDATED,
+					       &link_align);
 	if (retval)
 		return retval;
 
@@ -629,17 +623,18 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 	}
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
-			dp->link_train.training_lane[lane], lane);
+		exynos_dp_set_lane_link_training(
+				dp, dp->link_train.training_lane[lane], lane);
 
 	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, dp->link_train.training_lane);
+					       lane_count,
+					       dp->link_train.training_lane);
 
 	return retval;
 }
 
 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
-					u8 *bandwidth)
+					   u8 *bandwidth)
 {
 	u8 data;
 
@@ -652,7 +647,7 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 }
 
 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
-					u8 *lane_count)
+					    u8 *lane_count)
 {
 	u8 data;
 
@@ -665,8 +660,8 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 }
 
 static void exynos_dp_init_training(struct exynos_dp_device *dp,
-			enum link_lane_count_type max_lane,
-			enum link_rate_type max_rate)
+				    enum link_lane_count_type max_lane,
+				    enum link_rate_type max_rate)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
@@ -679,7 +674,7 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
 	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -739,8 +734,7 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 }
 
 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
-				u32 count,
-				u32 bwtype)
+				    u32 count, u32 bwtype)
 {
 	int i;
 	int retval;
@@ -828,21 +822,19 @@ static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
 	if (enable) {
 		exynos_dp_enable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
+		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+					      &data);
+		exynos_dp_write_byte_to_dpcd(
+				dp, DP_TRAINING_PATTERN_SET,
+				(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
 		exynos_dp_disable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
+		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+					      &data);
+		exynos_dp_write_byte_to_dpcd(
+				dp, DP_TRAINING_PATTERN_SET,
+				(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 	}
 }
 
@@ -913,7 +905,7 @@ static void exynos_dp_commit(struct drm_encoder *encoder)
 	}
 
 	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
-					dp->video_info->link_rate);
+				       dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -941,8 +933,8 @@ static void exynos_dp_commit(struct drm_encoder *encoder)
 	exynos_dp_start_video(dp);
 }
 
-static enum drm_connector_status exynos_dp_detect(
-				struct drm_connector *connector, bool force)
+static enum drm_connector_status
+exynos_dp_detect(struct drm_connector *connector, bool force)
 {
 	return connector_status_connected;
 }
@@ -990,8 +982,8 @@ static int exynos_dp_get_modes(struct drm_connector *connector)
 	return 1;
 }
 
-static struct drm_encoder *exynos_dp_best_encoder(
-			struct drm_connector *connector)
+static struct drm_encoder *
+exynos_dp_best_encoder(struct drm_connector *connector)
 {
 	struct exynos_dp_device *dp = ctx_from_connector(connector);
 
@@ -1005,7 +997,7 @@ static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
 
 /* returns the number of bridges attached */
 static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
-		struct drm_encoder *encoder)
+					struct drm_encoder *encoder)
 {
 	int ret;
 
@@ -1036,7 +1028,8 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	connector->polled = DRM_CONNECTOR_POLL_HPD;
 
 	ret = drm_connector_init(dp->drm_dev, connector,
-			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
+				 &exynos_dp_connector_funcs,
+				 DRM_MODE_CONNECTOR_eDP);
 	if (ret) {
 		DRM_ERROR("Failed to initialize connector with drm\n");
 		return ret;
@@ -1139,8 +1132,8 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
 
-	dp_video_config = devm_kzalloc(dev,
-				sizeof(*dp_video_config), GFP_KERNEL);
+	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
+				       GFP_KERNEL);
 	if (!dp_video_config)
 		return ERR_PTR(-ENOMEM);
 
@@ -1154,37 +1147,37 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
 		of_property_read_bool(dp_node, "interlaced");
 
 	if (of_property_read_u32(dp_node, "samsung,color-space",
-				&dp_video_config->color_space)) {
+				 &dp_video_config->color_space)) {
 		dev_err(dev, "failed to get color-space\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				&dp_video_config->dynamic_range)) {
+				 &dp_video_config->dynamic_range)) {
 		dev_err(dev, "failed to get dynamic-range\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				&dp_video_config->ycbcr_coeff)) {
+				 &dp_video_config->ycbcr_coeff)) {
 		dev_err(dev, "failed to get ycbcr-coeff\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				&dp_video_config->color_depth)) {
+				 &dp_video_config->color_depth)) {
 		dev_err(dev, "failed to get color-depth\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				&dp_video_config->link_rate)) {
+				 &dp_video_config->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				&dp_video_config->lane_count)) {
+				 &dp_video_config->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
 		return ERR_PTR(-EINVAL);
 	}
@@ -1197,7 +1190,7 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
 	int ret;
 
 	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
-			OF_USE_NATIVE_MODE);
+			       OF_USE_NATIVE_MODE);
 	if (ret) {
 		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
 		return ret;
@@ -1294,7 +1287,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	exynos_dp_init_dp(dp);
 
 	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
-			irq_flags, "exynos-dp", dp);
+			       irq_flags, "exynos-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		return ret;
@@ -1328,7 +1321,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 }
 
 static void exynos_dp_unbind(struct device *dev, struct device *master,
-				void *data)
+			     void *data)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
 
@@ -1347,7 +1340,7 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	struct exynos_dp_device *dp;
 
 	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
-				GFP_KERNEL);
+			  GFP_KERNEL);
 	if (!dp)
 		return -ENOMEM;
 
@@ -1369,8 +1362,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
 			of_node_put(bridge_node);
 			if (!dp->bridge)
 				return -EPROBE_DEFER;
-		} else
+		} else {
 			return -EPROBE_DEFER;
+		}
 	}
 
 	return component_add(&pdev->dev, &exynos_dp_ops);
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
index e413b6f..71f2b86 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
@@ -179,8 +179,8 @@ void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable);
+				     enum analog_power_block block,
+				     bool enable);
 void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
 void exynos_dp_init_hpd(struct exynos_dp_device *dp);
 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
@@ -191,50 +191,50 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
+				 unsigned int reg_addr,
+				 unsigned char data);
 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
+				  unsigned int reg_addr,
+				  unsigned char *data);
 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				  unsigned int reg_addr,
+				  unsigned int count,
+				  unsigned char data[]);
 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				   unsigned int reg_addr,
+				   unsigned int count,
+				   unsigned char data[]);
 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 				unsigned int device_addr,
 				unsigned int reg_addr);
 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
+				 unsigned int device_addr,
+				 unsigned int reg_addr,
+				 unsigned int *data);
 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
+				  unsigned int device_addr,
+				  unsigned int reg_addr,
+				  unsigned int count,
+				  unsigned char edid[]);
 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern);
+				    enum pattern_set pattern);
 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
+				       u32 training_lane);
 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
+				       u32 training_lane);
 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
+				       u32 training_lane);
 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
+				       u32 training_lane);
 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
@@ -245,9 +245,9 @@ void exynos_dp_init_video(struct exynos_dp_device *dp);
 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
+			       enum clock_recovery_m_value_type type,
+			       u32 m_value,
+			       u32 n_value);
 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
 void exynos_dp_start_video(struct exynos_dp_device *dp);
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
index c1f87a2..5aff19a 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_reg.c
@@ -202,8 +202,8 @@ void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
 }
 
 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
+				     enum analog_power_block block,
+				     bool enable)
 {
 	u32 reg;
 
@@ -399,8 +399,8 @@ void exynos_dp_init_aux(struct exynos_dp_device *dp)
 	exynos_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
+	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
@@ -483,8 +483,8 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
 }
 
 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
+				 unsigned int reg_addr,
+				 unsigned char data)
 {
 	u32 reg;
 	int i;
@@ -519,17 +519,16 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
 		retval = exynos_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	return retval;
 }
 
 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
+				  unsigned int reg_addr,
+				  unsigned char *data)
 {
 	u32 reg;
 	int i;
@@ -560,9 +559,8 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 		retval = exynos_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data buffer */
@@ -573,9 +571,9 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 }
 
 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				  unsigned int reg_addr,
+				  unsigned int count,
+				  unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -625,9 +623,9 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 			retval = exynos_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		start_offset += cur_data_count;
@@ -637,9 +635,9 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 }
 
 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				   unsigned int reg_addr,
+				   unsigned int count,
+				   unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -683,9 +681,9 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
 			retval = exynos_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
@@ -736,9 +734,9 @@ int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 }
 
 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
+				 unsigned int device_addr,
+				 unsigned int reg_addr,
+				 unsigned int *data)
 {
 	u32 reg;
 	int i;
@@ -767,9 +765,8 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 		retval = exynos_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data */
@@ -780,10 +777,10 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 }
 
 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
+				  unsigned int device_addr,
+				  unsigned int reg_addr,
+				  unsigned int count,
+				  unsigned char edid[])
 {
 	u32 reg;
 	unsigned int i, j;
@@ -807,8 +804,8 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 			 * request without sending address
 			 */
 			if (!defer)
-				retval = exynos_dp_select_i2c_device(dp,
-						device_addr, reg_addr + i);
+				retval = exynos_dp_select_i2c_device(
+						dp, device_addr, reg_addr + i);
 			else
 				defer = 0;
 
@@ -819,24 +816,23 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 				 * If Bit 3 is 0, I2C transaction.
 				 */
 				reg = AUX_LENGTH(16) |
-					AUX_TX_COMM_I2C_TRANSACTION |
-					AUX_TX_COMM_READ;
+				      AUX_TX_COMM_I2C_TRANSACTION |
+				      AUX_TX_COMM_READ;
 				writel(reg, dp->reg_base +
-					EXYNOS_DP_AUX_CH_CTL_1);
+				       EXYNOS_DP_AUX_CH_CTL_1);
 
 				/* Start AUX transaction */
 				retval = exynos_dp_start_aux_transaction(dp);
 				if (retval == 0)
 					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
+
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
 			}
 			/* Check if Rx sends defer */
 			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
 			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
+			    reg == AUX_RX_COMM_I2C_DEFER) {
 				dev_err(dp->dev, "Defer: %d\n\n", reg);
 				defer = 1;
 			}
@@ -901,7 +897,7 @@ void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
 }
 
 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern)
+				    enum pattern_set pattern)
 {
 	u32 reg;
 
@@ -974,7 +970,7 @@ void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 }
 
 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
+				       u32 training_lane)
 {
 	u32 reg;
 
@@ -983,7 +979,7 @@ void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
 }
 
 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
+				       u32 training_lane)
 {
 	u32 reg;
 
@@ -992,7 +988,7 @@ void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
 }
 
 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
+				       u32 training_lane)
 {
 	u32 reg;
 
@@ -1001,7 +997,7 @@ void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
 }
 
 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
+				       u32 training_lane)
 {
 	u32 reg;
 
@@ -1125,9 +1121,9 @@ int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
 }
 
 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
+			       enum clock_recovery_m_value_type type,
+			       u32 m_value,
+			       u32 n_value)
 {
 	u32 reg;
 
@@ -1221,7 +1217,7 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
 	u32 reg;
 
 	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
 	reg |= MASTER_VID_FUNC_EN_N;
 	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 01/16] drm: exynos/dp: fix code style
@ 2015-09-01  5:46   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:46 UTC (permalink / raw)
  To: linux-arm-kernel

After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.

- Take Romain suggest, rebase on linux-next branch

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
  avoid using some uncommon style like bellow:
  -  retval = exynos_dp_read_bytes_from_i2c(...
				...)
  +  retval =
  +  exynos_dp_read_bytes_from_i2c(......);

 drivers/gpu/drm/exynos/exynos_dp_core.c | 226 ++++++++++++++++----------------
 drivers/gpu/drm/exynos/exynos_dp_core.h |  54 ++++----
 drivers/gpu/drm/exynos/exynos_dp_reg.c  | 106 +++++++--------
 3 files changed, 188 insertions(+), 198 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index d66ade0..266f7f7 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -115,8 +115,8 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
 	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-				EDID_EXTENSION_FLAG,
-				&extend_block);
+					      EDID_EXTENSION_FLAG,
+					      &extend_block);
 	if (retval)
 		return retval;
 
@@ -124,10 +124,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-						EDID_HEADER_PATTERN,
-						EDID_BLOCK_LENGTH,
-						&edid[EDID_HEADER_PATTERN]);
+		retval = exynos_dp_read_bytes_from_i2c(
+					dp, I2C_EDID_DEVICE_ADDR,
+					EDID_HEADER_PATTERN,
+					EDID_BLOCK_LENGTH,
+					&edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -139,11 +140,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_BLOCK_LENGTH,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_BLOCK_LENGTH]);
+		retval = exynos_dp_read_bytes_from_i2c(
+					dp, I2C_EDID_DEVICE_ADDR,
+					EDID_BLOCK_LENGTH,
+					EDID_BLOCK_LENGTH,
+					&edid[EDID_BLOCK_LENGTH]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		}
 
 		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					&test_vector);
+					      &test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
+			exynos_dp_write_byte_to_dpcd(
+				dp, DP_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
+			exynos_dp_write_byte_to_dpcd(
+				dp, DP_TEST_RESPONSE,
 				DP_TEST_EDID_CHECKSUM_WRITE);
 		}
 	} else {
 		dev_info(dp->dev, "EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_HEADER_PATTERN,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_HEADER_PATTERN]);
+		retval = exynos_dp_read_bytes_from_i2c(
+				dp, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
+				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -183,16 +182,15 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp,
-			DP_TEST_REQUEST,
-			&test_vector);
+		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+					      &test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
+			exynos_dp_write_byte_to_dpcd(
+					dp, DP_TEST_EDID_CHECKSUM,
+					edid[EDID_CHECKSUM]);
+			exynos_dp_write_byte_to_dpcd(
+					dp, DP_TEST_RESPONSE,
+					DP_TEST_EDID_CHECKSUM_WRITE);
 		}
 	}
 
@@ -207,8 +205,7 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
-				12, buf);
+	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
 	if (retval)
 		return retval;
 
@@ -223,7 +220,7 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 }
 
 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
-						bool enable)
+						 bool enable)
 {
 	u8 data;
 
@@ -231,11 +228,11 @@ static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
 
 	if (enable)
 		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DP_LANE_COUNT_ENHANCED_FRAME_EN |
-			DPCD_LANE_COUNT_SET(data));
+					     DP_LANE_COUNT_ENHANCED_FRAME_EN |
+					     DPCD_LANE_COUNT_SET(data));
 	else
 		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DPCD_LANE_COUNT_SET(data));
+					     DPCD_LANE_COUNT_SET(data));
 }
 
 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
@@ -262,13 +259,12 @@ static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
 {
 	exynos_dp_set_training_pattern(dp, DP_NONE);
 
-	exynos_dp_write_byte_to_dpcd(dp,
-		DP_TRAINING_PATTERN_SET,
-		DP_TRAINING_PATTERN_DISABLE);
+	exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+				     DP_TRAINING_PATTERN_DISABLE);
 }
 
 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
-					int pre_emphasis, int lane)
+						 int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -308,15 +304,14 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
-				2, buf);
+	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
 	if (retval)
 		return retval;
 
 	/* Set TX pre-emphasis to minimum */
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_lane_pre_emphasis(dp,
-			PRE_EMPHASIS_LEVEL_0, lane);
+		exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0,
+						     lane);
 
 	/* Wait for PLL lock */
 	pll_tries = 0;
@@ -334,9 +329,9 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
 
 	/* Set RX training pattern */
-	retval = exynos_dp_write_byte_to_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
+	retval = exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+					      DP_LINK_SCRAMBLING_DISABLE |
+					      DP_TRAINING_PATTERN_1);
 	if (retval)
 		return retval;
 
@@ -345,7 +340,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
 	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, buf);
+					       lane_count, buf);
 
 	return retval;
 }
@@ -353,7 +348,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = link_status[lane>>1];
+	u8 link_value = link_status[lane >> 1];
 
 	return (link_value >> shift) & 0xf;
 }
@@ -372,7 +367,7 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 }
 
 static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				int lane_count)
+				   int lane_count)
 {
 	int lane;
 	u8 lane_status;
@@ -391,10 +386,10 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 }
 
 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							int lane)
+							  int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return (link_value >> shift) & 0x3;
 }
@@ -404,13 +399,13 @@ static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 					int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
-					u8 training_lane_set, int lane)
+					     u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -430,9 +425,8 @@ static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
 	}
 }
 
-static unsigned int exynos_dp_get_lane_link_training(
-				struct exynos_dp_device *dp,
-				int lane)
+static unsigned int
+exynos_dp_get_lane_link_training(struct exynos_dp_device *dp, int lane)
 {
 	u32 reg;
 
@@ -466,7 +460,7 @@ static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
 }
 
 static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
-					u8 adjust_request[2])
+					       u8 adjust_request[2])
 {
 	int lane, lane_count;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -499,13 +493,13 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
-			DP_LANE0_1_STATUS, 2, link_status);
+	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
+						 2, link_status);
 	if (retval)
 		return retval;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
-			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
+	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
+						 2, adjust_request);
 	if (retval)
 		return retval;
 
@@ -513,8 +507,8 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 		/* set training pattern 2 for EQ */
 		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
 
-		retval = exynos_dp_write_byte_to_dpcd(dp,
-				DP_TRAINING_PATTERN_SET,
+		retval = exynos_dp_write_byte_to_dpcd(
+				dp, DP_TRAINING_PATTERN_SET,
 				DP_LINK_SCRAMBLING_DISABLE |
 				DP_TRAINING_PATTERN_2);
 		if (retval)
@@ -552,11 +546,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 	exynos_dp_get_adjust_training_lane(dp, adjust_request);
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
-			dp->link_train.training_lane[lane], lane);
+		exynos_dp_set_lane_link_training(
+				dp, dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp,
-			DP_TRAINING_LANE0_SET, lane_count,
+	retval = exynos_dp_write_bytes_to_dpcd(
+			dp, DP_TRAINING_LANE0_SET, lane_count,
 			dp->link_train.training_lane);
 	if (retval)
 		return retval;
@@ -574,8 +568,8 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
-			DP_LANE0_1_STATUS, 2, link_status);
+	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
+						2, link_status);
 	if (retval)
 		return retval;
 
@@ -584,13 +578,13 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 		return -EIO;
 	}
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
-			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
+	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
+						2, adjust_request);
 	if (retval)
 		return retval;
 
-	retval = exynos_dp_read_byte_from_dpcd(dp,
-			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
+	retval = exynos_dp_read_byte_from_dpcd(dp, DP_LANE_ALIGN_STATUS_UPDATED,
+					       &link_align);
 	if (retval)
 		return retval;
 
@@ -629,17 +623,18 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 	}
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
-			dp->link_train.training_lane[lane], lane);
+		exynos_dp_set_lane_link_training(
+				dp, dp->link_train.training_lane[lane], lane);
 
 	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, dp->link_train.training_lane);
+					       lane_count,
+					       dp->link_train.training_lane);
 
 	return retval;
 }
 
 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
-					u8 *bandwidth)
+					   u8 *bandwidth)
 {
 	u8 data;
 
@@ -652,7 +647,7 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 }
 
 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
-					u8 *lane_count)
+					    u8 *lane_count)
 {
 	u8 data;
 
@@ -665,8 +660,8 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 }
 
 static void exynos_dp_init_training(struct exynos_dp_device *dp,
-			enum link_lane_count_type max_lane,
-			enum link_rate_type max_rate)
+				    enum link_lane_count_type max_lane,
+				    enum link_rate_type max_rate)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
@@ -679,7 +674,7 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
 	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -739,8 +734,7 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 }
 
 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
-				u32 count,
-				u32 bwtype)
+				    u32 count, u32 bwtype)
 {
 	int i;
 	int retval;
@@ -828,21 +822,19 @@ static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
 	if (enable) {
 		exynos_dp_enable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
+		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+					      &data);
+		exynos_dp_write_byte_to_dpcd(
+				dp, DP_TRAINING_PATTERN_SET,
+				(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
 		exynos_dp_disable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
+		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+					      &data);
+		exynos_dp_write_byte_to_dpcd(
+				dp, DP_TRAINING_PATTERN_SET,
+				(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 	}
 }
 
@@ -913,7 +905,7 @@ static void exynos_dp_commit(struct drm_encoder *encoder)
 	}
 
 	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
-					dp->video_info->link_rate);
+				       dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -941,8 +933,8 @@ static void exynos_dp_commit(struct drm_encoder *encoder)
 	exynos_dp_start_video(dp);
 }
 
-static enum drm_connector_status exynos_dp_detect(
-				struct drm_connector *connector, bool force)
+static enum drm_connector_status
+exynos_dp_detect(struct drm_connector *connector, bool force)
 {
 	return connector_status_connected;
 }
@@ -990,8 +982,8 @@ static int exynos_dp_get_modes(struct drm_connector *connector)
 	return 1;
 }
 
-static struct drm_encoder *exynos_dp_best_encoder(
-			struct drm_connector *connector)
+static struct drm_encoder *
+exynos_dp_best_encoder(struct drm_connector *connector)
 {
 	struct exynos_dp_device *dp = ctx_from_connector(connector);
 
@@ -1005,7 +997,7 @@ static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
 
 /* returns the number of bridges attached */
 static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
-		struct drm_encoder *encoder)
+					struct drm_encoder *encoder)
 {
 	int ret;
 
@@ -1036,7 +1028,8 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	connector->polled = DRM_CONNECTOR_POLL_HPD;
 
 	ret = drm_connector_init(dp->drm_dev, connector,
-			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
+				 &exynos_dp_connector_funcs,
+				 DRM_MODE_CONNECTOR_eDP);
 	if (ret) {
 		DRM_ERROR("Failed to initialize connector with drm\n");
 		return ret;
@@ -1139,8 +1132,8 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
 
-	dp_video_config = devm_kzalloc(dev,
-				sizeof(*dp_video_config), GFP_KERNEL);
+	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
+				       GFP_KERNEL);
 	if (!dp_video_config)
 		return ERR_PTR(-ENOMEM);
 
@@ -1154,37 +1147,37 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
 		of_property_read_bool(dp_node, "interlaced");
 
 	if (of_property_read_u32(dp_node, "samsung,color-space",
-				&dp_video_config->color_space)) {
+				 &dp_video_config->color_space)) {
 		dev_err(dev, "failed to get color-space\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				&dp_video_config->dynamic_range)) {
+				 &dp_video_config->dynamic_range)) {
 		dev_err(dev, "failed to get dynamic-range\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				&dp_video_config->ycbcr_coeff)) {
+				 &dp_video_config->ycbcr_coeff)) {
 		dev_err(dev, "failed to get ycbcr-coeff\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				&dp_video_config->color_depth)) {
+				 &dp_video_config->color_depth)) {
 		dev_err(dev, "failed to get color-depth\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				&dp_video_config->link_rate)) {
+				 &dp_video_config->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				&dp_video_config->lane_count)) {
+				 &dp_video_config->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
 		return ERR_PTR(-EINVAL);
 	}
@@ -1197,7 +1190,7 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
 	int ret;
 
 	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
-			OF_USE_NATIVE_MODE);
+			       OF_USE_NATIVE_MODE);
 	if (ret) {
 		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
 		return ret;
@@ -1294,7 +1287,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	exynos_dp_init_dp(dp);
 
 	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
-			irq_flags, "exynos-dp", dp);
+			       irq_flags, "exynos-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		return ret;
@@ -1328,7 +1321,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 }
 
 static void exynos_dp_unbind(struct device *dev, struct device *master,
-				void *data)
+			     void *data)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
 
@@ -1347,7 +1340,7 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	struct exynos_dp_device *dp;
 
 	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
-				GFP_KERNEL);
+			  GFP_KERNEL);
 	if (!dp)
 		return -ENOMEM;
 
@@ -1369,8 +1362,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
 			of_node_put(bridge_node);
 			if (!dp->bridge)
 				return -EPROBE_DEFER;
-		} else
+		} else {
 			return -EPROBE_DEFER;
+		}
 	}
 
 	return component_add(&pdev->dev, &exynos_dp_ops);
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
index e413b6f..71f2b86 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
@@ -179,8 +179,8 @@ void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable);
+				     enum analog_power_block block,
+				     bool enable);
 void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
 void exynos_dp_init_hpd(struct exynos_dp_device *dp);
 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
@@ -191,50 +191,50 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
+				 unsigned int reg_addr,
+				 unsigned char data);
 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
+				  unsigned int reg_addr,
+				  unsigned char *data);
 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				  unsigned int reg_addr,
+				  unsigned int count,
+				  unsigned char data[]);
 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				   unsigned int reg_addr,
+				   unsigned int count,
+				   unsigned char data[]);
 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 				unsigned int device_addr,
 				unsigned int reg_addr);
 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
+				 unsigned int device_addr,
+				 unsigned int reg_addr,
+				 unsigned int *data);
 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
+				  unsigned int device_addr,
+				  unsigned int reg_addr,
+				  unsigned int count,
+				  unsigned char edid[]);
 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern);
+				    enum pattern_set pattern);
 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
+				       u32 training_lane);
 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
+				       u32 training_lane);
 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
+				       u32 training_lane);
 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
+				       u32 training_lane);
 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
@@ -245,9 +245,9 @@ void exynos_dp_init_video(struct exynos_dp_device *dp);
 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
+			       enum clock_recovery_m_value_type type,
+			       u32 m_value,
+			       u32 n_value);
 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
 void exynos_dp_start_video(struct exynos_dp_device *dp);
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
index c1f87a2..5aff19a 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_reg.c
@@ -202,8 +202,8 @@ void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
 }
 
 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
+				     enum analog_power_block block,
+				     bool enable)
 {
 	u32 reg;
 
@@ -399,8 +399,8 @@ void exynos_dp_init_aux(struct exynos_dp_device *dp)
 	exynos_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
+	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
@@ -483,8 +483,8 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
 }
 
 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
+				 unsigned int reg_addr,
+				 unsigned char data)
 {
 	u32 reg;
 	int i;
@@ -519,17 +519,16 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
 		retval = exynos_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	return retval;
 }
 
 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
+				  unsigned int reg_addr,
+				  unsigned char *data)
 {
 	u32 reg;
 	int i;
@@ -560,9 +559,8 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 		retval = exynos_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data buffer */
@@ -573,9 +571,9 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 }
 
 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				  unsigned int reg_addr,
+				  unsigned int count,
+				  unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -625,9 +623,9 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 			retval = exynos_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		start_offset += cur_data_count;
@@ -637,9 +635,9 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 }
 
 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				   unsigned int reg_addr,
+				   unsigned int count,
+				   unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -683,9 +681,9 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
 			retval = exynos_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
@@ -736,9 +734,9 @@ int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 }
 
 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
+				 unsigned int device_addr,
+				 unsigned int reg_addr,
+				 unsigned int *data)
 {
 	u32 reg;
 	int i;
@@ -767,9 +765,8 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 		retval = exynos_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data */
@@ -780,10 +777,10 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 }
 
 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
+				  unsigned int device_addr,
+				  unsigned int reg_addr,
+				  unsigned int count,
+				  unsigned char edid[])
 {
 	u32 reg;
 	unsigned int i, j;
@@ -807,8 +804,8 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 			 * request without sending address
 			 */
 			if (!defer)
-				retval = exynos_dp_select_i2c_device(dp,
-						device_addr, reg_addr + i);
+				retval = exynos_dp_select_i2c_device(
+						dp, device_addr, reg_addr + i);
 			else
 				defer = 0;
 
@@ -819,24 +816,23 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 				 * If Bit 3 is 0, I2C transaction.
 				 */
 				reg = AUX_LENGTH(16) |
-					AUX_TX_COMM_I2C_TRANSACTION |
-					AUX_TX_COMM_READ;
+				      AUX_TX_COMM_I2C_TRANSACTION |
+				      AUX_TX_COMM_READ;
 				writel(reg, dp->reg_base +
-					EXYNOS_DP_AUX_CH_CTL_1);
+				       EXYNOS_DP_AUX_CH_CTL_1);
 
 				/* Start AUX transaction */
 				retval = exynos_dp_start_aux_transaction(dp);
 				if (retval == 0)
 					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
+
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
 			}
 			/* Check if Rx sends defer */
 			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
 			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
+			    reg == AUX_RX_COMM_I2C_DEFER) {
 				dev_err(dp->dev, "Defer: %d\n\n", reg);
 				defer = 1;
 			}
@@ -901,7 +897,7 @@ void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
 }
 
 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern)
+				    enum pattern_set pattern)
 {
 	u32 reg;
 
@@ -974,7 +970,7 @@ void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 }
 
 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
+				       u32 training_lane)
 {
 	u32 reg;
 
@@ -983,7 +979,7 @@ void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
 }
 
 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
+				       u32 training_lane)
 {
 	u32 reg;
 
@@ -992,7 +988,7 @@ void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
 }
 
 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
+				       u32 training_lane)
 {
 	u32 reg;
 
@@ -1001,7 +997,7 @@ void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
 }
 
 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
+				       u32 training_lane)
 {
 	u32 reg;
 
@@ -1125,9 +1121,9 @@ int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
 }
 
 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
+			       enum clock_recovery_m_value_type type,
+			       u32 m_value,
+			       u32 n_value)
 {
 	u32 reg;
 
@@ -1221,7 +1217,7 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
 	u32 reg;
 
 	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
 	reg |= MASTER_VID_FUNC_EN_N;
 	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 02/16] drm: exynos/dp: convert to drm bridge mode
  2015-09-01  5:46 ` Yakir Yang
@ 2015-09-01  5:49   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:49 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Romain suggest, rebase on linux-next branch.

Changes in v3: None
Changes in v2:
- Take Jingoo Han suggest, just remove my name from author list.

 drivers/gpu/drm/exynos/exynos_dp_core.c | 104 +++++++++++++++++++++++---------
 drivers/gpu/drm/exynos/exynos_dp_core.h |   1 +
 2 files changed, 78 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 266f7f7..bed0252 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -1001,9 +1001,9 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
 {
 	int ret;
 
-	encoder->bridge = dp->bridge;
-	dp->bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->bridge);
+	encoder->bridge->next = dp->ptn_bridge;
+	dp->ptn_bridge->encoder = encoder;
+	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
 	if (ret) {
 		DRM_ERROR("Failed to attach bridge to drm\n");
 		return ret;
@@ -1012,14 +1012,15 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
 	return 0;
 }
 
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = &dp->encoder;
 	struct drm_connector *connector = &dp->connector;
 	int ret;
 
 	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->bridge) {
+	if (dp->ptn_bridge) {
 		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
 		if (!ret)
 			return 0;
@@ -1045,22 +1046,9 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	return ret;
 }
 
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
-				 const struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
 	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
 
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
@@ -1085,9 +1073,9 @@ static void exynos_dp_enable(struct drm_encoder *encoder)
 	dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
-static void exynos_dp_disable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
 	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
 
 	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
@@ -1116,6 +1104,68 @@ static void exynos_dp_disable(struct drm_encoder *encoder)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+{
+	/* do nothing */
+}
+
+static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
+	.enable = exynos_dp_bridge_enable,
+	.disable = exynos_dp_bridge_disable,
+	.pre_enable = exynos_dp_bridge_nop,
+	.post_disable = exynos_dp_bridge_nop,
+	.attach = exynos_dp_bridge_attach,
+};
+
+static int exynos_dp_create_connector(struct drm_encoder *encoder)
+{
+	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct drm_bridge *bridge;
+	int ret;
+
+	bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
+	if (!bridge) {
+		DRM_ERROR("failed to allocate for drm bridge\n");
+		return -ENOMEM;
+	}
+
+	dp->bridge = bridge;
+
+	bridge->driver_private = dp;
+	bridge->encoder = encoder;
+	bridge->funcs = &exynos_dp_bridge_funcs;
+
+	ret = drm_bridge_attach(drm_dev, bridge);
+	if (ret) {
+		DRM_ERROR("failed to attach drm bridge\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+				 const struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
 static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
 	.mode_fixup = exynos_dp_mode_fixup,
 	.mode_set = exynos_dp_mode_set,
@@ -1358,9 +1408,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	if (endpoint) {
 		bridge_node = of_graph_get_remote_port_parent(endpoint);
 		if (bridge_node) {
-			dp->bridge = of_drm_find_bridge(bridge_node);
+			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
 			of_node_put(bridge_node);
-			if (!dp->bridge)
+			if (!dp->ptn_bridge)
 				return -EPROBE_DEFER;
 		} else {
 			return -EPROBE_DEFER;
@@ -1382,7 +1432,7 @@ static int exynos_dp_suspend(struct device *dev)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_disable(&dp->encoder);
+	exynos_dp_bridge_disable(dp->bridge);
 	return 0;
 }
 
@@ -1390,7 +1440,7 @@ static int exynos_dp_resume(struct device *dev)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_enable(&dp->encoder);
+	exynos_dp_bridge_enable(dp->bridge);
 	return 0;
 }
 #endif
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
index 71f2b86..7ff754f 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
@@ -153,6 +153,7 @@ struct exynos_dp_device {
 	struct drm_connector	connector;
 	struct drm_panel	*panel;
 	struct drm_bridge	*bridge;
+	struct drm_bridge	*ptn_bridge;
 	struct clk		*clock;
 	unsigned int		irq;
 	void __iomem		*reg_base;
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 02/16] drm: exynos/dp: convert to drm bridge mode
@ 2015-09-01  5:49   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:49 UTC (permalink / raw)
  To: linux-arm-kernel

In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Romain suggest, rebase on linux-next branch.

Changes in v3: None
Changes in v2:
- Take Jingoo Han suggest, just remove my name from author list.

 drivers/gpu/drm/exynos/exynos_dp_core.c | 104 +++++++++++++++++++++++---------
 drivers/gpu/drm/exynos/exynos_dp_core.h |   1 +
 2 files changed, 78 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 266f7f7..bed0252 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -1001,9 +1001,9 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
 {
 	int ret;
 
-	encoder->bridge = dp->bridge;
-	dp->bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->bridge);
+	encoder->bridge->next = dp->ptn_bridge;
+	dp->ptn_bridge->encoder = encoder;
+	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
 	if (ret) {
 		DRM_ERROR("Failed to attach bridge to drm\n");
 		return ret;
@@ -1012,14 +1012,15 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
 	return 0;
 }
 
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = &dp->encoder;
 	struct drm_connector *connector = &dp->connector;
 	int ret;
 
 	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->bridge) {
+	if (dp->ptn_bridge) {
 		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
 		if (!ret)
 			return 0;
@@ -1045,22 +1046,9 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	return ret;
 }
 
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
-				 const struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
 	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
 
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
@@ -1085,9 +1073,9 @@ static void exynos_dp_enable(struct drm_encoder *encoder)
 	dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
-static void exynos_dp_disable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
 	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
 
 	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
@@ -1116,6 +1104,68 @@ static void exynos_dp_disable(struct drm_encoder *encoder)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+{
+	/* do nothing */
+}
+
+static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
+	.enable = exynos_dp_bridge_enable,
+	.disable = exynos_dp_bridge_disable,
+	.pre_enable = exynos_dp_bridge_nop,
+	.post_disable = exynos_dp_bridge_nop,
+	.attach = exynos_dp_bridge_attach,
+};
+
+static int exynos_dp_create_connector(struct drm_encoder *encoder)
+{
+	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct drm_bridge *bridge;
+	int ret;
+
+	bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
+	if (!bridge) {
+		DRM_ERROR("failed to allocate for drm bridge\n");
+		return -ENOMEM;
+	}
+
+	dp->bridge = bridge;
+
+	bridge->driver_private = dp;
+	bridge->encoder = encoder;
+	bridge->funcs = &exynos_dp_bridge_funcs;
+
+	ret = drm_bridge_attach(drm_dev, bridge);
+	if (ret) {
+		DRM_ERROR("failed to attach drm bridge\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+				 const struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
 static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
 	.mode_fixup = exynos_dp_mode_fixup,
 	.mode_set = exynos_dp_mode_set,
@@ -1358,9 +1408,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	if (endpoint) {
 		bridge_node = of_graph_get_remote_port_parent(endpoint);
 		if (bridge_node) {
-			dp->bridge = of_drm_find_bridge(bridge_node);
+			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
 			of_node_put(bridge_node);
-			if (!dp->bridge)
+			if (!dp->ptn_bridge)
 				return -EPROBE_DEFER;
 		} else {
 			return -EPROBE_DEFER;
@@ -1382,7 +1432,7 @@ static int exynos_dp_suspend(struct device *dev)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_disable(&dp->encoder);
+	exynos_dp_bridge_disable(dp->bridge);
 	return 0;
 }
 
@@ -1390,7 +1440,7 @@ static int exynos_dp_resume(struct device *dev)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_enable(&dp->encoder);
+	exynos_dp_bridge_enable(dp->bridge);
 	return 0;
 }
 #endif
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
index 71f2b86..7ff754f 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
@@ -153,6 +153,7 @@ struct exynos_dp_device {
 	struct drm_connector	connector;
 	struct drm_panel	*panel;
 	struct drm_bridge	*bridge;
+	struct drm_bridge	*ptn_bridge;
 	struct clk		*clock;
 	unsigned int		irq;
 	void __iomem		*reg_base;
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-01  5:49   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:49 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Split the dp core driver from exynos directory to bridge
directory, and rename the core driver to analogix_dp_*,
leave the platform code to analogix_dp-exynos.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
- Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
- Take Archit suggest, create a separate folder for analogix code in bridge/

Changes in v3:
- Take Thierry Reding suggest, move exynos's video_timing code
  to analogix_dp-exynos platform driver, add get_modes method
  to struct analogix_dp_plat_data.
- Take Heiko suggest, rename some "samsung*" dts propery to "analogix*".

Changes in v2:
- Take Jingoo Han suggest, remove new copyright
- Fix compiled failed dut to analogix_dp_device misspell

 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 .../analogix/analogix_dp_core.c}                   |  817 ++++++-------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  283 +++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1265 ++++++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  258 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  306 +++++
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 -----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1259 -------------------
 include/drm/bridge/analogix_dp.h                   |   24 +
 14 files changed, 2357 insertions(+), 2150 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 rename drivers/gpu/drm/{exynos/exynos_dp_core.c => bridge/analogix/analogix_dp_core.c} (50%)
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (64%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 include/drm/bridge/analogix_dp.h

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 2de52a5..7b5b77a 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -29,4 +29,6 @@ config DRM_PARADE_PS8622
 	---help---
 	  Parade eDP-LVDS bridge chip driver.
 
+source "drivers/gpu/drm/bridge/analogix/Kconfig"
+
 endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index e2eef1c..5366c6b 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -3,3 +3,4 @@ ccflags-y := -Iinclude/drm
 obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
new file mode 100644
index 0000000..5ff6551
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -0,0 +1,4 @@
+config DRM_ANALOGIX_DP
+	tristate
+	depends on DRM
+	select DRM_KMS_HELPER
diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
new file mode 100644
index 0000000..9107b86
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
similarity index 50%
rename from drivers/gpu/drm/exynos/exynos_dp_core.c
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index bed0252..7d62f22 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1,14 +1,14 @@
 /*
- * Samsung SoC DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
+* Analogix DP (Display Port) core interface driver.
+*
+* Copyright (C) 2012 Samsung Electronics Co., Ltd.
+* Author: Jingoo Han <jg1.han@samsung.com>
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2 of the License, or (at your
+* option) any later version.
+*/
 
 #include <linux/module.h>
 #include <linux/platform_device.h>
@@ -18,12 +18,9 @@
 #include <linux/interrupt.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
-#include <linux/of_graph.h>
 #include <linux/gpio.h>
 #include <linux/component.h>
 #include <linux/phy/phy.h>
-#include <video/of_display_timing.h>
-#include <video/of_videomode.h>
 
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
@@ -31,52 +28,42 @@
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_panel.h>
 
-#include "exynos_dp_core.h"
-#include "exynos_drm_crtc.h"
+#include <drm/bridge/analogix_dp.h>
 
-#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
-					connector)
+#include "analogix_dp_core.h"
 
-static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
-{
-	return to_exynos_crtc(dp->encoder.crtc);
-}
-
-static inline struct exynos_dp_device *encoder_to_dp(
-						struct drm_encoder *e)
-{
-	return container_of(e, struct exynos_dp_device, encoder);
-}
+#define connector_to_dp(c) \
+	container_of(c, struct analogix_dp_device, connector)
 
 struct bridge_init {
 	struct i2c_client *client;
 	struct device_node *node;
 };
 
-static void exynos_dp_init_dp(struct exynos_dp_device *dp)
+static void analogix_dp_init_dp(struct analogix_dp_device *dp)
 {
-	exynos_dp_reset(dp);
+	analogix_dp_reset(dp);
 
-	exynos_dp_swreset(dp);
+	analogix_dp_swreset(dp);
 
-	exynos_dp_init_analog_param(dp);
-	exynos_dp_init_interrupt(dp);
+	analogix_dp_init_analog_param(dp);
+	analogix_dp_init_interrupt(dp);
 
 	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_function(dp);
+	analogix_dp_enable_sw_function(dp);
 
-	exynos_dp_config_interrupt(dp);
-	exynos_dp_init_analog_func(dp);
+	analogix_dp_config_interrupt(dp);
+	analogix_dp_init_analog_func(dp);
 
-	exynos_dp_init_hpd(dp);
-	exynos_dp_init_aux(dp);
+	analogix_dp_init_hpd(dp);
+	analogix_dp_init_aux(dp);
 }
 
-static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
+static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (exynos_dp_get_plug_in_status(dp) != 0) {
+	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
@@ -88,7 +75,7 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
 	return 0;
 }
 
-static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
+static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 {
 	int i;
 	unsigned char sum = 0;
@@ -99,7 +86,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
 	return sum;
 }
 
-static int exynos_dp_read_edid(struct exynos_dp_device *dp)
+static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
 	unsigned char edid[EDID_BLOCK_LENGTH * 2];
 	unsigned int extend_block = 0;
@@ -114,9 +101,9 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 	 */
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-					      EDID_EXTENSION_FLAG,
-					      &extend_block);
+	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+						EDID_EXTENSION_FLAG,
+						&extend_block);
 	if (retval)
 		return retval;
 
@@ -124,7 +111,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(
+		retval = analogix_dp_read_bytes_from_i2c(
 					dp, I2C_EDID_DEVICE_ADDR,
 					EDID_HEADER_PATTERN,
 					EDID_BLOCK_LENGTH,
@@ -133,14 +120,14 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
+		sum = analogix_dp_calc_edid_check_sum(edid);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(
+		retval = analogix_dp_read_bytes_from_i2c(
 					dp, I2C_EDID_DEVICE_ADDR,
 					EDID_BLOCK_LENGTH,
 					EDID_BLOCK_LENGTH,
@@ -149,19 +136,19 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
+		sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					      &test_vector);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(
+			analogix_dp_write_byte_to_dpcd(
 				dp, DP_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(
+			analogix_dp_write_byte_to_dpcd(
 				dp, DP_TEST_RESPONSE,
 				DP_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -169,26 +156,26 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_info(dp->dev, "EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(
+		retval = analogix_dp_read_bytes_from_i2c(
 				dp, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
 				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
+		sum = analogix_dp_calc_edid_check_sum(edid);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					      &test_vector);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(
+			analogix_dp_write_byte_to_dpcd(
 					dp, DP_TEST_EDID_CHECKSUM,
 					edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(
+			analogix_dp_write_byte_to_dpcd(
 					dp, DP_TEST_RESPONSE,
 					DP_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -198,20 +185,20 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 	return 0;
 }
 
-static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
+static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 {
 	u8 buf[12];
 	int i;
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
 	if (retval)
 		return retval;
 
 	/* Read EDID */
 	for (i = 0; i < 3; i++) {
-		retval = exynos_dp_read_edid(dp);
+		retval = analogix_dp_read_edid(dp);
 		if (!retval)
 			break;
 	}
@@ -219,72 +206,74 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
-						 bool enable)
+static void
+analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
+				       bool enable)
 {
 	u8 data;
 
-	exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
 
 	if (enable)
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-					     DP_LANE_COUNT_ENHANCED_FRAME_EN |
-					     DPCD_LANE_COUNT_SET(data));
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+					       DP_LANE_COUNT_ENHANCED_FRAME_EN |
+					       DPCD_LANE_COUNT_SET(data));
 	else
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-					     DPCD_LANE_COUNT_SET(data));
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+					       DPCD_LANE_COUNT_SET(data));
 }
 
-static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
+static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
 {
 	u8 data;
 	int retval;
 
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 	retval = DPCD_ENHANCED_FRAME_CAP(data);
 
 	return retval;
 }
 
-static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
+static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 {
 	u8 data;
 
-	data = exynos_dp_is_enhanced_mode_available(dp);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, data);
-	exynos_dp_enable_enhanced_mode(dp, data);
+	data = analogix_dp_is_enhanced_mode_available(dp);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, data);
+	analogix_dp_enable_enhanced_mode(dp, data);
 }
 
-static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
+static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
-	exynos_dp_set_training_pattern(dp, DP_NONE);
+	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
-				     DP_TRAINING_PATTERN_DISABLE);
+	analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+				       DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
-						 int pre_emphasis, int lane)
+static void
+analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
+				       int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
-		exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 		break;
 	case 1:
-		exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 		break;
 
 	case 2:
-		exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 		break;
 
 	case 3:
-		exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 		break;
 	}
 }
 
-static int exynos_dp_link_start(struct exynos_dp_device *dp)
+static int analogix_dp_link_start(struct analogix_dp_device *dp)
 {
 	u8 buf[4];
 	int lane, lane_count, pll_tries, retval;
@@ -298,24 +287,24 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		dp->link_train.cr_loop[lane] = 0;
 
 	/* Set link rate and count as you want to establish*/
-	exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
-	exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
+	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
 	if (retval)
 		return retval;
 
 	/* Set TX pre-emphasis to minimum */
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0,
-						     lane);
+		analogix_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0,
+						       lane);
 
 	/* Wait for PLL lock */
 	pll_tries = 0;
-	while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+	while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 		if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Wait for PLL lock timed out\n");
 			return -ETIMEDOUT;
@@ -326,12 +315,12 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 	}
 
 	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
+	analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 
 	/* Set RX training pattern */
-	retval = exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
-					      DP_LINK_SCRAMBLING_DISABLE |
-					      DP_TRAINING_PATTERN_1);
+	retval = analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						DP_LINK_SCRAMBLING_DISABLE |
+						DP_TRAINING_PATTERN_1);
 	if (retval)
 		return retval;
 
@@ -339,13 +328,13 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-					       lane_count, buf);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+						 lane_count, buf);
 
 	return retval;
 }
 
-static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
+static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
 	u8 link_value = link_status[lane >> 1];
@@ -353,21 +342,21 @@ static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
 	return (link_value >> shift) & 0xf;
 }
 
-static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
+static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 {
 	int lane;
 	u8 lane_status;
 
 	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
 		if ((lane_status & DP_LANE_CR_DONE) == 0)
 			return -EINVAL;
 	}
 	return 0;
 }
 
-static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				   int lane_count)
+static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
+				     int lane_count)
 {
 	int lane;
 	u8 lane_status;
@@ -376,7 +365,7 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 		return -EINVAL;
 
 	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
 		lane_status &= DP_CHANNEL_EQ_BITS;
 		if (lane_status != DP_CHANNEL_EQ_BITS)
 			return -EINVAL;
@@ -385,8 +374,8 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							  int lane)
+static unsigned char
+analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 {
 	int shift = (lane & 1) * 4;
 	u8 link_value = adjust_request[lane >> 1];
@@ -394,7 +383,7 @@ static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 	return (link_value >> shift) & 0x3;
 }
 
-static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
+static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					u8 adjust_request[2],
 					int lane)
 {
@@ -404,44 +393,44 @@ static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
-static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
-					     u8 training_lane_set, int lane)
+static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
+					       u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
-		exynos_dp_set_lane0_link_training(dp, training_lane_set);
+		analogix_dp_set_lane0_link_training(dp, training_lane_set);
 		break;
 	case 1:
-		exynos_dp_set_lane1_link_training(dp, training_lane_set);
+		analogix_dp_set_lane1_link_training(dp, training_lane_set);
 		break;
 
 	case 2:
-		exynos_dp_set_lane2_link_training(dp, training_lane_set);
+		analogix_dp_set_lane2_link_training(dp, training_lane_set);
 		break;
 
 	case 3:
-		exynos_dp_set_lane3_link_training(dp, training_lane_set);
+		analogix_dp_set_lane3_link_training(dp, training_lane_set);
 		break;
 	}
 }
 
 static unsigned int
-exynos_dp_get_lane_link_training(struct exynos_dp_device *dp, int lane)
+analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, int lane)
 {
 	u32 reg;
 
 	switch (lane) {
 	case 0:
-		reg = exynos_dp_get_lane0_link_training(dp);
+		reg = analogix_dp_get_lane0_link_training(dp);
 		break;
 	case 1:
-		reg = exynos_dp_get_lane1_link_training(dp);
+		reg = analogix_dp_get_lane1_link_training(dp);
 		break;
 	case 2:
-		reg = exynos_dp_get_lane2_link_training(dp);
+		reg = analogix_dp_get_lane2_link_training(dp);
 		break;
 	case 3:
-		reg = exynos_dp_get_lane3_link_training(dp);
+		reg = analogix_dp_get_lane3_link_training(dp);
 		break;
 	default:
 		WARN_ON(1);
@@ -451,25 +440,25 @@ exynos_dp_get_lane_link_training(struct exynos_dp_device *dp, int lane)
 	return reg;
 }
 
-static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
+static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 {
-	exynos_dp_training_pattern_dis(dp);
-	exynos_dp_set_enhanced_mode(dp);
+	analogix_dp_training_pattern_dis(dp);
+	analogix_dp_set_enhanced_mode(dp);
 
 	dp->link_train.lt_state = FAILED;
 }
 
-static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
-					       u8 adjust_request[2])
+static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
+						 u8 adjust_request[2])
 {
 	int lane, lane_count;
 	u8 voltage_swing, pre_emphasis, training_lane;
 
 	lane_count = dp->link_train.lane_count;
 	for (lane = 0; lane < lane_count; lane++) {
-		voltage_swing = exynos_dp_get_adjust_request_voltage(
+		voltage_swing = analogix_dp_get_adjust_request_voltage(
 						adjust_request, lane);
-		pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
+		pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 						adjust_request, lane);
 		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
@@ -483,7 +472,7 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
 	}
 }
 
-static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
+static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 {
 	int lane, lane_count, retval;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -493,21 +482,22 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
-						 2, link_status);
+	retval =  analogix_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
+						   2, link_status);
 	if (retval)
 		return retval;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
-						 2, adjust_request);
+	retval =  analogix_dp_read_bytes_from_dpcd(
+					dp, DP_ADJUST_REQUEST_LANE0_1,
+					2, adjust_request);
 	if (retval)
 		return retval;
 
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 		/* set training pattern 2 for EQ */
-		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
+		analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 
-		retval = exynos_dp_write_byte_to_dpcd(
+		retval = analogix_dp_write_byte_to_dpcd(
 				dp, DP_TRAINING_PATTERN_SET,
 				DP_LINK_SCRAMBLING_DISABLE |
 				DP_TRAINING_PATTERN_2);
@@ -518,11 +508,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 		dp->link_train.lt_state = EQUALIZER_TRAINING;
 	} else {
 		for (lane = 0; lane < lane_count; lane++) {
-			training_lane = exynos_dp_get_lane_link_training(
+			training_lane = analogix_dp_get_lane_link_training(
 							dp, lane);
-			voltage_swing = exynos_dp_get_adjust_request_voltage(
+			voltage_swing = analogix_dp_get_adjust_request_voltage(
 							adjust_request, lane);
-			pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
+			pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 							adjust_request, lane);
 
 			if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
@@ -537,19 +527,19 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 				dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 					dp->link_train.cr_loop[lane],
 					voltage_swing, pre_emphasis);
-				exynos_dp_reduce_link_rate(dp);
+				analogix_dp_reduce_link_rate(dp);
 				return -EIO;
 			}
 		}
 	}
 
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(
+		analogix_dp_set_lane_link_training(
 				dp, dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(
+	retval = analogix_dp_write_bytes_to_dpcd(
 			dp, DP_TRAINING_LANE0_SET, lane_count,
 			dp->link_train.training_lane);
 	if (retval)
@@ -558,7 +548,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
+static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 {
 	int lane, lane_count, retval;
 	u32 reg;
@@ -568,46 +558,46 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
-						2, link_status);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
+						  2, link_status);
 	if (retval)
 		return retval;
 
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
-		exynos_dp_reduce_link_rate(dp);
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
+		analogix_dp_reduce_link_rate(dp);
 		return -EIO;
 	}
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
-						2, adjust_request);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
+						  2, adjust_request);
 	if (retval)
 		return retval;
 
-	retval = exynos_dp_read_byte_from_dpcd(dp, DP_LANE_ALIGN_STATUS_UPDATED,
-					       &link_align);
+	retval = analogix_dp_read_byte_from_dpcd(
+			dp, DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
 	if (retval)
 		return retval;
 
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 
-	if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
+	if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 		/* traing pattern Set to Normal */
-		exynos_dp_training_pattern_dis(dp);
+		analogix_dp_training_pattern_dis(dp);
 
 		dev_info(dp->dev, "Link Training success!\n");
 
-		exynos_dp_get_link_bandwidth(dp, &reg);
+		analogix_dp_get_link_bandwidth(dp, &reg);
 		dp->link_train.link_rate = reg;
 		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 			dp->link_train.link_rate);
 
-		exynos_dp_get_lane_count(dp, &reg);
+		analogix_dp_get_lane_count(dp, &reg);
 		dp->link_train.lane_count = reg;
 		dev_dbg(dp->dev, "final lane count = %.2x\n",
 			dp->link_train.lane_count);
 
 		/* set enhanced mode if available */
-		exynos_dp_set_enhanced_mode(dp);
+		analogix_dp_set_enhanced_mode(dp);
 		dp->link_train.lt_state = FINISHED;
 
 		return 0;
@@ -618,23 +608,23 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 		dev_err(dp->dev, "EQ Max loop\n");
-		exynos_dp_reduce_link_rate(dp);
+		analogix_dp_reduce_link_rate(dp);
 		return -EIO;
 	}
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(
+		analogix_dp_set_lane_link_training(
 				dp, dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-					       lane_count,
-					       dp->link_train.training_lane);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+						 lane_count,
+						 dp->link_train.training_lane);
 
 	return retval;
 }
 
-static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
-					   u8 *bandwidth)
+static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
+					     u8 *bandwidth)
 {
 	u8 data;
 
@@ -642,12 +632,12 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
 }
 
-static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
-					    u8 *lane_count)
+static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
+					      u8 *lane_count)
 {
 	u8 data;
 
@@ -655,23 +645,23 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 	 * For DP rev.1.1, Maximum number of Main Link lanes
 	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 	*lane_count = DPCD_MAX_LANE_COUNT(data);
 }
 
-static void exynos_dp_init_training(struct exynos_dp_device *dp,
-				    enum link_lane_count_type max_lane,
-				    enum link_rate_type max_rate)
+static void analogix_dp_init_training(struct analogix_dp_device *dp,
+				      enum link_lane_count_type max_lane,
+				      enum link_rate_type max_rate)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 	 * the DP inter pair skew issue for at least 10 us
 	 */
-	exynos_dp_reset_macro(dp);
+	analogix_dp_reset_macro(dp);
 
 	/* Initialize by reading RX's DPCD */
-	exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
-	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
+	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
+	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
@@ -693,10 +683,10 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
 		dp->link_train.link_rate = max_rate;
 
 	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 }
 
-static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
+static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 {
 	int retval = 0, training_finished = 0;
 
@@ -706,17 +696,17 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 	while (!retval && !training_finished) {
 		switch (dp->link_train.lt_state) {
 		case START:
-			retval = exynos_dp_link_start(dp);
+			retval = analogix_dp_link_start(dp);
 			if (retval)
 				dev_err(dp->dev, "LT link start failed!\n");
 			break;
 		case CLOCK_RECOVERY:
-			retval = exynos_dp_process_clock_recovery(dp);
+			retval = analogix_dp_process_clock_recovery(dp);
 			if (retval)
 				dev_err(dp->dev, "LT CR failed!\n");
 			break;
 		case EQUALIZER_TRAINING:
-			retval = exynos_dp_process_equalizer_training(dp);
+			retval = analogix_dp_process_equalizer_training(dp);
 			if (retval)
 				dev_err(dp->dev, "LT EQ failed!\n");
 			break;
@@ -733,15 +723,15 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
-				    u32 count, u32 bwtype)
+static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
+				      u32 count, u32 bwtype)
 {
 	int i;
 	int retval;
 
 	for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
-		exynos_dp_init_training(dp, count, bwtype);
-		retval = exynos_dp_sw_link_training(dp);
+		analogix_dp_init_training(dp, count, bwtype);
+		retval = analogix_dp_sw_link_training(dp);
 		if (retval == 0)
 			break;
 
@@ -751,24 +741,24 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 	return retval;
 }
 
-static int exynos_dp_config_video(struct exynos_dp_device *dp)
+static int analogix_dp_config_video(struct analogix_dp_device *dp)
 {
 	int retval = 0;
 	int timeout_loop = 0;
 	int done_count = 0;
 
-	exynos_dp_config_video_slave_mode(dp);
+	analogix_dp_config_video_slave_mode(dp);
 
-	exynos_dp_set_video_color_format(dp);
+	analogix_dp_set_video_color_format(dp);
 
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 		dev_err(dp->dev, "PLL is not locked yet.\n");
 		return -EINVAL;
 	}
 
 	for (;;) {
 		timeout_loop++;
-		if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
+		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
@@ -779,22 +769,22 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
 	}
 
 	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
+	analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 
 	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
+	analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 
 	/* Disable video mute */
-	exynos_dp_enable_video_mute(dp, 0);
+	analogix_dp_enable_video_mute(dp, 0);
 
 	/* Configure video slave mode */
-	exynos_dp_enable_video_master(dp, 0);
+	analogix_dp_enable_video_master(dp, 0);
 
 	timeout_loop = 0;
 
 	for (;;) {
 		timeout_loop++;
-		if (exynos_dp_is_video_stream_on(dp) == 0) {
+		if (analogix_dp_is_video_stream_on(dp) == 0) {
 			done_count++;
 			if (done_count > 10)
 				break;
@@ -815,45 +805,46 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
+					bool enable)
 {
 	u8 data;
 
 	if (enable) {
-		exynos_dp_enable_scrambling(dp);
+		analogix_dp_enable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
-					      &data);
-		exynos_dp_write_byte_to_dpcd(
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
+		analogix_dp_write_byte_to_dpcd(
 				dp, DP_TRAINING_PATTERN_SET,
 				(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
-		exynos_dp_disable_scrambling(dp);
+		analogix_dp_disable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
-					      &data);
-		exynos_dp_write_byte_to_dpcd(
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
+		analogix_dp_write_byte_to_dpcd(
 				dp, DP_TRAINING_PATTERN_SET,
 				(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 	}
 }
 
-static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
+static irqreturn_t analogix_dp_irq_handler(int irq, void *arg)
 {
-	struct exynos_dp_device *dp = arg;
+	struct analogix_dp_device *dp = arg;
 
 	enum dp_irq_type irq_type;
 
-	irq_type = exynos_dp_get_irq_type(dp);
+	irq_type = analogix_dp_get_irq_type(dp);
 	switch (irq_type) {
 	case DP_IRQ_TYPE_HP_CABLE_IN:
 		dev_dbg(dp->dev, "Received irq - cable in\n");
 		schedule_work(&dp->hotplug_work);
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	case DP_IRQ_TYPE_HP_CABLE_OUT:
 		dev_dbg(dp->dev, "Received irq - cable out\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	case DP_IRQ_TYPE_HP_CHANGE:
 		/*
@@ -862,7 +853,7 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 		 * only handle cable changes.
 		 */
 		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	default:
 		dev_err(dp->dev, "Received irq - unknown type!\n");
@@ -871,218 +862,204 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
-static void exynos_dp_hotplug(struct work_struct *work)
+static void analogix_dp_hotplug(struct work_struct *work)
 {
-	struct exynos_dp_device *dp;
+	struct analogix_dp_device *dp;
 
-	dp = container_of(work, struct exynos_dp_device, hotplug_work);
+	dp = container_of(work, struct analogix_dp_device, hotplug_work);
 
 	if (dp->drm_dev)
 		drm_helper_hpd_irq_event(dp->drm_dev);
 }
 
-static void exynos_dp_commit(struct drm_encoder *encoder)
+static void analogix_dp_commit(struct analogix_dp_device *dp)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
 	int ret;
 
 	/* Keep the panel disabled while we configure video */
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel))
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel))
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = exynos_dp_detect_hpd(dp);
+	ret = analogix_dp_detect_hpd(dp);
 	if (ret) {
 		/* Cable has been disconnected, we're done */
 		return;
 	}
 
-	ret = exynos_dp_handle_edid(dp);
+	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
 		return;
 	}
 
-	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
-				       dp->video_info->link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
+					 dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
 	}
 
-	exynos_dp_enable_scramble(dp, 1);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
-	exynos_dp_enable_enhanced_mode(dp, 1);
+	analogix_dp_enable_scramble(dp, 1);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
+	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
-	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
+	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 
-	exynos_dp_init_video(dp);
-	ret = exynos_dp_config_video(dp);
+	analogix_dp_init_video(dp);
+	ret = analogix_dp_config_video(dp);
 	if (ret)
 		dev_err(dp->dev, "unable to config video\n");
 
 	/* Safe to enable the panel now */
-	if (dp->panel) {
-		if (drm_panel_enable(dp->panel))
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_enable(dp->plat_data->panel))
 			DRM_ERROR("failed to enable the panel\n");
 	}
 
 	/* Enable video */
-	exynos_dp_start_video(dp);
+	analogix_dp_start_video(dp);
 }
 
 static enum drm_connector_status
-exynos_dp_detect(struct drm_connector *connector, bool force)
+analogix_dp_detect(struct drm_connector *connector, bool force)
 {
 	return connector_status_connected;
 }
 
-static void exynos_dp_connector_destroy(struct drm_connector *connector)
+static void analogix_dp_connector_destroy(struct drm_connector *connector)
 {
 	drm_connector_unregister(connector);
 	drm_connector_cleanup(connector);
 }
 
-static struct drm_connector_funcs exynos_dp_connector_funcs = {
+static struct drm_connector_funcs analogix_dp_connector_funcs = {
 	.dpms = drm_atomic_helper_connector_dpms,
 	.fill_modes = drm_helper_probe_single_connector_modes,
-	.detect = exynos_dp_detect,
-	.destroy = exynos_dp_connector_destroy,
+	.detect = analogix_dp_detect,
+	.destroy = analogix_dp_connector_destroy,
 	.reset = drm_atomic_helper_connector_reset,
 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 };
 
-static int exynos_dp_get_modes(struct drm_connector *connector)
+static int analogix_dp_get_modes(struct drm_connector *connector)
 {
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
-	struct drm_display_mode *mode;
-
-	if (dp->panel)
-		return drm_panel_get_modes(dp->panel);
+	struct analogix_dp_device *dp = connector_to_dp(connector);
+	struct analogix_dp_plat_data *plat_data = dp->plat_data;
+	int num_modes = 0;
 
-	mode = drm_mode_create(connector->dev);
-	if (!mode) {
-		DRM_ERROR("failed to create a new display mode.\n");
-		return 0;
-	}
-
-	drm_display_mode_from_videomode(&dp->priv.vm, mode);
-	mode->width_mm = dp->priv.width_mm;
-	mode->height_mm = dp->priv.height_mm;
-	connector->display_info.width_mm = mode->width_mm;
-	connector->display_info.height_mm = mode->height_mm;
+	if (plat_data && plat_data->panel)
+		num_modes += drm_panel_get_modes(plat_data->panel);
 
-	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-	drm_mode_set_name(mode);
-	drm_mode_probed_add(connector, mode);
+	if (plat_data && plat_data->get_modes)
+		 num_modes += plat_data->get_modes(plat_data, connector);
 
-	return 1;
+	return num_modes;
 }
 
 static struct drm_encoder *
-exynos_dp_best_encoder(struct drm_connector *connector)
+analogix_dp_best_encoder(struct drm_connector *connector)
 {
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
+	struct analogix_dp_device *dp = connector_to_dp(connector);
 
-	return &dp->encoder;
+	return dp->encoder;
 }
 
-static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
-	.get_modes = exynos_dp_get_modes,
-	.best_encoder = exynos_dp_best_encoder,
+static struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
+	.get_modes = analogix_dp_get_modes,
+	.best_encoder = analogix_dp_best_encoder,
 };
 
-/* returns the number of bridges attached */
-static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
-					struct drm_encoder *encoder)
-{
-	int ret;
-
-	encoder->bridge->next = dp->ptn_bridge;
-	dp->ptn_bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
-	if (ret) {
-		DRM_ERROR("Failed to attach bridge to drm\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
+static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct drm_encoder *encoder = &dp->encoder;
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = dp->encoder;
 	struct drm_connector *connector = &dp->connector;
 	int ret;
 
-	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->ptn_bridge) {
-		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
-		if (!ret)
-			return 0;
+	if (!bridge->encoder) {
+		DRM_ERROR("Parent encoder object not found");
+		return -ENODEV;
 	}
 
+	encoder->bridge = bridge;
+
 	connector->polled = DRM_CONNECTOR_POLL_HPD;
 
 	ret = drm_connector_init(dp->drm_dev, connector,
-				 &exynos_dp_connector_funcs,
+				 &analogix_dp_connector_funcs,
 				 DRM_MODE_CONNECTOR_eDP);
 	if (ret) {
 		DRM_ERROR("Failed to initialize connector with drm\n");
 		return ret;
 	}
 
-	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
+	drm_connector_helper_add(connector,
+				 &analogix_dp_connector_helper_funcs);
 	drm_connector_register(connector);
 	drm_mode_connector_attach_encoder(connector, encoder);
 
-	if (dp->panel)
-		ret = drm_panel_attach(dp->panel, &dp->connector);
+	if (dp->plat_data && dp->plat_data->panel) {
+		ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
+		if (ret) {
+			DRM_ERROR("Failed to attach panel\n");
+			return ret;
+		}
+	}
+
+	/*
+	 * This should be the end of attach function, caused
+	 * we should ensure dp bridge could attach first.
+	 */
+	 if (dp->plat_data && dp->plat_data->attach) {
+		 ret = dp->plat_data->attach(dp->plat_data, bridge);
+		 if (ret) {
+			 DRM_ERROR("Failed at platform attch func\n");
+			 return ret;
+		 }
+	 }
 
-	return ret;
+	return 0;
 }
 
-static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
+static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
+	struct analogix_dp_device *dp = bridge->driver_private;
 
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->panel) {
-		if (drm_panel_prepare(dp->panel)) {
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
 			DRM_ERROR("failed to setup the panel\n");
 			return;
 		}
 	}
 
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), true);
+	if (dp->plat_data && dp->plat_data->power_on)
+		dp->plat_data->power_on(dp->plat_data);
 
 	clk_prepare_enable(dp->clock);
 	phy_power_on(dp->phy);
-	exynos_dp_init_dp(dp);
+	analogix_dp_init_dp(dp);
 	enable_irq(dp->irq);
-	exynos_dp_commit(&dp->encoder);
+	analogix_dp_commit(dp);
 
 	dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
-static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
+static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
+	struct analogix_dp_device *dp = bridge->driver_private;
 
 	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel)) {
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel)) {
 			DRM_ERROR("failed to disable the panel\n");
 			return;
 		}
@@ -1093,34 +1070,33 @@ static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 	phy_power_off(dp->phy);
 	clk_disable_unprepare(dp->clock);
 
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), false);
+	if (dp->plat_data && dp->plat_data->power_off)
+		dp->plat_data->power_off(dp->plat_data);
 
-	if (dp->panel) {
-		if (drm_panel_unprepare(dp->panel))
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_unprepare(dp->plat_data->panel))
 			DRM_ERROR("failed to turnoff the panel\n");
 	}
 
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
-static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
 }
 
-static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
-	.enable = exynos_dp_bridge_enable,
-	.disable = exynos_dp_bridge_disable,
-	.pre_enable = exynos_dp_bridge_nop,
-	.post_disable = exynos_dp_bridge_nop,
-	.attach = exynos_dp_bridge_attach,
+static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
+	.enable = analogix_dp_bridge_enable,
+	.disable = analogix_dp_bridge_disable,
+	.pre_enable = analogix_dp_bridge_nop,
+	.post_disable = analogix_dp_bridge_nop,
+	.attach = analogix_dp_bridge_attach,
 };
 
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int analogix_dp_create_bridge(struct drm_device *drm_dev,
+				     struct analogix_dp_device *dp)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
-	struct drm_device *drm_dev = dp->drm_dev;
 	struct drm_bridge *bridge;
 	int ret;
 
@@ -1133,8 +1109,8 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	dp->bridge = bridge;
 
 	bridge->driver_private = dp;
-	bridge->encoder = encoder;
-	bridge->funcs = &exynos_dp_bridge_funcs;
+	bridge->encoder = dp->encoder;
+	bridge->funcs = &analogix_dp_bridge_funcs;
 
 	ret = drm_bridge_attach(drm_dev, bridge);
 	if (ret) {
@@ -1145,39 +1121,7 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	return 0;
 }
 
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
-				 const struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
-{
-}
-
-static void exynos_dp_disable(struct drm_encoder *encoder)
-{
-}
-
-static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
-	.mode_fixup = exynos_dp_mode_fixup,
-	.mode_set = exynos_dp_mode_set,
-	.enable = exynos_dp_enable,
-	.disable = exynos_dp_disable,
-};
-
-static struct drm_encoder_funcs exynos_dp_encoder_funcs = {
-	.destroy = drm_encoder_cleanup,
-};
-
-static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
+static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 {
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
@@ -1235,33 +1179,33 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
 	return dp_video_config;
 }
 
-static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct drm_encoder *encoder,
+		     struct analogix_dp_plat_data *plat_data)
 {
-	int ret;
-
-	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
-			       OF_USE_NATIVE_MODE);
-	if (ret) {
-		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
-		return ret;
-	}
-	return 0;
-}
-
-static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
-{
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
 	struct platform_device *pdev = to_platform_device(dev);
-	struct drm_device *drm_dev = data;
-	struct drm_encoder *encoder = &dp->encoder;
+	struct analogix_dp_device *dp;
 	struct resource *res;
 	unsigned int irq_flags;
-	int pipe, ret = 0;
+	int ret;
+
+	dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, dp);
 
 	dp->dev = &pdev->dev;
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 
-	dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
+	/*
+	 * platform dp driver need containor_of the plat_data to get
+	 * the driver private data, so we need to store the point of
+	 * plat_data, not the context of plat_data.
+	 */
+	dp->plat_data = plat_data;
+
+	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
 	if (IS_ERR(dp->video_info))
 		return PTR_ERR(dp->video_info);
 
@@ -1281,12 +1225,6 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		}
 	}
 
-	if (!dp->panel && !dp->bridge) {
-		ret = exynos_dp_dt_parse_panel(dp);
-		if (ret)
-			return ret;
-	}
-
 	dp->clock = devm_clk_get(&pdev->dev, "dp");
 	if (IS_ERR(dp->clock)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
@@ -1301,7 +1239,10 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
-	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
+	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
+	if (gpio_is_valid(dp->hpd_gpio))
+		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
+						 "samsung,hpd-gpio", 0);
 
 	if (gpio_is_valid(dp->hpd_gpio)) {
 		/*
@@ -1330,14 +1271,14 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		return -ENODEV;
 	}
 
-	INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
+	INIT_WORK(&dp->hotplug_work, analogix_dp_hotplug);
 
 	phy_power_on(dp->phy);
 
-	exynos_dp_init_dp(dp);
+	analogix_dp_init_dp(dp);
 
-	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
-			       irq_flags, "exynos-dp", dp);
+	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
+			       irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		return ret;
@@ -1345,22 +1286,9 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	disable_irq(dp->irq);
 
 	dp->drm_dev = drm_dev;
+	dp->encoder = encoder;
 
-	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
-						  EXYNOS_DISPLAY_TYPE_LCD);
-	if (pipe < 0)
-		return pipe;
-
-	encoder->possible_crtcs = 1 << pipe;
-
-	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
-
-	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
-			 DRM_MODE_ENCODER_TMDS);
-
-	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
-
-	ret = exynos_dp_create_connector(encoder);
+	ret = analogix_dp_create_bridge(drm_dev, dp);
 	if (ret) {
 		DRM_ERROR("failed to create connector ret = %d\n", ret);
 		drm_encoder_cleanup(encoder);
@@ -1369,103 +1297,36 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_bind);
 
-static void exynos_dp_unbind(struct device *dev, struct device *master,
-			     void *data)
+void analogix_dp_unbind(struct device *dev, struct device *master, void *data)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_disable(&dp->encoder);
-}
-
-static const struct component_ops exynos_dp_ops = {
-	.bind	= exynos_dp_bind,
-	.unbind	= exynos_dp_unbind,
-};
-
-static int exynos_dp_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct device_node *panel_node, *bridge_node, *endpoint;
-	struct exynos_dp_device *dp;
-
-	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
-			  GFP_KERNEL);
-	if (!dp)
-		return -ENOMEM;
-
-	platform_set_drvdata(pdev, dp);
-
-	panel_node = of_parse_phandle(dev->of_node, "panel", 0);
-	if (panel_node) {
-		dp->panel = of_drm_find_panel(panel_node);
-		of_node_put(panel_node);
-		if (!dp->panel)
-			return -EPROBE_DEFER;
-	}
-
-	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
-	if (endpoint) {
-		bridge_node = of_graph_get_remote_port_parent(endpoint);
-		if (bridge_node) {
-			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
-			of_node_put(bridge_node);
-			if (!dp->ptn_bridge)
-				return -EPROBE_DEFER;
-		} else {
-			return -EPROBE_DEFER;
-		}
-	}
-
-	return component_add(&pdev->dev, &exynos_dp_ops);
-}
-
-static int exynos_dp_remove(struct platform_device *pdev)
-{
-	component_del(&pdev->dev, &exynos_dp_ops);
-
-	return 0;
+	analogix_dp_bridge_disable(dp->bridge);
 }
+EXPORT_SYMBOL_GPL(analogix_dp_unbind);
 
 #ifdef CONFIG_PM_SLEEP
-static int exynos_dp_suspend(struct device *dev)
+int analogix_dp_suspend(struct device *dev)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_bridge_disable(dp->bridge);
+	analogix_dp_bridge_disable(dp->bridge);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_suspend);
 
-static int exynos_dp_resume(struct device *dev)
+int analogix_dp_resume(struct device *dev)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_bridge_enable(dp->bridge);
+	analogix_dp_bridge_enable(dp->bridge);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_resume);
 #endif
 
-static const struct dev_pm_ops exynos_dp_pm_ops = {
-	SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
-};
-
-static const struct of_device_id exynos_dp_match[] = {
-	{ .compatible = "samsung,exynos5-dp" },
-	{},
-};
-MODULE_DEVICE_TABLE(of, exynos_dp_match);
-
-struct platform_driver dp_driver = {
-	.probe		= exynos_dp_probe,
-	.remove		= exynos_dp_remove,
-	.driver		= {
-		.name	= "exynos-dp",
-		.owner	= THIS_MODULE,
-		.pm	= &exynos_dp_pm_ops,
-		.of_match_table = exynos_dp_match,
-	},
-};
-
 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
-MODULE_DESCRIPTION("Samsung SoC DP Driver");
+MODULE_DESCRIPTION("Analogix Core DP Driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
new file mode 100644
index 0000000..d7e47e0
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -0,0 +1,283 @@
+/*
+ * Header file for Analogix DP (Display Port) core interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _ANALOGIX_DP_CORE_H
+#define _ANALOGIX_DP_CORE_H
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_dp_helper.h>
+
+#define DP_TIMEOUT_LOOP_COUNT 100
+#define MAX_CR_LOOP 5
+#define MAX_EQ_LOOP 5
+
+enum link_rate_type {
+	LINK_RATE_1_62GBPS = 0x06,
+	LINK_RATE_2_70GBPS = 0x0a
+};
+
+enum link_lane_count_type {
+	LANE_COUNT1 = 1,
+	LANE_COUNT2 = 2,
+	LANE_COUNT4 = 4
+};
+
+enum link_training_state {
+	START,
+	CLOCK_RECOVERY,
+	EQUALIZER_TRAINING,
+	FINISHED,
+	FAILED
+};
+
+enum voltage_swing_level {
+	VOLTAGE_LEVEL_0,
+	VOLTAGE_LEVEL_1,
+	VOLTAGE_LEVEL_2,
+	VOLTAGE_LEVEL_3,
+};
+
+enum pre_emphasis_level {
+	PRE_EMPHASIS_LEVEL_0,
+	PRE_EMPHASIS_LEVEL_1,
+	PRE_EMPHASIS_LEVEL_2,
+	PRE_EMPHASIS_LEVEL_3,
+};
+
+enum pattern_set {
+	PRBS7,
+	D10_2,
+	TRAINING_PTN1,
+	TRAINING_PTN2,
+	DP_NONE
+};
+
+enum color_space {
+	COLOR_RGB,
+	COLOR_YCBCR422,
+	COLOR_YCBCR444
+};
+
+enum color_depth {
+	COLOR_6,
+	COLOR_8,
+	COLOR_10,
+	COLOR_12
+};
+
+enum color_coefficient {
+	COLOR_YCBCR601,
+	COLOR_YCBCR709
+};
+
+enum dynamic_range {
+	VESA,
+	CEA
+};
+
+enum pll_status {
+	PLL_UNLOCKED,
+	PLL_LOCKED
+};
+
+enum clock_recovery_m_value_type {
+	CALCULATED_M,
+	REGISTER_M
+};
+
+enum video_timing_recognition_type {
+	VIDEO_TIMING_FROM_CAPTURE,
+	VIDEO_TIMING_FROM_REGISTER
+};
+
+enum analog_power_block {
+	AUX_BLOCK,
+	CH0_BLOCK,
+	CH1_BLOCK,
+	CH2_BLOCK,
+	CH3_BLOCK,
+	ANALOG_TOTAL,
+	POWER_ALL
+};
+
+enum dp_irq_type {
+	DP_IRQ_TYPE_HP_CABLE_IN,
+	DP_IRQ_TYPE_HP_CABLE_OUT,
+	DP_IRQ_TYPE_HP_CHANGE,
+	DP_IRQ_TYPE_UNKNOWN,
+};
+
+struct video_info {
+	char *name;
+
+	bool h_sync_polarity;
+	bool v_sync_polarity;
+	bool interlaced;
+
+	enum color_space color_space;
+	enum dynamic_range dynamic_range;
+	enum color_coefficient ycbcr_coeff;
+	enum color_depth color_depth;
+
+	enum link_rate_type link_rate;
+	enum link_lane_count_type lane_count;
+};
+
+struct link_train {
+	int eq_loop;
+	int cr_loop[4];
+
+	u8 link_rate;
+	u8 lane_count;
+	u8 training_lane[4];
+
+	enum link_training_state lt_state;
+};
+
+struct analogix_dp_device {
+	struct device		*dev;
+	struct drm_device	*drm_dev;
+	struct drm_connector	connector;
+	struct drm_encoder	*encoder;
+	struct drm_bridge	*bridge;
+	struct clk		*clock;
+	unsigned int		irq;
+	void __iomem		*reg_base;
+
+	struct video_info	*video_info;
+	struct link_train	link_train;
+	struct work_struct	hotplug_work;
+	struct phy		*phy;
+	int			dpms_mode;
+	int			hpd_gpio;
+
+	struct analogix_dp_plat_data *plat_data;
+};
+
+/* analogix_dp_reg.c */
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_stop_video(struct analogix_dp_device *dp);
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
+void analogix_dp_reset(struct analogix_dp_device *dp);
+void analogix_dp_swreset(struct analogix_dp_device *dp);
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				       enum analog_power_block block,
+				       bool enable);
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
+void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
+void analogix_dp_reset_aux(struct analogix_dp_device *dp);
+void analogix_dp_init_aux(struct analogix_dp_device *dp);
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				   unsigned int reg_addr,
+				   unsigned char data);
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				    unsigned int reg_addr,
+				    unsigned char *data);
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[]);
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[]);
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				  unsigned int device_addr,
+				  unsigned int reg_addr);
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data);
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[]);
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable);
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				      enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane);
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane);
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane);
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane);
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
+void analogix_dp_reset_macro(struct analogix_dp_device *dp);
+void analogix_dp_init_video(struct analogix_dp_device *dp);
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value,
+				 u32 n_value);
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
+				     bool enable);
+void analogix_dp_start_video(struct analogix_dp_device *dp);
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
+#endif /* _ANALOGIX_DP_CORE_H */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
new file mode 100644
index 0000000..b879d8c
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -0,0 +1,1265 @@
+/*
+ * Analogix DP (Display port) core register interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include "analogix_dp_core.h"
+#include "analogix_dp_reg.h"
+
+#define COMMON_INT_MASK_1	0
+#define COMMON_INT_MASK_2	0
+#define COMMON_INT_MASK_3	0
+#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
+#define INT_STA_MASK		INT_HPD
+
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+		reg |= HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+		reg &= ~HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	}
+}
+
+void analogix_dp_stop_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	reg &= ~VIDEO_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+}
+
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable)
+		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
+			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+	else
+		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
+			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
+}
+
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = TX_TERMINAL_CTRL_50_OHM;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
+
+	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
+
+	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
+
+	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
+		TX_CUR1_2X | TX_CUR_16_MA;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
+
+	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
+		CH1_AMP_400_MV | CH0_AMP_400_MV;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
+}
+
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
+{
+	/* Set interrupt pin assertion polarity as high */
+	writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
+
+	/* Clear pending regisers */
+	writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+	writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
+	writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
+	writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+	writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	/* 0:mask,1: unmask */
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+void analogix_dp_reset(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	analogix_dp_stop_video(dp);
+	analogix_dp_enable_video_mute(dp, 0);
+
+	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
+		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
+		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+
+	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
+		SERDES_FIFO_FUNC_EN_N |
+		LS_CLK_DOMAIN_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+
+	usleep_range(20, 30);
+
+	analogix_dp_lane_swap(dp, 0);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
+
+	writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
+	writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
+
+	writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
+	writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
+
+	writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
+	writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
+
+	writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_swreset(struct analogix_dp_device *dp)
+{
+	writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
+}
+
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* 0: mask, 1: unmask */
+	reg = COMMON_INT_MASK_1;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+
+	reg = COMMON_INT_MASK_2;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+
+	reg = COMMON_INT_MASK_3;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+
+	reg = COMMON_INT_MASK_4;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+
+	reg = INT_STA_MASK;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+	if (reg & PLL_LOCK)
+		return PLL_LOCKED;
+	else
+		return PLL_UNLOCKED;
+}
+
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
+		reg |= DP_PLL_PD;
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
+		reg &= ~DP_PLL_PD;
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+	}
+}
+
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				       enum analog_power_block block,
+				       bool enable)
+{
+	u32 reg;
+
+	switch (block) {
+	case AUX_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= AUX_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~AUX_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH0_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH1_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH1_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH1_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH2_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH2_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH2_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH3_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH3_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH3_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case ANALOG_TOTAL:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= DP_PHY_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~DP_PHY_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case POWER_ALL:
+		if (enable) {
+			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
+				CH1_PD | CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
+{
+	u32 reg;
+	int timeout_loop = 0;
+
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
+
+	reg = PLL_LOCK_CHG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+
+	/* Power up PLL */
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		analogix_dp_set_pll_power_down(dp, 0);
+
+		while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+			timeout_loop++;
+			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+				dev_err(dp->dev, "failed to get pll lock status\n");
+				return;
+			}
+			usleep_range(10, 20);
+		}
+	}
+
+	/* Enable Serdes FIFO function and Link symbol clock domain module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
+		| AUX_FUNC_EN_N);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+
+	reg = INT_HPD;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+}
+
+void analogix_dp_init_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	analogix_dp_clear_hotplug_interrupts(dp);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg &= ~(F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		reg = gpio_get_value(dp->hpd_gpio);
+		if (reg)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+		else
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+	} else {
+		/* Parse hotplug interrupt status register */
+		reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+
+		if (reg & PLUG)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+
+		if (reg & HPD_LOST)
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+
+		if (reg & HOTPLUG_CHG)
+			return DP_IRQ_TYPE_HP_CHANGE;
+
+		return DP_IRQ_TYPE_UNKNOWN;
+	}
+}
+
+void analogix_dp_reset_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Disable AUX channel module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg |= AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+void analogix_dp_init_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Clear inerrupts related to AUX channel */
+	reg = RPLY_RECEIV | AUX_ERR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	analogix_dp_reset_aux(dp);
+
+	/* Disable AUX transaction H/W retry */
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
+	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
+
+	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
+	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
+
+	/* Enable AUX channel module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg &= ~AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		if (gpio_get_value(dp->hpd_gpio))
+			return 0;
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+		if (reg & HPD_STATUS)
+			return 0;
+	}
+
+	return -EINVAL;
+}
+
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+	reg &= ~SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+}
+
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
+{
+	int reg;
+	int retval = 0;
+	int timeout_loop = 0;
+
+	/* Enable AUX CH operation */
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+	reg |= AUX_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+
+	/* Is AUX CH command reply received? */
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+	while (!(reg & RPLY_RECEIV)) {
+		timeout_loop++;
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "AUX CH command reply failed!\n");
+			return -ETIMEDOUT;
+		}
+		reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+		usleep_range(10, 11);
+	}
+
+	/* Clear interrupt source for AUX CH command reply */
+	writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	/* Clear interrupt source for AUX CH access error */
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+	if (reg & AUX_ERR) {
+		writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
+		return -EREMOTEIO;
+	}
+
+	/* Check AUX CH error access status */
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
+	if ((reg & AUX_STATUS_MASK) != 0) {
+		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
+			reg & AUX_STATUS_MASK);
+		return -EREMOTEIO;
+	}
+
+	return retval;
+}
+
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				   unsigned int reg_addr,
+				   unsigned char data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+		/* Write data buffer */
+		reg = (unsigned int)data;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+		/*
+		 * Set DisplayPort transaction and write 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				    unsigned int reg_addr,
+				    unsigned char *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+		/*
+		 * Set DisplayPort transaction and read 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+	}
+
+	/* Read data buffer */
+	reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+	*data = (unsigned char)(reg & 0xff);
+
+	return retval;
+}
+
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+			     cur_data_idx++) {
+				reg = data[start_offset + cur_data_idx];
+				writel(reg, dp->reg_base +
+				       ANALOGIX_DP_BUF_DATA_0 +
+				       4 * cur_data_idx);
+			}
+
+			/*
+			 * Set DisplayPort transaction and write
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		/* AUX CH Request Transaction process */
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+			/*
+			 * Set DisplayPort transaction and read
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+		    cur_data_idx++) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			data[start_offset + cur_data_idx] =
+				(unsigned char)reg;
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				  unsigned int device_addr,
+				  unsigned int reg_addr)
+{
+	u32 reg;
+	int retval;
+
+	/* Set EDID device address */
+	reg = device_addr;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+	/* Set offset from base address of EDID device */
+	writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+	/*
+	 * Set I2C transaction and write address
+	 * If bit 3 is 1, DisplayPort transaction.
+	 * If Bit 3 is 0, I2C transaction.
+	 */
+	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
+		AUX_TX_COMM_WRITE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+	/* Start AUX transaction */
+	retval = analogix_dp_start_aux_transaction(dp);
+	if (retval != 0)
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select EDID device */
+		retval = analogix_dp_select_i2c_device(dp, device_addr,
+						       reg_addr);
+		if (retval != 0)
+			continue;
+
+		/*
+		 * Set I2C transaction and read data
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_I2C_TRANSACTION |
+			AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+	}
+
+	/* Read data */
+	if (retval == 0)
+		*data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[])
+{
+	u32 reg;
+	unsigned int i, j;
+	unsigned int cur_data_idx;
+	unsigned int defer = 0;
+	int retval = 0;
+
+	for (i = 0; i < count; i += 16) {
+		for (j = 0; j < 3; j++) {
+			/* Clear AUX CH data buffer */
+			reg = BUF_CLR;
+			writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+			/* Set normal AUX CH command */
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+			reg &= ~ADDR_ONLY;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+
+			/*
+			 * If Rx sends defer, Tx sends only reads
+			 * request without sending address
+			 */
+			if (!defer)
+				retval = analogix_dp_select_i2c_device(
+						dp, device_addr, reg_addr + i);
+			else
+				defer = 0;
+
+			if (retval == 0) {
+				/*
+				 * Set I2C transaction and write data
+				 * If bit 3 is 1, DisplayPort transaction.
+				 * If Bit 3 is 0, I2C transaction.
+				 */
+				reg = AUX_LENGTH(16) |
+					AUX_TX_COMM_I2C_TRANSACTION |
+					AUX_TX_COMM_READ;
+				writel(reg, dp->reg_base +
+					ANALOGIX_DP_AUX_CH_CTL_1);
+
+				/* Start AUX transaction */
+				retval = analogix_dp_start_aux_transaction(dp);
+				if (retval == 0)
+					break;
+
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
+			}
+			/* Check if Rx sends defer */
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
+			if (reg == AUX_RX_COMM_AUX_DEFER ||
+			    reg == AUX_RX_COMM_I2C_DEFER) {
+				dev_err(dp->dev, "Defer: %d\n\n", reg);
+				defer = 1;
+			}
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			edid[i + cur_data_idx] = (unsigned char)reg;
+		}
+	}
+
+	return retval;
+}
+
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
+{
+	u32 reg;
+
+	reg = bwtype;
+	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
+		writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
+}
+
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
+	*bwtype = reg;
+}
+
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
+{
+	u32 reg;
+
+	reg = count;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
+}
+
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
+	*count = reg;
+}
+
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg |= ENHANCED;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg &= ~ENHANCED;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+	}
+}
+
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				      enum pattern_set pattern)
+{
+	u32 reg;
+
+	switch (pattern) {
+	case PRBS7:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case D10_2:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN1:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN2:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case DP_NONE:
+		reg = SCRAMBLING_ENABLE |
+			LINK_QUAL_PATTERN_SET_DISABLE |
+			SW_TRAINING_PATTERN_SET_NORMAL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+}
+
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+	return reg;
+}
+
+void analogix_dp_reset_macro(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
+	reg |= MACRO_RST;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+
+	/* 10 us is the minimum reset time. */
+	usleep_range(10, 20);
+
+	reg &= ~MACRO_RST;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+}
+
+void analogix_dp_init_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	reg = CHA_CRI(4) | CHA_CTRL;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+
+	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
+}
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Configure the input color depth, color space, dynamic range */
+	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info->color_depth << IN_BPC_SHIFT) |
+		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
+
+	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
+	reg &= ~IN_YC_COEFFI_MASK;
+	if (dp->video_info->ycbcr_coeff)
+		reg |= IN_YC_COEFFI_ITU709;
+	else
+		reg |= IN_YC_COEFFI_ITU601;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
+}
+
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	if (!(reg & DET_STA)) {
+		dev_dbg(dp->dev, "Input stream clock not detected.\n");
+		return -EINVAL;
+	}
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
+
+	if (reg & CHA_STA) {
+		dev_dbg(dp->dev, "Input stream clk is changing\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value, u32 n_value)
+{
+	u32 reg;
+
+	if (type == REGISTER_M) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg |= FIX_M_VID;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg = m_value & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
+		reg = (m_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
+		reg = (m_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
+
+		reg = n_value & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		reg = (n_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		reg = (n_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
+	} else  {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg &= ~FIX_M_VID;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
+	}
+}
+
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
+{
+	u32 reg;
+
+	if (type == VIDEO_TIMING_FROM_CAPTURE) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+		reg &= ~FORMAT_SEL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+		reg |= FORMAT_SEL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	}
+}
+
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MODE_SLAVE_MODE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+	}
+}
+
+void analogix_dp_start_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	reg |= VIDEO_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+}
+
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	if (!(reg & STRM_VALID)) {
+		dev_dbg(dp->dev, "Input video stream is not detected.\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
+	reg |= MASTER_VID_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~INTERACE_SCAN_CFG;
+	reg |= (dp->video_info->interlaced << 2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~VSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->v_sync_polarity << 1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~HSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->h_sync_polarity << 0);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+	reg &= ~SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+}
+
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+	reg |= SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
similarity index 64%
rename from drivers/gpu/drm/exynos/exynos_dp_reg.h
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 2e9bd0e..2d878fd 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -1,5 +1,5 @@
 /*
- * Register definition file for Samsung DP driver
+ * Register definition file for Analogix DP core driver
  *
  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  * Author: Jingoo Han <jg1.han@samsung.com>
@@ -9,96 +9,96 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef _EXYNOS_DP_REG_H
-#define _EXYNOS_DP_REG_H
-
-#define EXYNOS_DP_TX_SW_RESET			0x14
-#define EXYNOS_DP_FUNC_EN_1			0x18
-#define EXYNOS_DP_FUNC_EN_2			0x1C
-#define EXYNOS_DP_VIDEO_CTL_1			0x20
-#define EXYNOS_DP_VIDEO_CTL_2			0x24
-#define EXYNOS_DP_VIDEO_CTL_3			0x28
-
-#define EXYNOS_DP_VIDEO_CTL_8			0x3C
-#define EXYNOS_DP_VIDEO_CTL_10			0x44
-
-#define EXYNOS_DP_LANE_MAP			0x35C
-
-#define EXYNOS_DP_ANALOG_CTL_1			0x370
-#define EXYNOS_DP_ANALOG_CTL_2			0x374
-#define EXYNOS_DP_ANALOG_CTL_3			0x378
-#define EXYNOS_DP_PLL_FILTER_CTL_1		0x37C
-#define EXYNOS_DP_TX_AMP_TUNING_CTL		0x380
-
-#define EXYNOS_DP_AUX_HW_RETRY_CTL		0x390
-
-#define EXYNOS_DP_COMMON_INT_STA_1		0x3C4
-#define EXYNOS_DP_COMMON_INT_STA_2		0x3C8
-#define EXYNOS_DP_COMMON_INT_STA_3		0x3CC
-#define EXYNOS_DP_COMMON_INT_STA_4		0x3D0
-#define EXYNOS_DP_INT_STA			0x3DC
-#define EXYNOS_DP_COMMON_INT_MASK_1		0x3E0
-#define EXYNOS_DP_COMMON_INT_MASK_2		0x3E4
-#define EXYNOS_DP_COMMON_INT_MASK_3		0x3E8
-#define EXYNOS_DP_COMMON_INT_MASK_4		0x3EC
-#define EXYNOS_DP_INT_STA_MASK			0x3F8
-#define EXYNOS_DP_INT_CTL			0x3FC
-
-#define EXYNOS_DP_SYS_CTL_1			0x600
-#define EXYNOS_DP_SYS_CTL_2			0x604
-#define EXYNOS_DP_SYS_CTL_3			0x608
-#define EXYNOS_DP_SYS_CTL_4			0x60C
-
-#define EXYNOS_DP_PKT_SEND_CTL			0x640
-#define EXYNOS_DP_HDCP_CTL			0x648
-
-#define EXYNOS_DP_LINK_BW_SET			0x680
-#define EXYNOS_DP_LANE_COUNT_SET		0x684
-#define EXYNOS_DP_TRAINING_PTN_SET		0x688
-#define EXYNOS_DP_LN0_LINK_TRAINING_CTL		0x68C
-#define EXYNOS_DP_LN1_LINK_TRAINING_CTL		0x690
-#define EXYNOS_DP_LN2_LINK_TRAINING_CTL		0x694
-#define EXYNOS_DP_LN3_LINK_TRAINING_CTL		0x698
-
-#define EXYNOS_DP_DEBUG_CTL			0x6C0
-#define EXYNOS_DP_HPD_DEGLITCH_L		0x6C4
-#define EXYNOS_DP_HPD_DEGLITCH_H		0x6C8
-#define EXYNOS_DP_LINK_DEBUG_CTL		0x6E0
-
-#define EXYNOS_DP_M_VID_0			0x700
-#define EXYNOS_DP_M_VID_1			0x704
-#define EXYNOS_DP_M_VID_2			0x708
-#define EXYNOS_DP_N_VID_0			0x70C
-#define EXYNOS_DP_N_VID_1			0x710
-#define EXYNOS_DP_N_VID_2			0x714
-
-#define EXYNOS_DP_PLL_CTL			0x71C
-#define EXYNOS_DP_PHY_PD			0x720
-#define EXYNOS_DP_PHY_TEST			0x724
-
-#define EXYNOS_DP_VIDEO_FIFO_THRD		0x730
-#define EXYNOS_DP_AUDIO_MARGIN			0x73C
-
-#define EXYNOS_DP_M_VID_GEN_FILTER_TH		0x764
-#define EXYNOS_DP_M_AUD_GEN_FILTER_TH		0x778
-#define EXYNOS_DP_AUX_CH_STA			0x780
-#define EXYNOS_DP_AUX_CH_DEFER_CTL		0x788
-#define EXYNOS_DP_AUX_RX_COMM			0x78C
-#define EXYNOS_DP_BUFFER_DATA_CTL		0x790
-#define EXYNOS_DP_AUX_CH_CTL_1			0x794
-#define EXYNOS_DP_AUX_ADDR_7_0			0x798
-#define EXYNOS_DP_AUX_ADDR_15_8			0x79C
-#define EXYNOS_DP_AUX_ADDR_19_16		0x7A0
-#define EXYNOS_DP_AUX_CH_CTL_2			0x7A4
-
-#define EXYNOS_DP_BUF_DATA_0			0x7C0
-
-#define EXYNOS_DP_SOC_GENERAL_CTL		0x800
-
-/* EXYNOS_DP_TX_SW_RESET */
+#ifndef _ANALOGIX_DP_REG_H
+#define _ANALOGIX_DP_REG_H
+
+#define ANALOGIX_DP_TX_SW_RESET			0x14
+#define ANALOGIX_DP_FUNC_EN_1			0x18
+#define ANALOGIX_DP_FUNC_EN_2			0x1C
+#define ANALOGIX_DP_VIDEO_CTL_1			0x20
+#define ANALOGIX_DP_VIDEO_CTL_2			0x24
+#define ANALOGIX_DP_VIDEO_CTL_3			0x28
+
+#define ANALOGIX_DP_VIDEO_CTL_8			0x3C
+#define ANALOGIX_DP_VIDEO_CTL_10			0x44
+
+#define ANALOGIX_DP_LANE_MAP			0x35C
+
+#define ANALOGIX_DP_ANALOG_CTL_1			0x370
+#define ANALOGIX_DP_ANALOG_CTL_2			0x374
+#define ANALOGIX_DP_ANALOG_CTL_3			0x378
+#define ANALOGIX_DP_PLL_FILTER_CTL_1		0x37C
+#define ANALOGIX_DP_TX_AMP_TUNING_CTL		0x380
+
+#define ANALOGIX_DP_AUX_HW_RETRY_CTL		0x390
+
+#define ANALOGIX_DP_COMMON_INT_STA_1		0x3C4
+#define ANALOGIX_DP_COMMON_INT_STA_2		0x3C8
+#define ANALOGIX_DP_COMMON_INT_STA_3		0x3CC
+#define ANALOGIX_DP_COMMON_INT_STA_4		0x3D0
+#define ANALOGIX_DP_INT_STA			0x3DC
+#define ANALOGIX_DP_COMMON_INT_MASK_1		0x3E0
+#define ANALOGIX_DP_COMMON_INT_MASK_2		0x3E4
+#define ANALOGIX_DP_COMMON_INT_MASK_3		0x3E8
+#define ANALOGIX_DP_COMMON_INT_MASK_4		0x3EC
+#define ANALOGIX_DP_INT_STA_MASK			0x3F8
+#define ANALOGIX_DP_INT_CTL			0x3FC
+
+#define ANALOGIX_DP_SYS_CTL_1			0x600
+#define ANALOGIX_DP_SYS_CTL_2			0x604
+#define ANALOGIX_DP_SYS_CTL_3			0x608
+#define ANALOGIX_DP_SYS_CTL_4			0x60C
+
+#define ANALOGIX_DP_PKT_SEND_CTL			0x640
+#define ANALOGIX_DP_HDCP_CTL			0x648
+
+#define ANALOGIX_DP_LINK_BW_SET			0x680
+#define ANALOGIX_DP_LANE_COUNT_SET		0x684
+#define ANALOGIX_DP_TRAINING_PTN_SET		0x688
+#define ANALOGIX_DP_LN0_LINK_TRAINING_CTL		0x68C
+#define ANALOGIX_DP_LN1_LINK_TRAINING_CTL		0x690
+#define ANALOGIX_DP_LN2_LINK_TRAINING_CTL		0x694
+#define ANALOGIX_DP_LN3_LINK_TRAINING_CTL		0x698
+
+#define ANALOGIX_DP_DEBUG_CTL			0x6C0
+#define ANALOGIX_DP_HPD_DEGLITCH_L		0x6C4
+#define ANALOGIX_DP_HPD_DEGLITCH_H		0x6C8
+#define ANALOGIX_DP_LINK_DEBUG_CTL		0x6E0
+
+#define ANALOGIX_DP_M_VID_0			0x700
+#define ANALOGIX_DP_M_VID_1			0x704
+#define ANALOGIX_DP_M_VID_2			0x708
+#define ANALOGIX_DP_N_VID_0			0x70C
+#define ANALOGIX_DP_N_VID_1			0x710
+#define ANALOGIX_DP_N_VID_2			0x714
+
+#define ANALOGIX_DP_PLL_CTL			0x71C
+#define ANALOGIX_DP_PHY_PD			0x720
+#define ANALOGIX_DP_PHY_TEST			0x724
+
+#define ANALOGIX_DP_VIDEO_FIFO_THRD		0x730
+#define ANALOGIX_DP_AUDIO_MARGIN			0x73C
+
+#define ANALOGIX_DP_M_VID_GEN_FILTER_TH		0x764
+#define ANALOGIX_DP_M_AUD_GEN_FILTER_TH		0x778
+#define ANALOGIX_DP_AUX_CH_STA			0x780
+#define ANALOGIX_DP_AUX_CH_DEFER_CTL		0x788
+#define ANALOGIX_DP_AUX_RX_COMM			0x78C
+#define ANALOGIX_DP_BUFFER_DATA_CTL		0x790
+#define ANALOGIX_DP_AUX_CH_CTL_1			0x794
+#define ANALOGIX_DP_AUX_ADDR_7_0			0x798
+#define ANALOGIX_DP_AUX_ADDR_15_8			0x79C
+#define ANALOGIX_DP_AUX_ADDR_19_16		0x7A0
+#define ANALOGIX_DP_AUX_CH_CTL_2			0x7A4
+
+#define ANALOGIX_DP_BUF_DATA_0			0x7C0
+
+#define ANALOGIX_DP_SOC_GENERAL_CTL		0x800
+
+/* ANALOGIX_DP_TX_SW_RESET */
 #define RESET_DP_TX				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_1 */
+/* ANALOGIX_DP_FUNC_EN_1 */
 #define MASTER_VID_FUNC_EN_N			(0x1 << 7)
 #define SLAVE_VID_FUNC_EN_N			(0x1 << 5)
 #define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
@@ -107,17 +107,17 @@
 #define CRC_FUNC_EN_N				(0x1 << 1)
 #define SW_FUNC_EN_N				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_2 */
+/* ANALOGIX_DP_FUNC_EN_2 */
 #define SSC_FUNC_EN_N				(0x1 << 7)
 #define AUX_FUNC_EN_N				(0x1 << 2)
 #define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
 #define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define VIDEO_EN				(0x1 << 7)
 #define HDCP_VIDEO_MUTE				(0x1 << 6)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define IN_D_RANGE_MASK				(0x1 << 7)
 #define IN_D_RANGE_SHIFT			(7)
 #define IN_D_RANGE_CEA				(0x1 << 7)
@@ -134,7 +134,7 @@
 #define IN_COLOR_F_YCBCR422			(0x1 << 0)
 #define IN_COLOR_F_RGB				(0x0 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_3 */
+/* ANALOGIX_DP_VIDEO_CTL_3 */
 #define IN_YC_COEFFI_MASK			(0x1 << 7)
 #define IN_YC_COEFFI_SHIFT			(7)
 #define IN_YC_COEFFI_ITU709			(0x1 << 7)
@@ -144,17 +144,17 @@
 #define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
 #define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
 
-/* EXYNOS_DP_VIDEO_CTL_8 */
+/* ANALOGIX_DP_VIDEO_CTL_8 */
 #define VID_HRES_TH(x)				(((x) & 0xf) << 4)
 #define VID_VRES_TH(x)				(((x) & 0xf) << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_10 */
+/* ANALOGIX_DP_VIDEO_CTL_10 */
 #define FORMAT_SEL				(0x1 << 4)
 #define INTERACE_SCAN_CFG			(0x1 << 2)
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
-/* EXYNOS_DP_LANE_MAP */
+/* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
 #define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
@@ -172,30 +172,30 @@
 #define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
 #define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_1 */
+/* ANALOGIX_DP_ANALOG_CTL_1 */
 #define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
 
-/* EXYNOS_DP_ANALOG_CTL_2 */
+/* ANALOGIX_DP_ANALOG_CTL_2 */
 #define SEL_24M					(0x1 << 3)
 #define TX_DVDD_BIT_1_0625V			(0x4 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_3 */
+/* ANALOGIX_DP_ANALOG_CTL_3 */
 #define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
 #define VCO_BIT_600_MICRO			(0x5 << 0)
 
-/* EXYNOS_DP_PLL_FILTER_CTL_1 */
+/* ANALOGIX_DP_PLL_FILTER_CTL_1 */
 #define PD_RING_OSC				(0x1 << 6)
 #define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
 #define TX_CUR1_2X				(0x1 << 2)
 #define TX_CUR_16_MA				(0x3 << 0)
 
-/* EXYNOS_DP_TX_AMP_TUNING_CTL */
+/* ANALOGIX_DP_TX_AMP_TUNING_CTL */
 #define CH3_AMP_400_MV				(0x0 << 24)
 #define CH2_AMP_400_MV				(0x0 << 16)
 #define CH1_AMP_400_MV				(0x0 << 8)
 #define CH0_AMP_400_MV				(0x0 << 0)
 
-/* EXYNOS_DP_AUX_HW_RETRY_CTL */
+/* ANALOGIX_DP_AUX_HW_RETRY_CTL */
 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x)	(((x) & 0x7) << 8)
 #define AUX_HW_RETRY_INTERVAL_MASK		(0x3 << 3)
 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS	(0x0 << 3)
@@ -204,7 +204,7 @@
 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS	(0x3 << 3)
 #define AUX_HW_RETRY_COUNT_SEL(x)		(((x) & 0x7) << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_1 */
+/* ANALOGIX_DP_COMMON_INT_STA_1 */
 #define VSYNC_DET				(0x1 << 7)
 #define PLL_LOCK_CHG				(0x1 << 6)
 #define SPDIF_ERR				(0x1 << 5)
@@ -214,19 +214,19 @@
 #define VID_CLK_CHG				(0x1 << 1)
 #define SW_INT					(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_2 */
+/* ANALOGIX_DP_COMMON_INT_STA_2 */
 #define ENC_EN_CHG				(0x1 << 6)
 #define HW_BKSV_RDY				(0x1 << 3)
 #define HW_SHA_DONE				(0x1 << 2)
 #define HW_AUTH_STATE_CHG			(0x1 << 1)
 #define HW_AUTH_DONE				(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_3 */
+/* ANALOGIX_DP_COMMON_INT_STA_3 */
 #define AFIFO_UNDER				(0x1 << 7)
 #define AFIFO_OVER				(0x1 << 6)
 #define R0_CHK_FLAG				(0x1 << 5)
 
-/* EXYNOS_DP_COMMON_INT_STA_4 */
+/* ANALOGIX_DP_COMMON_INT_STA_4 */
 #define PSR_ACTIVE				(0x1 << 7)
 #define PSR_INACTIVE				(0x1 << 6)
 #define SPDIF_BI_PHASE_ERR			(0x1 << 5)
@@ -234,29 +234,29 @@
 #define HPD_LOST				(0x1 << 1)
 #define PLUG					(0x1 << 0)
 
-/* EXYNOS_DP_INT_STA */
+/* ANALOGIX_DP_INT_STA */
 #define INT_HPD					(0x1 << 6)
 #define HW_TRAINING_FINISH			(0x1 << 5)
 #define RPLY_RECEIV				(0x1 << 1)
 #define AUX_ERR					(0x1 << 0)
 
-/* EXYNOS_DP_INT_CTL */
+/* ANALOGIX_DP_INT_CTL */
 #define SOFT_INT_CTRL				(0x1 << 2)
 #define INT_POL1				(0x1 << 1)
 #define INT_POL0				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_1 */
+/* ANALOGIX_DP_SYS_CTL_1 */
 #define DET_STA					(0x1 << 2)
 #define FORCE_DET				(0x1 << 1)
 #define DET_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_2 */
+/* ANALOGIX_DP_SYS_CTL_2 */
 #define CHA_CRI(x)				(((x) & 0xf) << 4)
 #define CHA_STA					(0x1 << 2)
 #define FORCE_CHA				(0x1 << 1)
 #define CHA_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_3 */
+/* ANALOGIX_DP_SYS_CTL_3 */
 #define HPD_STATUS				(0x1 << 6)
 #define F_HPD					(0x1 << 5)
 #define HPD_CTRL				(0x1 << 4)
@@ -265,13 +265,13 @@
 #define F_VALID					(0x1 << 1)
 #define VALID_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_4 */
+/* ANALOGIX_DP_SYS_CTL_4 */
 #define FIX_M_AUD				(0x1 << 4)
 #define ENHANCED				(0x1 << 3)
 #define FIX_M_VID				(0x1 << 2)
 #define M_VID_UPDATE_CTRL			(0x3 << 0)
 
-/* EXYNOS_DP_TRAINING_PTN_SET */
+/* ANALOGIX_DP_TRAINING_PTN_SET */
 #define SCRAMBLER_TYPE				(0x1 << 9)
 #define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
 #define SCRAMBLING_DISABLE			(0x1 << 5)
@@ -285,24 +285,24 @@
 #define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
 #define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
 
-/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+/* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */
 #define PRE_EMPHASIS_SET_MASK			(0x3 << 3)
 #define PRE_EMPHASIS_SET_SHIFT			(3)
 
-/* EXYNOS_DP_DEBUG_CTL */
+/* ANALOGIX_DP_DEBUG_CTL */
 #define PLL_LOCK				(0x1 << 4)
 #define F_PLL_LOCK				(0x1 << 3)
 #define PLL_LOCK_CTRL				(0x1 << 2)
 #define PN_INV					(0x1 << 0)
 
-/* EXYNOS_DP_PLL_CTL */
+/* ANALOGIX_DP_PLL_CTL */
 #define DP_PLL_PD				(0x1 << 7)
 #define DP_PLL_RESET				(0x1 << 6)
 #define DP_PLL_LOOP_BIT_DEFAULT			(0x1 << 4)
 #define DP_PLL_REF_BIT_1_1250V			(0x5 << 0)
 #define DP_PLL_REF_BIT_1_2500V			(0x7 << 0)
 
-/* EXYNOS_DP_PHY_PD */
+/* ANALOGIX_DP_PHY_PD */
 #define DP_PHY_PD				(0x1 << 5)
 #define AUX_PD					(0x1 << 4)
 #define CH3_PD					(0x1 << 3)
@@ -310,28 +310,28 @@
 #define CH1_PD					(0x1 << 1)
 #define CH0_PD					(0x1 << 0)
 
-/* EXYNOS_DP_PHY_TEST */
+/* ANALOGIX_DP_PHY_TEST */
 #define MACRO_RST				(0x1 << 5)
 #define CH1_TEST				(0x1 << 1)
 #define CH0_TEST				(0x1 << 0)
 
-/* EXYNOS_DP_AUX_CH_STA */
+/* ANALOGIX_DP_AUX_CH_STA */
 #define AUX_BUSY				(0x1 << 4)
 #define AUX_STATUS_MASK				(0xf << 0)
 
-/* EXYNOS_DP_AUX_CH_DEFER_CTL */
+/* ANALOGIX_DP_AUX_CH_DEFER_CTL */
 #define DEFER_CTRL_EN				(0x1 << 7)
 #define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
 
-/* EXYNOS_DP_AUX_RX_COMM */
+/* ANALOGIX_DP_AUX_RX_COMM */
 #define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
 #define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
 
-/* EXYNOS_DP_BUFFER_DATA_CTL */
+/* ANALOGIX_DP_BUFFER_DATA_CTL */
 #define BUF_CLR					(0x1 << 7)
 #define BUF_DATA_COUNT(x)			(((x) & 0x1f) << 0)
 
-/* EXYNOS_DP_AUX_CH_CTL_1 */
+/* ANALOGIX_DP_AUX_CH_CTL_1 */
 #define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
 #define AUX_TX_COMM_MASK			(0xf << 0)
 #define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
@@ -340,20 +340,20 @@
 #define AUX_TX_COMM_WRITE			(0x0 << 0)
 #define AUX_TX_COMM_READ			(0x1 << 0)
 
-/* EXYNOS_DP_AUX_ADDR_7_0 */
+/* ANALOGIX_DP_AUX_ADDR_7_0 */
 #define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_15_8 */
+/* ANALOGIX_DP_AUX_ADDR_15_8 */
 #define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_19_16 */
+/* ANALOGIX_DP_AUX_ADDR_19_16 */
 #define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
 
-/* EXYNOS_DP_AUX_CH_CTL_2 */
+/* ANALOGIX_DP_AUX_CH_CTL_2 */
 #define ADDR_ONLY				(0x1 << 1)
 #define AUX_EN					(0x1 << 0)
 
-/* EXYNOS_DP_SOC_GENERAL_CTL */
+/* ANALOGIX_DP_SOC_GENERAL_CTL */
 #define AUDIO_MODE_SPDIF_MODE			(0x1 << 8)
 #define AUDIO_MODE_MASTER_MODE			(0x0 << 8)
 #define MASTER_VIDEO_INTERLACE_EN		(0x1 << 4)
@@ -363,4 +363,4 @@
 #define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
 #define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
 
-#endif /* _EXYNOS_DP_REG_H */
+#endif /* _ANALOGIX_DP_REG_H */
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index bd1a415..5f74f80 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -55,8 +55,9 @@ config DRM_EXYNOS_DSI
 	  This enables support for Exynos MIPI-DSI device.
 
 config DRM_EXYNOS_DP
-	bool "EXYNOS DRM DP driver support"
+	bool "EXYNOS specific extensions for Analogix DP driver"
 	depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON)
+	select DRM_ANALOGIX_DP
 	default DRM_EXYNOS
 	select DRM_PANEL
 	help
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index 02aecfe..4453798 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -13,7 +13,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON)	+= exynos5433_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON)	+= exynos7_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DPI)	+= exynos_drm_dpi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DSI)	+= exynos_drm_dsi.o
-exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o exynos_dp_reg.o
+exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)	+= exynos_hdmi.o exynos_mixer.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI)	+= exynos_drm_vidi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_G2D)	+= exynos_drm_g2d.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
new file mode 100644
index 0000000..7e1be72
--- /dev/null
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -0,0 +1,306 @@
+/*
+ * Samsung SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_graph.h>
+#include <video/of_display_timing.h>
+#include <video/of_videomode.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_crtc_helper.h>
+
+#include <drm/bridge/analogix_dp.h>
+#include <drm/exynos_drm.h>
+
+#include "exynos_drm_crtc.h"
+
+#define plat_data_to_dp(pd) \
+		container_of(pd, struct exynos_dp_device, plat_data)
+
+struct exynos_dp_device {
+	struct drm_encoder         encoder;
+	struct drm_bridge          *ptn_bridge;
+	struct drm_device          *drm_dev;
+	struct device              *dev;
+
+	struct exynos_drm_panel_info priv;
+	struct analogix_dp_plat_data plat_data;
+};
+
+int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
+				bool enable)
+{
+	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct exynos_drm_crtc *crtc;
+
+	if (!encoder)
+		return -1;
+
+	crtc = to_exynos_crtc(encoder->crtc);
+	if (crtc && crtc->ops && crtc->ops->clock_enable)
+		crtc->ops->clock_enable(crtc, enable);
+
+	return 0;
+}
+
+static int exynos_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	return exynos_dp_crtc_clock_enable(plat_data, true);
+}
+
+static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
+{
+	return exynos_dp_crtc_clock_enable(plat_data, false);
+}
+
+static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
+			       struct drm_connector *connector)
+{
+	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
+	struct drm_display_mode *mode;
+
+	if (dp->plat_data.panel)
+		return 0;
+
+	mode = drm_mode_create(connector->dev);
+	if (!mode) {
+		DRM_ERROR("failed to create a new display mode.\n");
+		return 0;
+	}
+
+	drm_display_mode_from_videomode(&dp->priv.vm, mode);
+	mode->width_mm = dp->priv.width_mm;
+	mode->height_mm = dp->priv.height_mm;
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_set_name(mode);
+	drm_mode_probed_add(connector, mode);
+
+	return 1;
+}
+
+static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+				   struct drm_bridge *bridge)
+{
+	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
+	struct drm_encoder *encoder = &dp->encoder;
+	int ret;
+
+	/* Pre-empt DP connector creation if there's a bridge */
+	if (dp->ptn_bridge) {
+		bridge->next = dp->ptn_bridge;
+		dp->ptn_bridge->encoder = encoder;
+		ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
+		if (ret) {
+			DRM_ERROR("Failed to attach bridge to drm\n");
+			bridge->next = NULL;
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+				 const struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
+static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
+	.mode_fixup = exynos_dp_mode_fixup,
+	.mode_set = exynos_dp_mode_set,
+	.enable = exynos_dp_enable,
+	.disable = exynos_dp_disable,
+};
+
+static struct drm_encoder_funcs exynos_dp_encoder_funcs = {
+	.destroy = drm_encoder_cleanup,
+};
+
+static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
+{
+	int ret;
+
+	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
+			       OF_USE_NATIVE_MODE);
+	if (ret) {
+		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
+		return ret;
+	}
+	return 0;
+}
+
+static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
+{
+	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = data;
+	int pipe, ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	dp->dev = dev;
+	dp->drm_dev = drm_dev;
+
+	dp->plat_data.power_on = exynos_dp_poweron;
+	dp->plat_data.power_off = exynos_dp_poweroff;
+	dp->plat_data.get_modes = exynos_dp_get_modes;
+	dp->plat_data.attach = exynos_dp_bridge_attach;
+
+	if (!dp->plat_data.panel || !dp->ptn_bridge) {
+		ret = exynos_dp_dt_parse_panel(dp);
+		if (ret)
+			return ret;
+	}
+
+	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
+						  EXYNOS_DISPLAY_TYPE_LCD);
+	if (pipe < 0)
+		return pipe;
+
+	encoder->possible_crtcs = 1 << pipe;
+
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
+			 DRM_MODE_ENCODER_TMDS);
+
+	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
+
+	return analogix_dp_bind(dev, dp->drm_dev, encoder, &dp->plat_data);
+}
+
+static void exynos_dp_unbind(struct device *dev, struct device *master,
+			     void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops exynos_dp_ops = {
+	.bind	= exynos_dp_bind,
+	.unbind	= exynos_dp_unbind,
+};
+
+static int exynos_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *bridge_node, *endpoint;
+	struct exynos_dp_device *dp;
+
+	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
+			  GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver would take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	panel_node = of_parse_phandle(dev->of_node, "panel", 0);
+	if (panel_node) {
+		dp->plat_data.panel = of_drm_find_panel(panel_node);
+		of_node_put(panel_node);
+		if (!dp->plat_data.panel)
+			return -EPROBE_DEFER;
+	}
+
+	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
+	if (endpoint) {
+		bridge_node = of_graph_get_remote_port_parent(endpoint);
+		if (bridge_node) {
+			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
+			of_node_put(bridge_node);
+			if (!dp->ptn_bridge)
+				return -EPROBE_DEFER;
+		} else {
+			return -EPROBE_DEFER;
+		}
+	}
+
+	return component_add(&pdev->dev, &exynos_dp_ops);
+}
+
+static int exynos_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &exynos_dp_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int exynos_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops exynos_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
+};
+
+static const struct of_device_id exynos_dp_match[] = {
+	{ .compatible = "samsung,exynos5-dp" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, exynos_dp_match);
+
+struct platform_driver dp_driver = {
+	.probe		= exynos_dp_probe,
+	.remove		= exynos_dp_remove,
+	.driver		= {
+		.name	= "exynos-dp",
+		.owner	= THIS_MODULE,
+		.pm	= &exynos_dp_pm_ops,
+		.of_match_table = exynos_dp_match,
+	},
+};
+
+MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
+MODULE_DESCRIPTION("Samsung Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
deleted file mode 100644
index 7ff754f..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Header file for Samsung DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef _EXYNOS_DP_CORE_H
-#define _EXYNOS_DP_CORE_H
-
-#include <drm/drm_crtc.h>
-#include <drm/drm_dp_helper.h>
-#include <drm/exynos_drm.h>
-
-#include "exynos_drm_drv.h"
-
-#define DP_TIMEOUT_LOOP_COUNT 100
-#define MAX_CR_LOOP 5
-#define MAX_EQ_LOOP 5
-
-enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
-};
-
-enum link_lane_count_type {
-	LANE_COUNT1 = 1,
-	LANE_COUNT2 = 2,
-	LANE_COUNT4 = 4
-};
-
-enum link_training_state {
-	START,
-	CLOCK_RECOVERY,
-	EQUALIZER_TRAINING,
-	FINISHED,
-	FAILED
-};
-
-enum voltage_swing_level {
-	VOLTAGE_LEVEL_0,
-	VOLTAGE_LEVEL_1,
-	VOLTAGE_LEVEL_2,
-	VOLTAGE_LEVEL_3,
-};
-
-enum pre_emphasis_level {
-	PRE_EMPHASIS_LEVEL_0,
-	PRE_EMPHASIS_LEVEL_1,
-	PRE_EMPHASIS_LEVEL_2,
-	PRE_EMPHASIS_LEVEL_3,
-};
-
-enum pattern_set {
-	PRBS7,
-	D10_2,
-	TRAINING_PTN1,
-	TRAINING_PTN2,
-	DP_NONE
-};
-
-enum color_space {
-	COLOR_RGB,
-	COLOR_YCBCR422,
-	COLOR_YCBCR444
-};
-
-enum color_depth {
-	COLOR_6,
-	COLOR_8,
-	COLOR_10,
-	COLOR_12
-};
-
-enum color_coefficient {
-	COLOR_YCBCR601,
-	COLOR_YCBCR709
-};
-
-enum dynamic_range {
-	VESA,
-	CEA
-};
-
-enum pll_status {
-	PLL_UNLOCKED,
-	PLL_LOCKED
-};
-
-enum clock_recovery_m_value_type {
-	CALCULATED_M,
-	REGISTER_M
-};
-
-enum video_timing_recognition_type {
-	VIDEO_TIMING_FROM_CAPTURE,
-	VIDEO_TIMING_FROM_REGISTER
-};
-
-enum analog_power_block {
-	AUX_BLOCK,
-	CH0_BLOCK,
-	CH1_BLOCK,
-	CH2_BLOCK,
-	CH3_BLOCK,
-	ANALOG_TOTAL,
-	POWER_ALL
-};
-
-enum dp_irq_type {
-	DP_IRQ_TYPE_HP_CABLE_IN,
-	DP_IRQ_TYPE_HP_CABLE_OUT,
-	DP_IRQ_TYPE_HP_CHANGE,
-	DP_IRQ_TYPE_UNKNOWN,
-};
-
-struct video_info {
-	char *name;
-
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
-
-	enum color_space color_space;
-	enum dynamic_range dynamic_range;
-	enum color_coefficient ycbcr_coeff;
-	enum color_depth color_depth;
-
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
-};
-
-struct link_train {
-	int eq_loop;
-	int cr_loop[4];
-
-	u8 link_rate;
-	u8 lane_count;
-	u8 training_lane[4];
-
-	enum link_training_state lt_state;
-};
-
-struct exynos_dp_device {
-	struct drm_encoder	encoder;
-	struct device		*dev;
-	struct drm_device	*drm_dev;
-	struct drm_connector	connector;
-	struct drm_panel	*panel;
-	struct drm_bridge	*bridge;
-	struct drm_bridge	*ptn_bridge;
-	struct clk		*clock;
-	unsigned int		irq;
-	void __iomem		*reg_base;
-
-	struct video_info	*video_info;
-	struct link_train	link_train;
-	struct work_struct	hotplug_work;
-	struct phy		*phy;
-	int			dpms_mode;
-	int			hpd_gpio;
-
-	struct exynos_drm_panel_info priv;
-};
-
-/* exynos_dp_reg.c */
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_stop_video(struct exynos_dp_device *dp);
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
-void exynos_dp_reset(struct exynos_dp_device *dp);
-void exynos_dp_swreset(struct exynos_dp_device *dp);
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				     enum analog_power_block block,
-				     bool enable);
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
-void exynos_dp_init_hpd(struct exynos_dp_device *dp);
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
-void exynos_dp_reset_aux(struct exynos_dp_device *dp);
-void exynos_dp_init_aux(struct exynos_dp_device *dp);
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				 unsigned int reg_addr,
-				 unsigned char data);
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				  unsigned int reg_addr,
-				  unsigned char *data);
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				  unsigned int reg_addr,
-				  unsigned int count,
-				  unsigned char data[]);
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				   unsigned int reg_addr,
-				   unsigned int count,
-				   unsigned char data[]);
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				 unsigned int device_addr,
-				 unsigned int reg_addr,
-				 unsigned int *data);
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				  unsigned int device_addr,
-				  unsigned int reg_addr,
-				  unsigned int count,
-				  unsigned char edid[]);
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				    enum pattern_set pattern);
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane);
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane);
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane);
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane);
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
-void exynos_dp_reset_macro(struct exynos_dp_device *dp);
-void exynos_dp_init_video(struct exynos_dp_device *dp);
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-			       enum clock_recovery_m_value_type type,
-			       u32 m_value,
-			       u32 n_value);
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_start_video(struct exynos_dp_device *dp);
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
-#endif /* _EXYNOS_DP_CORE_H */
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
deleted file mode 100644
index 5aff19a..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
+++ /dev/null
@@ -1,1259 +0,0 @@
-/*
- * Samsung DP (Display port) register interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-
-#include "exynos_dp_core.h"
-#include "exynos_dp_reg.h"
-
-#define COMMON_INT_MASK_1	0
-#define COMMON_INT_MASK_2	0
-#define COMMON_INT_MASK_3	0
-#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
-#define INT_STA_MASK		INT_HPD
-
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg |= HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg &= ~HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	}
-}
-
-void exynos_dp_stop_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg &= ~VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable)
-		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
-	else
-		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
-
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
-}
-
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = TX_TERMINAL_CTRL_50_OHM;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
-
-	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
-
-	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
-
-	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
-		TX_CUR1_2X | TX_CUR_16_MA;
-	writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
-
-	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
-		CH1_AMP_400_MV | CH0_AMP_400_MV;
-	writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
-}
-
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
-{
-	/* Set interrupt pin assertion polarity as high */
-	writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
-
-	/* Clear pending regisers */
-	writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-	writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
-	writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
-	writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-	writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* 0:mask,1: unmask */
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-	writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-void exynos_dp_reset(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	exynos_dp_stop_video(dp);
-	exynos_dp_enable_video_mute(dp, 0);
-
-	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
-		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
-		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
-		SERDES_FIFO_FUNC_EN_N |
-		LS_CLK_DOMAIN_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-
-	usleep_range(20, 30);
-
-	exynos_dp_lane_swap(dp, 0);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
-	writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
-
-	writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
-	writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
-
-	writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
-	writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
-
-	writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
-	writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
-
-	writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_swreset(struct exynos_dp_device *dp)
-{
-	writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
-}
-
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* 0: mask, 1: unmask */
-	reg = COMMON_INT_MASK_1;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-
-	reg = COMMON_INT_MASK_2;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-
-	reg = COMMON_INT_MASK_3;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-
-	reg = COMMON_INT_MASK_4;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-
-	reg = INT_STA_MASK;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	if (reg & PLL_LOCK)
-		return PLL_LOCKED;
-	else
-		return PLL_UNLOCKED;
-}
-
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg |= DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg &= ~DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	}
-}
-
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				     enum analog_power_block block,
-				     bool enable)
-{
-	u32 reg;
-
-	switch (block) {
-	case AUX_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH0_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH1_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH2_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH3_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case ANALOG_TOTAL:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case POWER_ALL:
-		if (enable) {
-			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
-				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
-{
-	u32 reg;
-	int timeout_loop = 0;
-
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
-
-	reg = PLL_LOCK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-
-	/* Power up PLL */
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-		exynos_dp_set_pll_power_down(dp, 0);
-
-		while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-			timeout_loop++;
-			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-				dev_err(dp->dev, "failed to get pll lock status\n");
-				return;
-			}
-			usleep_range(10, 20);
-		}
-	}
-
-	/* Enable Serdes FIFO function and Link symbol clock domain module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
-		| AUX_FUNC_EN_N);
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-	reg = INT_HPD;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-}
-
-void exynos_dp_init_hpd(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	exynos_dp_clear_hotplug_interrupts(dp);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	reg &= ~(F_HPD | HPD_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-}
-
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		reg = gpio_get_value(dp->hpd_gpio);
-		if (reg)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-		else
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-	} else {
-		/* Parse hotplug interrupt status register */
-		reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-		if (reg & PLUG)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-
-		if (reg & HPD_LOST)
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-
-		if (reg & HOTPLUG_CHG)
-			return DP_IRQ_TYPE_HP_CHANGE;
-
-		return DP_IRQ_TYPE_UNKNOWN;
-	}
-}
-
-void exynos_dp_reset_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Disable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg |= AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_init_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Clear inerrupts related to AUX channel */
-	reg = RPLY_RECEIV | AUX_ERR;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	exynos_dp_reset_aux(dp);
-
-	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
-	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
-
-	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
-	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
-
-	/* Enable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		if (gpio_get_value(dp->hpd_gpio))
-			return 0;
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-		if (reg & HPD_STATUS)
-			return 0;
-	}
-
-	return -EINVAL;
-}
-
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-}
-
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
-{
-	int reg;
-	int retval = 0;
-	int timeout_loop = 0;
-
-	/* Enable AUX CH operation */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-	reg |= AUX_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-	/* Is AUX CH command reply received? */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	while (!(reg & RPLY_RECEIV)) {
-		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "AUX CH command reply failed!\n");
-			return -ETIMEDOUT;
-		}
-		reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-		usleep_range(10, 11);
-	}
-
-	/* Clear interrupt source for AUX CH command reply */
-	writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* Clear interrupt source for AUX CH access error */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	if (reg & AUX_ERR) {
-		writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
-		return -EREMOTEIO;
-	}
-
-	/* Check AUX CH error access status */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
-	if ((reg & AUX_STATUS_MASK) != 0) {
-		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
-			reg & AUX_STATUS_MASK);
-		return -EREMOTEIO;
-	}
-
-	return retval;
-}
-
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				 unsigned int reg_addr,
-				 unsigned char data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/* Write data buffer */
-		reg = (unsigned int)data;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-		/*
-		 * Set DisplayPort transaction and write 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				  unsigned int reg_addr,
-				  unsigned char *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/*
-		 * Set DisplayPort transaction and read 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-	}
-
-	/* Read data buffer */
-	reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-	*data = (unsigned char)(reg & 0xff);
-
-	return retval;
-}
-
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				  unsigned int reg_addr,
-				  unsigned int count,
-				  unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-			     cur_data_idx++) {
-				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
-			}
-
-			/*
-			 * Set DisplayPort transaction and write
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				   unsigned int reg_addr,
-				   unsigned int count,
-				   unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		/* AUX CH Request Transaction process */
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			/*
-			 * Set DisplayPort transaction and read
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-		    cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			data[start_offset + cur_data_idx] =
-				(unsigned char)reg;
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
-{
-	u32 reg;
-	int retval;
-
-	/* Set EDID device address */
-	reg = device_addr;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-	/* Set offset from base address of EDID device */
-	writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	/*
-	 * Set I2C transaction and write address
-	 * If bit 3 is 1, DisplayPort transaction.
-	 * If Bit 3 is 0, I2C transaction.
-	 */
-	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
-		AUX_TX_COMM_WRITE;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction(dp);
-	if (retval != 0)
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				 unsigned int device_addr,
-				 unsigned int reg_addr,
-				 unsigned int *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select EDID device */
-		retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
-		if (retval != 0)
-			continue;
-
-		/*
-		 * Set I2C transaction and read data
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_I2C_TRANSACTION |
-			AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-	}
-
-	/* Read data */
-	if (retval == 0)
-		*data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				  unsigned int device_addr,
-				  unsigned int reg_addr,
-				  unsigned int count,
-				  unsigned char edid[])
-{
-	u32 reg;
-	unsigned int i, j;
-	unsigned int cur_data_idx;
-	unsigned int defer = 0;
-	int retval = 0;
-
-	for (i = 0; i < count; i += 16) {
-		for (j = 0; j < 3; j++) {
-			/* Clear AUX CH data buffer */
-			reg = BUF_CLR;
-			writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-			/* Set normal AUX CH command */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-			reg &= ~ADDR_ONLY;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-			/*
-			 * If Rx sends defer, Tx sends only reads
-			 * request without sending address
-			 */
-			if (!defer)
-				retval = exynos_dp_select_i2c_device(
-						dp, device_addr, reg_addr + i);
-			else
-				defer = 0;
-
-			if (retval == 0) {
-				/*
-				 * Set I2C transaction and write data
-				 * If bit 3 is 1, DisplayPort transaction.
-				 * If Bit 3 is 0, I2C transaction.
-				 */
-				reg = AUX_LENGTH(16) |
-				      AUX_TX_COMM_I2C_TRANSACTION |
-				      AUX_TX_COMM_READ;
-				writel(reg, dp->reg_base +
-				       EXYNOS_DP_AUX_CH_CTL_1);
-
-				/* Start AUX transaction */
-				retval = exynos_dp_start_aux_transaction(dp);
-				if (retval == 0)
-					break;
-
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
-			}
-			/* Check if Rx sends defer */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
-			if (reg == AUX_RX_COMM_AUX_DEFER ||
-			    reg == AUX_RX_COMM_I2C_DEFER) {
-				dev_err(dp->dev, "Defer: %d\n\n", reg);
-				defer = 1;
-			}
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			edid[i + cur_data_idx] = (unsigned char)reg;
-		}
-	}
-
-	return retval;
-}
-
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
-{
-	u32 reg;
-
-	reg = bwtype;
-	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
-		writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-}
-
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-	*bwtype = reg;
-}
-
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
-{
-	u32 reg;
-
-	reg = count;
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-}
-
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-	*count = reg;
-}
-
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	}
-}
-
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				    enum pattern_set pattern)
-{
-	u32 reg;
-
-	switch (pattern) {
-	case PRBS7:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case D10_2:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN1:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN2:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case DP_NONE:
-		reg = SCRAMBLING_ENABLE |
-			LINK_QUAL_PATTERN_SET_DISABLE |
-			SW_TRAINING_PATTERN_SET_NORMAL;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	return reg;
-}
-
-void exynos_dp_reset_macro(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
-	reg |= MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	/* 10 us is the minimum reset time. */
-	usleep_range(10, 20);
-
-	reg &= ~MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-}
-
-void exynos_dp_init_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = CHA_CRI(4) | CHA_CTRL;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
-}
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
-
-	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
-		reg |= IN_YC_COEFFI_ITU709;
-	else
-		reg |= IN_YC_COEFFI_ITU601;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-}
-
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	if (!(reg & DET_STA)) {
-		dev_dbg(dp->dev, "Input stream clock not detected.\n");
-		return -EINVAL;
-	}
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
-
-	if (reg & CHA_STA) {
-		dev_dbg(dp->dev, "Input stream clk is changing\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-			       enum clock_recovery_m_value_type type,
-			       u32 m_value,
-			       u32 n_value)
-{
-	u32 reg;
-
-	if (type == REGISTER_M) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg = m_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
-		reg = (m_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
-		reg = (m_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
-
-		reg = n_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
-		reg = (n_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
-		reg = (n_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
-	} else  {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
-		writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
-	}
-}
-
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
-{
-	u32 reg;
-
-	if (type == VIDEO_TIMING_FROM_CAPTURE) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg &= ~FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg |= FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	}
-}
-
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MODE_SLAVE_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	}
-}
-
-void exynos_dp_start_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg |= VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	if (!(reg & STRM_VALID)) {
-		dev_dbg(dp->dev, "Input video stream is not detected.\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
-	reg |= MASTER_VID_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-	writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg &= ~SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
-
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg |= SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
new file mode 100644
index 0000000..8b4ffad
--- /dev/null
+++ b/include/drm/bridge/analogix_dp.h
@@ -0,0 +1,24 @@
+#ifndef _ANALOGIX_DP_H_
+#define _ANALOGIX_DP_H_
+
+#include <drm/drm_crtc.h>
+
+struct analogix_dp_plat_data {
+	struct drm_panel *panel;
+
+	int (*power_on)(struct analogix_dp_plat_data *);
+	int (*power_off)(struct analogix_dp_plat_data *);
+	int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *);
+	int (*get_modes)(struct analogix_dp_plat_data *,
+			 struct drm_connector *);
+};
+
+int analogix_dp_resume(struct device *dev);
+int analogix_dp_suspend(struct device *dev);
+
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct drm_encoder *encoder,
+		     struct analogix_dp_plat_data *plat_data);
+void analogix_dp_unbind(struct device *dev, struct device *master, void *data);
+
+#endif /* _ANALOGIX_DP_H_ */
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-01  5:49   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:49 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe-6d6DIl74uiNBDgjK7y7TUQ, Kukjin Kim, Krzysztof Kozlowski,
	Mark Yao
  Cc: Russell King, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	dianders-F7+t8E8rja9Wk0Htik3J/w, seanpaul-F7+t8E8rja9Wk0Htik3J/w,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt-sgV2jX0FEOL9JmXXK+q4OQ,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Yakir Yang,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Split the dp core driver from exynos directory to bridge
directory, and rename the core driver to analogix_dp_*,
leave the platform code to analogix_dp-exynos.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v4:
- Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
- Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
- Take Archit suggest, create a separate folder for analogix code in bridge/

Changes in v3:
- Take Thierry Reding suggest, move exynos's video_timing code
  to analogix_dp-exynos platform driver, add get_modes method
  to struct analogix_dp_plat_data.
- Take Heiko suggest, rename some "samsung*" dts propery to "analogix*".

Changes in v2:
- Take Jingoo Han suggest, remove new copyright
- Fix compiled failed dut to analogix_dp_device misspell

 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 .../analogix/analogix_dp_core.c}                   |  817 ++++++-------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  283 +++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1265 ++++++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  258 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  306 +++++
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 -----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1259 -------------------
 include/drm/bridge/analogix_dp.h                   |   24 +
 14 files changed, 2357 insertions(+), 2150 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 rename drivers/gpu/drm/{exynos/exynos_dp_core.c => bridge/analogix/analogix_dp_core.c} (50%)
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (64%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 include/drm/bridge/analogix_dp.h

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 2de52a5..7b5b77a 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -29,4 +29,6 @@ config DRM_PARADE_PS8622
 	---help---
 	  Parade eDP-LVDS bridge chip driver.
 
+source "drivers/gpu/drm/bridge/analogix/Kconfig"
+
 endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index e2eef1c..5366c6b 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -3,3 +3,4 @@ ccflags-y := -Iinclude/drm
 obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
new file mode 100644
index 0000000..5ff6551
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -0,0 +1,4 @@
+config DRM_ANALOGIX_DP
+	tristate
+	depends on DRM
+	select DRM_KMS_HELPER
diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
new file mode 100644
index 0000000..9107b86
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
similarity index 50%
rename from drivers/gpu/drm/exynos/exynos_dp_core.c
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index bed0252..7d62f22 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1,14 +1,14 @@
 /*
- * Samsung SoC DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
+* Analogix DP (Display Port) core interface driver.
+*
+* Copyright (C) 2012 Samsung Electronics Co., Ltd.
+* Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2 of the License, or (at your
+* option) any later version.
+*/
 
 #include <linux/module.h>
 #include <linux/platform_device.h>
@@ -18,12 +18,9 @@
 #include <linux/interrupt.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
-#include <linux/of_graph.h>
 #include <linux/gpio.h>
 #include <linux/component.h>
 #include <linux/phy/phy.h>
-#include <video/of_display_timing.h>
-#include <video/of_videomode.h>
 
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
@@ -31,52 +28,42 @@
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_panel.h>
 
-#include "exynos_dp_core.h"
-#include "exynos_drm_crtc.h"
+#include <drm/bridge/analogix_dp.h>
 
-#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
-					connector)
+#include "analogix_dp_core.h"
 
-static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
-{
-	return to_exynos_crtc(dp->encoder.crtc);
-}
-
-static inline struct exynos_dp_device *encoder_to_dp(
-						struct drm_encoder *e)
-{
-	return container_of(e, struct exynos_dp_device, encoder);
-}
+#define connector_to_dp(c) \
+	container_of(c, struct analogix_dp_device, connector)
 
 struct bridge_init {
 	struct i2c_client *client;
 	struct device_node *node;
 };
 
-static void exynos_dp_init_dp(struct exynos_dp_device *dp)
+static void analogix_dp_init_dp(struct analogix_dp_device *dp)
 {
-	exynos_dp_reset(dp);
+	analogix_dp_reset(dp);
 
-	exynos_dp_swreset(dp);
+	analogix_dp_swreset(dp);
 
-	exynos_dp_init_analog_param(dp);
-	exynos_dp_init_interrupt(dp);
+	analogix_dp_init_analog_param(dp);
+	analogix_dp_init_interrupt(dp);
 
 	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_function(dp);
+	analogix_dp_enable_sw_function(dp);
 
-	exynos_dp_config_interrupt(dp);
-	exynos_dp_init_analog_func(dp);
+	analogix_dp_config_interrupt(dp);
+	analogix_dp_init_analog_func(dp);
 
-	exynos_dp_init_hpd(dp);
-	exynos_dp_init_aux(dp);
+	analogix_dp_init_hpd(dp);
+	analogix_dp_init_aux(dp);
 }
 
-static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
+static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (exynos_dp_get_plug_in_status(dp) != 0) {
+	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
@@ -88,7 +75,7 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
 	return 0;
 }
 
-static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
+static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 {
 	int i;
 	unsigned char sum = 0;
@@ -99,7 +86,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
 	return sum;
 }
 
-static int exynos_dp_read_edid(struct exynos_dp_device *dp)
+static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
 	unsigned char edid[EDID_BLOCK_LENGTH * 2];
 	unsigned int extend_block = 0;
@@ -114,9 +101,9 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 	 */
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-					      EDID_EXTENSION_FLAG,
-					      &extend_block);
+	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+						EDID_EXTENSION_FLAG,
+						&extend_block);
 	if (retval)
 		return retval;
 
@@ -124,7 +111,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(
+		retval = analogix_dp_read_bytes_from_i2c(
 					dp, I2C_EDID_DEVICE_ADDR,
 					EDID_HEADER_PATTERN,
 					EDID_BLOCK_LENGTH,
@@ -133,14 +120,14 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
+		sum = analogix_dp_calc_edid_check_sum(edid);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(
+		retval = analogix_dp_read_bytes_from_i2c(
 					dp, I2C_EDID_DEVICE_ADDR,
 					EDID_BLOCK_LENGTH,
 					EDID_BLOCK_LENGTH,
@@ -149,19 +136,19 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
+		sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					      &test_vector);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(
+			analogix_dp_write_byte_to_dpcd(
 				dp, DP_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(
+			analogix_dp_write_byte_to_dpcd(
 				dp, DP_TEST_RESPONSE,
 				DP_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -169,26 +156,26 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_info(dp->dev, "EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(
+		retval = analogix_dp_read_bytes_from_i2c(
 				dp, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
 				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
+		sum = analogix_dp_calc_edid_check_sum(edid);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					      &test_vector);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(
+			analogix_dp_write_byte_to_dpcd(
 					dp, DP_TEST_EDID_CHECKSUM,
 					edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(
+			analogix_dp_write_byte_to_dpcd(
 					dp, DP_TEST_RESPONSE,
 					DP_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -198,20 +185,20 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 	return 0;
 }
 
-static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
+static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 {
 	u8 buf[12];
 	int i;
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
 	if (retval)
 		return retval;
 
 	/* Read EDID */
 	for (i = 0; i < 3; i++) {
-		retval = exynos_dp_read_edid(dp);
+		retval = analogix_dp_read_edid(dp);
 		if (!retval)
 			break;
 	}
@@ -219,72 +206,74 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
-						 bool enable)
+static void
+analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
+				       bool enable)
 {
 	u8 data;
 
-	exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
 
 	if (enable)
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-					     DP_LANE_COUNT_ENHANCED_FRAME_EN |
-					     DPCD_LANE_COUNT_SET(data));
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+					       DP_LANE_COUNT_ENHANCED_FRAME_EN |
+					       DPCD_LANE_COUNT_SET(data));
 	else
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-					     DPCD_LANE_COUNT_SET(data));
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+					       DPCD_LANE_COUNT_SET(data));
 }
 
-static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
+static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
 {
 	u8 data;
 	int retval;
 
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 	retval = DPCD_ENHANCED_FRAME_CAP(data);
 
 	return retval;
 }
 
-static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
+static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 {
 	u8 data;
 
-	data = exynos_dp_is_enhanced_mode_available(dp);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, data);
-	exynos_dp_enable_enhanced_mode(dp, data);
+	data = analogix_dp_is_enhanced_mode_available(dp);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, data);
+	analogix_dp_enable_enhanced_mode(dp, data);
 }
 
-static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
+static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
-	exynos_dp_set_training_pattern(dp, DP_NONE);
+	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
-				     DP_TRAINING_PATTERN_DISABLE);
+	analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+				       DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
-						 int pre_emphasis, int lane)
+static void
+analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
+				       int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
-		exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 		break;
 	case 1:
-		exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 		break;
 
 	case 2:
-		exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 		break;
 
 	case 3:
-		exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 		break;
 	}
 }
 
-static int exynos_dp_link_start(struct exynos_dp_device *dp)
+static int analogix_dp_link_start(struct analogix_dp_device *dp)
 {
 	u8 buf[4];
 	int lane, lane_count, pll_tries, retval;
@@ -298,24 +287,24 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		dp->link_train.cr_loop[lane] = 0;
 
 	/* Set link rate and count as you want to establish*/
-	exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
-	exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
+	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
 	if (retval)
 		return retval;
 
 	/* Set TX pre-emphasis to minimum */
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0,
-						     lane);
+		analogix_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0,
+						       lane);
 
 	/* Wait for PLL lock */
 	pll_tries = 0;
-	while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+	while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 		if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Wait for PLL lock timed out\n");
 			return -ETIMEDOUT;
@@ -326,12 +315,12 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 	}
 
 	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
+	analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 
 	/* Set RX training pattern */
-	retval = exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
-					      DP_LINK_SCRAMBLING_DISABLE |
-					      DP_TRAINING_PATTERN_1);
+	retval = analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						DP_LINK_SCRAMBLING_DISABLE |
+						DP_TRAINING_PATTERN_1);
 	if (retval)
 		return retval;
 
@@ -339,13 +328,13 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-					       lane_count, buf);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+						 lane_count, buf);
 
 	return retval;
 }
 
-static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
+static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
 	u8 link_value = link_status[lane >> 1];
@@ -353,21 +342,21 @@ static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
 	return (link_value >> shift) & 0xf;
 }
 
-static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
+static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 {
 	int lane;
 	u8 lane_status;
 
 	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
 		if ((lane_status & DP_LANE_CR_DONE) == 0)
 			return -EINVAL;
 	}
 	return 0;
 }
 
-static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				   int lane_count)
+static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
+				     int lane_count)
 {
 	int lane;
 	u8 lane_status;
@@ -376,7 +365,7 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 		return -EINVAL;
 
 	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
 		lane_status &= DP_CHANNEL_EQ_BITS;
 		if (lane_status != DP_CHANNEL_EQ_BITS)
 			return -EINVAL;
@@ -385,8 +374,8 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							  int lane)
+static unsigned char
+analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 {
 	int shift = (lane & 1) * 4;
 	u8 link_value = adjust_request[lane >> 1];
@@ -394,7 +383,7 @@ static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 	return (link_value >> shift) & 0x3;
 }
 
-static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
+static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					u8 adjust_request[2],
 					int lane)
 {
@@ -404,44 +393,44 @@ static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
-static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
-					     u8 training_lane_set, int lane)
+static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
+					       u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
-		exynos_dp_set_lane0_link_training(dp, training_lane_set);
+		analogix_dp_set_lane0_link_training(dp, training_lane_set);
 		break;
 	case 1:
-		exynos_dp_set_lane1_link_training(dp, training_lane_set);
+		analogix_dp_set_lane1_link_training(dp, training_lane_set);
 		break;
 
 	case 2:
-		exynos_dp_set_lane2_link_training(dp, training_lane_set);
+		analogix_dp_set_lane2_link_training(dp, training_lane_set);
 		break;
 
 	case 3:
-		exynos_dp_set_lane3_link_training(dp, training_lane_set);
+		analogix_dp_set_lane3_link_training(dp, training_lane_set);
 		break;
 	}
 }
 
 static unsigned int
-exynos_dp_get_lane_link_training(struct exynos_dp_device *dp, int lane)
+analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, int lane)
 {
 	u32 reg;
 
 	switch (lane) {
 	case 0:
-		reg = exynos_dp_get_lane0_link_training(dp);
+		reg = analogix_dp_get_lane0_link_training(dp);
 		break;
 	case 1:
-		reg = exynos_dp_get_lane1_link_training(dp);
+		reg = analogix_dp_get_lane1_link_training(dp);
 		break;
 	case 2:
-		reg = exynos_dp_get_lane2_link_training(dp);
+		reg = analogix_dp_get_lane2_link_training(dp);
 		break;
 	case 3:
-		reg = exynos_dp_get_lane3_link_training(dp);
+		reg = analogix_dp_get_lane3_link_training(dp);
 		break;
 	default:
 		WARN_ON(1);
@@ -451,25 +440,25 @@ exynos_dp_get_lane_link_training(struct exynos_dp_device *dp, int lane)
 	return reg;
 }
 
-static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
+static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 {
-	exynos_dp_training_pattern_dis(dp);
-	exynos_dp_set_enhanced_mode(dp);
+	analogix_dp_training_pattern_dis(dp);
+	analogix_dp_set_enhanced_mode(dp);
 
 	dp->link_train.lt_state = FAILED;
 }
 
-static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
-					       u8 adjust_request[2])
+static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
+						 u8 adjust_request[2])
 {
 	int lane, lane_count;
 	u8 voltage_swing, pre_emphasis, training_lane;
 
 	lane_count = dp->link_train.lane_count;
 	for (lane = 0; lane < lane_count; lane++) {
-		voltage_swing = exynos_dp_get_adjust_request_voltage(
+		voltage_swing = analogix_dp_get_adjust_request_voltage(
 						adjust_request, lane);
-		pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
+		pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 						adjust_request, lane);
 		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
@@ -483,7 +472,7 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
 	}
 }
 
-static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
+static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 {
 	int lane, lane_count, retval;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -493,21 +482,22 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
-						 2, link_status);
+	retval =  analogix_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
+						   2, link_status);
 	if (retval)
 		return retval;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
-						 2, adjust_request);
+	retval =  analogix_dp_read_bytes_from_dpcd(
+					dp, DP_ADJUST_REQUEST_LANE0_1,
+					2, adjust_request);
 	if (retval)
 		return retval;
 
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 		/* set training pattern 2 for EQ */
-		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
+		analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 
-		retval = exynos_dp_write_byte_to_dpcd(
+		retval = analogix_dp_write_byte_to_dpcd(
 				dp, DP_TRAINING_PATTERN_SET,
 				DP_LINK_SCRAMBLING_DISABLE |
 				DP_TRAINING_PATTERN_2);
@@ -518,11 +508,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 		dp->link_train.lt_state = EQUALIZER_TRAINING;
 	} else {
 		for (lane = 0; lane < lane_count; lane++) {
-			training_lane = exynos_dp_get_lane_link_training(
+			training_lane = analogix_dp_get_lane_link_training(
 							dp, lane);
-			voltage_swing = exynos_dp_get_adjust_request_voltage(
+			voltage_swing = analogix_dp_get_adjust_request_voltage(
 							adjust_request, lane);
-			pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
+			pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 							adjust_request, lane);
 
 			if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
@@ -537,19 +527,19 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 				dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 					dp->link_train.cr_loop[lane],
 					voltage_swing, pre_emphasis);
-				exynos_dp_reduce_link_rate(dp);
+				analogix_dp_reduce_link_rate(dp);
 				return -EIO;
 			}
 		}
 	}
 
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(
+		analogix_dp_set_lane_link_training(
 				dp, dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(
+	retval = analogix_dp_write_bytes_to_dpcd(
 			dp, DP_TRAINING_LANE0_SET, lane_count,
 			dp->link_train.training_lane);
 	if (retval)
@@ -558,7 +548,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
+static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 {
 	int lane, lane_count, retval;
 	u32 reg;
@@ -568,46 +558,46 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
-						2, link_status);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
+						  2, link_status);
 	if (retval)
 		return retval;
 
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
-		exynos_dp_reduce_link_rate(dp);
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
+		analogix_dp_reduce_link_rate(dp);
 		return -EIO;
 	}
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
-						2, adjust_request);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
+						  2, adjust_request);
 	if (retval)
 		return retval;
 
-	retval = exynos_dp_read_byte_from_dpcd(dp, DP_LANE_ALIGN_STATUS_UPDATED,
-					       &link_align);
+	retval = analogix_dp_read_byte_from_dpcd(
+			dp, DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
 	if (retval)
 		return retval;
 
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 
-	if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
+	if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 		/* traing pattern Set to Normal */
-		exynos_dp_training_pattern_dis(dp);
+		analogix_dp_training_pattern_dis(dp);
 
 		dev_info(dp->dev, "Link Training success!\n");
 
-		exynos_dp_get_link_bandwidth(dp, &reg);
+		analogix_dp_get_link_bandwidth(dp, &reg);
 		dp->link_train.link_rate = reg;
 		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 			dp->link_train.link_rate);
 
-		exynos_dp_get_lane_count(dp, &reg);
+		analogix_dp_get_lane_count(dp, &reg);
 		dp->link_train.lane_count = reg;
 		dev_dbg(dp->dev, "final lane count = %.2x\n",
 			dp->link_train.lane_count);
 
 		/* set enhanced mode if available */
-		exynos_dp_set_enhanced_mode(dp);
+		analogix_dp_set_enhanced_mode(dp);
 		dp->link_train.lt_state = FINISHED;
 
 		return 0;
@@ -618,23 +608,23 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 		dev_err(dp->dev, "EQ Max loop\n");
-		exynos_dp_reduce_link_rate(dp);
+		analogix_dp_reduce_link_rate(dp);
 		return -EIO;
 	}
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(
+		analogix_dp_set_lane_link_training(
 				dp, dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-					       lane_count,
-					       dp->link_train.training_lane);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+						 lane_count,
+						 dp->link_train.training_lane);
 
 	return retval;
 }
 
-static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
-					   u8 *bandwidth)
+static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
+					     u8 *bandwidth)
 {
 	u8 data;
 
@@ -642,12 +632,12 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
 }
 
-static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
-					    u8 *lane_count)
+static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
+					      u8 *lane_count)
 {
 	u8 data;
 
@@ -655,23 +645,23 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 	 * For DP rev.1.1, Maximum number of Main Link lanes
 	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 	*lane_count = DPCD_MAX_LANE_COUNT(data);
 }
 
-static void exynos_dp_init_training(struct exynos_dp_device *dp,
-				    enum link_lane_count_type max_lane,
-				    enum link_rate_type max_rate)
+static void analogix_dp_init_training(struct analogix_dp_device *dp,
+				      enum link_lane_count_type max_lane,
+				      enum link_rate_type max_rate)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 	 * the DP inter pair skew issue for at least 10 us
 	 */
-	exynos_dp_reset_macro(dp);
+	analogix_dp_reset_macro(dp);
 
 	/* Initialize by reading RX's DPCD */
-	exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
-	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
+	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
+	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
@@ -693,10 +683,10 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
 		dp->link_train.link_rate = max_rate;
 
 	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 }
 
-static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
+static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 {
 	int retval = 0, training_finished = 0;
 
@@ -706,17 +696,17 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 	while (!retval && !training_finished) {
 		switch (dp->link_train.lt_state) {
 		case START:
-			retval = exynos_dp_link_start(dp);
+			retval = analogix_dp_link_start(dp);
 			if (retval)
 				dev_err(dp->dev, "LT link start failed!\n");
 			break;
 		case CLOCK_RECOVERY:
-			retval = exynos_dp_process_clock_recovery(dp);
+			retval = analogix_dp_process_clock_recovery(dp);
 			if (retval)
 				dev_err(dp->dev, "LT CR failed!\n");
 			break;
 		case EQUALIZER_TRAINING:
-			retval = exynos_dp_process_equalizer_training(dp);
+			retval = analogix_dp_process_equalizer_training(dp);
 			if (retval)
 				dev_err(dp->dev, "LT EQ failed!\n");
 			break;
@@ -733,15 +723,15 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
-				    u32 count, u32 bwtype)
+static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
+				      u32 count, u32 bwtype)
 {
 	int i;
 	int retval;
 
 	for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
-		exynos_dp_init_training(dp, count, bwtype);
-		retval = exynos_dp_sw_link_training(dp);
+		analogix_dp_init_training(dp, count, bwtype);
+		retval = analogix_dp_sw_link_training(dp);
 		if (retval == 0)
 			break;
 
@@ -751,24 +741,24 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 	return retval;
 }
 
-static int exynos_dp_config_video(struct exynos_dp_device *dp)
+static int analogix_dp_config_video(struct analogix_dp_device *dp)
 {
 	int retval = 0;
 	int timeout_loop = 0;
 	int done_count = 0;
 
-	exynos_dp_config_video_slave_mode(dp);
+	analogix_dp_config_video_slave_mode(dp);
 
-	exynos_dp_set_video_color_format(dp);
+	analogix_dp_set_video_color_format(dp);
 
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 		dev_err(dp->dev, "PLL is not locked yet.\n");
 		return -EINVAL;
 	}
 
 	for (;;) {
 		timeout_loop++;
-		if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
+		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
@@ -779,22 +769,22 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
 	}
 
 	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
+	analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 
 	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
+	analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 
 	/* Disable video mute */
-	exynos_dp_enable_video_mute(dp, 0);
+	analogix_dp_enable_video_mute(dp, 0);
 
 	/* Configure video slave mode */
-	exynos_dp_enable_video_master(dp, 0);
+	analogix_dp_enable_video_master(dp, 0);
 
 	timeout_loop = 0;
 
 	for (;;) {
 		timeout_loop++;
-		if (exynos_dp_is_video_stream_on(dp) == 0) {
+		if (analogix_dp_is_video_stream_on(dp) == 0) {
 			done_count++;
 			if (done_count > 10)
 				break;
@@ -815,45 +805,46 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
+					bool enable)
 {
 	u8 data;
 
 	if (enable) {
-		exynos_dp_enable_scrambling(dp);
+		analogix_dp_enable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
-					      &data);
-		exynos_dp_write_byte_to_dpcd(
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
+		analogix_dp_write_byte_to_dpcd(
 				dp, DP_TRAINING_PATTERN_SET,
 				(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
-		exynos_dp_disable_scrambling(dp);
+		analogix_dp_disable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
-					      &data);
-		exynos_dp_write_byte_to_dpcd(
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
+		analogix_dp_write_byte_to_dpcd(
 				dp, DP_TRAINING_PATTERN_SET,
 				(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 	}
 }
 
-static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
+static irqreturn_t analogix_dp_irq_handler(int irq, void *arg)
 {
-	struct exynos_dp_device *dp = arg;
+	struct analogix_dp_device *dp = arg;
 
 	enum dp_irq_type irq_type;
 
-	irq_type = exynos_dp_get_irq_type(dp);
+	irq_type = analogix_dp_get_irq_type(dp);
 	switch (irq_type) {
 	case DP_IRQ_TYPE_HP_CABLE_IN:
 		dev_dbg(dp->dev, "Received irq - cable in\n");
 		schedule_work(&dp->hotplug_work);
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	case DP_IRQ_TYPE_HP_CABLE_OUT:
 		dev_dbg(dp->dev, "Received irq - cable out\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	case DP_IRQ_TYPE_HP_CHANGE:
 		/*
@@ -862,7 +853,7 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 		 * only handle cable changes.
 		 */
 		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	default:
 		dev_err(dp->dev, "Received irq - unknown type!\n");
@@ -871,218 +862,204 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
-static void exynos_dp_hotplug(struct work_struct *work)
+static void analogix_dp_hotplug(struct work_struct *work)
 {
-	struct exynos_dp_device *dp;
+	struct analogix_dp_device *dp;
 
-	dp = container_of(work, struct exynos_dp_device, hotplug_work);
+	dp = container_of(work, struct analogix_dp_device, hotplug_work);
 
 	if (dp->drm_dev)
 		drm_helper_hpd_irq_event(dp->drm_dev);
 }
 
-static void exynos_dp_commit(struct drm_encoder *encoder)
+static void analogix_dp_commit(struct analogix_dp_device *dp)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
 	int ret;
 
 	/* Keep the panel disabled while we configure video */
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel))
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel))
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = exynos_dp_detect_hpd(dp);
+	ret = analogix_dp_detect_hpd(dp);
 	if (ret) {
 		/* Cable has been disconnected, we're done */
 		return;
 	}
 
-	ret = exynos_dp_handle_edid(dp);
+	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
 		return;
 	}
 
-	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
-				       dp->video_info->link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
+					 dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
 	}
 
-	exynos_dp_enable_scramble(dp, 1);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
-	exynos_dp_enable_enhanced_mode(dp, 1);
+	analogix_dp_enable_scramble(dp, 1);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
+	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
-	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
+	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 
-	exynos_dp_init_video(dp);
-	ret = exynos_dp_config_video(dp);
+	analogix_dp_init_video(dp);
+	ret = analogix_dp_config_video(dp);
 	if (ret)
 		dev_err(dp->dev, "unable to config video\n");
 
 	/* Safe to enable the panel now */
-	if (dp->panel) {
-		if (drm_panel_enable(dp->panel))
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_enable(dp->plat_data->panel))
 			DRM_ERROR("failed to enable the panel\n");
 	}
 
 	/* Enable video */
-	exynos_dp_start_video(dp);
+	analogix_dp_start_video(dp);
 }
 
 static enum drm_connector_status
-exynos_dp_detect(struct drm_connector *connector, bool force)
+analogix_dp_detect(struct drm_connector *connector, bool force)
 {
 	return connector_status_connected;
 }
 
-static void exynos_dp_connector_destroy(struct drm_connector *connector)
+static void analogix_dp_connector_destroy(struct drm_connector *connector)
 {
 	drm_connector_unregister(connector);
 	drm_connector_cleanup(connector);
 }
 
-static struct drm_connector_funcs exynos_dp_connector_funcs = {
+static struct drm_connector_funcs analogix_dp_connector_funcs = {
 	.dpms = drm_atomic_helper_connector_dpms,
 	.fill_modes = drm_helper_probe_single_connector_modes,
-	.detect = exynos_dp_detect,
-	.destroy = exynos_dp_connector_destroy,
+	.detect = analogix_dp_detect,
+	.destroy = analogix_dp_connector_destroy,
 	.reset = drm_atomic_helper_connector_reset,
 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 };
 
-static int exynos_dp_get_modes(struct drm_connector *connector)
+static int analogix_dp_get_modes(struct drm_connector *connector)
 {
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
-	struct drm_display_mode *mode;
-
-	if (dp->panel)
-		return drm_panel_get_modes(dp->panel);
+	struct analogix_dp_device *dp = connector_to_dp(connector);
+	struct analogix_dp_plat_data *plat_data = dp->plat_data;
+	int num_modes = 0;
 
-	mode = drm_mode_create(connector->dev);
-	if (!mode) {
-		DRM_ERROR("failed to create a new display mode.\n");
-		return 0;
-	}
-
-	drm_display_mode_from_videomode(&dp->priv.vm, mode);
-	mode->width_mm = dp->priv.width_mm;
-	mode->height_mm = dp->priv.height_mm;
-	connector->display_info.width_mm = mode->width_mm;
-	connector->display_info.height_mm = mode->height_mm;
+	if (plat_data && plat_data->panel)
+		num_modes += drm_panel_get_modes(plat_data->panel);
 
-	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-	drm_mode_set_name(mode);
-	drm_mode_probed_add(connector, mode);
+	if (plat_data && plat_data->get_modes)
+		 num_modes += plat_data->get_modes(plat_data, connector);
 
-	return 1;
+	return num_modes;
 }
 
 static struct drm_encoder *
-exynos_dp_best_encoder(struct drm_connector *connector)
+analogix_dp_best_encoder(struct drm_connector *connector)
 {
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
+	struct analogix_dp_device *dp = connector_to_dp(connector);
 
-	return &dp->encoder;
+	return dp->encoder;
 }
 
-static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
-	.get_modes = exynos_dp_get_modes,
-	.best_encoder = exynos_dp_best_encoder,
+static struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
+	.get_modes = analogix_dp_get_modes,
+	.best_encoder = analogix_dp_best_encoder,
 };
 
-/* returns the number of bridges attached */
-static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
-					struct drm_encoder *encoder)
-{
-	int ret;
-
-	encoder->bridge->next = dp->ptn_bridge;
-	dp->ptn_bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
-	if (ret) {
-		DRM_ERROR("Failed to attach bridge to drm\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
+static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct drm_encoder *encoder = &dp->encoder;
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = dp->encoder;
 	struct drm_connector *connector = &dp->connector;
 	int ret;
 
-	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->ptn_bridge) {
-		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
-		if (!ret)
-			return 0;
+	if (!bridge->encoder) {
+		DRM_ERROR("Parent encoder object not found");
+		return -ENODEV;
 	}
 
+	encoder->bridge = bridge;
+
 	connector->polled = DRM_CONNECTOR_POLL_HPD;
 
 	ret = drm_connector_init(dp->drm_dev, connector,
-				 &exynos_dp_connector_funcs,
+				 &analogix_dp_connector_funcs,
 				 DRM_MODE_CONNECTOR_eDP);
 	if (ret) {
 		DRM_ERROR("Failed to initialize connector with drm\n");
 		return ret;
 	}
 
-	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
+	drm_connector_helper_add(connector,
+				 &analogix_dp_connector_helper_funcs);
 	drm_connector_register(connector);
 	drm_mode_connector_attach_encoder(connector, encoder);
 
-	if (dp->panel)
-		ret = drm_panel_attach(dp->panel, &dp->connector);
+	if (dp->plat_data && dp->plat_data->panel) {
+		ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
+		if (ret) {
+			DRM_ERROR("Failed to attach panel\n");
+			return ret;
+		}
+	}
+
+	/*
+	 * This should be the end of attach function, caused
+	 * we should ensure dp bridge could attach first.
+	 */
+	 if (dp->plat_data && dp->plat_data->attach) {
+		 ret = dp->plat_data->attach(dp->plat_data, bridge);
+		 if (ret) {
+			 DRM_ERROR("Failed at platform attch func\n");
+			 return ret;
+		 }
+	 }
 
-	return ret;
+	return 0;
 }
 
-static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
+static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
+	struct analogix_dp_device *dp = bridge->driver_private;
 
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->panel) {
-		if (drm_panel_prepare(dp->panel)) {
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
 			DRM_ERROR("failed to setup the panel\n");
 			return;
 		}
 	}
 
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), true);
+	if (dp->plat_data && dp->plat_data->power_on)
+		dp->plat_data->power_on(dp->plat_data);
 
 	clk_prepare_enable(dp->clock);
 	phy_power_on(dp->phy);
-	exynos_dp_init_dp(dp);
+	analogix_dp_init_dp(dp);
 	enable_irq(dp->irq);
-	exynos_dp_commit(&dp->encoder);
+	analogix_dp_commit(dp);
 
 	dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
-static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
+static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
+	struct analogix_dp_device *dp = bridge->driver_private;
 
 	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel)) {
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel)) {
 			DRM_ERROR("failed to disable the panel\n");
 			return;
 		}
@@ -1093,34 +1070,33 @@ static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 	phy_power_off(dp->phy);
 	clk_disable_unprepare(dp->clock);
 
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), false);
+	if (dp->plat_data && dp->plat_data->power_off)
+		dp->plat_data->power_off(dp->plat_data);
 
-	if (dp->panel) {
-		if (drm_panel_unprepare(dp->panel))
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_unprepare(dp->plat_data->panel))
 			DRM_ERROR("failed to turnoff the panel\n");
 	}
 
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
-static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
 }
 
-static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
-	.enable = exynos_dp_bridge_enable,
-	.disable = exynos_dp_bridge_disable,
-	.pre_enable = exynos_dp_bridge_nop,
-	.post_disable = exynos_dp_bridge_nop,
-	.attach = exynos_dp_bridge_attach,
+static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
+	.enable = analogix_dp_bridge_enable,
+	.disable = analogix_dp_bridge_disable,
+	.pre_enable = analogix_dp_bridge_nop,
+	.post_disable = analogix_dp_bridge_nop,
+	.attach = analogix_dp_bridge_attach,
 };
 
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int analogix_dp_create_bridge(struct drm_device *drm_dev,
+				     struct analogix_dp_device *dp)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
-	struct drm_device *drm_dev = dp->drm_dev;
 	struct drm_bridge *bridge;
 	int ret;
 
@@ -1133,8 +1109,8 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	dp->bridge = bridge;
 
 	bridge->driver_private = dp;
-	bridge->encoder = encoder;
-	bridge->funcs = &exynos_dp_bridge_funcs;
+	bridge->encoder = dp->encoder;
+	bridge->funcs = &analogix_dp_bridge_funcs;
 
 	ret = drm_bridge_attach(drm_dev, bridge);
 	if (ret) {
@@ -1145,39 +1121,7 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	return 0;
 }
 
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
-				 const struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
-{
-}
-
-static void exynos_dp_disable(struct drm_encoder *encoder)
-{
-}
-
-static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
-	.mode_fixup = exynos_dp_mode_fixup,
-	.mode_set = exynos_dp_mode_set,
-	.enable = exynos_dp_enable,
-	.disable = exynos_dp_disable,
-};
-
-static struct drm_encoder_funcs exynos_dp_encoder_funcs = {
-	.destroy = drm_encoder_cleanup,
-};
-
-static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
+static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 {
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
@@ -1235,33 +1179,33 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
 	return dp_video_config;
 }
 
-static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct drm_encoder *encoder,
+		     struct analogix_dp_plat_data *plat_data)
 {
-	int ret;
-
-	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
-			       OF_USE_NATIVE_MODE);
-	if (ret) {
-		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
-		return ret;
-	}
-	return 0;
-}
-
-static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
-{
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
 	struct platform_device *pdev = to_platform_device(dev);
-	struct drm_device *drm_dev = data;
-	struct drm_encoder *encoder = &dp->encoder;
+	struct analogix_dp_device *dp;
 	struct resource *res;
 	unsigned int irq_flags;
-	int pipe, ret = 0;
+	int ret;
+
+	dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, dp);
 
 	dp->dev = &pdev->dev;
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 
-	dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
+	/*
+	 * platform dp driver need containor_of the plat_data to get
+	 * the driver private data, so we need to store the point of
+	 * plat_data, not the context of plat_data.
+	 */
+	dp->plat_data = plat_data;
+
+	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
 	if (IS_ERR(dp->video_info))
 		return PTR_ERR(dp->video_info);
 
@@ -1281,12 +1225,6 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		}
 	}
 
-	if (!dp->panel && !dp->bridge) {
-		ret = exynos_dp_dt_parse_panel(dp);
-		if (ret)
-			return ret;
-	}
-
 	dp->clock = devm_clk_get(&pdev->dev, "dp");
 	if (IS_ERR(dp->clock)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
@@ -1301,7 +1239,10 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
-	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
+	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
+	if (gpio_is_valid(dp->hpd_gpio))
+		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
+						 "samsung,hpd-gpio", 0);
 
 	if (gpio_is_valid(dp->hpd_gpio)) {
 		/*
@@ -1330,14 +1271,14 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		return -ENODEV;
 	}
 
-	INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
+	INIT_WORK(&dp->hotplug_work, analogix_dp_hotplug);
 
 	phy_power_on(dp->phy);
 
-	exynos_dp_init_dp(dp);
+	analogix_dp_init_dp(dp);
 
-	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
-			       irq_flags, "exynos-dp", dp);
+	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
+			       irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		return ret;
@@ -1345,22 +1286,9 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	disable_irq(dp->irq);
 
 	dp->drm_dev = drm_dev;
+	dp->encoder = encoder;
 
-	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
-						  EXYNOS_DISPLAY_TYPE_LCD);
-	if (pipe < 0)
-		return pipe;
-
-	encoder->possible_crtcs = 1 << pipe;
-
-	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
-
-	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
-			 DRM_MODE_ENCODER_TMDS);
-
-	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
-
-	ret = exynos_dp_create_connector(encoder);
+	ret = analogix_dp_create_bridge(drm_dev, dp);
 	if (ret) {
 		DRM_ERROR("failed to create connector ret = %d\n", ret);
 		drm_encoder_cleanup(encoder);
@@ -1369,103 +1297,36 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_bind);
 
-static void exynos_dp_unbind(struct device *dev, struct device *master,
-			     void *data)
+void analogix_dp_unbind(struct device *dev, struct device *master, void *data)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_disable(&dp->encoder);
-}
-
-static const struct component_ops exynos_dp_ops = {
-	.bind	= exynos_dp_bind,
-	.unbind	= exynos_dp_unbind,
-};
-
-static int exynos_dp_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct device_node *panel_node, *bridge_node, *endpoint;
-	struct exynos_dp_device *dp;
-
-	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
-			  GFP_KERNEL);
-	if (!dp)
-		return -ENOMEM;
-
-	platform_set_drvdata(pdev, dp);
-
-	panel_node = of_parse_phandle(dev->of_node, "panel", 0);
-	if (panel_node) {
-		dp->panel = of_drm_find_panel(panel_node);
-		of_node_put(panel_node);
-		if (!dp->panel)
-			return -EPROBE_DEFER;
-	}
-
-	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
-	if (endpoint) {
-		bridge_node = of_graph_get_remote_port_parent(endpoint);
-		if (bridge_node) {
-			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
-			of_node_put(bridge_node);
-			if (!dp->ptn_bridge)
-				return -EPROBE_DEFER;
-		} else {
-			return -EPROBE_DEFER;
-		}
-	}
-
-	return component_add(&pdev->dev, &exynos_dp_ops);
-}
-
-static int exynos_dp_remove(struct platform_device *pdev)
-{
-	component_del(&pdev->dev, &exynos_dp_ops);
-
-	return 0;
+	analogix_dp_bridge_disable(dp->bridge);
 }
+EXPORT_SYMBOL_GPL(analogix_dp_unbind);
 
 #ifdef CONFIG_PM_SLEEP
-static int exynos_dp_suspend(struct device *dev)
+int analogix_dp_suspend(struct device *dev)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_bridge_disable(dp->bridge);
+	analogix_dp_bridge_disable(dp->bridge);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_suspend);
 
-static int exynos_dp_resume(struct device *dev)
+int analogix_dp_resume(struct device *dev)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_bridge_enable(dp->bridge);
+	analogix_dp_bridge_enable(dp->bridge);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_resume);
 #endif
 
-static const struct dev_pm_ops exynos_dp_pm_ops = {
-	SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
-};
-
-static const struct of_device_id exynos_dp_match[] = {
-	{ .compatible = "samsung,exynos5-dp" },
-	{},
-};
-MODULE_DEVICE_TABLE(of, exynos_dp_match);
-
-struct platform_driver dp_driver = {
-	.probe		= exynos_dp_probe,
-	.remove		= exynos_dp_remove,
-	.driver		= {
-		.name	= "exynos-dp",
-		.owner	= THIS_MODULE,
-		.pm	= &exynos_dp_pm_ops,
-		.of_match_table = exynos_dp_match,
-	},
-};
-
 MODULE_AUTHOR("Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
-MODULE_DESCRIPTION("Samsung SoC DP Driver");
+MODULE_DESCRIPTION("Analogix Core DP Driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
new file mode 100644
index 0000000..d7e47e0
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -0,0 +1,283 @@
+/*
+ * Header file for Analogix DP (Display Port) core interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _ANALOGIX_DP_CORE_H
+#define _ANALOGIX_DP_CORE_H
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_dp_helper.h>
+
+#define DP_TIMEOUT_LOOP_COUNT 100
+#define MAX_CR_LOOP 5
+#define MAX_EQ_LOOP 5
+
+enum link_rate_type {
+	LINK_RATE_1_62GBPS = 0x06,
+	LINK_RATE_2_70GBPS = 0x0a
+};
+
+enum link_lane_count_type {
+	LANE_COUNT1 = 1,
+	LANE_COUNT2 = 2,
+	LANE_COUNT4 = 4
+};
+
+enum link_training_state {
+	START,
+	CLOCK_RECOVERY,
+	EQUALIZER_TRAINING,
+	FINISHED,
+	FAILED
+};
+
+enum voltage_swing_level {
+	VOLTAGE_LEVEL_0,
+	VOLTAGE_LEVEL_1,
+	VOLTAGE_LEVEL_2,
+	VOLTAGE_LEVEL_3,
+};
+
+enum pre_emphasis_level {
+	PRE_EMPHASIS_LEVEL_0,
+	PRE_EMPHASIS_LEVEL_1,
+	PRE_EMPHASIS_LEVEL_2,
+	PRE_EMPHASIS_LEVEL_3,
+};
+
+enum pattern_set {
+	PRBS7,
+	D10_2,
+	TRAINING_PTN1,
+	TRAINING_PTN2,
+	DP_NONE
+};
+
+enum color_space {
+	COLOR_RGB,
+	COLOR_YCBCR422,
+	COLOR_YCBCR444
+};
+
+enum color_depth {
+	COLOR_6,
+	COLOR_8,
+	COLOR_10,
+	COLOR_12
+};
+
+enum color_coefficient {
+	COLOR_YCBCR601,
+	COLOR_YCBCR709
+};
+
+enum dynamic_range {
+	VESA,
+	CEA
+};
+
+enum pll_status {
+	PLL_UNLOCKED,
+	PLL_LOCKED
+};
+
+enum clock_recovery_m_value_type {
+	CALCULATED_M,
+	REGISTER_M
+};
+
+enum video_timing_recognition_type {
+	VIDEO_TIMING_FROM_CAPTURE,
+	VIDEO_TIMING_FROM_REGISTER
+};
+
+enum analog_power_block {
+	AUX_BLOCK,
+	CH0_BLOCK,
+	CH1_BLOCK,
+	CH2_BLOCK,
+	CH3_BLOCK,
+	ANALOG_TOTAL,
+	POWER_ALL
+};
+
+enum dp_irq_type {
+	DP_IRQ_TYPE_HP_CABLE_IN,
+	DP_IRQ_TYPE_HP_CABLE_OUT,
+	DP_IRQ_TYPE_HP_CHANGE,
+	DP_IRQ_TYPE_UNKNOWN,
+};
+
+struct video_info {
+	char *name;
+
+	bool h_sync_polarity;
+	bool v_sync_polarity;
+	bool interlaced;
+
+	enum color_space color_space;
+	enum dynamic_range dynamic_range;
+	enum color_coefficient ycbcr_coeff;
+	enum color_depth color_depth;
+
+	enum link_rate_type link_rate;
+	enum link_lane_count_type lane_count;
+};
+
+struct link_train {
+	int eq_loop;
+	int cr_loop[4];
+
+	u8 link_rate;
+	u8 lane_count;
+	u8 training_lane[4];
+
+	enum link_training_state lt_state;
+};
+
+struct analogix_dp_device {
+	struct device		*dev;
+	struct drm_device	*drm_dev;
+	struct drm_connector	connector;
+	struct drm_encoder	*encoder;
+	struct drm_bridge	*bridge;
+	struct clk		*clock;
+	unsigned int		irq;
+	void __iomem		*reg_base;
+
+	struct video_info	*video_info;
+	struct link_train	link_train;
+	struct work_struct	hotplug_work;
+	struct phy		*phy;
+	int			dpms_mode;
+	int			hpd_gpio;
+
+	struct analogix_dp_plat_data *plat_data;
+};
+
+/* analogix_dp_reg.c */
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_stop_video(struct analogix_dp_device *dp);
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
+void analogix_dp_reset(struct analogix_dp_device *dp);
+void analogix_dp_swreset(struct analogix_dp_device *dp);
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				       enum analog_power_block block,
+				       bool enable);
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
+void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
+void analogix_dp_reset_aux(struct analogix_dp_device *dp);
+void analogix_dp_init_aux(struct analogix_dp_device *dp);
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				   unsigned int reg_addr,
+				   unsigned char data);
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				    unsigned int reg_addr,
+				    unsigned char *data);
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[]);
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[]);
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				  unsigned int device_addr,
+				  unsigned int reg_addr);
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data);
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[]);
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable);
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				      enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane);
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane);
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane);
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane);
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
+void analogix_dp_reset_macro(struct analogix_dp_device *dp);
+void analogix_dp_init_video(struct analogix_dp_device *dp);
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value,
+				 u32 n_value);
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
+				     bool enable);
+void analogix_dp_start_video(struct analogix_dp_device *dp);
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
+#endif /* _ANALOGIX_DP_CORE_H */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
new file mode 100644
index 0000000..b879d8c
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -0,0 +1,1265 @@
+/*
+ * Analogix DP (Display port) core register interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include "analogix_dp_core.h"
+#include "analogix_dp_reg.h"
+
+#define COMMON_INT_MASK_1	0
+#define COMMON_INT_MASK_2	0
+#define COMMON_INT_MASK_3	0
+#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
+#define INT_STA_MASK		INT_HPD
+
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+		reg |= HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+		reg &= ~HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	}
+}
+
+void analogix_dp_stop_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	reg &= ~VIDEO_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+}
+
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable)
+		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
+			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+	else
+		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
+			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
+}
+
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = TX_TERMINAL_CTRL_50_OHM;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
+
+	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
+
+	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
+
+	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
+		TX_CUR1_2X | TX_CUR_16_MA;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
+
+	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
+		CH1_AMP_400_MV | CH0_AMP_400_MV;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
+}
+
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
+{
+	/* Set interrupt pin assertion polarity as high */
+	writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
+
+	/* Clear pending regisers */
+	writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+	writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
+	writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
+	writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+	writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	/* 0:mask,1: unmask */
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+void analogix_dp_reset(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	analogix_dp_stop_video(dp);
+	analogix_dp_enable_video_mute(dp, 0);
+
+	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
+		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
+		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+
+	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
+		SERDES_FIFO_FUNC_EN_N |
+		LS_CLK_DOMAIN_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+
+	usleep_range(20, 30);
+
+	analogix_dp_lane_swap(dp, 0);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
+
+	writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
+	writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
+
+	writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
+	writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
+
+	writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
+	writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
+
+	writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_swreset(struct analogix_dp_device *dp)
+{
+	writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
+}
+
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* 0: mask, 1: unmask */
+	reg = COMMON_INT_MASK_1;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+
+	reg = COMMON_INT_MASK_2;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+
+	reg = COMMON_INT_MASK_3;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+
+	reg = COMMON_INT_MASK_4;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+
+	reg = INT_STA_MASK;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+	if (reg & PLL_LOCK)
+		return PLL_LOCKED;
+	else
+		return PLL_UNLOCKED;
+}
+
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
+		reg |= DP_PLL_PD;
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
+		reg &= ~DP_PLL_PD;
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+	}
+}
+
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				       enum analog_power_block block,
+				       bool enable)
+{
+	u32 reg;
+
+	switch (block) {
+	case AUX_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= AUX_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~AUX_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH0_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH1_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH1_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH1_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH2_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH2_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH2_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH3_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH3_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH3_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case ANALOG_TOTAL:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= DP_PHY_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~DP_PHY_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case POWER_ALL:
+		if (enable) {
+			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
+				CH1_PD | CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
+{
+	u32 reg;
+	int timeout_loop = 0;
+
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
+
+	reg = PLL_LOCK_CHG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+
+	/* Power up PLL */
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		analogix_dp_set_pll_power_down(dp, 0);
+
+		while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+			timeout_loop++;
+			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+				dev_err(dp->dev, "failed to get pll lock status\n");
+				return;
+			}
+			usleep_range(10, 20);
+		}
+	}
+
+	/* Enable Serdes FIFO function and Link symbol clock domain module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
+		| AUX_FUNC_EN_N);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+
+	reg = INT_HPD;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+}
+
+void analogix_dp_init_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	analogix_dp_clear_hotplug_interrupts(dp);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg &= ~(F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		reg = gpio_get_value(dp->hpd_gpio);
+		if (reg)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+		else
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+	} else {
+		/* Parse hotplug interrupt status register */
+		reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+
+		if (reg & PLUG)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+
+		if (reg & HPD_LOST)
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+
+		if (reg & HOTPLUG_CHG)
+			return DP_IRQ_TYPE_HP_CHANGE;
+
+		return DP_IRQ_TYPE_UNKNOWN;
+	}
+}
+
+void analogix_dp_reset_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Disable AUX channel module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg |= AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+void analogix_dp_init_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Clear inerrupts related to AUX channel */
+	reg = RPLY_RECEIV | AUX_ERR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	analogix_dp_reset_aux(dp);
+
+	/* Disable AUX transaction H/W retry */
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
+	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
+
+	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
+	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
+
+	/* Enable AUX channel module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg &= ~AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		if (gpio_get_value(dp->hpd_gpio))
+			return 0;
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+		if (reg & HPD_STATUS)
+			return 0;
+	}
+
+	return -EINVAL;
+}
+
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+	reg &= ~SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+}
+
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
+{
+	int reg;
+	int retval = 0;
+	int timeout_loop = 0;
+
+	/* Enable AUX CH operation */
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+	reg |= AUX_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+
+	/* Is AUX CH command reply received? */
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+	while (!(reg & RPLY_RECEIV)) {
+		timeout_loop++;
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "AUX CH command reply failed!\n");
+			return -ETIMEDOUT;
+		}
+		reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+		usleep_range(10, 11);
+	}
+
+	/* Clear interrupt source for AUX CH command reply */
+	writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	/* Clear interrupt source for AUX CH access error */
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+	if (reg & AUX_ERR) {
+		writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
+		return -EREMOTEIO;
+	}
+
+	/* Check AUX CH error access status */
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
+	if ((reg & AUX_STATUS_MASK) != 0) {
+		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
+			reg & AUX_STATUS_MASK);
+		return -EREMOTEIO;
+	}
+
+	return retval;
+}
+
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				   unsigned int reg_addr,
+				   unsigned char data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+		/* Write data buffer */
+		reg = (unsigned int)data;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+		/*
+		 * Set DisplayPort transaction and write 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				    unsigned int reg_addr,
+				    unsigned char *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+		/*
+		 * Set DisplayPort transaction and read 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+	}
+
+	/* Read data buffer */
+	reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+	*data = (unsigned char)(reg & 0xff);
+
+	return retval;
+}
+
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+			     cur_data_idx++) {
+				reg = data[start_offset + cur_data_idx];
+				writel(reg, dp->reg_base +
+				       ANALOGIX_DP_BUF_DATA_0 +
+				       4 * cur_data_idx);
+			}
+
+			/*
+			 * Set DisplayPort transaction and write
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		/* AUX CH Request Transaction process */
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+			/*
+			 * Set DisplayPort transaction and read
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+		    cur_data_idx++) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			data[start_offset + cur_data_idx] =
+				(unsigned char)reg;
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				  unsigned int device_addr,
+				  unsigned int reg_addr)
+{
+	u32 reg;
+	int retval;
+
+	/* Set EDID device address */
+	reg = device_addr;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+	/* Set offset from base address of EDID device */
+	writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+	/*
+	 * Set I2C transaction and write address
+	 * If bit 3 is 1, DisplayPort transaction.
+	 * If Bit 3 is 0, I2C transaction.
+	 */
+	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
+		AUX_TX_COMM_WRITE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+	/* Start AUX transaction */
+	retval = analogix_dp_start_aux_transaction(dp);
+	if (retval != 0)
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select EDID device */
+		retval = analogix_dp_select_i2c_device(dp, device_addr,
+						       reg_addr);
+		if (retval != 0)
+			continue;
+
+		/*
+		 * Set I2C transaction and read data
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_I2C_TRANSACTION |
+			AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+	}
+
+	/* Read data */
+	if (retval == 0)
+		*data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[])
+{
+	u32 reg;
+	unsigned int i, j;
+	unsigned int cur_data_idx;
+	unsigned int defer = 0;
+	int retval = 0;
+
+	for (i = 0; i < count; i += 16) {
+		for (j = 0; j < 3; j++) {
+			/* Clear AUX CH data buffer */
+			reg = BUF_CLR;
+			writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+			/* Set normal AUX CH command */
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+			reg &= ~ADDR_ONLY;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+
+			/*
+			 * If Rx sends defer, Tx sends only reads
+			 * request without sending address
+			 */
+			if (!defer)
+				retval = analogix_dp_select_i2c_device(
+						dp, device_addr, reg_addr + i);
+			else
+				defer = 0;
+
+			if (retval == 0) {
+				/*
+				 * Set I2C transaction and write data
+				 * If bit 3 is 1, DisplayPort transaction.
+				 * If Bit 3 is 0, I2C transaction.
+				 */
+				reg = AUX_LENGTH(16) |
+					AUX_TX_COMM_I2C_TRANSACTION |
+					AUX_TX_COMM_READ;
+				writel(reg, dp->reg_base +
+					ANALOGIX_DP_AUX_CH_CTL_1);
+
+				/* Start AUX transaction */
+				retval = analogix_dp_start_aux_transaction(dp);
+				if (retval == 0)
+					break;
+
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
+			}
+			/* Check if Rx sends defer */
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
+			if (reg == AUX_RX_COMM_AUX_DEFER ||
+			    reg == AUX_RX_COMM_I2C_DEFER) {
+				dev_err(dp->dev, "Defer: %d\n\n", reg);
+				defer = 1;
+			}
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			edid[i + cur_data_idx] = (unsigned char)reg;
+		}
+	}
+
+	return retval;
+}
+
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
+{
+	u32 reg;
+
+	reg = bwtype;
+	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
+		writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
+}
+
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
+	*bwtype = reg;
+}
+
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
+{
+	u32 reg;
+
+	reg = count;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
+}
+
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
+	*count = reg;
+}
+
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg |= ENHANCED;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg &= ~ENHANCED;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+	}
+}
+
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				      enum pattern_set pattern)
+{
+	u32 reg;
+
+	switch (pattern) {
+	case PRBS7:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case D10_2:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN1:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN2:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case DP_NONE:
+		reg = SCRAMBLING_ENABLE |
+			LINK_QUAL_PATTERN_SET_DISABLE |
+			SW_TRAINING_PATTERN_SET_NORMAL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+}
+
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+	return reg;
+}
+
+void analogix_dp_reset_macro(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
+	reg |= MACRO_RST;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+
+	/* 10 us is the minimum reset time. */
+	usleep_range(10, 20);
+
+	reg &= ~MACRO_RST;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+}
+
+void analogix_dp_init_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	reg = CHA_CRI(4) | CHA_CTRL;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+
+	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
+}
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Configure the input color depth, color space, dynamic range */
+	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info->color_depth << IN_BPC_SHIFT) |
+		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
+
+	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
+	reg &= ~IN_YC_COEFFI_MASK;
+	if (dp->video_info->ycbcr_coeff)
+		reg |= IN_YC_COEFFI_ITU709;
+	else
+		reg |= IN_YC_COEFFI_ITU601;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
+}
+
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	if (!(reg & DET_STA)) {
+		dev_dbg(dp->dev, "Input stream clock not detected.\n");
+		return -EINVAL;
+	}
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
+
+	if (reg & CHA_STA) {
+		dev_dbg(dp->dev, "Input stream clk is changing\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value, u32 n_value)
+{
+	u32 reg;
+
+	if (type == REGISTER_M) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg |= FIX_M_VID;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg = m_value & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
+		reg = (m_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
+		reg = (m_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
+
+		reg = n_value & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		reg = (n_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		reg = (n_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
+	} else  {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg &= ~FIX_M_VID;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
+	}
+}
+
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
+{
+	u32 reg;
+
+	if (type == VIDEO_TIMING_FROM_CAPTURE) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+		reg &= ~FORMAT_SEL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+		reg |= FORMAT_SEL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	}
+}
+
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MODE_SLAVE_MODE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+	}
+}
+
+void analogix_dp_start_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	reg |= VIDEO_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+}
+
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	if (!(reg & STRM_VALID)) {
+		dev_dbg(dp->dev, "Input video stream is not detected.\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
+	reg |= MASTER_VID_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~INTERACE_SCAN_CFG;
+	reg |= (dp->video_info->interlaced << 2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~VSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->v_sync_polarity << 1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~HSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->h_sync_polarity << 0);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+	reg &= ~SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+}
+
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+	reg |= SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
similarity index 64%
rename from drivers/gpu/drm/exynos/exynos_dp_reg.h
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 2e9bd0e..2d878fd 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -1,5 +1,5 @@
 /*
- * Register definition file for Samsung DP driver
+ * Register definition file for Analogix DP core driver
  *
  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
@@ -9,96 +9,96 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef _EXYNOS_DP_REG_H
-#define _EXYNOS_DP_REG_H
-
-#define EXYNOS_DP_TX_SW_RESET			0x14
-#define EXYNOS_DP_FUNC_EN_1			0x18
-#define EXYNOS_DP_FUNC_EN_2			0x1C
-#define EXYNOS_DP_VIDEO_CTL_1			0x20
-#define EXYNOS_DP_VIDEO_CTL_2			0x24
-#define EXYNOS_DP_VIDEO_CTL_3			0x28
-
-#define EXYNOS_DP_VIDEO_CTL_8			0x3C
-#define EXYNOS_DP_VIDEO_CTL_10			0x44
-
-#define EXYNOS_DP_LANE_MAP			0x35C
-
-#define EXYNOS_DP_ANALOG_CTL_1			0x370
-#define EXYNOS_DP_ANALOG_CTL_2			0x374
-#define EXYNOS_DP_ANALOG_CTL_3			0x378
-#define EXYNOS_DP_PLL_FILTER_CTL_1		0x37C
-#define EXYNOS_DP_TX_AMP_TUNING_CTL		0x380
-
-#define EXYNOS_DP_AUX_HW_RETRY_CTL		0x390
-
-#define EXYNOS_DP_COMMON_INT_STA_1		0x3C4
-#define EXYNOS_DP_COMMON_INT_STA_2		0x3C8
-#define EXYNOS_DP_COMMON_INT_STA_3		0x3CC
-#define EXYNOS_DP_COMMON_INT_STA_4		0x3D0
-#define EXYNOS_DP_INT_STA			0x3DC
-#define EXYNOS_DP_COMMON_INT_MASK_1		0x3E0
-#define EXYNOS_DP_COMMON_INT_MASK_2		0x3E4
-#define EXYNOS_DP_COMMON_INT_MASK_3		0x3E8
-#define EXYNOS_DP_COMMON_INT_MASK_4		0x3EC
-#define EXYNOS_DP_INT_STA_MASK			0x3F8
-#define EXYNOS_DP_INT_CTL			0x3FC
-
-#define EXYNOS_DP_SYS_CTL_1			0x600
-#define EXYNOS_DP_SYS_CTL_2			0x604
-#define EXYNOS_DP_SYS_CTL_3			0x608
-#define EXYNOS_DP_SYS_CTL_4			0x60C
-
-#define EXYNOS_DP_PKT_SEND_CTL			0x640
-#define EXYNOS_DP_HDCP_CTL			0x648
-
-#define EXYNOS_DP_LINK_BW_SET			0x680
-#define EXYNOS_DP_LANE_COUNT_SET		0x684
-#define EXYNOS_DP_TRAINING_PTN_SET		0x688
-#define EXYNOS_DP_LN0_LINK_TRAINING_CTL		0x68C
-#define EXYNOS_DP_LN1_LINK_TRAINING_CTL		0x690
-#define EXYNOS_DP_LN2_LINK_TRAINING_CTL		0x694
-#define EXYNOS_DP_LN3_LINK_TRAINING_CTL		0x698
-
-#define EXYNOS_DP_DEBUG_CTL			0x6C0
-#define EXYNOS_DP_HPD_DEGLITCH_L		0x6C4
-#define EXYNOS_DP_HPD_DEGLITCH_H		0x6C8
-#define EXYNOS_DP_LINK_DEBUG_CTL		0x6E0
-
-#define EXYNOS_DP_M_VID_0			0x700
-#define EXYNOS_DP_M_VID_1			0x704
-#define EXYNOS_DP_M_VID_2			0x708
-#define EXYNOS_DP_N_VID_0			0x70C
-#define EXYNOS_DP_N_VID_1			0x710
-#define EXYNOS_DP_N_VID_2			0x714
-
-#define EXYNOS_DP_PLL_CTL			0x71C
-#define EXYNOS_DP_PHY_PD			0x720
-#define EXYNOS_DP_PHY_TEST			0x724
-
-#define EXYNOS_DP_VIDEO_FIFO_THRD		0x730
-#define EXYNOS_DP_AUDIO_MARGIN			0x73C
-
-#define EXYNOS_DP_M_VID_GEN_FILTER_TH		0x764
-#define EXYNOS_DP_M_AUD_GEN_FILTER_TH		0x778
-#define EXYNOS_DP_AUX_CH_STA			0x780
-#define EXYNOS_DP_AUX_CH_DEFER_CTL		0x788
-#define EXYNOS_DP_AUX_RX_COMM			0x78C
-#define EXYNOS_DP_BUFFER_DATA_CTL		0x790
-#define EXYNOS_DP_AUX_CH_CTL_1			0x794
-#define EXYNOS_DP_AUX_ADDR_7_0			0x798
-#define EXYNOS_DP_AUX_ADDR_15_8			0x79C
-#define EXYNOS_DP_AUX_ADDR_19_16		0x7A0
-#define EXYNOS_DP_AUX_CH_CTL_2			0x7A4
-
-#define EXYNOS_DP_BUF_DATA_0			0x7C0
-
-#define EXYNOS_DP_SOC_GENERAL_CTL		0x800
-
-/* EXYNOS_DP_TX_SW_RESET */
+#ifndef _ANALOGIX_DP_REG_H
+#define _ANALOGIX_DP_REG_H
+
+#define ANALOGIX_DP_TX_SW_RESET			0x14
+#define ANALOGIX_DP_FUNC_EN_1			0x18
+#define ANALOGIX_DP_FUNC_EN_2			0x1C
+#define ANALOGIX_DP_VIDEO_CTL_1			0x20
+#define ANALOGIX_DP_VIDEO_CTL_2			0x24
+#define ANALOGIX_DP_VIDEO_CTL_3			0x28
+
+#define ANALOGIX_DP_VIDEO_CTL_8			0x3C
+#define ANALOGIX_DP_VIDEO_CTL_10			0x44
+
+#define ANALOGIX_DP_LANE_MAP			0x35C
+
+#define ANALOGIX_DP_ANALOG_CTL_1			0x370
+#define ANALOGIX_DP_ANALOG_CTL_2			0x374
+#define ANALOGIX_DP_ANALOG_CTL_3			0x378
+#define ANALOGIX_DP_PLL_FILTER_CTL_1		0x37C
+#define ANALOGIX_DP_TX_AMP_TUNING_CTL		0x380
+
+#define ANALOGIX_DP_AUX_HW_RETRY_CTL		0x390
+
+#define ANALOGIX_DP_COMMON_INT_STA_1		0x3C4
+#define ANALOGIX_DP_COMMON_INT_STA_2		0x3C8
+#define ANALOGIX_DP_COMMON_INT_STA_3		0x3CC
+#define ANALOGIX_DP_COMMON_INT_STA_4		0x3D0
+#define ANALOGIX_DP_INT_STA			0x3DC
+#define ANALOGIX_DP_COMMON_INT_MASK_1		0x3E0
+#define ANALOGIX_DP_COMMON_INT_MASK_2		0x3E4
+#define ANALOGIX_DP_COMMON_INT_MASK_3		0x3E8
+#define ANALOGIX_DP_COMMON_INT_MASK_4		0x3EC
+#define ANALOGIX_DP_INT_STA_MASK			0x3F8
+#define ANALOGIX_DP_INT_CTL			0x3FC
+
+#define ANALOGIX_DP_SYS_CTL_1			0x600
+#define ANALOGIX_DP_SYS_CTL_2			0x604
+#define ANALOGIX_DP_SYS_CTL_3			0x608
+#define ANALOGIX_DP_SYS_CTL_4			0x60C
+
+#define ANALOGIX_DP_PKT_SEND_CTL			0x640
+#define ANALOGIX_DP_HDCP_CTL			0x648
+
+#define ANALOGIX_DP_LINK_BW_SET			0x680
+#define ANALOGIX_DP_LANE_COUNT_SET		0x684
+#define ANALOGIX_DP_TRAINING_PTN_SET		0x688
+#define ANALOGIX_DP_LN0_LINK_TRAINING_CTL		0x68C
+#define ANALOGIX_DP_LN1_LINK_TRAINING_CTL		0x690
+#define ANALOGIX_DP_LN2_LINK_TRAINING_CTL		0x694
+#define ANALOGIX_DP_LN3_LINK_TRAINING_CTL		0x698
+
+#define ANALOGIX_DP_DEBUG_CTL			0x6C0
+#define ANALOGIX_DP_HPD_DEGLITCH_L		0x6C4
+#define ANALOGIX_DP_HPD_DEGLITCH_H		0x6C8
+#define ANALOGIX_DP_LINK_DEBUG_CTL		0x6E0
+
+#define ANALOGIX_DP_M_VID_0			0x700
+#define ANALOGIX_DP_M_VID_1			0x704
+#define ANALOGIX_DP_M_VID_2			0x708
+#define ANALOGIX_DP_N_VID_0			0x70C
+#define ANALOGIX_DP_N_VID_1			0x710
+#define ANALOGIX_DP_N_VID_2			0x714
+
+#define ANALOGIX_DP_PLL_CTL			0x71C
+#define ANALOGIX_DP_PHY_PD			0x720
+#define ANALOGIX_DP_PHY_TEST			0x724
+
+#define ANALOGIX_DP_VIDEO_FIFO_THRD		0x730
+#define ANALOGIX_DP_AUDIO_MARGIN			0x73C
+
+#define ANALOGIX_DP_M_VID_GEN_FILTER_TH		0x764
+#define ANALOGIX_DP_M_AUD_GEN_FILTER_TH		0x778
+#define ANALOGIX_DP_AUX_CH_STA			0x780
+#define ANALOGIX_DP_AUX_CH_DEFER_CTL		0x788
+#define ANALOGIX_DP_AUX_RX_COMM			0x78C
+#define ANALOGIX_DP_BUFFER_DATA_CTL		0x790
+#define ANALOGIX_DP_AUX_CH_CTL_1			0x794
+#define ANALOGIX_DP_AUX_ADDR_7_0			0x798
+#define ANALOGIX_DP_AUX_ADDR_15_8			0x79C
+#define ANALOGIX_DP_AUX_ADDR_19_16		0x7A0
+#define ANALOGIX_DP_AUX_CH_CTL_2			0x7A4
+
+#define ANALOGIX_DP_BUF_DATA_0			0x7C0
+
+#define ANALOGIX_DP_SOC_GENERAL_CTL		0x800
+
+/* ANALOGIX_DP_TX_SW_RESET */
 #define RESET_DP_TX				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_1 */
+/* ANALOGIX_DP_FUNC_EN_1 */
 #define MASTER_VID_FUNC_EN_N			(0x1 << 7)
 #define SLAVE_VID_FUNC_EN_N			(0x1 << 5)
 #define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
@@ -107,17 +107,17 @@
 #define CRC_FUNC_EN_N				(0x1 << 1)
 #define SW_FUNC_EN_N				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_2 */
+/* ANALOGIX_DP_FUNC_EN_2 */
 #define SSC_FUNC_EN_N				(0x1 << 7)
 #define AUX_FUNC_EN_N				(0x1 << 2)
 #define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
 #define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define VIDEO_EN				(0x1 << 7)
 #define HDCP_VIDEO_MUTE				(0x1 << 6)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define IN_D_RANGE_MASK				(0x1 << 7)
 #define IN_D_RANGE_SHIFT			(7)
 #define IN_D_RANGE_CEA				(0x1 << 7)
@@ -134,7 +134,7 @@
 #define IN_COLOR_F_YCBCR422			(0x1 << 0)
 #define IN_COLOR_F_RGB				(0x0 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_3 */
+/* ANALOGIX_DP_VIDEO_CTL_3 */
 #define IN_YC_COEFFI_MASK			(0x1 << 7)
 #define IN_YC_COEFFI_SHIFT			(7)
 #define IN_YC_COEFFI_ITU709			(0x1 << 7)
@@ -144,17 +144,17 @@
 #define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
 #define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
 
-/* EXYNOS_DP_VIDEO_CTL_8 */
+/* ANALOGIX_DP_VIDEO_CTL_8 */
 #define VID_HRES_TH(x)				(((x) & 0xf) << 4)
 #define VID_VRES_TH(x)				(((x) & 0xf) << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_10 */
+/* ANALOGIX_DP_VIDEO_CTL_10 */
 #define FORMAT_SEL				(0x1 << 4)
 #define INTERACE_SCAN_CFG			(0x1 << 2)
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
-/* EXYNOS_DP_LANE_MAP */
+/* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
 #define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
@@ -172,30 +172,30 @@
 #define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
 #define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_1 */
+/* ANALOGIX_DP_ANALOG_CTL_1 */
 #define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
 
-/* EXYNOS_DP_ANALOG_CTL_2 */
+/* ANALOGIX_DP_ANALOG_CTL_2 */
 #define SEL_24M					(0x1 << 3)
 #define TX_DVDD_BIT_1_0625V			(0x4 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_3 */
+/* ANALOGIX_DP_ANALOG_CTL_3 */
 #define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
 #define VCO_BIT_600_MICRO			(0x5 << 0)
 
-/* EXYNOS_DP_PLL_FILTER_CTL_1 */
+/* ANALOGIX_DP_PLL_FILTER_CTL_1 */
 #define PD_RING_OSC				(0x1 << 6)
 #define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
 #define TX_CUR1_2X				(0x1 << 2)
 #define TX_CUR_16_MA				(0x3 << 0)
 
-/* EXYNOS_DP_TX_AMP_TUNING_CTL */
+/* ANALOGIX_DP_TX_AMP_TUNING_CTL */
 #define CH3_AMP_400_MV				(0x0 << 24)
 #define CH2_AMP_400_MV				(0x0 << 16)
 #define CH1_AMP_400_MV				(0x0 << 8)
 #define CH0_AMP_400_MV				(0x0 << 0)
 
-/* EXYNOS_DP_AUX_HW_RETRY_CTL */
+/* ANALOGIX_DP_AUX_HW_RETRY_CTL */
 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x)	(((x) & 0x7) << 8)
 #define AUX_HW_RETRY_INTERVAL_MASK		(0x3 << 3)
 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS	(0x0 << 3)
@@ -204,7 +204,7 @@
 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS	(0x3 << 3)
 #define AUX_HW_RETRY_COUNT_SEL(x)		(((x) & 0x7) << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_1 */
+/* ANALOGIX_DP_COMMON_INT_STA_1 */
 #define VSYNC_DET				(0x1 << 7)
 #define PLL_LOCK_CHG				(0x1 << 6)
 #define SPDIF_ERR				(0x1 << 5)
@@ -214,19 +214,19 @@
 #define VID_CLK_CHG				(0x1 << 1)
 #define SW_INT					(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_2 */
+/* ANALOGIX_DP_COMMON_INT_STA_2 */
 #define ENC_EN_CHG				(0x1 << 6)
 #define HW_BKSV_RDY				(0x1 << 3)
 #define HW_SHA_DONE				(0x1 << 2)
 #define HW_AUTH_STATE_CHG			(0x1 << 1)
 #define HW_AUTH_DONE				(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_3 */
+/* ANALOGIX_DP_COMMON_INT_STA_3 */
 #define AFIFO_UNDER				(0x1 << 7)
 #define AFIFO_OVER				(0x1 << 6)
 #define R0_CHK_FLAG				(0x1 << 5)
 
-/* EXYNOS_DP_COMMON_INT_STA_4 */
+/* ANALOGIX_DP_COMMON_INT_STA_4 */
 #define PSR_ACTIVE				(0x1 << 7)
 #define PSR_INACTIVE				(0x1 << 6)
 #define SPDIF_BI_PHASE_ERR			(0x1 << 5)
@@ -234,29 +234,29 @@
 #define HPD_LOST				(0x1 << 1)
 #define PLUG					(0x1 << 0)
 
-/* EXYNOS_DP_INT_STA */
+/* ANALOGIX_DP_INT_STA */
 #define INT_HPD					(0x1 << 6)
 #define HW_TRAINING_FINISH			(0x1 << 5)
 #define RPLY_RECEIV				(0x1 << 1)
 #define AUX_ERR					(0x1 << 0)
 
-/* EXYNOS_DP_INT_CTL */
+/* ANALOGIX_DP_INT_CTL */
 #define SOFT_INT_CTRL				(0x1 << 2)
 #define INT_POL1				(0x1 << 1)
 #define INT_POL0				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_1 */
+/* ANALOGIX_DP_SYS_CTL_1 */
 #define DET_STA					(0x1 << 2)
 #define FORCE_DET				(0x1 << 1)
 #define DET_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_2 */
+/* ANALOGIX_DP_SYS_CTL_2 */
 #define CHA_CRI(x)				(((x) & 0xf) << 4)
 #define CHA_STA					(0x1 << 2)
 #define FORCE_CHA				(0x1 << 1)
 #define CHA_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_3 */
+/* ANALOGIX_DP_SYS_CTL_3 */
 #define HPD_STATUS				(0x1 << 6)
 #define F_HPD					(0x1 << 5)
 #define HPD_CTRL				(0x1 << 4)
@@ -265,13 +265,13 @@
 #define F_VALID					(0x1 << 1)
 #define VALID_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_4 */
+/* ANALOGIX_DP_SYS_CTL_4 */
 #define FIX_M_AUD				(0x1 << 4)
 #define ENHANCED				(0x1 << 3)
 #define FIX_M_VID				(0x1 << 2)
 #define M_VID_UPDATE_CTRL			(0x3 << 0)
 
-/* EXYNOS_DP_TRAINING_PTN_SET */
+/* ANALOGIX_DP_TRAINING_PTN_SET */
 #define SCRAMBLER_TYPE				(0x1 << 9)
 #define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
 #define SCRAMBLING_DISABLE			(0x1 << 5)
@@ -285,24 +285,24 @@
 #define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
 #define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
 
-/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+/* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */
 #define PRE_EMPHASIS_SET_MASK			(0x3 << 3)
 #define PRE_EMPHASIS_SET_SHIFT			(3)
 
-/* EXYNOS_DP_DEBUG_CTL */
+/* ANALOGIX_DP_DEBUG_CTL */
 #define PLL_LOCK				(0x1 << 4)
 #define F_PLL_LOCK				(0x1 << 3)
 #define PLL_LOCK_CTRL				(0x1 << 2)
 #define PN_INV					(0x1 << 0)
 
-/* EXYNOS_DP_PLL_CTL */
+/* ANALOGIX_DP_PLL_CTL */
 #define DP_PLL_PD				(0x1 << 7)
 #define DP_PLL_RESET				(0x1 << 6)
 #define DP_PLL_LOOP_BIT_DEFAULT			(0x1 << 4)
 #define DP_PLL_REF_BIT_1_1250V			(0x5 << 0)
 #define DP_PLL_REF_BIT_1_2500V			(0x7 << 0)
 
-/* EXYNOS_DP_PHY_PD */
+/* ANALOGIX_DP_PHY_PD */
 #define DP_PHY_PD				(0x1 << 5)
 #define AUX_PD					(0x1 << 4)
 #define CH3_PD					(0x1 << 3)
@@ -310,28 +310,28 @@
 #define CH1_PD					(0x1 << 1)
 #define CH0_PD					(0x1 << 0)
 
-/* EXYNOS_DP_PHY_TEST */
+/* ANALOGIX_DP_PHY_TEST */
 #define MACRO_RST				(0x1 << 5)
 #define CH1_TEST				(0x1 << 1)
 #define CH0_TEST				(0x1 << 0)
 
-/* EXYNOS_DP_AUX_CH_STA */
+/* ANALOGIX_DP_AUX_CH_STA */
 #define AUX_BUSY				(0x1 << 4)
 #define AUX_STATUS_MASK				(0xf << 0)
 
-/* EXYNOS_DP_AUX_CH_DEFER_CTL */
+/* ANALOGIX_DP_AUX_CH_DEFER_CTL */
 #define DEFER_CTRL_EN				(0x1 << 7)
 #define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
 
-/* EXYNOS_DP_AUX_RX_COMM */
+/* ANALOGIX_DP_AUX_RX_COMM */
 #define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
 #define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
 
-/* EXYNOS_DP_BUFFER_DATA_CTL */
+/* ANALOGIX_DP_BUFFER_DATA_CTL */
 #define BUF_CLR					(0x1 << 7)
 #define BUF_DATA_COUNT(x)			(((x) & 0x1f) << 0)
 
-/* EXYNOS_DP_AUX_CH_CTL_1 */
+/* ANALOGIX_DP_AUX_CH_CTL_1 */
 #define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
 #define AUX_TX_COMM_MASK			(0xf << 0)
 #define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
@@ -340,20 +340,20 @@
 #define AUX_TX_COMM_WRITE			(0x0 << 0)
 #define AUX_TX_COMM_READ			(0x1 << 0)
 
-/* EXYNOS_DP_AUX_ADDR_7_0 */
+/* ANALOGIX_DP_AUX_ADDR_7_0 */
 #define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_15_8 */
+/* ANALOGIX_DP_AUX_ADDR_15_8 */
 #define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_19_16 */
+/* ANALOGIX_DP_AUX_ADDR_19_16 */
 #define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
 
-/* EXYNOS_DP_AUX_CH_CTL_2 */
+/* ANALOGIX_DP_AUX_CH_CTL_2 */
 #define ADDR_ONLY				(0x1 << 1)
 #define AUX_EN					(0x1 << 0)
 
-/* EXYNOS_DP_SOC_GENERAL_CTL */
+/* ANALOGIX_DP_SOC_GENERAL_CTL */
 #define AUDIO_MODE_SPDIF_MODE			(0x1 << 8)
 #define AUDIO_MODE_MASTER_MODE			(0x0 << 8)
 #define MASTER_VIDEO_INTERLACE_EN		(0x1 << 4)
@@ -363,4 +363,4 @@
 #define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
 #define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
 
-#endif /* _EXYNOS_DP_REG_H */
+#endif /* _ANALOGIX_DP_REG_H */
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index bd1a415..5f74f80 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -55,8 +55,9 @@ config DRM_EXYNOS_DSI
 	  This enables support for Exynos MIPI-DSI device.
 
 config DRM_EXYNOS_DP
-	bool "EXYNOS DRM DP driver support"
+	bool "EXYNOS specific extensions for Analogix DP driver"
 	depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON)
+	select DRM_ANALOGIX_DP
 	default DRM_EXYNOS
 	select DRM_PANEL
 	help
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index 02aecfe..4453798 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -13,7 +13,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON)	+= exynos5433_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON)	+= exynos7_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DPI)	+= exynos_drm_dpi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DSI)	+= exynos_drm_dsi.o
-exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o exynos_dp_reg.o
+exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)	+= exynos_hdmi.o exynos_mixer.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI)	+= exynos_drm_vidi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_G2D)	+= exynos_drm_g2d.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
new file mode 100644
index 0000000..7e1be72
--- /dev/null
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -0,0 +1,306 @@
+/*
+ * Samsung SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_graph.h>
+#include <video/of_display_timing.h>
+#include <video/of_videomode.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_crtc_helper.h>
+
+#include <drm/bridge/analogix_dp.h>
+#include <drm/exynos_drm.h>
+
+#include "exynos_drm_crtc.h"
+
+#define plat_data_to_dp(pd) \
+		container_of(pd, struct exynos_dp_device, plat_data)
+
+struct exynos_dp_device {
+	struct drm_encoder         encoder;
+	struct drm_bridge          *ptn_bridge;
+	struct drm_device          *drm_dev;
+	struct device              *dev;
+
+	struct exynos_drm_panel_info priv;
+	struct analogix_dp_plat_data plat_data;
+};
+
+int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
+				bool enable)
+{
+	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct exynos_drm_crtc *crtc;
+
+	if (!encoder)
+		return -1;
+
+	crtc = to_exynos_crtc(encoder->crtc);
+	if (crtc && crtc->ops && crtc->ops->clock_enable)
+		crtc->ops->clock_enable(crtc, enable);
+
+	return 0;
+}
+
+static int exynos_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	return exynos_dp_crtc_clock_enable(plat_data, true);
+}
+
+static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
+{
+	return exynos_dp_crtc_clock_enable(plat_data, false);
+}
+
+static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
+			       struct drm_connector *connector)
+{
+	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
+	struct drm_display_mode *mode;
+
+	if (dp->plat_data.panel)
+		return 0;
+
+	mode = drm_mode_create(connector->dev);
+	if (!mode) {
+		DRM_ERROR("failed to create a new display mode.\n");
+		return 0;
+	}
+
+	drm_display_mode_from_videomode(&dp->priv.vm, mode);
+	mode->width_mm = dp->priv.width_mm;
+	mode->height_mm = dp->priv.height_mm;
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_set_name(mode);
+	drm_mode_probed_add(connector, mode);
+
+	return 1;
+}
+
+static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+				   struct drm_bridge *bridge)
+{
+	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
+	struct drm_encoder *encoder = &dp->encoder;
+	int ret;
+
+	/* Pre-empt DP connector creation if there's a bridge */
+	if (dp->ptn_bridge) {
+		bridge->next = dp->ptn_bridge;
+		dp->ptn_bridge->encoder = encoder;
+		ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
+		if (ret) {
+			DRM_ERROR("Failed to attach bridge to drm\n");
+			bridge->next = NULL;
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+				 const struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
+static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
+	.mode_fixup = exynos_dp_mode_fixup,
+	.mode_set = exynos_dp_mode_set,
+	.enable = exynos_dp_enable,
+	.disable = exynos_dp_disable,
+};
+
+static struct drm_encoder_funcs exynos_dp_encoder_funcs = {
+	.destroy = drm_encoder_cleanup,
+};
+
+static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
+{
+	int ret;
+
+	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
+			       OF_USE_NATIVE_MODE);
+	if (ret) {
+		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
+		return ret;
+	}
+	return 0;
+}
+
+static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
+{
+	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = data;
+	int pipe, ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	dp->dev = dev;
+	dp->drm_dev = drm_dev;
+
+	dp->plat_data.power_on = exynos_dp_poweron;
+	dp->plat_data.power_off = exynos_dp_poweroff;
+	dp->plat_data.get_modes = exynos_dp_get_modes;
+	dp->plat_data.attach = exynos_dp_bridge_attach;
+
+	if (!dp->plat_data.panel || !dp->ptn_bridge) {
+		ret = exynos_dp_dt_parse_panel(dp);
+		if (ret)
+			return ret;
+	}
+
+	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
+						  EXYNOS_DISPLAY_TYPE_LCD);
+	if (pipe < 0)
+		return pipe;
+
+	encoder->possible_crtcs = 1 << pipe;
+
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
+			 DRM_MODE_ENCODER_TMDS);
+
+	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
+
+	return analogix_dp_bind(dev, dp->drm_dev, encoder, &dp->plat_data);
+}
+
+static void exynos_dp_unbind(struct device *dev, struct device *master,
+			     void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops exynos_dp_ops = {
+	.bind	= exynos_dp_bind,
+	.unbind	= exynos_dp_unbind,
+};
+
+static int exynos_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *bridge_node, *endpoint;
+	struct exynos_dp_device *dp;
+
+	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
+			  GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver would take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	panel_node = of_parse_phandle(dev->of_node, "panel", 0);
+	if (panel_node) {
+		dp->plat_data.panel = of_drm_find_panel(panel_node);
+		of_node_put(panel_node);
+		if (!dp->plat_data.panel)
+			return -EPROBE_DEFER;
+	}
+
+	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
+	if (endpoint) {
+		bridge_node = of_graph_get_remote_port_parent(endpoint);
+		if (bridge_node) {
+			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
+			of_node_put(bridge_node);
+			if (!dp->ptn_bridge)
+				return -EPROBE_DEFER;
+		} else {
+			return -EPROBE_DEFER;
+		}
+	}
+
+	return component_add(&pdev->dev, &exynos_dp_ops);
+}
+
+static int exynos_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &exynos_dp_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int exynos_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops exynos_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
+};
+
+static const struct of_device_id exynos_dp_match[] = {
+	{ .compatible = "samsung,exynos5-dp" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, exynos_dp_match);
+
+struct platform_driver dp_driver = {
+	.probe		= exynos_dp_probe,
+	.remove		= exynos_dp_remove,
+	.driver		= {
+		.name	= "exynos-dp",
+		.owner	= THIS_MODULE,
+		.pm	= &exynos_dp_pm_ops,
+		.of_match_table = exynos_dp_match,
+	},
+};
+
+MODULE_AUTHOR("Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
+MODULE_DESCRIPTION("Samsung Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
deleted file mode 100644
index 7ff754f..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Header file for Samsung DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef _EXYNOS_DP_CORE_H
-#define _EXYNOS_DP_CORE_H
-
-#include <drm/drm_crtc.h>
-#include <drm/drm_dp_helper.h>
-#include <drm/exynos_drm.h>
-
-#include "exynos_drm_drv.h"
-
-#define DP_TIMEOUT_LOOP_COUNT 100
-#define MAX_CR_LOOP 5
-#define MAX_EQ_LOOP 5
-
-enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
-};
-
-enum link_lane_count_type {
-	LANE_COUNT1 = 1,
-	LANE_COUNT2 = 2,
-	LANE_COUNT4 = 4
-};
-
-enum link_training_state {
-	START,
-	CLOCK_RECOVERY,
-	EQUALIZER_TRAINING,
-	FINISHED,
-	FAILED
-};
-
-enum voltage_swing_level {
-	VOLTAGE_LEVEL_0,
-	VOLTAGE_LEVEL_1,
-	VOLTAGE_LEVEL_2,
-	VOLTAGE_LEVEL_3,
-};
-
-enum pre_emphasis_level {
-	PRE_EMPHASIS_LEVEL_0,
-	PRE_EMPHASIS_LEVEL_1,
-	PRE_EMPHASIS_LEVEL_2,
-	PRE_EMPHASIS_LEVEL_3,
-};
-
-enum pattern_set {
-	PRBS7,
-	D10_2,
-	TRAINING_PTN1,
-	TRAINING_PTN2,
-	DP_NONE
-};
-
-enum color_space {
-	COLOR_RGB,
-	COLOR_YCBCR422,
-	COLOR_YCBCR444
-};
-
-enum color_depth {
-	COLOR_6,
-	COLOR_8,
-	COLOR_10,
-	COLOR_12
-};
-
-enum color_coefficient {
-	COLOR_YCBCR601,
-	COLOR_YCBCR709
-};
-
-enum dynamic_range {
-	VESA,
-	CEA
-};
-
-enum pll_status {
-	PLL_UNLOCKED,
-	PLL_LOCKED
-};
-
-enum clock_recovery_m_value_type {
-	CALCULATED_M,
-	REGISTER_M
-};
-
-enum video_timing_recognition_type {
-	VIDEO_TIMING_FROM_CAPTURE,
-	VIDEO_TIMING_FROM_REGISTER
-};
-
-enum analog_power_block {
-	AUX_BLOCK,
-	CH0_BLOCK,
-	CH1_BLOCK,
-	CH2_BLOCK,
-	CH3_BLOCK,
-	ANALOG_TOTAL,
-	POWER_ALL
-};
-
-enum dp_irq_type {
-	DP_IRQ_TYPE_HP_CABLE_IN,
-	DP_IRQ_TYPE_HP_CABLE_OUT,
-	DP_IRQ_TYPE_HP_CHANGE,
-	DP_IRQ_TYPE_UNKNOWN,
-};
-
-struct video_info {
-	char *name;
-
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
-
-	enum color_space color_space;
-	enum dynamic_range dynamic_range;
-	enum color_coefficient ycbcr_coeff;
-	enum color_depth color_depth;
-
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
-};
-
-struct link_train {
-	int eq_loop;
-	int cr_loop[4];
-
-	u8 link_rate;
-	u8 lane_count;
-	u8 training_lane[4];
-
-	enum link_training_state lt_state;
-};
-
-struct exynos_dp_device {
-	struct drm_encoder	encoder;
-	struct device		*dev;
-	struct drm_device	*drm_dev;
-	struct drm_connector	connector;
-	struct drm_panel	*panel;
-	struct drm_bridge	*bridge;
-	struct drm_bridge	*ptn_bridge;
-	struct clk		*clock;
-	unsigned int		irq;
-	void __iomem		*reg_base;
-
-	struct video_info	*video_info;
-	struct link_train	link_train;
-	struct work_struct	hotplug_work;
-	struct phy		*phy;
-	int			dpms_mode;
-	int			hpd_gpio;
-
-	struct exynos_drm_panel_info priv;
-};
-
-/* exynos_dp_reg.c */
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_stop_video(struct exynos_dp_device *dp);
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
-void exynos_dp_reset(struct exynos_dp_device *dp);
-void exynos_dp_swreset(struct exynos_dp_device *dp);
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				     enum analog_power_block block,
-				     bool enable);
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
-void exynos_dp_init_hpd(struct exynos_dp_device *dp);
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
-void exynos_dp_reset_aux(struct exynos_dp_device *dp);
-void exynos_dp_init_aux(struct exynos_dp_device *dp);
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				 unsigned int reg_addr,
-				 unsigned char data);
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				  unsigned int reg_addr,
-				  unsigned char *data);
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				  unsigned int reg_addr,
-				  unsigned int count,
-				  unsigned char data[]);
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				   unsigned int reg_addr,
-				   unsigned int count,
-				   unsigned char data[]);
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				 unsigned int device_addr,
-				 unsigned int reg_addr,
-				 unsigned int *data);
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				  unsigned int device_addr,
-				  unsigned int reg_addr,
-				  unsigned int count,
-				  unsigned char edid[]);
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				    enum pattern_set pattern);
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane);
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane);
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane);
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane);
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
-void exynos_dp_reset_macro(struct exynos_dp_device *dp);
-void exynos_dp_init_video(struct exynos_dp_device *dp);
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-			       enum clock_recovery_m_value_type type,
-			       u32 m_value,
-			       u32 n_value);
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_start_video(struct exynos_dp_device *dp);
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
-#endif /* _EXYNOS_DP_CORE_H */
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
deleted file mode 100644
index 5aff19a..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
+++ /dev/null
@@ -1,1259 +0,0 @@
-/*
- * Samsung DP (Display port) register interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-
-#include "exynos_dp_core.h"
-#include "exynos_dp_reg.h"
-
-#define COMMON_INT_MASK_1	0
-#define COMMON_INT_MASK_2	0
-#define COMMON_INT_MASK_3	0
-#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
-#define INT_STA_MASK		INT_HPD
-
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg |= HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg &= ~HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	}
-}
-
-void exynos_dp_stop_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg &= ~VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable)
-		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
-	else
-		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
-
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
-}
-
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = TX_TERMINAL_CTRL_50_OHM;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
-
-	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
-
-	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
-
-	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
-		TX_CUR1_2X | TX_CUR_16_MA;
-	writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
-
-	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
-		CH1_AMP_400_MV | CH0_AMP_400_MV;
-	writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
-}
-
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
-{
-	/* Set interrupt pin assertion polarity as high */
-	writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
-
-	/* Clear pending regisers */
-	writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-	writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
-	writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
-	writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-	writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* 0:mask,1: unmask */
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-	writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-void exynos_dp_reset(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	exynos_dp_stop_video(dp);
-	exynos_dp_enable_video_mute(dp, 0);
-
-	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
-		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
-		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
-		SERDES_FIFO_FUNC_EN_N |
-		LS_CLK_DOMAIN_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-
-	usleep_range(20, 30);
-
-	exynos_dp_lane_swap(dp, 0);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
-	writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
-
-	writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
-	writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
-
-	writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
-	writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
-
-	writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
-	writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
-
-	writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_swreset(struct exynos_dp_device *dp)
-{
-	writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
-}
-
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* 0: mask, 1: unmask */
-	reg = COMMON_INT_MASK_1;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-
-	reg = COMMON_INT_MASK_2;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-
-	reg = COMMON_INT_MASK_3;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-
-	reg = COMMON_INT_MASK_4;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-
-	reg = INT_STA_MASK;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	if (reg & PLL_LOCK)
-		return PLL_LOCKED;
-	else
-		return PLL_UNLOCKED;
-}
-
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg |= DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg &= ~DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	}
-}
-
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				     enum analog_power_block block,
-				     bool enable)
-{
-	u32 reg;
-
-	switch (block) {
-	case AUX_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH0_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH1_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH2_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH3_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case ANALOG_TOTAL:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case POWER_ALL:
-		if (enable) {
-			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
-				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
-{
-	u32 reg;
-	int timeout_loop = 0;
-
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
-
-	reg = PLL_LOCK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-
-	/* Power up PLL */
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-		exynos_dp_set_pll_power_down(dp, 0);
-
-		while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-			timeout_loop++;
-			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-				dev_err(dp->dev, "failed to get pll lock status\n");
-				return;
-			}
-			usleep_range(10, 20);
-		}
-	}
-
-	/* Enable Serdes FIFO function and Link symbol clock domain module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
-		| AUX_FUNC_EN_N);
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-	reg = INT_HPD;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-}
-
-void exynos_dp_init_hpd(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	exynos_dp_clear_hotplug_interrupts(dp);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	reg &= ~(F_HPD | HPD_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-}
-
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		reg = gpio_get_value(dp->hpd_gpio);
-		if (reg)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-		else
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-	} else {
-		/* Parse hotplug interrupt status register */
-		reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-		if (reg & PLUG)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-
-		if (reg & HPD_LOST)
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-
-		if (reg & HOTPLUG_CHG)
-			return DP_IRQ_TYPE_HP_CHANGE;
-
-		return DP_IRQ_TYPE_UNKNOWN;
-	}
-}
-
-void exynos_dp_reset_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Disable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg |= AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_init_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Clear inerrupts related to AUX channel */
-	reg = RPLY_RECEIV | AUX_ERR;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	exynos_dp_reset_aux(dp);
-
-	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
-	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
-
-	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
-	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
-
-	/* Enable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		if (gpio_get_value(dp->hpd_gpio))
-			return 0;
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-		if (reg & HPD_STATUS)
-			return 0;
-	}
-
-	return -EINVAL;
-}
-
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-}
-
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
-{
-	int reg;
-	int retval = 0;
-	int timeout_loop = 0;
-
-	/* Enable AUX CH operation */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-	reg |= AUX_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-	/* Is AUX CH command reply received? */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	while (!(reg & RPLY_RECEIV)) {
-		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "AUX CH command reply failed!\n");
-			return -ETIMEDOUT;
-		}
-		reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-		usleep_range(10, 11);
-	}
-
-	/* Clear interrupt source for AUX CH command reply */
-	writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* Clear interrupt source for AUX CH access error */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	if (reg & AUX_ERR) {
-		writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
-		return -EREMOTEIO;
-	}
-
-	/* Check AUX CH error access status */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
-	if ((reg & AUX_STATUS_MASK) != 0) {
-		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
-			reg & AUX_STATUS_MASK);
-		return -EREMOTEIO;
-	}
-
-	return retval;
-}
-
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				 unsigned int reg_addr,
-				 unsigned char data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/* Write data buffer */
-		reg = (unsigned int)data;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-		/*
-		 * Set DisplayPort transaction and write 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				  unsigned int reg_addr,
-				  unsigned char *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/*
-		 * Set DisplayPort transaction and read 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-	}
-
-	/* Read data buffer */
-	reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-	*data = (unsigned char)(reg & 0xff);
-
-	return retval;
-}
-
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				  unsigned int reg_addr,
-				  unsigned int count,
-				  unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-			     cur_data_idx++) {
-				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
-			}
-
-			/*
-			 * Set DisplayPort transaction and write
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				   unsigned int reg_addr,
-				   unsigned int count,
-				   unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		/* AUX CH Request Transaction process */
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			/*
-			 * Set DisplayPort transaction and read
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-		    cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			data[start_offset + cur_data_idx] =
-				(unsigned char)reg;
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
-{
-	u32 reg;
-	int retval;
-
-	/* Set EDID device address */
-	reg = device_addr;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-	/* Set offset from base address of EDID device */
-	writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	/*
-	 * Set I2C transaction and write address
-	 * If bit 3 is 1, DisplayPort transaction.
-	 * If Bit 3 is 0, I2C transaction.
-	 */
-	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
-		AUX_TX_COMM_WRITE;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction(dp);
-	if (retval != 0)
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				 unsigned int device_addr,
-				 unsigned int reg_addr,
-				 unsigned int *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select EDID device */
-		retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
-		if (retval != 0)
-			continue;
-
-		/*
-		 * Set I2C transaction and read data
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_I2C_TRANSACTION |
-			AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-	}
-
-	/* Read data */
-	if (retval == 0)
-		*data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				  unsigned int device_addr,
-				  unsigned int reg_addr,
-				  unsigned int count,
-				  unsigned char edid[])
-{
-	u32 reg;
-	unsigned int i, j;
-	unsigned int cur_data_idx;
-	unsigned int defer = 0;
-	int retval = 0;
-
-	for (i = 0; i < count; i += 16) {
-		for (j = 0; j < 3; j++) {
-			/* Clear AUX CH data buffer */
-			reg = BUF_CLR;
-			writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-			/* Set normal AUX CH command */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-			reg &= ~ADDR_ONLY;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-			/*
-			 * If Rx sends defer, Tx sends only reads
-			 * request without sending address
-			 */
-			if (!defer)
-				retval = exynos_dp_select_i2c_device(
-						dp, device_addr, reg_addr + i);
-			else
-				defer = 0;
-
-			if (retval == 0) {
-				/*
-				 * Set I2C transaction and write data
-				 * If bit 3 is 1, DisplayPort transaction.
-				 * If Bit 3 is 0, I2C transaction.
-				 */
-				reg = AUX_LENGTH(16) |
-				      AUX_TX_COMM_I2C_TRANSACTION |
-				      AUX_TX_COMM_READ;
-				writel(reg, dp->reg_base +
-				       EXYNOS_DP_AUX_CH_CTL_1);
-
-				/* Start AUX transaction */
-				retval = exynos_dp_start_aux_transaction(dp);
-				if (retval == 0)
-					break;
-
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
-			}
-			/* Check if Rx sends defer */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
-			if (reg == AUX_RX_COMM_AUX_DEFER ||
-			    reg == AUX_RX_COMM_I2C_DEFER) {
-				dev_err(dp->dev, "Defer: %d\n\n", reg);
-				defer = 1;
-			}
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			edid[i + cur_data_idx] = (unsigned char)reg;
-		}
-	}
-
-	return retval;
-}
-
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
-{
-	u32 reg;
-
-	reg = bwtype;
-	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
-		writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-}
-
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-	*bwtype = reg;
-}
-
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
-{
-	u32 reg;
-
-	reg = count;
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-}
-
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-	*count = reg;
-}
-
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	}
-}
-
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				    enum pattern_set pattern)
-{
-	u32 reg;
-
-	switch (pattern) {
-	case PRBS7:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case D10_2:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN1:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN2:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case DP_NONE:
-		reg = SCRAMBLING_ENABLE |
-			LINK_QUAL_PATTERN_SET_DISABLE |
-			SW_TRAINING_PATTERN_SET_NORMAL;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-				       u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	return reg;
-}
-
-void exynos_dp_reset_macro(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
-	reg |= MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	/* 10 us is the minimum reset time. */
-	usleep_range(10, 20);
-
-	reg &= ~MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-}
-
-void exynos_dp_init_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = CHA_CRI(4) | CHA_CTRL;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
-}
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
-
-	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
-		reg |= IN_YC_COEFFI_ITU709;
-	else
-		reg |= IN_YC_COEFFI_ITU601;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-}
-
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	if (!(reg & DET_STA)) {
-		dev_dbg(dp->dev, "Input stream clock not detected.\n");
-		return -EINVAL;
-	}
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
-
-	if (reg & CHA_STA) {
-		dev_dbg(dp->dev, "Input stream clk is changing\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-			       enum clock_recovery_m_value_type type,
-			       u32 m_value,
-			       u32 n_value)
-{
-	u32 reg;
-
-	if (type == REGISTER_M) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg = m_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
-		reg = (m_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
-		reg = (m_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
-
-		reg = n_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
-		reg = (n_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
-		reg = (n_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
-	} else  {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
-		writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
-	}
-}
-
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
-{
-	u32 reg;
-
-	if (type == VIDEO_TIMING_FROM_CAPTURE) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg &= ~FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg |= FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	}
-}
-
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MODE_SLAVE_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	}
-}
-
-void exynos_dp_start_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg |= VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	if (!(reg & STRM_VALID)) {
-		dev_dbg(dp->dev, "Input video stream is not detected.\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
-	reg |= MASTER_VID_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-	writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg &= ~SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
-
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg |= SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
new file mode 100644
index 0000000..8b4ffad
--- /dev/null
+++ b/include/drm/bridge/analogix_dp.h
@@ -0,0 +1,24 @@
+#ifndef _ANALOGIX_DP_H_
+#define _ANALOGIX_DP_H_
+
+#include <drm/drm_crtc.h>
+
+struct analogix_dp_plat_data {
+	struct drm_panel *panel;
+
+	int (*power_on)(struct analogix_dp_plat_data *);
+	int (*power_off)(struct analogix_dp_plat_data *);
+	int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *);
+	int (*get_modes)(struct analogix_dp_plat_data *,
+			 struct drm_connector *);
+};
+
+int analogix_dp_resume(struct device *dev);
+int analogix_dp_suspend(struct device *dev);
+
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct drm_encoder *encoder,
+		     struct analogix_dp_plat_data *plat_data);
+void analogix_dp_unbind(struct device *dev, struct device *master, void *data);
+
+#endif /* _ANALOGIX_DP_H_ */
-- 
2.1.2


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^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 04/16] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
  2015-09-01  5:46 ` Yakir Yang
@ 2015-09-01  5:52   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:52 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.

Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Jingoo Han suggest, update commit message more readable.
- Adjust the order from 05 to 04

Changes in v3:
- Take Thierry Reding suggest, link_rate and lane_count shouldn't config to
  the DT property value directly, but we can take those as hardware limite.
  For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lane,
  so DT property would like "link-rate = 0x0a" "lane-count = 4".

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 7d62f22..7196097 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -631,6 +631,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 	/*
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+	 * For DP rev.1.2, Maximum link rate of Main Link lanes
+	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 	 */
 	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
@@ -664,7 +666,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS) &&
+	    (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -905,9 +908,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
 	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
-	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
 	analogix_dp_init_video(dp);
 	ret = analogix_dp_config_video(dp);
 	if (ret)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index d7e47e0..ffabbd0 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -21,8 +21,9 @@
 #define MAX_EQ_LOOP 5
 
 enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
+	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
+	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
+	LINK_RATE_5_40GBPS = DP_LINK_BW_5_4,
 };
 
 enum link_lane_count_type {
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 04/16] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
@ 2015-09-01  5:52   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:52 UTC (permalink / raw)
  To: linux-arm-kernel

link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.

Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Jingoo Han suggest, update commit message more readable.
- Adjust the order from 05 to 04

Changes in v3:
- Take Thierry Reding suggest, link_rate and lane_count shouldn't config to
  the DT property value directly, but we can take those as hardware limite.
  For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lane,
  so DT property would like "link-rate = 0x0a" "lane-count = 4".

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 7d62f22..7196097 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -631,6 +631,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 	/*
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+	 * For DP rev.1.2, Maximum link rate of Main Link lanes
+	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 	 */
 	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
@@ -664,7 +666,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS) &&
+	    (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -905,9 +908,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
 	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
-	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
 	analogix_dp_init_video(dp);
 	ret = analogix_dp_config_video(dp);
 	if (ret)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index d7e47e0..ffabbd0 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -21,8 +21,9 @@
 #define MAX_EQ_LOOP 5
 
 enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
+	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
+	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
+	LINK_RATE_5_40GBPS = DP_LINK_BW_5_4,
 };
 
 enum link_lane_count_type {
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 05/16] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & colorimetry
  2015-09-01  5:46 ` Yakir Yang
@ 2015-09-01  5:55   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:55 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code, same to color space and color depth can be
parsed from EDID.

But presumably Exynos still relaies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Krzysztof suggest, provide backword compatibility with samsung.
- Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.

Changes in v3:
- Take Thierry Reding suggest, dynamic parse video timing info from
  struct drm_display_mode and struct drm_display_info.

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 141 +++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  58 ++++++++-
 4 files changed, 151 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 7196097..f0db92e 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -897,8 +897,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					 dp->video_info->link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
+					 dp->video_info.link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1081,6 +1081,82 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
+					struct drm_display_mode *orig_mode,
+					struct drm_display_mode *mode)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_display_info *display_info = &dp->connector.display_info;
+	struct video_info *video_info = &dp->video_info;
+	struct device_node *dp_node = dp->dev->of_node;
+	int vic;
+
+	/* interlaces & hsync pol & vsync pol */
+	video_info->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+	video_info->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+	video_info->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+	/* dynamic_range & colorimetry */
+	vic = drm_match_cea_mode(mode);
+	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
+	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
+		video_info->dynamic_range = CEA;
+		video_info->ycbcr_coeff = COLOR_YCBCR601;
+	} else if (vic) {
+		video_info->dynamic_range = CEA;
+		video_info->ycbcr_coeff = COLOR_YCBCR709;
+	} else {
+		video_info->dynamic_range = VESA;
+		video_info->ycbcr_coeff = COLOR_YCBCR709;
+	}
+
+	switch (display_info->bpc) {
+	case 12:
+		video_info->color_depth = COLOR_12;
+		break;
+	case 10:
+		video_info->color_depth = COLOR_10;
+		break;
+	case 8:
+		video_info->color_depth = COLOR_8;
+		break;
+	case 6:
+		video_info->color_depth = COLOR_6;
+		break;
+	default:
+		video_info->color_depth = COLOR_8;
+		break;
+	}
+
+	if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB444)
+		video_info->color_space = COLOR_YCBCR444;
+	else if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB422)
+		video_info->color_space = COLOR_YCBCR422;
+	else if (display_info->color_formats | DRM_COLOR_FORMAT_RGB444)
+		video_info->color_space = COLOR_RGB;
+	else
+		video_info->color_space = COLOR_RGB;
+
+	/*
+	 * NOTE: those property parseing code is used for
+	 * providing backward compatibility for samsung platform.
+	 */
+	of_property_read_u32(dp_node, "samsung,color-space",
+			     &video_info->color_space);
+	of_property_read_u32(dp_node, "samsung,dynamic-range",
+			     &video_info->dynamic_range);
+	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+			     &video_info->ycbcr_coeff);
+	of_property_read_u32(dp_node, "samsung,color-depth",
+			     &video_info->color_depth);
+	of_property_read_u32(dp_node, "hsync-active-high",
+			     (unsigned int *)&video_info->h_sync_polarity);
+	of_property_read_u32(dp_node, "vsync-active-high",
+			     (unsigned int *)&video_info->v_sync_polarity);
+	of_property_read_u32(dp_node, "interlaced",
+			     (unsigned int *)&video_info->interlaced);
+}
+
 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
@@ -1091,6 +1167,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
 	.disable = analogix_dp_bridge_disable,
 	.pre_enable = analogix_dp_bridge_nop,
 	.post_disable = analogix_dp_bridge_nop,
+	.mode_set = analogix_dp_bridge_mode_set,
 	.attach = analogix_dp_bridge_attach,
 };
 
@@ -1121,62 +1198,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 	return 0;
 }
 
-static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
-	struct device_node *dp_node = dev->of_node;
-	struct video_info *dp_video_config;
-
-	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
-				       GFP_KERNEL);
-	if (!dp_video_config)
-		return ERR_PTR(-ENOMEM);
-
-	dp_video_config->h_sync_polarity =
-		of_property_read_bool(dp_node, "hsync-active-high");
-
-	dp_video_config->v_sync_polarity =
-		of_property_read_bool(dp_node, "vsync-active-high");
-
-	dp_video_config->interlaced =
-		of_property_read_bool(dp_node, "interlaced");
-
-	if (of_property_read_u32(dp_node, "samsung,color-space",
-				 &dp_video_config->color_space)) {
-		dev_err(dev, "failed to get color-space\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				 &dp_video_config->dynamic_range)) {
-		dev_err(dev, "failed to get dynamic-range\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				 &dp_video_config->ycbcr_coeff)) {
-		dev_err(dev, "failed to get ycbcr-coeff\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				 &dp_video_config->color_depth)) {
-		dev_err(dev, "failed to get color-depth\n");
-		return ERR_PTR(-EINVAL);
-	}
+	struct device_node *dp_node = dp->dev->of_node;
+	struct video_info *video_config = &dp->video_info;
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &dp_video_config->link_rate)) {
+				 &video_info->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
-		return ERR_PTR(-EINVAL);
+		return -EINVAL;
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &dp_video_config->lane_count)) {
+				 &video_info->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
-		return ERR_PTR(-EINVAL);
+		return -EINVAL;
 	}
 
-	return dp_video_config;
+	return 0;
 }
 
 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
@@ -1205,9 +1244,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	 */
 	dp->plat_data = plat_data;
 
-	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
-	if (IS_ERR(dp->video_info))
-		return PTR_ERR(dp->video_info);
+	ret = analogix_dp_dt_parse_pdata(dp);
+	if (ret)
+		return ret;
 
 	dp->phy = devm_phy_get(dp->dev, "dp");
 	if (IS_ERR(dp->phy)) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index ffabbd0..6e3d5bc 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -154,7 +154,7 @@ struct analogix_dp_device {
 	unsigned int		irq;
 	void __iomem		*reg_base;
 
-	struct video_info	*video_info;
+	struct video_info	video_info;
 	struct link_train	link_train;
 	struct work_struct	hotplug_work;
 	struct phy		*phy;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index b879d8c..6a643be 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
 	u32 reg;
 
 	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info.color_depth << IN_BPC_SHIFT) |
+		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
 	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
+	if (dp->video_info.ycbcr_coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
@@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
+	reg |= (dp->video_info.interlaced << 2);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
+	reg |= (dp->video_info.v_sync_polarity << 1);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
+	reg |= (dp->video_info.h_sync_polarity << 0);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
index 7e1be72..6060d2c 100644
--- a/drivers/gpu/drm/exynos/exynos_dp.c
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -28,8 +28,13 @@
 
 #include "exynos_drm_crtc.h"
 
-#define plat_data_to_dp(pd) \
-		container_of(pd, struct exynos_dp_device, plat_data)
+#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
+
+struct video_info {
+	bool h_sync_polarity;
+	bool v_sync_polarity;
+	bool interlaced;
+};
 
 struct exynos_dp_device {
 	struct drm_encoder         encoder;
@@ -39,12 +44,13 @@ struct exynos_dp_device {
 
 	struct exynos_drm_panel_info priv;
 	struct analogix_dp_plat_data plat_data;
+	struct video_info            video_info;
 };
 
 int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
 				bool enable)
 {
-	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
+	struct exynos_dp_device *dp = to_dp(plat_data);
 	struct drm_encoder *encoder = &dp->encoder;
 	struct exynos_drm_crtc *crtc;
 
@@ -71,7 +77,7 @@ static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
 static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
 			       struct drm_connector *connector)
 {
-	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
+	struct exynos_dp_device *dp = to_dp(plat_data);
 	struct drm_display_mode *mode;
 
 	if (dp->plat_data.panel)
@@ -99,7 +105,7 @@ static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
 static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
 				   struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
+	struct exynos_dp_device *dp = to_dp(plat_data);
 	struct drm_encoder *encoder = &dp->encoder;
 	int ret;
 
@@ -122,6 +128,28 @@ static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
 				 const struct drm_display_mode *mode,
 				 struct drm_display_mode *adjusted_mode)
 {
+	struct exynos_dp_device *dp = to_dp(encoder);
+	int flags = adjusted_mode->flags;
+
+	flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |
+		   DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC |
+		   DRM_MODE_FLAG_INTERLACE);
+
+	if (dp->video_info.h_sync_polarity)
+		flags |= DRM_MODE_FLAG_PHSYNC;
+	else
+		flags |= DRM_MODE_FLAG_NHSYNC;
+
+	if (dp->video_info.v_sync_polarity)
+		flags |= DRM_MODE_FLAG_PVSYNC;
+	else
+		flags |= DRM_MODE_FLAG_NVSYNC;
+
+	if (dp->video_info.interlaced)
+		flags |= DRM_MODE_FLAG_INTERLACE;
+
+	adjusted_mode->flags = flags;
+
 	return true;
 }
 
@@ -163,6 +191,22 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
 	return 0;
 }
 
+static int exynos_dp_dt_parse_video_info(struct exynos_dp_device *dp)
+{
+	struct device_node *dp_node = dp->dev->of_node;
+
+	dp->video_info.h_sync_polarity =
+		of_property_read_bool(dp_node, "hsync-active-high");
+
+	dp->video_info.v_sync_polarity =
+		of_property_read_bool(dp_node, "vsync-active-high");
+
+	dp->video_info.interlaced =
+		of_property_read_bool(dp_node, "interlaced");
+
+	return 0;
+}
+
 static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
@@ -191,6 +235,10 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 			return ret;
 	}
 
+	ret = exynos_dp_dt_parse_video_info(dp);
+	if (ret)
+		return ret;
+
 	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
 						  EXYNOS_DISPLAY_TYPE_LCD);
 	if (pipe < 0)
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 05/16] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & colorimetry
@ 2015-09-01  5:55   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:55 UTC (permalink / raw)
  To: linux-arm-kernel

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code, same to color space and color depth can be
parsed from EDID.

But presumably Exynos still relaies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Krzysztof suggest, provide backword compatibility with samsung.
- Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.

Changes in v3:
- Take Thierry Reding suggest, dynamic parse video timing info from
  struct drm_display_mode and struct drm_display_info.

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 141 +++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  58 ++++++++-
 4 files changed, 151 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 7196097..f0db92e 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -897,8 +897,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					 dp->video_info->link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
+					 dp->video_info.link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1081,6 +1081,82 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
+					struct drm_display_mode *orig_mode,
+					struct drm_display_mode *mode)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_display_info *display_info = &dp->connector.display_info;
+	struct video_info *video_info = &dp->video_info;
+	struct device_node *dp_node = dp->dev->of_node;
+	int vic;
+
+	/* interlaces & hsync pol & vsync pol */
+	video_info->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+	video_info->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+	video_info->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+	/* dynamic_range & colorimetry */
+	vic = drm_match_cea_mode(mode);
+	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
+	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
+		video_info->dynamic_range = CEA;
+		video_info->ycbcr_coeff = COLOR_YCBCR601;
+	} else if (vic) {
+		video_info->dynamic_range = CEA;
+		video_info->ycbcr_coeff = COLOR_YCBCR709;
+	} else {
+		video_info->dynamic_range = VESA;
+		video_info->ycbcr_coeff = COLOR_YCBCR709;
+	}
+
+	switch (display_info->bpc) {
+	case 12:
+		video_info->color_depth = COLOR_12;
+		break;
+	case 10:
+		video_info->color_depth = COLOR_10;
+		break;
+	case 8:
+		video_info->color_depth = COLOR_8;
+		break;
+	case 6:
+		video_info->color_depth = COLOR_6;
+		break;
+	default:
+		video_info->color_depth = COLOR_8;
+		break;
+	}
+
+	if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB444)
+		video_info->color_space = COLOR_YCBCR444;
+	else if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB422)
+		video_info->color_space = COLOR_YCBCR422;
+	else if (display_info->color_formats | DRM_COLOR_FORMAT_RGB444)
+		video_info->color_space = COLOR_RGB;
+	else
+		video_info->color_space = COLOR_RGB;
+
+	/*
+	 * NOTE: those property parseing code is used for
+	 * providing backward compatibility for samsung platform.
+	 */
+	of_property_read_u32(dp_node, "samsung,color-space",
+			     &video_info->color_space);
+	of_property_read_u32(dp_node, "samsung,dynamic-range",
+			     &video_info->dynamic_range);
+	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+			     &video_info->ycbcr_coeff);
+	of_property_read_u32(dp_node, "samsung,color-depth",
+			     &video_info->color_depth);
+	of_property_read_u32(dp_node, "hsync-active-high",
+			     (unsigned int *)&video_info->h_sync_polarity);
+	of_property_read_u32(dp_node, "vsync-active-high",
+			     (unsigned int *)&video_info->v_sync_polarity);
+	of_property_read_u32(dp_node, "interlaced",
+			     (unsigned int *)&video_info->interlaced);
+}
+
 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
@@ -1091,6 +1167,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
 	.disable = analogix_dp_bridge_disable,
 	.pre_enable = analogix_dp_bridge_nop,
 	.post_disable = analogix_dp_bridge_nop,
+	.mode_set = analogix_dp_bridge_mode_set,
 	.attach = analogix_dp_bridge_attach,
 };
 
@@ -1121,62 +1198,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 	return 0;
 }
 
-static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
-	struct device_node *dp_node = dev->of_node;
-	struct video_info *dp_video_config;
-
-	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
-				       GFP_KERNEL);
-	if (!dp_video_config)
-		return ERR_PTR(-ENOMEM);
-
-	dp_video_config->h_sync_polarity =
-		of_property_read_bool(dp_node, "hsync-active-high");
-
-	dp_video_config->v_sync_polarity =
-		of_property_read_bool(dp_node, "vsync-active-high");
-
-	dp_video_config->interlaced =
-		of_property_read_bool(dp_node, "interlaced");
-
-	if (of_property_read_u32(dp_node, "samsung,color-space",
-				 &dp_video_config->color_space)) {
-		dev_err(dev, "failed to get color-space\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				 &dp_video_config->dynamic_range)) {
-		dev_err(dev, "failed to get dynamic-range\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				 &dp_video_config->ycbcr_coeff)) {
-		dev_err(dev, "failed to get ycbcr-coeff\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				 &dp_video_config->color_depth)) {
-		dev_err(dev, "failed to get color-depth\n");
-		return ERR_PTR(-EINVAL);
-	}
+	struct device_node *dp_node = dp->dev->of_node;
+	struct video_info *video_config = &dp->video_info;
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &dp_video_config->link_rate)) {
+				 &video_info->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
-		return ERR_PTR(-EINVAL);
+		return -EINVAL;
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &dp_video_config->lane_count)) {
+				 &video_info->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
-		return ERR_PTR(-EINVAL);
+		return -EINVAL;
 	}
 
-	return dp_video_config;
+	return 0;
 }
 
 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
@@ -1205,9 +1244,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	 */
 	dp->plat_data = plat_data;
 
-	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
-	if (IS_ERR(dp->video_info))
-		return PTR_ERR(dp->video_info);
+	ret = analogix_dp_dt_parse_pdata(dp);
+	if (ret)
+		return ret;
 
 	dp->phy = devm_phy_get(dp->dev, "dp");
 	if (IS_ERR(dp->phy)) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index ffabbd0..6e3d5bc 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -154,7 +154,7 @@ struct analogix_dp_device {
 	unsigned int		irq;
 	void __iomem		*reg_base;
 
-	struct video_info	*video_info;
+	struct video_info	video_info;
 	struct link_train	link_train;
 	struct work_struct	hotplug_work;
 	struct phy		*phy;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index b879d8c..6a643be 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
 	u32 reg;
 
 	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info.color_depth << IN_BPC_SHIFT) |
+		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
 	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
+	if (dp->video_info.ycbcr_coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
@@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
+	reg |= (dp->video_info.interlaced << 2);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
+	reg |= (dp->video_info.v_sync_polarity << 1);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
+	reg |= (dp->video_info.h_sync_polarity << 0);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
index 7e1be72..6060d2c 100644
--- a/drivers/gpu/drm/exynos/exynos_dp.c
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -28,8 +28,13 @@
 
 #include "exynos_drm_crtc.h"
 
-#define plat_data_to_dp(pd) \
-		container_of(pd, struct exynos_dp_device, plat_data)
+#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
+
+struct video_info {
+	bool h_sync_polarity;
+	bool v_sync_polarity;
+	bool interlaced;
+};
 
 struct exynos_dp_device {
 	struct drm_encoder         encoder;
@@ -39,12 +44,13 @@ struct exynos_dp_device {
 
 	struct exynos_drm_panel_info priv;
 	struct analogix_dp_plat_data plat_data;
+	struct video_info            video_info;
 };
 
 int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
 				bool enable)
 {
-	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
+	struct exynos_dp_device *dp = to_dp(plat_data);
 	struct drm_encoder *encoder = &dp->encoder;
 	struct exynos_drm_crtc *crtc;
 
@@ -71,7 +77,7 @@ static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
 static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
 			       struct drm_connector *connector)
 {
-	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
+	struct exynos_dp_device *dp = to_dp(plat_data);
 	struct drm_display_mode *mode;
 
 	if (dp->plat_data.panel)
@@ -99,7 +105,7 @@ static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
 static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
 				   struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
+	struct exynos_dp_device *dp = to_dp(plat_data);
 	struct drm_encoder *encoder = &dp->encoder;
 	int ret;
 
@@ -122,6 +128,28 @@ static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
 				 const struct drm_display_mode *mode,
 				 struct drm_display_mode *adjusted_mode)
 {
+	struct exynos_dp_device *dp = to_dp(encoder);
+	int flags = adjusted_mode->flags;
+
+	flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |
+		   DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC |
+		   DRM_MODE_FLAG_INTERLACE);
+
+	if (dp->video_info.h_sync_polarity)
+		flags |= DRM_MODE_FLAG_PHSYNC;
+	else
+		flags |= DRM_MODE_FLAG_NHSYNC;
+
+	if (dp->video_info.v_sync_polarity)
+		flags |= DRM_MODE_FLAG_PVSYNC;
+	else
+		flags |= DRM_MODE_FLAG_NVSYNC;
+
+	if (dp->video_info.interlaced)
+		flags |= DRM_MODE_FLAG_INTERLACE;
+
+	adjusted_mode->flags = flags;
+
 	return true;
 }
 
@@ -163,6 +191,22 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
 	return 0;
 }
 
+static int exynos_dp_dt_parse_video_info(struct exynos_dp_device *dp)
+{
+	struct device_node *dp_node = dp->dev->of_node;
+
+	dp->video_info.h_sync_polarity =
+		of_property_read_bool(dp_node, "hsync-active-high");
+
+	dp->video_info.v_sync_polarity =
+		of_property_read_bool(dp_node, "vsync-active-high");
+
+	dp->video_info.interlaced =
+		of_property_read_bool(dp_node, "interlaced");
+
+	return 0;
+}
+
 static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
@@ -191,6 +235,10 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 			return ret;
 	}
 
+	ret = exynos_dp_dt_parse_video_info(dp);
+	if (ret)
+		return ret;
+
 	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
 						  EXYNOS_DISPLAY_TYPE_LCD);
 	if (pipe < 0)
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 06/16] Documentation: drm/bridge: add document for analogix_dp
  2015-09-01  5:46 ` Yakir Yang
@ 2015-09-01  5:58   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:58 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt

Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Krzysztof suggest, split all DTS changes, and provide backward compatibility.
  Mark old properties as deprecated but still support them.
- Take Rob suggest, update "analogix,hpd-gpio" to "hpd-gpios" prop name.
- Take Thierry suggest, deprecated some properties which could parsed from Edid/Mode/DPCD.
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"

Changes in v3:
- Take Heiko suggest, add devicetree binding documents.
- Take Thierry Reding suggest, remove sync pol & colorimetry properies
  from the new analogix dp driver devicetree binding.
- Update the exist exynos dtsi file with the latest DP DT properies.

Changes in v2: None

 .../devicetree/bindings/drm/bridge/analogix_dp.txt | 50 +++++++++++++++++
 .../devicetree/bindings/video/exynos_dp.txt        | 63 ++++++++--------------
 2 files changed, 71 insertions(+), 42 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt

diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
new file mode 100644
index 0000000..f54dc3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -0,0 +1,50 @@
+Analogix Display Port bridge bindings
+
+Required properties for dp-controller:
+	-compatible:
+		platform specific such as:
+		 * "samsung,exynos5-dp"
+		 * "rockchip,rk3288-dp"
+	-reg:
+		physical base address of the controller and length
+		of memory mapped region.
+	-interrupts:
+		interrupt combiner values.
+	-clocks:
+		from common clock binding: handle to dp clock.
+	-clock-names:
+		from common clock binding: Shall be "dp".
+	-interrupt-parent:
+		phandle to Interrupt combiner node.
+	-phys:
+		from general PHY binding: the phandle for the PHY device.
+	-phy-names:
+		from general PHY binding: Should be "dp".
+
+Optional properties for dp-controller:
+	-hpd-gpios:
+		Hotplug detect GPIO.
+		Indicates which GPIO should be used for hotplug detection
+	-port@[X]: SoC specific port nodes with endpoint definitions as defined
+		in Documentation/devicetree/bindings/media/video-interfaces.txt,
+		please refer to the SoC specific binding document:
+		* Documentation/devicetree/bindings/video/exynos_dp.txt
+		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+-------------------------------------------------------------------------------
+
+Example:
+
+	dp-controller {
+		compatible = "samsung,exynos5-dp";
+		reg = <0x145b0000 0x10000>;
+		interrupts = <10 3>;
+		interrupt-parent = <&combiner>;
+		clocks = <&clock 342>;
+		clock-names = "dp";
+
+		phys = <&dp_phy>;
+		phy-names = "dp";
+	};
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index 7a3a9cd..ea03b3a 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -31,45 +31,31 @@ Required properties for dp-controller:
 		from general PHY binding: the phandle for the PHY device.
 	-phy-names:
 		from general PHY binding: Should be "dp".
-	-samsung,color-space:
-		input video data format.
-			COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
-	-samsung,dynamic-range:
-		dynamic range for input video data.
-			VESA = 0, CEA = 1
-	-samsung,ycbcr-coeff:
-		YCbCr co-efficients for input video.
-			COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
-	-samsung,color-depth:
-		number of bits per colour component.
-			COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
-	-samsung,link-rate:
-		link rate supported by the panel.
-			LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
-	-samsung,lane-count:
-		number of lanes supported by the panel.
-			LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
+
+Optional properties for dp-controller:
 	- display-timings: timings for the connected panel as described by
 		Documentation/devicetree/bindings/video/display-timing.txt
 
-Optional properties for dp-controller:
-	-interlaced:
-		interlace scan mode.
-			Progressive if defined, Interlaced if not defined
-	-vsync-active-high:
-		VSYNC polarity configuration.
-			High if defined, Low if not defined
-	-hsync-active-high:
-		HSYNC polarity configuration.
-			High if defined, Low if not defined
-	-samsung,hpd-gpio:
-		Hotplug detect GPIO.
-			Indicates which GPIO should be used for hotplug
-			detection
-	-video interfaces: Device node can contain video interface port
-			    nodes according to [1].
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+	-phys (required)
+	-phy-names (required)
+	-hpd-gpios (optional)
+	-video interfaces (optional)
 
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+Deprecated properties for DisplayPort:
+-interlaced:            deprecated prop that can parsed frm drm_display_mode.
+-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-samsung,ycbcr-coeff:   deprecated prop that can parsed frm drm_display_mode.
+-samsung,dynamic-range: deprecated prop that can parsed frm drm_display_mode.
+-samsung,color-space:   deprecated prop that can parsed from drm_display_info.
+-samsung,color-depth:   deprecated prop that can parsed from drm_display_info.
+-samsung,link-rate:     deprecated prop that can reading from monitor by dpcd method.
+-samsung,lane-count:    deprecated prop that can reading from monitor by dpcd method.
+-samsung,hpd-gpio:      deprecated name for hpd-gpios.
+
+-------------------------------------------------------------------------------
 
 Example:
 
@@ -88,13 +74,6 @@ SOC specific portion:
 
 Board Specific portion:
 	dp-controller {
-		samsung,color-space = <0>;
-		samsung,dynamic-range = <0>;
-		samsung,ycbcr-coeff = <0>;
-		samsung,color-depth = <1>;
-		samsung,link-rate = <0x0a>;
-		samsung,lane-count = <4>;
-
 		display-timings {
 			native-mode = <&lcd_timing>;
 			lcd_timing: 1366x768 {
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 06/16] Documentation: drm/bridge: add document for analogix_dp
@ 2015-09-01  5:58   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  5:58 UTC (permalink / raw)
  To: linux-arm-kernel

Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt

Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Krzysztof suggest, split all DTS changes, and provide backward compatibility.
  Mark old properties as deprecated but still support them.
- Take Rob suggest, update "analogix,hpd-gpio" to "hpd-gpios" prop name.
- Take Thierry suggest, deprecated some properties which could parsed from Edid/Mode/DPCD.
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"

Changes in v3:
- Take Heiko suggest, add devicetree binding documents.
- Take Thierry Reding suggest, remove sync pol & colorimetry properies
  from the new analogix dp driver devicetree binding.
- Update the exist exynos dtsi file with the latest DP DT properies.

Changes in v2: None

 .../devicetree/bindings/drm/bridge/analogix_dp.txt | 50 +++++++++++++++++
 .../devicetree/bindings/video/exynos_dp.txt        | 63 ++++++++--------------
 2 files changed, 71 insertions(+), 42 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt

diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
new file mode 100644
index 0000000..f54dc3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -0,0 +1,50 @@
+Analogix Display Port bridge bindings
+
+Required properties for dp-controller:
+	-compatible:
+		platform specific such as:
+		 * "samsung,exynos5-dp"
+		 * "rockchip,rk3288-dp"
+	-reg:
+		physical base address of the controller and length
+		of memory mapped region.
+	-interrupts:
+		interrupt combiner values.
+	-clocks:
+		from common clock binding: handle to dp clock.
+	-clock-names:
+		from common clock binding: Shall be "dp".
+	-interrupt-parent:
+		phandle to Interrupt combiner node.
+	-phys:
+		from general PHY binding: the phandle for the PHY device.
+	-phy-names:
+		from general PHY binding: Should be "dp".
+
+Optional properties for dp-controller:
+	-hpd-gpios:
+		Hotplug detect GPIO.
+		Indicates which GPIO should be used for hotplug detection
+	-port@[X]: SoC specific port nodes with endpoint definitions as defined
+		in Documentation/devicetree/bindings/media/video-interfaces.txt,
+		please refer to the SoC specific binding document:
+		* Documentation/devicetree/bindings/video/exynos_dp.txt
+		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+-------------------------------------------------------------------------------
+
+Example:
+
+	dp-controller {
+		compatible = "samsung,exynos5-dp";
+		reg = <0x145b0000 0x10000>;
+		interrupts = <10 3>;
+		interrupt-parent = <&combiner>;
+		clocks = <&clock 342>;
+		clock-names = "dp";
+
+		phys = <&dp_phy>;
+		phy-names = "dp";
+	};
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index 7a3a9cd..ea03b3a 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -31,45 +31,31 @@ Required properties for dp-controller:
 		from general PHY binding: the phandle for the PHY device.
 	-phy-names:
 		from general PHY binding: Should be "dp".
-	-samsung,color-space:
-		input video data format.
-			COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
-	-samsung,dynamic-range:
-		dynamic range for input video data.
-			VESA = 0, CEA = 1
-	-samsung,ycbcr-coeff:
-		YCbCr co-efficients for input video.
-			COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
-	-samsung,color-depth:
-		number of bits per colour component.
-			COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
-	-samsung,link-rate:
-		link rate supported by the panel.
-			LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
-	-samsung,lane-count:
-		number of lanes supported by the panel.
-			LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
+
+Optional properties for dp-controller:
 	- display-timings: timings for the connected panel as described by
 		Documentation/devicetree/bindings/video/display-timing.txt
 
-Optional properties for dp-controller:
-	-interlaced:
-		interlace scan mode.
-			Progressive if defined, Interlaced if not defined
-	-vsync-active-high:
-		VSYNC polarity configuration.
-			High if defined, Low if not defined
-	-hsync-active-high:
-		HSYNC polarity configuration.
-			High if defined, Low if not defined
-	-samsung,hpd-gpio:
-		Hotplug detect GPIO.
-			Indicates which GPIO should be used for hotplug
-			detection
-	-video interfaces: Device node can contain video interface port
-			    nodes according to [1].
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+	-phys (required)
+	-phy-names (required)
+	-hpd-gpios (optional)
+	-video interfaces (optional)
 
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+Deprecated properties for DisplayPort:
+-interlaced:            deprecated prop that can parsed frm drm_display_mode.
+-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-samsung,ycbcr-coeff:   deprecated prop that can parsed frm drm_display_mode.
+-samsung,dynamic-range: deprecated prop that can parsed frm drm_display_mode.
+-samsung,color-space:   deprecated prop that can parsed from drm_display_info.
+-samsung,color-depth:   deprecated prop that can parsed from drm_display_info.
+-samsung,link-rate:     deprecated prop that can reading from monitor by dpcd method.
+-samsung,lane-count:    deprecated prop that can reading from monitor by dpcd method.
+-samsung,hpd-gpio:      deprecated name for hpd-gpios.
+
+-------------------------------------------------------------------------------
 
 Example:
 
@@ -88,13 +74,6 @@ SOC specific portion:
 
 Board Specific portion:
 	dp-controller {
-		samsung,color-space = <0>;
-		samsung,dynamic-range = <0>;
-		samsung,ycbcr-coeff = <0>;
-		samsung,color-depth = <1>;
-		samsung,link-rate = <0x0a>;
-		samsung,lane-count = <4>;
-
 		display-timings {
 			native-mode = <&lcd_timing>;
 			lcd_timing: 1366x768 {
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 07/16] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
  2015-09-01  5:46 ` Yakir Yang
@ 2015-09-01  6:01   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:01 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

After exynos_dp have been splited the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some samsung platform properties which
could be dynamic parsed from EDID/MODE/DPCD message, so this is an update for
exynos DTS file for dp-controller.

Beside analogix_dp have provide the backward compatibility, so there are no
bisectability break that make this change in a separate patch.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Krzysztof suggest, separate all DTS changes to a separate patch.

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/exynos5250-arndale.dts   | 2 --
 arch/arm/boot/dts/exynos5250-smdk5250.dts  | 2 --
 arch/arm/boot/dts/exynos5250-snow.dts      | 4 +---
 arch/arm/boot/dts/exynos5250-spring.dts    | 4 +---
 arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
 arch/arm/boot/dts/exynos5420-smdk5420.dts  | 2 --
 arch/arm/boot/dts/exynos5800-peach-pi.dts  | 4 +---
 7 files changed, 4 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index db3f65f..4636862 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -124,8 +124,6 @@
 &dp {
 	status = "okay";
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index c625e71..cd424d6 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -80,8 +80,6 @@
 
 &dp {
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 0720caa..242b621 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -244,12 +244,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
 
 	ports {
 		port@0 {
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index c1edd6d..91881d7 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -74,12 +74,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <1>;
-	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
 };
 
 &ehci {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 8f4d76c..7433683 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -148,12 +148,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x06>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 0>;
+	hpd-gpio = <&gpx2 6 0>;
 
 	ports {
 		port@0 {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 98871f9..b3df3c1 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -92,8 +92,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7d5b386..b89bff5 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -142,12 +142,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 0>;
+	hpd-gpios = <&gpx2 6 0>;
 	panel = <&panel>;
 };
 
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 07/16] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
@ 2015-09-01  6:01   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:01 UTC (permalink / raw)
  To: linux-arm-kernel

After exynos_dp have been splited the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some samsung platform properties which
could be dynamic parsed from EDID/MODE/DPCD message, so this is an update for
exynos DTS file for dp-controller.

Beside analogix_dp have provide the backward compatibility, so there are no
bisectability break that make this change in a separate patch.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Krzysztof suggest, separate all DTS changes to a separate patch.

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/exynos5250-arndale.dts   | 2 --
 arch/arm/boot/dts/exynos5250-smdk5250.dts  | 2 --
 arch/arm/boot/dts/exynos5250-snow.dts      | 4 +---
 arch/arm/boot/dts/exynos5250-spring.dts    | 4 +---
 arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
 arch/arm/boot/dts/exynos5420-smdk5420.dts  | 2 --
 arch/arm/boot/dts/exynos5800-peach-pi.dts  | 4 +---
 7 files changed, 4 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index db3f65f..4636862 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -124,8 +124,6 @@
 &dp {
 	status = "okay";
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index c625e71..cd424d6 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -80,8 +80,6 @@
 
 &dp {
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 0720caa..242b621 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -244,12 +244,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
 
 	ports {
 		port at 0 {
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index c1edd6d..91881d7 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -74,12 +74,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <1>;
-	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
 };
 
 &ehci {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 8f4d76c..7433683 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -148,12 +148,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x06>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 0>;
+	hpd-gpio = <&gpx2 6 0>;
 
 	ports {
 		port at 0 {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 98871f9..b3df3c1 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -92,8 +92,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7d5b386..b89bff5 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -142,12 +142,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 0>;
+	hpd-gpios = <&gpx2 6 0>;
 	panel = <&panel>;
 };
 
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
@ 2015-09-01  6:01   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:01 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.

Changes in v3:
- Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
  dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
  core driver which name to "dp", and leave "pclk_edp" to rockchip dp platform
  driver which name to "pclk".
- Take Heiko suggest, add devicetree binding document.
- Take Heiko suggest, remove "rockchip,panel" DT property, take use of remote
  point to get panel node.
- Add the new function point analogix_dp_platdata.get_modes init.

Changes in v2:
- Take Heiko suggest, get panel node with remote-endpoint method,
  and create devicetree binding for driver.
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.

 .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
 drivers/gpu/drm/rockchip/Kconfig                   |   9 +
 drivers/gpu/drm/rockchip/Makefile                  |   1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389 +++++++++++++++++++++
 4 files changed, 473 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..502483e
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -0,0 +1,74 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+	  of memory mapped region.
+
+- clock-names: from common clock binding:
+	       Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+	  See ../reset/reset.txt for details.
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+	dp-controller: dp@ff970000 {
+		compatible = "rockchip,rk3288-dp";
+		reg = <0xff970000 0x4000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+		clock-names = "dp", "pclk";
+		phys = <&dp_phy>;
+		phy-names = "dp";
+
+		rockchip,grf = <&grf>;
+		resets = <&cru 111>;
+		reset-names = "dp";
+
+		status = "disabled";
+
+		ports {
+			edp_in: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_edp>;
+				};
+				edp_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_edp>;
+				};
+			};
+
+			edp_out: port@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_out_panel: endpoint {
+					reg = <0>;
+					remote-endpoint = <&panel_in_edp>
+				};
+			};
+		};
+	};
+
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..c2ba945 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
 	  for the Synopsys DesignWare HDMI driver. If you want to
 	  enable HDMI on RK3288 based SoC, you should selet this
 	  option.
+
+config ROCKCHIP_ANALOGIX_DP
+        tristate "Rockchip specific extensions for Analogix DP driver"
+        depends on DRM_ROCKCHIP
+        select DRM_ANALOGIX_DP
+        help
+	  This selects support for Rockchip SoC specific extensions
+	  for the Analogix Core DP driver. If you want to enable DP
+	  on RK3288 based SoC, you should selet this option.
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..8ad01fb 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \
 		rockchip_drm_gem.o
 
 obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 
 obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
new file mode 100644
index 0000000..cebff9e
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -0,0 +1,389 @@
+/*
+ * Rockchip SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ *         Yakir Yang <ykk@rock-chips.com>
+ *         Jeff Chen <jeff.chen@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_of.h>
+#include <drm/drm_dp_helper.h>
+
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define encoder_to_dp(c) \
+		container_of(c, struct rockchip_dp_device, encoder)
+
+#define plat_data_to_dp(pd) \
+		container_of(pd, struct rockchip_dp_device, plat_data)
+
+/* dp grf register offset */
+#define GRF_GPIO7B_IOMUX                        0x0070
+#define GPIO7B3_SEL_MASK                        (0x03 << 6)
+#define GPIO7B3_SEL_EDP_HOTPLUG                 BIT(7)
+
+#define GRF_SOC_CON6                            0x025c
+#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
+#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
+#define GRF_EDP_SEL_VOP_BIG                     0
+
+struct rockchip_dp_device {
+	struct drm_device        *drm_dev;
+	struct device            *dev;
+	struct drm_encoder       encoder;
+	struct drm_display_mode  mode;
+
+	struct clk               *pclk;
+	struct regmap            *grf;
+	struct reset_control     *rst;
+
+	struct analogix_dp_plat_data plat_data;
+};
+
+static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+{
+	u32 val;
+	int ret;
+
+	val = GPIO7B3_SEL_EDP_HOTPLUG | (GPIO7B3_SEL_MASK << 16);
+	ret = regmap_write(dp->grf, GRF_GPIO7B_IOMUX, val);
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not config GRF edp hpd: %d\n", ret);
+		return ret;
+	}
+
+	reset_control_assert(dp->rst);
+	usleep_range(10, 20);
+	reset_control_deassert(dp->rst);
+
+	return 0;
+}
+
+static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = plat_data_to_dp(plat_data);
+	int ret;
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = plat_data_to_dp(plat_data);
+
+	clk_disable_unprepare(dp->pclk);
+
+	return 0;
+}
+
+static bool
+rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
+				   const struct drm_display_mode *mode,
+				   struct drm_display_mode *adjusted_mode)
+{
+	/* do nothing */
+	return true;
+}
+
+static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
+					     struct drm_display_mode *mode,
+					     struct drm_display_mode *adjusted)
+{
+	/* do nothing */
+}
+
+static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
+{
+	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
+	u32 val;
+	int ret;
+
+	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					    DRM_MODE_CONNECTOR_eDP,
+					    ROCKCHIP_OUT_MODE_AAAA);
+	if (ret < 0) {
+		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+		return;
+	}
+
+	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
+	if (ret < 0)
+		return;
+
+	if (ret)
+		val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
+	else
+		val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
+
+	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+		return;
+	}
+}
+
+static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
+{
+	/* do nothing */
+}
+
+static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
+	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
+	.mode_set = rockchip_dp_drm_encoder_mode_set,
+	.prepare = rockchip_dp_drm_encoder_prepare,
+	.commit = rockchip_dp_drm_encoder_nop,
+	.disable = rockchip_dp_drm_encoder_nop,
+};
+
+static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
+	.destroy = rockchip_dp_drm_encoder_destroy,
+};
+
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+	struct device *dev = dp->dev;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "failed to get rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	dp->pclk = devm_clk_get(dev, "pclk");
+	if (IS_ERR(dp->pclk)) {
+		dev_err(dev, "failed to get pclk property\n");
+		return PTR_ERR(dp->pclk);
+	}
+
+	dp->rst = devm_reset_control_get(dev, "dp");
+	if (IS_ERR(dp->rst)) {
+		dev_err(dev, "failed to get dp reset control\n");
+		return PTR_ERR(dp->rst);
+	}
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
+{
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct device *dev = dp->dev;
+	int ret;
+
+	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+							     dev->of_node);
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
+			       DRM_MODE_ENCODER_TMDS);
+	if (ret) {
+		DRM_ERROR("failed to initialize encoder with drm\n");
+		return ret;
+	}
+
+	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
+
+	return 0;
+}
+
+static int rockchip_dp_bind(struct device *dev, struct device *master,
+			    void *data)
+{
+	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_device *drm_dev = data;
+	int ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	ret = rockchip_dp_init(dp);
+	if (ret < 0)
+		return ret;
+
+	dp->drm_dev = drm_dev;
+
+	ret = rockchip_dp_drm_create_encoder(dp);
+	if (ret) {
+		DRM_ERROR("failed to create drm encoder\n");
+		return ret;
+	}
+
+	dp->plat_data.attach = NULL;
+	dp->plat_data.get_modes = NULL;
+	dp->plat_data.power_on = rockchip_dp_poweron;
+	dp->plat_data.power_off = rockchip_dp_powerdown;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->encoder,
+				&dp->plat_data);
+}
+
+static void rockchip_dp_unbind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops rockchip_dp_component_ops = {
+	.bind = rockchip_dp_bind,
+	.unbind = rockchip_dp_unbind,
+};
+
+static int rockchip_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *port, *endpoint;
+	struct rockchip_dp_device *dp;
+	struct drm_panel *panel;
+
+	port = of_graph_get_port_by_id(dev->of_node, 1);
+	if (!port) {
+		dev_err(dev, "can't find output port\n");
+		return -EINVAL;
+	}
+
+	endpoint = of_get_child_by_name(port, "endpoint");
+	of_node_put(port);
+	if (!endpoint) {
+		dev_err(dev, "no output endpoint found\n");
+		return -EINVAL;
+	}
+
+	panel_node = of_graph_get_remote_port_parent(endpoint);
+	of_node_put(endpoint);
+	if (!panel_node) {
+		dev_err(dev, "no output node found\n");
+		return -EINVAL;
+	}
+
+	panel = of_drm_find_panel(panel_node);
+	if (!panel) {
+		DRM_ERROR("failed to find panel\n");
+		of_node_put(panel_node);
+		return -EPROBE_DEFER;
+	}
+
+	of_node_put(panel_node);
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->plat_data.panel = panel;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver could take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	return component_add(dev, &rockchip_dp_component_ops);
+}
+
+static int rockchip_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &rockchip_dp_component_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int rockchip_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops rockchip_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
+};
+
+static const struct of_device_id rockchip_dp_dt_ids[] = {
+	{.compatible = "rockchip,rk3288-dp",},
+	{}
+};
+MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
+
+static struct platform_driver rockchip_dp_driver = {
+	.probe = rockchip_dp_probe,
+	.remove = rockchip_dp_remove,
+	.driver = {
+		   .name = "rockchip-dp",
+		   .owner = THIS_MODULE,
+		   .pm = &rockchip_dp_pm_ops,
+		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
+	},
+};
+
+module_platform_driver(rockchip_dp_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
@ 2015-09-01  6:01   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:01 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe-6d6DIl74uiNBDgjK7y7TUQ, Kukjin Kim, Krzysztof Kozlowski,
	Mark Yao
  Cc: Russell King, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	dianders-F7+t8E8rja9Wk0Htik3J/w, seanpaul-F7+t8E8rja9Wk0Htik3J/w,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt-sgV2jX0FEOL9JmXXK+q4OQ,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Yakir Yang,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.

Changes in v3:
- Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
  dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
  core driver which name to "dp", and leave "pclk_edp" to rockchip dp platform
  driver which name to "pclk".
- Take Heiko suggest, add devicetree binding document.
- Take Heiko suggest, remove "rockchip,panel" DT property, take use of remote
  point to get panel node.
- Add the new function point analogix_dp_platdata.get_modes init.

Changes in v2:
- Take Heiko suggest, get panel node with remote-endpoint method,
  and create devicetree binding for driver.
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.

 .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
 drivers/gpu/drm/rockchip/Kconfig                   |   9 +
 drivers/gpu/drm/rockchip/Makefile                  |   1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389 +++++++++++++++++++++
 4 files changed, 473 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..502483e
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -0,0 +1,74 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+	  of memory mapped region.
+
+- clock-names: from common clock binding:
+	       Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+	  See ../reset/reset.txt for details.
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+	dp-controller: dp@ff970000 {
+		compatible = "rockchip,rk3288-dp";
+		reg = <0xff970000 0x4000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+		clock-names = "dp", "pclk";
+		phys = <&dp_phy>;
+		phy-names = "dp";
+
+		rockchip,grf = <&grf>;
+		resets = <&cru 111>;
+		reset-names = "dp";
+
+		status = "disabled";
+
+		ports {
+			edp_in: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_edp>;
+				};
+				edp_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_edp>;
+				};
+			};
+
+			edp_out: port@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_out_panel: endpoint {
+					reg = <0>;
+					remote-endpoint = <&panel_in_edp>
+				};
+			};
+		};
+	};
+
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..c2ba945 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
 	  for the Synopsys DesignWare HDMI driver. If you want to
 	  enable HDMI on RK3288 based SoC, you should selet this
 	  option.
+
+config ROCKCHIP_ANALOGIX_DP
+        tristate "Rockchip specific extensions for Analogix DP driver"
+        depends on DRM_ROCKCHIP
+        select DRM_ANALOGIX_DP
+        help
+	  This selects support for Rockchip SoC specific extensions
+	  for the Analogix Core DP driver. If you want to enable DP
+	  on RK3288 based SoC, you should selet this option.
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..8ad01fb 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \
 		rockchip_drm_gem.o
 
 obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 
 obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
new file mode 100644
index 0000000..cebff9e
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -0,0 +1,389 @@
+/*
+ * Rockchip SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
+ *         Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
+ *         Jeff Chen <jeff.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_of.h>
+#include <drm/drm_dp_helper.h>
+
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define encoder_to_dp(c) \
+		container_of(c, struct rockchip_dp_device, encoder)
+
+#define plat_data_to_dp(pd) \
+		container_of(pd, struct rockchip_dp_device, plat_data)
+
+/* dp grf register offset */
+#define GRF_GPIO7B_IOMUX                        0x0070
+#define GPIO7B3_SEL_MASK                        (0x03 << 6)
+#define GPIO7B3_SEL_EDP_HOTPLUG                 BIT(7)
+
+#define GRF_SOC_CON6                            0x025c
+#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
+#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
+#define GRF_EDP_SEL_VOP_BIG                     0
+
+struct rockchip_dp_device {
+	struct drm_device        *drm_dev;
+	struct device            *dev;
+	struct drm_encoder       encoder;
+	struct drm_display_mode  mode;
+
+	struct clk               *pclk;
+	struct regmap            *grf;
+	struct reset_control     *rst;
+
+	struct analogix_dp_plat_data plat_data;
+};
+
+static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+{
+	u32 val;
+	int ret;
+
+	val = GPIO7B3_SEL_EDP_HOTPLUG | (GPIO7B3_SEL_MASK << 16);
+	ret = regmap_write(dp->grf, GRF_GPIO7B_IOMUX, val);
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not config GRF edp hpd: %d\n", ret);
+		return ret;
+	}
+
+	reset_control_assert(dp->rst);
+	usleep_range(10, 20);
+	reset_control_deassert(dp->rst);
+
+	return 0;
+}
+
+static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = plat_data_to_dp(plat_data);
+	int ret;
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = plat_data_to_dp(plat_data);
+
+	clk_disable_unprepare(dp->pclk);
+
+	return 0;
+}
+
+static bool
+rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
+				   const struct drm_display_mode *mode,
+				   struct drm_display_mode *adjusted_mode)
+{
+	/* do nothing */
+	return true;
+}
+
+static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
+					     struct drm_display_mode *mode,
+					     struct drm_display_mode *adjusted)
+{
+	/* do nothing */
+}
+
+static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
+{
+	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
+	u32 val;
+	int ret;
+
+	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					    DRM_MODE_CONNECTOR_eDP,
+					    ROCKCHIP_OUT_MODE_AAAA);
+	if (ret < 0) {
+		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+		return;
+	}
+
+	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
+	if (ret < 0)
+		return;
+
+	if (ret)
+		val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
+	else
+		val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
+
+	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+		return;
+	}
+}
+
+static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
+{
+	/* do nothing */
+}
+
+static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
+	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
+	.mode_set = rockchip_dp_drm_encoder_mode_set,
+	.prepare = rockchip_dp_drm_encoder_prepare,
+	.commit = rockchip_dp_drm_encoder_nop,
+	.disable = rockchip_dp_drm_encoder_nop,
+};
+
+static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
+	.destroy = rockchip_dp_drm_encoder_destroy,
+};
+
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+	struct device *dev = dp->dev;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "failed to get rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	dp->pclk = devm_clk_get(dev, "pclk");
+	if (IS_ERR(dp->pclk)) {
+		dev_err(dev, "failed to get pclk property\n");
+		return PTR_ERR(dp->pclk);
+	}
+
+	dp->rst = devm_reset_control_get(dev, "dp");
+	if (IS_ERR(dp->rst)) {
+		dev_err(dev, "failed to get dp reset control\n");
+		return PTR_ERR(dp->rst);
+	}
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
+{
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct device *dev = dp->dev;
+	int ret;
+
+	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+							     dev->of_node);
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
+			       DRM_MODE_ENCODER_TMDS);
+	if (ret) {
+		DRM_ERROR("failed to initialize encoder with drm\n");
+		return ret;
+	}
+
+	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
+
+	return 0;
+}
+
+static int rockchip_dp_bind(struct device *dev, struct device *master,
+			    void *data)
+{
+	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_device *drm_dev = data;
+	int ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	ret = rockchip_dp_init(dp);
+	if (ret < 0)
+		return ret;
+
+	dp->drm_dev = drm_dev;
+
+	ret = rockchip_dp_drm_create_encoder(dp);
+	if (ret) {
+		DRM_ERROR("failed to create drm encoder\n");
+		return ret;
+	}
+
+	dp->plat_data.attach = NULL;
+	dp->plat_data.get_modes = NULL;
+	dp->plat_data.power_on = rockchip_dp_poweron;
+	dp->plat_data.power_off = rockchip_dp_powerdown;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->encoder,
+				&dp->plat_data);
+}
+
+static void rockchip_dp_unbind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops rockchip_dp_component_ops = {
+	.bind = rockchip_dp_bind,
+	.unbind = rockchip_dp_unbind,
+};
+
+static int rockchip_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *port, *endpoint;
+	struct rockchip_dp_device *dp;
+	struct drm_panel *panel;
+
+	port = of_graph_get_port_by_id(dev->of_node, 1);
+	if (!port) {
+		dev_err(dev, "can't find output port\n");
+		return -EINVAL;
+	}
+
+	endpoint = of_get_child_by_name(port, "endpoint");
+	of_node_put(port);
+	if (!endpoint) {
+		dev_err(dev, "no output endpoint found\n");
+		return -EINVAL;
+	}
+
+	panel_node = of_graph_get_remote_port_parent(endpoint);
+	of_node_put(endpoint);
+	if (!panel_node) {
+		dev_err(dev, "no output node found\n");
+		return -EINVAL;
+	}
+
+	panel = of_drm_find_panel(panel_node);
+	if (!panel) {
+		DRM_ERROR("failed to find panel\n");
+		of_node_put(panel_node);
+		return -EPROBE_DEFER;
+	}
+
+	of_node_put(panel_node);
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->plat_data.panel = panel;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver could take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	return component_add(dev, &rockchip_dp_component_ops);
+}
+
+static int rockchip_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &rockchip_dp_component_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int rockchip_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops rockchip_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
+};
+
+static const struct of_device_id rockchip_dp_dt_ids[] = {
+	{.compatible = "rockchip,rk3288-dp",},
+	{}
+};
+MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
+
+static struct platform_driver rockchip_dp_driver = {
+	.probe = rockchip_dp_probe,
+	.remove = rockchip_dp_remove,
+	.driver = {
+		   .name = "rockchip-dp",
+		   .owner = THIS_MODULE,
+		   .pm = &rockchip_dp_pm_ops,
+		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
+	},
+};
+
+module_platform_driver(rockchip_dp_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>");
+MODULE_AUTHOR("Jeff chen <jeff.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org>");
+MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
-- 
2.1.2


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^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
@ 2015-09-01  6:01   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:01 UTC (permalink / raw)
  To: linux-arm-kernel

Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.

Changes in v3:
- Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
  dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
  core driver which name to "dp", and leave "pclk_edp" to rockchip dp platform
  driver which name to "pclk".
- Take Heiko suggest, add devicetree binding document.
- Take Heiko suggest, remove "rockchip,panel" DT property, take use of remote
  point to get panel node.
- Add the new function point analogix_dp_platdata.get_modes init.

Changes in v2:
- Take Heiko suggest, get panel node with remote-endpoint method,
  and create devicetree binding for driver.
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.

 .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
 drivers/gpu/drm/rockchip/Kconfig                   |   9 +
 drivers/gpu/drm/rockchip/Makefile                  |   1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389 +++++++++++++++++++++
 4 files changed, 473 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..502483e
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -0,0 +1,74 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+	  of memory mapped region.
+
+- clock-names: from common clock binding:
+	       Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+	  See ../reset/reset.txt for details.
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+	dp-controller: dp at ff970000 {
+		compatible = "rockchip,rk3288-dp";
+		reg = <0xff970000 0x4000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+		clock-names = "dp", "pclk";
+		phys = <&dp_phy>;
+		phy-names = "dp";
+
+		rockchip,grf = <&grf>;
+		resets = <&cru 111>;
+		reset-names = "dp";
+
+		status = "disabled";
+
+		ports {
+			edp_in: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_in_vopb: endpoint at 0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_edp>;
+				};
+				edp_in_vopl: endpoint at 1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_edp>;
+				};
+			};
+
+			edp_out: port at 1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_out_panel: endpoint {
+					reg = <0>;
+					remote-endpoint = <&panel_in_edp>
+				};
+			};
+		};
+	};
+
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..c2ba945 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
 	  for the Synopsys DesignWare HDMI driver. If you want to
 	  enable HDMI on RK3288 based SoC, you should selet this
 	  option.
+
+config ROCKCHIP_ANALOGIX_DP
+        tristate "Rockchip specific extensions for Analogix DP driver"
+        depends on DRM_ROCKCHIP
+        select DRM_ANALOGIX_DP
+        help
+	  This selects support for Rockchip SoC specific extensions
+	  for the Analogix Core DP driver. If you want to enable DP
+	  on RK3288 based SoC, you should selet this option.
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..8ad01fb 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \
 		rockchip_drm_gem.o
 
 obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 
 obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
new file mode 100644
index 0000000..cebff9e
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -0,0 +1,389 @@
+/*
+ * Rockchip SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ *         Yakir Yang <ykk@rock-chips.com>
+ *         Jeff Chen <jeff.chen@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_of.h>
+#include <drm/drm_dp_helper.h>
+
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define encoder_to_dp(c) \
+		container_of(c, struct rockchip_dp_device, encoder)
+
+#define plat_data_to_dp(pd) \
+		container_of(pd, struct rockchip_dp_device, plat_data)
+
+/* dp grf register offset */
+#define GRF_GPIO7B_IOMUX                        0x0070
+#define GPIO7B3_SEL_MASK                        (0x03 << 6)
+#define GPIO7B3_SEL_EDP_HOTPLUG                 BIT(7)
+
+#define GRF_SOC_CON6                            0x025c
+#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
+#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
+#define GRF_EDP_SEL_VOP_BIG                     0
+
+struct rockchip_dp_device {
+	struct drm_device        *drm_dev;
+	struct device            *dev;
+	struct drm_encoder       encoder;
+	struct drm_display_mode  mode;
+
+	struct clk               *pclk;
+	struct regmap            *grf;
+	struct reset_control     *rst;
+
+	struct analogix_dp_plat_data plat_data;
+};
+
+static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+{
+	u32 val;
+	int ret;
+
+	val = GPIO7B3_SEL_EDP_HOTPLUG | (GPIO7B3_SEL_MASK << 16);
+	ret = regmap_write(dp->grf, GRF_GPIO7B_IOMUX, val);
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not config GRF edp hpd: %d\n", ret);
+		return ret;
+	}
+
+	reset_control_assert(dp->rst);
+	usleep_range(10, 20);
+	reset_control_deassert(dp->rst);
+
+	return 0;
+}
+
+static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = plat_data_to_dp(plat_data);
+	int ret;
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = plat_data_to_dp(plat_data);
+
+	clk_disable_unprepare(dp->pclk);
+
+	return 0;
+}
+
+static bool
+rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
+				   const struct drm_display_mode *mode,
+				   struct drm_display_mode *adjusted_mode)
+{
+	/* do nothing */
+	return true;
+}
+
+static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
+					     struct drm_display_mode *mode,
+					     struct drm_display_mode *adjusted)
+{
+	/* do nothing */
+}
+
+static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
+{
+	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
+	u32 val;
+	int ret;
+
+	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					    DRM_MODE_CONNECTOR_eDP,
+					    ROCKCHIP_OUT_MODE_AAAA);
+	if (ret < 0) {
+		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+		return;
+	}
+
+	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
+	if (ret < 0)
+		return;
+
+	if (ret)
+		val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
+	else
+		val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
+
+	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+		return;
+	}
+}
+
+static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
+{
+	/* do nothing */
+}
+
+static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
+	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
+	.mode_set = rockchip_dp_drm_encoder_mode_set,
+	.prepare = rockchip_dp_drm_encoder_prepare,
+	.commit = rockchip_dp_drm_encoder_nop,
+	.disable = rockchip_dp_drm_encoder_nop,
+};
+
+static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
+	.destroy = rockchip_dp_drm_encoder_destroy,
+};
+
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+	struct device *dev = dp->dev;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "failed to get rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	dp->pclk = devm_clk_get(dev, "pclk");
+	if (IS_ERR(dp->pclk)) {
+		dev_err(dev, "failed to get pclk property\n");
+		return PTR_ERR(dp->pclk);
+	}
+
+	dp->rst = devm_reset_control_get(dev, "dp");
+	if (IS_ERR(dp->rst)) {
+		dev_err(dev, "failed to get dp reset control\n");
+		return PTR_ERR(dp->rst);
+	}
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
+{
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct device *dev = dp->dev;
+	int ret;
+
+	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+							     dev->of_node);
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
+			       DRM_MODE_ENCODER_TMDS);
+	if (ret) {
+		DRM_ERROR("failed to initialize encoder with drm\n");
+		return ret;
+	}
+
+	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
+
+	return 0;
+}
+
+static int rockchip_dp_bind(struct device *dev, struct device *master,
+			    void *data)
+{
+	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_device *drm_dev = data;
+	int ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	ret = rockchip_dp_init(dp);
+	if (ret < 0)
+		return ret;
+
+	dp->drm_dev = drm_dev;
+
+	ret = rockchip_dp_drm_create_encoder(dp);
+	if (ret) {
+		DRM_ERROR("failed to create drm encoder\n");
+		return ret;
+	}
+
+	dp->plat_data.attach = NULL;
+	dp->plat_data.get_modes = NULL;
+	dp->plat_data.power_on = rockchip_dp_poweron;
+	dp->plat_data.power_off = rockchip_dp_powerdown;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->encoder,
+				&dp->plat_data);
+}
+
+static void rockchip_dp_unbind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops rockchip_dp_component_ops = {
+	.bind = rockchip_dp_bind,
+	.unbind = rockchip_dp_unbind,
+};
+
+static int rockchip_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *port, *endpoint;
+	struct rockchip_dp_device *dp;
+	struct drm_panel *panel;
+
+	port = of_graph_get_port_by_id(dev->of_node, 1);
+	if (!port) {
+		dev_err(dev, "can't find output port\n");
+		return -EINVAL;
+	}
+
+	endpoint = of_get_child_by_name(port, "endpoint");
+	of_node_put(port);
+	if (!endpoint) {
+		dev_err(dev, "no output endpoint found\n");
+		return -EINVAL;
+	}
+
+	panel_node = of_graph_get_remote_port_parent(endpoint);
+	of_node_put(endpoint);
+	if (!panel_node) {
+		dev_err(dev, "no output node found\n");
+		return -EINVAL;
+	}
+
+	panel = of_drm_find_panel(panel_node);
+	if (!panel) {
+		DRM_ERROR("failed to find panel\n");
+		of_node_put(panel_node);
+		return -EPROBE_DEFER;
+	}
+
+	of_node_put(panel_node);
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->plat_data.panel = panel;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver could take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	return component_add(dev, &rockchip_dp_component_ops);
+}
+
+static int rockchip_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &rockchip_dp_component_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int rockchip_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops rockchip_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
+};
+
+static const struct of_device_id rockchip_dp_dt_ids[] = {
+	{.compatible = "rockchip,rk3288-dp",},
+	{}
+};
+MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
+
+static struct platform_driver rockchip_dp_driver = {
+	.probe = rockchip_dp_probe,
+	.remove = rockchip_dp_remove,
+	.driver = {
+		   .name = "rockchip-dp",
+		   .owner = THIS_MODULE,
+		   .pm = &rockchip_dp_pm_ops,
+		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
+	},
+};
+
+module_platform_driver(rockchip_dp_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
@ 2015-09-01  6:01   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:01 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel, Mark Yao

From: Mark Yao <yzq@rock-chips.com>

Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.

Signed-off-by: Mark Yao <yzq@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 46 +++++++++++++++++++------
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 33 ++++++++++++++++--
 4 files changed, 68 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index cebff9e..efea045 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -11,11 +11,6 @@
  * Free Software Foundation; either version 2 of the License, or (at your
  * option) any later version.
  */
-#include <drm/drmP.h>
-#include <drm/drm_crtc_helper.h>
-#include <drm/drm_panel.h>
-#include <drm/drm_of.h>
-#include <drm/drm_dp_helper.h>
 
 #include <linux/component.h>
 #include <linux/mfd/syscon.h>
@@ -27,6 +22,13 @@
 #include <video/of_videomode.h>
 #include <video/videomode.h>
 
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_of.h>
+#include <drm/drm_dp_helper.h>
+
 #include <drm/bridge/analogix_dp.h>
 
 #include "rockchip_drm_drv.h"
@@ -125,20 +127,44 @@ static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
 	/* do nothing */
 }
 
+static drm_connector *rockchip_dp_get_connector(struct rockchip_dp_device *dp)
+{
+	struct drm_connector *connector;
+	struct drm_device *drm_dev = dp->drm_dev;
+
+	drm_for_each_connector(connector, drm_dev) {
+		if (connector->encoder != &dp->encoder)
+			return connector;
+	}
+
+	return NULL;
+}
+
 static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
+	struct drm_connector *connector;
+	int ret = 0;
 	u32 val;
-	int ret;
 
-	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
-					    DRM_MODE_CONNECTOR_eDP,
-					    ROCKCHIP_OUT_MODE_AAAA);
-	if (ret < 0) {
+	connector = rockchip_dp_get_connector(dp);
+	if (!connector) {
+		DRM_ERROR("Failed to get connector by encoder[%p]\n", encoder);
+		return;
+	}
+
+	if (connector->display_info.color_formats | DRM_COLOR_FORMAT_RGB444)
+		ret = rockchip_drm_crtc_mode_config(
+			encoder->crtc, DRM_MODE_CONNECTOR_eDP,
+			connector->display_info.bpc, DRM_COLOR_FORMAT_RGB444);
+	if (!ret) {
 		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
 		return;
 	}
 
+	connector->display_info.bpc = ret;
+	connector->display_info.color_formats = DRM_COLOR_FORMAT_RGB444;
+
 	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
 	if (ret < 0)
 		return;
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 80d6fc8..428a3c1 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
 static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
 {
 	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
-				      ROCKCHIP_OUT_MODE_AAAA);
+				      10, DRM_COLOR_FORMAT_RGB444);
 }
 
 static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index dc4e5f0..ef1d7fb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe);
 int rockchip_drm_encoder_get_mux_id(struct device_node *node,
 				    struct drm_encoder *encoder);
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
-				  int out_mode);
+				  int bpc, int color);
 int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
 				   struct device *dev);
 void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 34b78e7..5d7f9b6 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs = {
 
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
 				  int connector_type,
-				  int out_mode)
+				  int bpc, int color)
 {
 	struct vop *vop = to_vop(crtc);
-
 	vop->connector_type = connector_type;
 	vop->connector_out_mode = out_mode;
 
-	return 0;
+	/*
+	 * RK3288 vop only support RGB Color output.
+	 */
+	if (color != DRM_COLOR_FORMAT_RGB444) {
+		DRM_ERROR("Only support output RGB444, not support%d\n",
+			  color);
+		return -EINVAL;
+	}
+
+	/*
+	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
+	 * bpc, 5 or 6?
+	 *
+	 */
+	if (bpc >= 10) {
+		bpc = 10;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
+	} else if (bpc >= 8) {
+		bpc = 8;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+	} else if (bpc >= 6) {
+		bpc = 6;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+	} else {
+		DRM_ERROR("unsupport bpc %d\n", bpc);
+		return -EINVAL;
+	}
+
+	return bpc;
 }
 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
 
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
@ 2015-09-01  6:01   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:01 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe-6d6DIl74uiNBDgjK7y7TUQ, Kukjin Kim, Krzysztof Kozlowski,
	Mark Yao
  Cc: Russell King, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	dianders-F7+t8E8rja9Wk0Htik3J/w, seanpaul-F7+t8E8rja9Wk0Htik3J/w,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt-sgV2jX0FEOL9JmXXK+q4OQ,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Yakir Yang,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Yao

From: Mark Yao <yzq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.

Signed-off-by: Mark Yao <yzq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 46 +++++++++++++++++++------
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 33 ++++++++++++++++--
 4 files changed, 68 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index cebff9e..efea045 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -11,11 +11,6 @@
  * Free Software Foundation; either version 2 of the License, or (at your
  * option) any later version.
  */
-#include <drm/drmP.h>
-#include <drm/drm_crtc_helper.h>
-#include <drm/drm_panel.h>
-#include <drm/drm_of.h>
-#include <drm/drm_dp_helper.h>
 
 #include <linux/component.h>
 #include <linux/mfd/syscon.h>
@@ -27,6 +22,13 @@
 #include <video/of_videomode.h>
 #include <video/videomode.h>
 
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_of.h>
+#include <drm/drm_dp_helper.h>
+
 #include <drm/bridge/analogix_dp.h>
 
 #include "rockchip_drm_drv.h"
@@ -125,20 +127,44 @@ static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
 	/* do nothing */
 }
 
+static drm_connector *rockchip_dp_get_connector(struct rockchip_dp_device *dp)
+{
+	struct drm_connector *connector;
+	struct drm_device *drm_dev = dp->drm_dev;
+
+	drm_for_each_connector(connector, drm_dev) {
+		if (connector->encoder != &dp->encoder)
+			return connector;
+	}
+
+	return NULL;
+}
+
 static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
+	struct drm_connector *connector;
+	int ret = 0;
 	u32 val;
-	int ret;
 
-	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
-					    DRM_MODE_CONNECTOR_eDP,
-					    ROCKCHIP_OUT_MODE_AAAA);
-	if (ret < 0) {
+	connector = rockchip_dp_get_connector(dp);
+	if (!connector) {
+		DRM_ERROR("Failed to get connector by encoder[%p]\n", encoder);
+		return;
+	}
+
+	if (connector->display_info.color_formats | DRM_COLOR_FORMAT_RGB444)
+		ret = rockchip_drm_crtc_mode_config(
+			encoder->crtc, DRM_MODE_CONNECTOR_eDP,
+			connector->display_info.bpc, DRM_COLOR_FORMAT_RGB444);
+	if (!ret) {
 		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
 		return;
 	}
 
+	connector->display_info.bpc = ret;
+	connector->display_info.color_formats = DRM_COLOR_FORMAT_RGB444;
+
 	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
 	if (ret < 0)
 		return;
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 80d6fc8..428a3c1 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
 static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
 {
 	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
-				      ROCKCHIP_OUT_MODE_AAAA);
+				      10, DRM_COLOR_FORMAT_RGB444);
 }
 
 static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index dc4e5f0..ef1d7fb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe);
 int rockchip_drm_encoder_get_mux_id(struct device_node *node,
 				    struct drm_encoder *encoder);
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
-				  int out_mode);
+				  int bpc, int color);
 int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
 				   struct device *dev);
 void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 34b78e7..5d7f9b6 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs = {
 
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
 				  int connector_type,
-				  int out_mode)
+				  int bpc, int color)
 {
 	struct vop *vop = to_vop(crtc);
-
 	vop->connector_type = connector_type;
 	vop->connector_out_mode = out_mode;
 
-	return 0;
+	/*
+	 * RK3288 vop only support RGB Color output.
+	 */
+	if (color != DRM_COLOR_FORMAT_RGB444) {
+		DRM_ERROR("Only support output RGB444, not support%d\n",
+			  color);
+		return -EINVAL;
+	}
+
+	/*
+	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
+	 * bpc, 5 or 6?
+	 *
+	 */
+	if (bpc >= 10) {
+		bpc = 10;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
+	} else if (bpc >= 8) {
+		bpc = 8;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+	} else if (bpc >= 6) {
+		bpc = 6;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+	} else {
+		DRM_ERROR("unsupport bpc %d\n", bpc);
+		return -EINVAL;
+	}
+
+	return bpc;
 }
 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
 
-- 
2.1.2


--
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^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
@ 2015-09-01  6:01   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:01 UTC (permalink / raw)
  To: linux-arm-kernel

From: Mark Yao <yzq@rock-chips.com>

Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.

Signed-off-by: Mark Yao <yzq@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 46 +++++++++++++++++++------
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 33 ++++++++++++++++--
 4 files changed, 68 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index cebff9e..efea045 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -11,11 +11,6 @@
  * Free Software Foundation; either version 2 of the License, or (at your
  * option) any later version.
  */
-#include <drm/drmP.h>
-#include <drm/drm_crtc_helper.h>
-#include <drm/drm_panel.h>
-#include <drm/drm_of.h>
-#include <drm/drm_dp_helper.h>
 
 #include <linux/component.h>
 #include <linux/mfd/syscon.h>
@@ -27,6 +22,13 @@
 #include <video/of_videomode.h>
 #include <video/videomode.h>
 
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_of.h>
+#include <drm/drm_dp_helper.h>
+
 #include <drm/bridge/analogix_dp.h>
 
 #include "rockchip_drm_drv.h"
@@ -125,20 +127,44 @@ static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
 	/* do nothing */
 }
 
+static drm_connector *rockchip_dp_get_connector(struct rockchip_dp_device *dp)
+{
+	struct drm_connector *connector;
+	struct drm_device *drm_dev = dp->drm_dev;
+
+	drm_for_each_connector(connector, drm_dev) {
+		if (connector->encoder != &dp->encoder)
+			return connector;
+	}
+
+	return NULL;
+}
+
 static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
+	struct drm_connector *connector;
+	int ret = 0;
 	u32 val;
-	int ret;
 
-	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
-					    DRM_MODE_CONNECTOR_eDP,
-					    ROCKCHIP_OUT_MODE_AAAA);
-	if (ret < 0) {
+	connector = rockchip_dp_get_connector(dp);
+	if (!connector) {
+		DRM_ERROR("Failed to get connector by encoder[%p]\n", encoder);
+		return;
+	}
+
+	if (connector->display_info.color_formats | DRM_COLOR_FORMAT_RGB444)
+		ret = rockchip_drm_crtc_mode_config(
+			encoder->crtc, DRM_MODE_CONNECTOR_eDP,
+			connector->display_info.bpc, DRM_COLOR_FORMAT_RGB444);
+	if (!ret) {
 		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
 		return;
 	}
 
+	connector->display_info.bpc = ret;
+	connector->display_info.color_formats = DRM_COLOR_FORMAT_RGB444;
+
 	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
 	if (ret < 0)
 		return;
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 80d6fc8..428a3c1 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
 static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
 {
 	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
-				      ROCKCHIP_OUT_MODE_AAAA);
+				      10, DRM_COLOR_FORMAT_RGB444);
 }
 
 static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index dc4e5f0..ef1d7fb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe);
 int rockchip_drm_encoder_get_mux_id(struct device_node *node,
 				    struct drm_encoder *encoder);
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
-				  int out_mode);
+				  int bpc, int color);
 int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
 				   struct device *dev);
 void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 34b78e7..5d7f9b6 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs = {
 
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
 				  int connector_type,
-				  int out_mode)
+				  int bpc, int color)
 {
 	struct vop *vop = to_vop(crtc);
-
 	vop->connector_type = connector_type;
 	vop->connector_out_mode = out_mode;
 
-	return 0;
+	/*
+	 * RK3288 vop only support RGB Color output.
+	 */
+	if (color != DRM_COLOR_FORMAT_RGB444) {
+		DRM_ERROR("Only support output RGB444, not support%d\n",
+			  color);
+		return -EINVAL;
+	}
+
+	/*
+	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
+	 * bpc, 5 or 6?
+	 *
+	 */
+	if (bpc >= 10) {
+		bpc = 10;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
+	} else if (bpc >= 8) {
+		bpc = 8;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+	} else if (bpc >= 6) {
+		bpc = 6;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+	} else {
+		DRM_ERROR("unsupport bpc %d\n", bpc);
+		return -EINVAL;
+	}
+
+	return bpc;
 }
 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
 
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-01  6:04   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:04 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Kishon suggest, add commit message, and remove the redundant
  rockchip_dp_phy_init() function, move those code to probe() method.
  And remove driver .owner number.

Changes in v3:
- Take Heiko suggest, add rockchip dp phy driver,
  collect the phy clocks and power control.

Changes in v2: None

 .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++
 drivers/phy/Kconfig                                |   7 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-rockchip-dp.c                      | 166 +++++++++++++++++++++
 4 files changed, 200 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
 create mode 100644 drivers/phy/phy-rockchip-dp.c

diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
new file mode 100644
index 0000000..5de1088
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
@@ -0,0 +1,26 @@
+Rockchip Soc Seroes Display Port PHY
+------------------------------------
+
+Required properties:
+- compatible : should be one of the following supported values:
+	 - "rockchip.rk3288-dp-phy"
+
+- reg : a list of registers used by phy driver
+- clocks: from common clock binding: handle to dp clock.
+	of memory mapped region.
+- clock-names: from common clock binding:
+	Required elements: "sclk_dp" "sclk_dp_24m"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+- #phy-cells : from the generic PHY bindings, must be 0;
+
+Example:
+
+edp_phy: phy@ff770274 {
+	compatilble = "rockchip,rk3288-dp-phy";
+	reg = <0xff770274 4>;
+	rockchip,grf = <&grf>;
+	clocks = <&cru SCLK_EDP_24M>;
+	clock-names = "24m";
+	#phy-cells = <0>;
+}
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573..8f2bc4f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
 	help
 	  Enable this to support the Rockchip USB 2.0 PHY.
 
+config PHY_ROCKCHIP_DP
+	tristate "Rockchip Display Port PHY Driver"
+	depends on ARCH_ROCKCHIP && OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the Rockchip Display Port PHY.
+
 config PHY_ST_SPEAR1310_MIPHY
 	tristate "ST SPEAR1310-MIPHY driver"
 	select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a5b18c1..e281f35 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
 obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 0000000..e9a726e
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,166 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#define GRF_SOC_CON12                   0x0274
+#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
+
+#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
+#define DP_PHY_SIDDQ_ON                 0
+#define DP_PHY_SIDDQ_OFF                BIT(5)
+
+struct rockchip_dp_phy {
+	struct device  *dev;
+	struct regmap  *grf;
+	void __iomem   *regs;
+	struct clk     *phy_24m;
+};
+
+static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
+{
+	int ret = 0;
+
+	ret = clk_set_rate(dp->phy_24m, 24000000);
+	if (ret < 0) {
+		dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(dp->phy_24m);
+	if (ret < 0) {
+		dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
+{
+	clk_disable_unprepare(dp->phy_24m);
+
+	return 0;
+}
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+
+	if (enable) {
+		rockchip_dp_phy_clk_enable(dp);
+		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
+	} else {
+		rockchip_dp_phy_clk_disable(dp);
+		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, false);
+}
+
+static struct phy_ops rockchip_dp_phy_ops = {
+	.power_on	= rockchip_dp_phy_power_on,
+	.power_off	= rockchip_dp_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct phy_provider *phy_provider;
+	struct rockchip_dp_phy *dp;
+	struct resource *res;
+	struct phy *phy;
+	int ret;
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (IS_ERR(dp))
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dp->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(dp->regs))
+		return PTR_ERR(dp->regs);
+
+	dp->phy_24m = devm_clk_get(dev, "24m");
+	if (IS_ERR(dp->phy_24m)) {
+		dev_err(dev, "cannot get clock 24m\n");
+		return PTR_ERR(dp->phy_24m);
+	}
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON12,
+			   GRF_EDP_REF_CLK_SEL_INTER |
+			   (GRF_EDP_REF_CLK_SEL_INTER << 16));
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+		return ret;
+	}
+
+	phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
+	if (IS_ERR(phy)) {
+		dev_err(dev, "failed to create phy\n");
+		return PTR_ERR(phy);
+	}
+	phy_set_drvdata(phy, dp);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+	{ .compatible = "rockchip,rk3288-dp-phy" },
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+	.probe		= rockchip_dp_phy_probe,
+	.driver		= {
+		.name	= "rockchip-dp-phy",
+		.of_match_table = rockchip_dp_phy_dt_ids,
+	},
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-01  6:04   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:04 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe-6d6DIl74uiNBDgjK7y7TUQ, Kukjin Kim, Krzysztof Kozlowski,
	Mark Yao
  Cc: David Airlie, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	Andrzej Hajda, Yakir Yang, Gustavo Padovan,
	architt-sgV2jX0FEOL9JmXXK+q4OQ,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Russell King,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Rob Herring, dianders-F7+t8E8rja9Wk0Htik3J/w,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kyungmin Park, Kumar Gala,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan

This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v4:
- Take Kishon suggest, add commit message, and remove the redundant
  rockchip_dp_phy_init() function, move those code to probe() method.
  And remove driver .owner number.

Changes in v3:
- Take Heiko suggest, add rockchip dp phy driver,
  collect the phy clocks and power control.

Changes in v2: None

 .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++
 drivers/phy/Kconfig                                |   7 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-rockchip-dp.c                      | 166 +++++++++++++++++++++
 4 files changed, 200 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
 create mode 100644 drivers/phy/phy-rockchip-dp.c

diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
new file mode 100644
index 0000000..5de1088
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
@@ -0,0 +1,26 @@
+Rockchip Soc Seroes Display Port PHY
+------------------------------------
+
+Required properties:
+- compatible : should be one of the following supported values:
+	 - "rockchip.rk3288-dp-phy"
+
+- reg : a list of registers used by phy driver
+- clocks: from common clock binding: handle to dp clock.
+	of memory mapped region.
+- clock-names: from common clock binding:
+	Required elements: "sclk_dp" "sclk_dp_24m"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+- #phy-cells : from the generic PHY bindings, must be 0;
+
+Example:
+
+edp_phy: phy@ff770274 {
+	compatilble = "rockchip,rk3288-dp-phy";
+	reg = <0xff770274 4>;
+	rockchip,grf = <&grf>;
+	clocks = <&cru SCLK_EDP_24M>;
+	clock-names = "24m";
+	#phy-cells = <0>;
+}
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573..8f2bc4f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
 	help
 	  Enable this to support the Rockchip USB 2.0 PHY.
 
+config PHY_ROCKCHIP_DP
+	tristate "Rockchip Display Port PHY Driver"
+	depends on ARCH_ROCKCHIP && OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the Rockchip Display Port PHY.
+
 config PHY_ST_SPEAR1310_MIPHY
 	tristate "ST SPEAR1310-MIPHY driver"
 	select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a5b18c1..e281f35 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
 obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 0000000..e9a726e
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,166 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#define GRF_SOC_CON12                   0x0274
+#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
+
+#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
+#define DP_PHY_SIDDQ_ON                 0
+#define DP_PHY_SIDDQ_OFF                BIT(5)
+
+struct rockchip_dp_phy {
+	struct device  *dev;
+	struct regmap  *grf;
+	void __iomem   *regs;
+	struct clk     *phy_24m;
+};
+
+static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
+{
+	int ret = 0;
+
+	ret = clk_set_rate(dp->phy_24m, 24000000);
+	if (ret < 0) {
+		dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(dp->phy_24m);
+	if (ret < 0) {
+		dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
+{
+	clk_disable_unprepare(dp->phy_24m);
+
+	return 0;
+}
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+
+	if (enable) {
+		rockchip_dp_phy_clk_enable(dp);
+		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
+	} else {
+		rockchip_dp_phy_clk_disable(dp);
+		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, false);
+}
+
+static struct phy_ops rockchip_dp_phy_ops = {
+	.power_on	= rockchip_dp_phy_power_on,
+	.power_off	= rockchip_dp_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct phy_provider *phy_provider;
+	struct rockchip_dp_phy *dp;
+	struct resource *res;
+	struct phy *phy;
+	int ret;
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (IS_ERR(dp))
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dp->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(dp->regs))
+		return PTR_ERR(dp->regs);
+
+	dp->phy_24m = devm_clk_get(dev, "24m");
+	if (IS_ERR(dp->phy_24m)) {
+		dev_err(dev, "cannot get clock 24m\n");
+		return PTR_ERR(dp->phy_24m);
+	}
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON12,
+			   GRF_EDP_REF_CLK_SEL_INTER |
+			   (GRF_EDP_REF_CLK_SEL_INTER << 16));
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+		return ret;
+	}
+
+	phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
+	if (IS_ERR(phy)) {
+		dev_err(dev, "failed to create phy\n");
+		return PTR_ERR(phy);
+	}
+	phy_set_drvdata(phy, dp);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+	{ .compatible = "rockchip,rk3288-dp-phy" },
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+	.probe		= rockchip_dp_phy_probe,
+	.driver		= {
+		.name	= "rockchip-dp-phy",
+		.of_match_table = rockchip_dp_phy_dt_ids,
+	},
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-01  6:04   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:04 UTC (permalink / raw)
  To: linux-arm-kernel

This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Kishon suggest, add commit message, and remove the redundant
  rockchip_dp_phy_init() function, move those code to probe() method.
  And remove driver .owner number.

Changes in v3:
- Take Heiko suggest, add rockchip dp phy driver,
  collect the phy clocks and power control.

Changes in v2: None

 .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++
 drivers/phy/Kconfig                                |   7 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-rockchip-dp.c                      | 166 +++++++++++++++++++++
 4 files changed, 200 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
 create mode 100644 drivers/phy/phy-rockchip-dp.c

diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
new file mode 100644
index 0000000..5de1088
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
@@ -0,0 +1,26 @@
+Rockchip Soc Seroes Display Port PHY
+------------------------------------
+
+Required properties:
+- compatible : should be one of the following supported values:
+	 - "rockchip.rk3288-dp-phy"
+
+- reg : a list of registers used by phy driver
+- clocks: from common clock binding: handle to dp clock.
+	of memory mapped region.
+- clock-names: from common clock binding:
+	Required elements: "sclk_dp" "sclk_dp_24m"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+- #phy-cells : from the generic PHY bindings, must be 0;
+
+Example:
+
+edp_phy: phy at ff770274 {
+	compatilble = "rockchip,rk3288-dp-phy";
+	reg = <0xff770274 4>;
+	rockchip,grf = <&grf>;
+	clocks = <&cru SCLK_EDP_24M>;
+	clock-names = "24m";
+	#phy-cells = <0>;
+}
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573..8f2bc4f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
 	help
 	  Enable this to support the Rockchip USB 2.0 PHY.
 
+config PHY_ROCKCHIP_DP
+	tristate "Rockchip Display Port PHY Driver"
+	depends on ARCH_ROCKCHIP && OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the Rockchip Display Port PHY.
+
 config PHY_ST_SPEAR1310_MIPHY
 	tristate "ST SPEAR1310-MIPHY driver"
 	select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a5b18c1..e281f35 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
 obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 0000000..e9a726e
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,166 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#define GRF_SOC_CON12                   0x0274
+#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
+
+#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
+#define DP_PHY_SIDDQ_ON                 0
+#define DP_PHY_SIDDQ_OFF                BIT(5)
+
+struct rockchip_dp_phy {
+	struct device  *dev;
+	struct regmap  *grf;
+	void __iomem   *regs;
+	struct clk     *phy_24m;
+};
+
+static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
+{
+	int ret = 0;
+
+	ret = clk_set_rate(dp->phy_24m, 24000000);
+	if (ret < 0) {
+		dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(dp->phy_24m);
+	if (ret < 0) {
+		dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
+{
+	clk_disable_unprepare(dp->phy_24m);
+
+	return 0;
+}
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+
+	if (enable) {
+		rockchip_dp_phy_clk_enable(dp);
+		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
+	} else {
+		rockchip_dp_phy_clk_disable(dp);
+		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, false);
+}
+
+static struct phy_ops rockchip_dp_phy_ops = {
+	.power_on	= rockchip_dp_phy_power_on,
+	.power_off	= rockchip_dp_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct phy_provider *phy_provider;
+	struct rockchip_dp_phy *dp;
+	struct resource *res;
+	struct phy *phy;
+	int ret;
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (IS_ERR(dp))
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dp->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(dp->regs))
+		return PTR_ERR(dp->regs);
+
+	dp->phy_24m = devm_clk_get(dev, "24m");
+	if (IS_ERR(dp->phy_24m)) {
+		dev_err(dev, "cannot get clock 24m\n");
+		return PTR_ERR(dp->phy_24m);
+	}
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON12,
+			   GRF_EDP_REF_CLK_SEL_INTER |
+			   (GRF_EDP_REF_CLK_SEL_INTER << 16));
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+		return ret;
+	}
+
+	phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
+	if (IS_ERR(phy)) {
+		dev_err(dev, "failed to create phy\n");
+		return PTR_ERR(phy);
+	}
+	phy_set_drvdata(phy, dp);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+	{ .compatible = "rockchip,rk3288-dp-phy" },
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+	.probe		= rockchip_dp_phy_probe,
+	.driver		= {
+		.name	= "rockchip-dp-phy",
+		.of_match_table = rockchip_dp_phy_dt_ids,
+	},
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support
  2015-09-01  5:46 ` Yakir Yang
@ 2015-09-01  6:07   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:07 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Add GNU license v2 declared and samsung copyright

 drivers/gpu/drm/exynos/exynos_dp.c              |  1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c |  1 +
 include/drm/bridge/analogix_dp.h                | 16 ++++++++++++++++
 3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
index 6060d2c..40ef727 100644
--- a/drivers/gpu/drm/exynos/exynos_dp.c
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -224,6 +224,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	dp->dev = dev;
 	dp->drm_dev = drm_dev;
 
+	dp->plat_data.dev_type = EXYNOS_DP;
 	dp->plat_data.power_on = exynos_dp_poweron;
 	dp->plat_data.power_off = exynos_dp_poweroff;
 	dp->plat_data.get_modes = exynos_dp_get_modes;
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index efea045..4934271 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -293,6 +293,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
 		return ret;
 	}
 
+	dp->plat_data.dev_type = RK3288_DP;
 	dp->plat_data.attach = NULL;
 	dp->plat_data.get_modes = NULL;
 	dp->plat_data.power_on = rockchip_dp_poweron;
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index 8b4ffad..7209a64 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -1,9 +1,25 @@
+/*
+ * Analogix Core DP (Display Port) interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
 #ifndef _ANALOGIX_DP_H_
 #define _ANALOGIX_DP_H_
 
 #include <drm/drm_crtc.h>
 
+enum analogix_dp_devtype {
+	EXYNOS_DP,
+	RK3288_DP,
+};
+
 struct analogix_dp_plat_data {
+	enum analogix_dp_devtype dev_type;
 	struct drm_panel *panel;
 
 	int (*power_on)(struct analogix_dp_plat_data *);
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support
@ 2015-09-01  6:07   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:07 UTC (permalink / raw)
  To: linux-arm-kernel

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Add GNU license v2 declared and samsung copyright

 drivers/gpu/drm/exynos/exynos_dp.c              |  1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c |  1 +
 include/drm/bridge/analogix_dp.h                | 16 ++++++++++++++++
 3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
index 6060d2c..40ef727 100644
--- a/drivers/gpu/drm/exynos/exynos_dp.c
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -224,6 +224,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	dp->dev = dev;
 	dp->drm_dev = drm_dev;
 
+	dp->plat_data.dev_type = EXYNOS_DP;
 	dp->plat_data.power_on = exynos_dp_poweron;
 	dp->plat_data.power_off = exynos_dp_poweroff;
 	dp->plat_data.get_modes = exynos_dp_get_modes;
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index efea045..4934271 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -293,6 +293,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
 		return ret;
 	}
 
+	dp->plat_data.dev_type = RK3288_DP;
 	dp->plat_data.attach = NULL;
 	dp->plat_data.get_modes = NULL;
 	dp->plat_data.power_on = rockchip_dp_poweron;
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index 8b4ffad..7209a64 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -1,9 +1,25 @@
+/*
+ * Analogix Core DP (Display Port) interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
 #ifndef _ANALOGIX_DP_H_
 #define _ANALOGIX_DP_H_
 
 #include <drm/drm_crtc.h>
 
+enum analogix_dp_devtype {
+	EXYNOS_DP,
+	RK3288_DP,
+};
+
 struct analogix_dp_plat_data {
+	enum analogix_dp_devtype dev_type;
 	struct drm_panel *panel;
 
 	int (*power_on)(struct analogix_dp_plat_data *);
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 12/16] drm: bridge: analogix/dp: add some rk3288 special registers setting
  2015-09-01  5:46 ` Yakir Yang
@ 2015-09-01  6:09   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:09 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++++++++++++++---------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 ++++
 2 files changed, 60 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 6a643be..15346fe 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -15,6 +15,8 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
+#include <drm/bridge/analogix_dp.h>
+
 #include "analogix_dp_core.h"
 #include "analogix_dp_reg.h"
 
@@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
 	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
 
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
+		writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
+		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
+		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
+		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
+	}
+
 	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
 
@@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable)
 {
 	u32 reg;
+	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		phy_pd_addr = ANALOGIX_DP_PD;
 
 	switch (block) {
 	case AUX_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH0_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH1_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH2_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH3_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case ANALOG_TOTAL:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case POWER_ALL:
 		if (enable) {
 			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(0x00, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	default:
@@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
-	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
+		      AUX_HW_RETRY_COUNT_SEL(3) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	else
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
+		      AUX_HW_RETRY_COUNT_SEL(0) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 2d878fd..21330aa 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -22,6 +22,14 @@
 #define ANALOGIX_DP_VIDEO_CTL_8			0x3C
 #define ANALOGIX_DP_VIDEO_CTL_10			0x44
 
+#define ANALOGIX_DP_PLL_REG_1			0xfc
+#define ANALOGIX_DP_PLL_REG_2			0x9e4
+#define ANALOGIX_DP_PLL_REG_3			0x9e8
+#define ANALOGIX_DP_PLL_REG_4			0x9ec
+#define ANALOGIX_DP_PLL_REG_5			0xa00
+
+#define ANALOGIX_DP_PD                          0x12c
+
 #define ANALOGIX_DP_LANE_MAP			0x35C
 
 #define ANALOGIX_DP_ANALOG_CTL_1			0x370
@@ -154,6 +162,10 @@
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
+/* ANALOGIX_DP_PLL_REG_1 */
+#define REF_CLK_24M				(0x1 << 1)
+#define REF_CLK_27M				(0x0 << 1)
+
 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 12/16] drm: bridge: analogix/dp: add some rk3288 special registers setting
@ 2015-09-01  6:09   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:09 UTC (permalink / raw)
  To: linux-arm-kernel

RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++++++++++++++---------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 ++++
 2 files changed, 60 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 6a643be..15346fe 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -15,6 +15,8 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
+#include <drm/bridge/analogix_dp.h>
+
 #include "analogix_dp_core.h"
 #include "analogix_dp_reg.h"
 
@@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
 	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
 
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
+		writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
+		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
+		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
+		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
+	}
+
 	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
 
@@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable)
 {
 	u32 reg;
+	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		phy_pd_addr = ANALOGIX_DP_PD;
 
 	switch (block) {
 	case AUX_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH0_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH1_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH2_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH3_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case ANALOG_TOTAL:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case POWER_ALL:
 		if (enable) {
 			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(0x00, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	default:
@@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
-	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
+		      AUX_HW_RETRY_COUNT_SEL(3) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	else
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
+		      AUX_HW_RETRY_COUNT_SEL(0) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 2d878fd..21330aa 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -22,6 +22,14 @@
 #define ANALOGIX_DP_VIDEO_CTL_8			0x3C
 #define ANALOGIX_DP_VIDEO_CTL_10			0x44
 
+#define ANALOGIX_DP_PLL_REG_1			0xfc
+#define ANALOGIX_DP_PLL_REG_2			0x9e4
+#define ANALOGIX_DP_PLL_REG_3			0x9e8
+#define ANALOGIX_DP_PLL_REG_4			0x9ec
+#define ANALOGIX_DP_PLL_REG_5			0xa00
+
+#define ANALOGIX_DP_PD                          0x12c
+
 #define ANALOGIX_DP_LANE_MAP			0x35C
 
 #define ANALOGIX_DP_ANALOG_CTL_1			0x370
@@ -154,6 +162,10 @@
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
+/* ANALOGIX_DP_PLL_REG_1 */
+#define REF_CLK_24M				(0x1 << 1)
+#define REF_CLK_27M				(0x0 << 1)
+
 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 13/16] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
  2015-09-01  5:46 ` Yakir Yang
@ 2015-09-01  6:11   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:11 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Thierry suggest, seprate the link-rate and lane-count limit
  out with the device_type flag.

Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 35 ++++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  4 +--
 2 files changed, 24 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index f0db92e..f7227ec 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -897,8 +897,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
-					 dp->video_info.link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
+					 dp->video_info.max_link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1201,18 +1201,27 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
 	struct device_node *dp_node = dp->dev->of_node;
-	struct video_info *video_config = &dp->video_info;
-
-	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &video_info->link_rate)) {
-		dev_err(dev, "failed to get link-rate\n");
-		return -EINVAL;
-	}
+	struct video_info *video_info = &dp->video_info;
 
-	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &video_info->lane_count)) {
-		dev_err(dev, "failed to get lane-count\n");
-		return -EINVAL;
+	switch (dp->plat_data && dp->plat_data->dev_type) {
+	case RK3288_DP:
+		/*
+		 * Like Rk3288 DisplayPort TRM indicate that "Main link
+		 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
+		 */
+		video_info->max_link_rate = 0x0A;
+		video_info->max_lane_count = 0x04;
+		break;
+	case EXYNOS_DP:
+		/*
+		 * NOTE: those property parseing code is used for
+		 * providing backward compatibility for samsung platform.
+		 */
+		of_property_read_u32(dp_node, "samsung,link-rate",
+				     &video_info->max_link_rate);
+		of_property_read_u32(dp_node, "samsung,lane-count",
+				     &video_info->max_lane_count);
+		break;
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 6e3d5bc..d8945e2 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -129,8 +129,8 @@ struct video_info {
 	enum color_coefficient ycbcr_coeff;
 	enum color_depth color_depth;
 
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
+	enum link_rate_type max_link_rate;
+	enum link_lane_count_type max_lane_count;
 };
 
 struct link_train {
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 13/16] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
@ 2015-09-01  6:11   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:11 UTC (permalink / raw)
  To: linux-arm-kernel

There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Thierry suggest, seprate the link-rate and lane-count limit
  out with the device_type flag.

Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 35 ++++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  4 +--
 2 files changed, 24 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index f0db92e..f7227ec 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -897,8 +897,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
-					 dp->video_info.link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
+					 dp->video_info.max_link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1201,18 +1201,27 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
 	struct device_node *dp_node = dp->dev->of_node;
-	struct video_info *video_config = &dp->video_info;
-
-	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &video_info->link_rate)) {
-		dev_err(dev, "failed to get link-rate\n");
-		return -EINVAL;
-	}
+	struct video_info *video_info = &dp->video_info;
 
-	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &video_info->lane_count)) {
-		dev_err(dev, "failed to get lane-count\n");
-		return -EINVAL;
+	switch (dp->plat_data && dp->plat_data->dev_type) {
+	case RK3288_DP:
+		/*
+		 * Like Rk3288 DisplayPort TRM indicate that "Main link
+		 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
+		 */
+		video_info->max_link_rate = 0x0A;
+		video_info->max_lane_count = 0x04;
+		break;
+	case EXYNOS_DP:
+		/*
+		 * NOTE: those property parseing code is used for
+		 * providing backward compatibility for samsung platform.
+		 */
+		of_property_read_u32(dp_node, "samsung,link-rate",
+				     &video_info->max_link_rate);
+		of_property_read_u32(dp_node, "samsung,lane-count",
+				     &video_info->max_lane_count);
+		break;
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 6e3d5bc..d8945e2 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -129,8 +129,8 @@ struct video_info {
 	enum color_coefficient ycbcr_coeff;
 	enum color_depth color_depth;
 
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
+	enum link_rate_type max_link_rate;
+	enum link_lane_count_type max_lane_count;
 };
 
 struct link_train {
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2015-09-01  5:46 ` Yakir Yang
@ 2015-09-01  6:14   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:14 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.

This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.

Changes in v2: None

 .../devicetree/bindings/drm/bridge/analogix_dp.txt |  4 ++-
 .../bindings/video/analogix_dp-rockchip.txt        |  1 +
 .../devicetree/bindings/video/exynos_dp.txt        |  1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
 6 files changed, 47 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
index f54dc3e..c310367 100644
--- a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -22,6 +22,9 @@ Required properties for dp-controller:
 		from general PHY binding: Should be "dp".
 
 Optional properties for dp-controller:
+	-analogix,need-force-hpd:
+		Indicate driver need force hpd when hpd detect failed, this
+		is used for some eDP screen which don't have hpd signal.
 	-hpd-gpios:
 		Hotplug detect GPIO.
 		Indicates which GPIO should be used for hotplug detection
@@ -31,7 +34,6 @@ Optional properties for dp-controller:
 		* Documentation/devicetree/bindings/video/exynos_dp.txt
 		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 
-
 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
 -------------------------------------------------------------------------------
 
diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
index 502483e..8b9ed7d 100644
--- a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -28,6 +28,7 @@ For the below properties, please refer to Analogix DP binding document:
 - phys (required)
 - phy-names (required)
 - hpd-gpios (optional)
+- analogix,need-force-hpd (optional)
 -------------------------------------------------------------------------------
 
 Example:
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index ea03b3a..4f06e80 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
 	-phys (required)
 	-phy-names (required)
 	-hpd-gpios (optional)
+	-analogix,need-force-hpd (optional)
 	-video interfaces (optional)
 
 Deprecated properties for DisplayPort:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index f7227ec..e6b328a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -63,15 +63,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (analogix_dp_get_plug_in_status(dp) != 0) {
+	while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
+		if (analogix_dp_get_plug_in_status(dp) == 0)
+			return 0;
+
 		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "failed to get hpd plug status\n");
-			return -ETIMEDOUT;
-		}
 		usleep_range(10, 11);
 	}
 
+	/*
+	 * Some edp screen do not have hpd signal, so we can't just
+	 * return failed when hpd plug in detect failed, DT property
+	 * "need-force-hpd" would indicate whether driver need this.
+	 */
+	if (!dp->need_force_hpd)
+		return -ETIMEDOUT;
+
+	/*
+	 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
+	 * will not work, so we need to give a force hpd action to
+	 * set HPD_STATUS manually.
+	 */
+	dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
+
+	analogix_dp_force_hpd(dp);
+
+	if (analogix_dp_get_plug_in_status(dp) != 0) {
+		dev_err(dp->dev, "failed to get hpd plug in status\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
+
 	return 0;
 }
 
@@ -1287,6 +1310,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
+	dp->need_force_hpd =
+		of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
+
 	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
 	if (gpio_is_valid(dp->hpd_gpio))
 		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index d8945e2..6960ab3 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -160,6 +160,7 @@ struct analogix_dp_device {
 	struct phy		*phy;
 	int			dpms_mode;
 	int			hpd_gpio;
+	bool                    need_force_hpd;
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable);
 void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
 void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+void analogix_dp_force_hpd(struct analogix_dp_device *dp);
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
 void analogix_dp_reset_aux(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 15346fe..3086afc 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 }
 
+void analogix_dp_force_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg = (F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
 {
 	u32 reg;
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-01  6:14   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:14 UTC (permalink / raw)
  To: linux-arm-kernel

Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.

This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.

Changes in v2: None

 .../devicetree/bindings/drm/bridge/analogix_dp.txt |  4 ++-
 .../bindings/video/analogix_dp-rockchip.txt        |  1 +
 .../devicetree/bindings/video/exynos_dp.txt        |  1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
 6 files changed, 47 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
index f54dc3e..c310367 100644
--- a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -22,6 +22,9 @@ Required properties for dp-controller:
 		from general PHY binding: Should be "dp".
 
 Optional properties for dp-controller:
+	-analogix,need-force-hpd:
+		Indicate driver need force hpd when hpd detect failed, this
+		is used for some eDP screen which don't have hpd signal.
 	-hpd-gpios:
 		Hotplug detect GPIO.
 		Indicates which GPIO should be used for hotplug detection
@@ -31,7 +34,6 @@ Optional properties for dp-controller:
 		* Documentation/devicetree/bindings/video/exynos_dp.txt
 		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 
-
 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
 -------------------------------------------------------------------------------
 
diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
index 502483e..8b9ed7d 100644
--- a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -28,6 +28,7 @@ For the below properties, please refer to Analogix DP binding document:
 - phys (required)
 - phy-names (required)
 - hpd-gpios (optional)
+- analogix,need-force-hpd (optional)
 -------------------------------------------------------------------------------
 
 Example:
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index ea03b3a..4f06e80 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
 	-phys (required)
 	-phy-names (required)
 	-hpd-gpios (optional)
+	-analogix,need-force-hpd (optional)
 	-video interfaces (optional)
 
 Deprecated properties for DisplayPort:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index f7227ec..e6b328a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -63,15 +63,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (analogix_dp_get_plug_in_status(dp) != 0) {
+	while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
+		if (analogix_dp_get_plug_in_status(dp) == 0)
+			return 0;
+
 		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "failed to get hpd plug status\n");
-			return -ETIMEDOUT;
-		}
 		usleep_range(10, 11);
 	}
 
+	/*
+	 * Some edp screen do not have hpd signal, so we can't just
+	 * return failed when hpd plug in detect failed, DT property
+	 * "need-force-hpd" would indicate whether driver need this.
+	 */
+	if (!dp->need_force_hpd)
+		return -ETIMEDOUT;
+
+	/*
+	 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
+	 * will not work, so we need to give a force hpd action to
+	 * set HPD_STATUS manually.
+	 */
+	dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
+
+	analogix_dp_force_hpd(dp);
+
+	if (analogix_dp_get_plug_in_status(dp) != 0) {
+		dev_err(dp->dev, "failed to get hpd plug in status\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
+
 	return 0;
 }
 
@@ -1287,6 +1310,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
+	dp->need_force_hpd =
+		of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
+
 	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
 	if (gpio_is_valid(dp->hpd_gpio))
 		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index d8945e2..6960ab3 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -160,6 +160,7 @@ struct analogix_dp_device {
 	struct phy		*phy;
 	int			dpms_mode;
 	int			hpd_gpio;
+	bool                    need_force_hpd;
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable);
 void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
 void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+void analogix_dp_force_hpd(struct analogix_dp_device *dp);
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
 void analogix_dp_reset_aux(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 15346fe..3086afc 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 }
 
+void analogix_dp_force_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg = (F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
 {
 	u32 reg;
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 15/16] drm: bridge: analogix/dp: move hpd detect to connector detect function
  2015-09-01  5:46 ` Yakir Yang
@ 2015-09-01  6:17   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:17 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Jingoo suggest, add commit messages.

Changes in v3:
- move dp hpd detect to connector detect function.

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index e6b328a..499ec57 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -908,12 +908,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_detect_hpd(dp);
-	if (ret) {
-		/* Cable has been disconnected, we're done */
-		return;
-	}
-
 	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
@@ -949,6 +943,12 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 static enum drm_connector_status
 analogix_dp_detect(struct drm_connector *connector, bool force)
 {
+	struct analogix_dp_device *dp = connector_to_dp(connector);
+
+	if (analogix_dp_detect_hpd(dp))
+		/* Cable has been disconnected, we're done */
+		return connector_status_disconnected;
+
 	return connector_status_connected;
 }
 
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 15/16] drm: bridge: analogix/dp: move hpd detect to connector detect function
@ 2015-09-01  6:17   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:17 UTC (permalink / raw)
  To: linux-arm-kernel

This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Take Jingoo suggest, add commit messages.

Changes in v3:
- move dp hpd detect to connector detect function.

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index e6b328a..499ec57 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -908,12 +908,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_detect_hpd(dp);
-	if (ret) {
-		/* Cable has been disconnected, we're done */
-		return;
-	}
-
 	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
@@ -949,6 +943,12 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 static enum drm_connector_status
 analogix_dp_detect(struct drm_connector *connector, bool force)
 {
+	struct analogix_dp_device *dp = connector_to_dp(connector);
+
+	if (analogix_dp_detect_hpd(dp))
+		/* Cable has been disconnected, we're done */
+		return connector_status_disconnected;
+
 	return connector_status_connected;
 }
 
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 16/16] drm: bridge: analogix/dp: add edid modes parse in get_modes method
@ 2015-09-01  6:20   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:20 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, Yakir Yang,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Add edid modes parse support

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 31 ++++++++-------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 46 +++++++++++-----------
 2 files changed, 40 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 499ec57..c71e5f6 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -111,7 +111,7 @@ static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 
 static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
-	unsigned char edid[EDID_BLOCK_LENGTH * 2];
+	unsigned char *edid = dp->edid;
 	unsigned int extend_block = 0;
 	unsigned char sum;
 	unsigned char test_vector;
@@ -908,12 +908,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_handle_edid(dp);
-	if (ret) {
-		dev_err(dp->dev, "unable to handle edid\n");
-		return;
-	}
-
 	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
 					 dp->video_info.max_link_rate);
 	if (ret) {
@@ -972,8 +966,24 @@ static int analogix_dp_get_modes(struct drm_connector *connector)
 {
 	struct analogix_dp_device *dp = connector_to_dp(connector);
 	struct analogix_dp_plat_data *plat_data = dp->plat_data;
+	struct edid *edid = (struct edid *)dp->edid;
 	int num_modes = 0;
 
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
+			DRM_ERROR("failed to setup the panel\n");
+			return -EINVAL;
+		}
+	}
+
+	if (analogix_dp_handle_edid(dp)) {
+		dev_err(dp->dev, "unable to handle edid\n");
+		return -EINVAL;
+	}
+
+	drm_mode_connector_update_edid_property(connector, edid);
+	num_modes += drm_add_edid_modes(connector, edid);
+
 	if (plat_data && plat_data->panel)
 		num_modes += drm_panel_get_modes(plat_data->panel);
 
@@ -1055,13 +1065,6 @@ static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->plat_data && dp->plat_data->panel) {
-		if (drm_panel_prepare(dp->plat_data->panel)) {
-			DRM_ERROR("failed to setup the panel\n");
-			return;
-		}
-	}
-
 	if (dp->plat_data && dp->plat_data->power_on)
 		dp->plat_data->power_on(dp->plat_data);
 
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 6960ab3..5348b1b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,28 @@
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
 
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
 enum link_rate_type {
 	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
 	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
@@ -161,6 +183,7 @@ struct analogix_dp_device {
 	int			dpms_mode;
 	int			hpd_gpio;
 	bool                    need_force_hpd;
+	unsigned char           edid[EDID_BLOCK_LENGTH * 2];
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -260,27 +283,4 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
 #endif /* _ANALOGIX_DP_CORE_H */
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 16/16] drm: bridge: analogix/dp: add edid modes parse in get_modes method
@ 2015-09-01  6:20   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:20 UTC (permalink / raw)
  To: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe-6d6DIl74uiNBDgjK7y7TUQ, Kukjin Kim, Krzysztof Kozlowski,
	Mark Yao
  Cc: Russell King, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	dianders-F7+t8E8rja9Wk0Htik3J/w, seanpaul-F7+t8E8rja9Wk0Htik3J/w,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt-sgV2jX0FEOL9JmXXK+q4OQ,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Yakir Yang,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Add edid modes parse support

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 31 ++++++++-------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 46 +++++++++++-----------
 2 files changed, 40 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 499ec57..c71e5f6 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -111,7 +111,7 @@ static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 
 static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
-	unsigned char edid[EDID_BLOCK_LENGTH * 2];
+	unsigned char *edid = dp->edid;
 	unsigned int extend_block = 0;
 	unsigned char sum;
 	unsigned char test_vector;
@@ -908,12 +908,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_handle_edid(dp);
-	if (ret) {
-		dev_err(dp->dev, "unable to handle edid\n");
-		return;
-	}
-
 	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
 					 dp->video_info.max_link_rate);
 	if (ret) {
@@ -972,8 +966,24 @@ static int analogix_dp_get_modes(struct drm_connector *connector)
 {
 	struct analogix_dp_device *dp = connector_to_dp(connector);
 	struct analogix_dp_plat_data *plat_data = dp->plat_data;
+	struct edid *edid = (struct edid *)dp->edid;
 	int num_modes = 0;
 
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
+			DRM_ERROR("failed to setup the panel\n");
+			return -EINVAL;
+		}
+	}
+
+	if (analogix_dp_handle_edid(dp)) {
+		dev_err(dp->dev, "unable to handle edid\n");
+		return -EINVAL;
+	}
+
+	drm_mode_connector_update_edid_property(connector, edid);
+	num_modes += drm_add_edid_modes(connector, edid);
+
 	if (plat_data && plat_data->panel)
 		num_modes += drm_panel_get_modes(plat_data->panel);
 
@@ -1055,13 +1065,6 @@ static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->plat_data && dp->plat_data->panel) {
-		if (drm_panel_prepare(dp->plat_data->panel)) {
-			DRM_ERROR("failed to setup the panel\n");
-			return;
-		}
-	}
-
 	if (dp->plat_data && dp->plat_data->power_on)
 		dp->plat_data->power_on(dp->plat_data);
 
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 6960ab3..5348b1b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,28 @@
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
 
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
 enum link_rate_type {
 	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
 	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
@@ -161,6 +183,7 @@ struct analogix_dp_device {
 	int			dpms_mode;
 	int			hpd_gpio;
 	bool                    need_force_hpd;
+	unsigned char           edid[EDID_BLOCK_LENGTH * 2];
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -260,27 +283,4 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
 #endif /* _ANALOGIX_DP_CORE_H */
-- 
2.1.2


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^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v4 16/16] drm: bridge: analogix/dp: add edid modes parse in get_modes method
@ 2015-09-01  6:20   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01  6:20 UTC (permalink / raw)
  To: linux-arm-kernel

Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Add edid modes parse support

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 31 ++++++++-------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 46 +++++++++++-----------
 2 files changed, 40 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 499ec57..c71e5f6 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -111,7 +111,7 @@ static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 
 static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
-	unsigned char edid[EDID_BLOCK_LENGTH * 2];
+	unsigned char *edid = dp->edid;
 	unsigned int extend_block = 0;
 	unsigned char sum;
 	unsigned char test_vector;
@@ -908,12 +908,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_handle_edid(dp);
-	if (ret) {
-		dev_err(dp->dev, "unable to handle edid\n");
-		return;
-	}
-
 	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
 					 dp->video_info.max_link_rate);
 	if (ret) {
@@ -972,8 +966,24 @@ static int analogix_dp_get_modes(struct drm_connector *connector)
 {
 	struct analogix_dp_device *dp = connector_to_dp(connector);
 	struct analogix_dp_plat_data *plat_data = dp->plat_data;
+	struct edid *edid = (struct edid *)dp->edid;
 	int num_modes = 0;
 
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
+			DRM_ERROR("failed to setup the panel\n");
+			return -EINVAL;
+		}
+	}
+
+	if (analogix_dp_handle_edid(dp)) {
+		dev_err(dp->dev, "unable to handle edid\n");
+		return -EINVAL;
+	}
+
+	drm_mode_connector_update_edid_property(connector, edid);
+	num_modes += drm_add_edid_modes(connector, edid);
+
 	if (plat_data && plat_data->panel)
 		num_modes += drm_panel_get_modes(plat_data->panel);
 
@@ -1055,13 +1065,6 @@ static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->plat_data && dp->plat_data->panel) {
-		if (drm_panel_prepare(dp->plat_data->panel)) {
-			DRM_ERROR("failed to setup the panel\n");
-			return;
-		}
-	}
-
 	if (dp->plat_data && dp->plat_data->power_on)
 		dp->plat_data->power_on(dp->plat_data);
 
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 6960ab3..5348b1b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,28 @@
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
 
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
 enum link_rate_type {
 	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
 	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
@@ -161,6 +183,7 @@ struct analogix_dp_device {
 	int			dpms_mode;
 	int			hpd_gpio;
 	bool                    need_force_hpd;
+	unsigned char           edid[EDID_BLOCK_LENGTH * 2];
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -260,27 +283,4 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
 #endif /* _ANALOGIX_DP_CORE_H */
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
  2015-09-01  6:01   ` Yakir Yang
  (?)
@ 2015-09-01 14:24     ` Heiko Stuebner
  -1 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 14:24 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
> Rockchip have three clocks for dp controller, we leave pclk_edp
> to analogix_dp driver control, and keep the sclk_edp_24m and
> sclk_edp in platform driver.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Remove some deprecated DT properties in rockchip dp document.
> 
> Changes in v3:
> - Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
>   dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
>   core driver which name to "dp", and leave "pclk_edp" to rockchip dp
> platform driver which name to "pclk".
> - Take Heiko suggest, add devicetree binding document.
> - Take Heiko suggest, remove "rockchip,panel" DT property, take use of
> remote point to get panel node.
> - Add the new function point analogix_dp_platdata.get_modes init.
> 
> Changes in v2:
> - Take Heiko suggest, get panel node with remote-endpoint method,
>   and create devicetree binding for driver.
> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>   leave those clock to rockchip dp phy driver.
> 
>  .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
>  drivers/gpu/drm/rockchip/Kconfig                   |   9 +
>  drivers/gpu/drm/rockchip/Makefile                  |   1 +
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389
> +++++++++++++++++++++ 4 files changed, 473 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt create
> mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> 
> diff --git
> a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt new file
> mode 100644
> index 0000000..502483e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> @@ -0,0 +1,74 @@
> +Rockchip RK3288 specific extensions to the Analogix Display Port
> +================================
> +
> +Required properties:
> +- compatible: "rockchip,rk3288-edp";
> +
> +- reg: physical base address of the controller and length
> +
> +- clocks: from common clock binding: handle to dp clock.
> +	  of memory mapped region.
> +
> +- clock-names: from common clock binding:
> +	       Required elements: "dp" "pclk"
> +
> +- resets: Must contain an entry for each entry in reset-names.
> +	  See ../reset/reset.txt for details.
> +
> +- reset-names: Must include the name "dp"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +
> +- ports: contain a port node with endpoint definitions as defined in
> +  Documentation/devicetree/bindings/media/video-interfaces.txt.
> +
> +
> +For the below properties, please refer to Analogix DP binding document:
> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> +- phys (required)
> +- phy-names (required)
> +- hpd-gpios (optional)
> +---------------------------------------------------------------------------
> ---- +
> +Example:
> +	dp-controller: dp@ff970000 {
> +		compatible = "rockchip,rk3288-dp";
> +		reg = <0xff970000 0x4000>;
> +		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
> +		clock-names = "dp", "pclk";
> +		phys = <&dp_phy>;
> +		phy-names = "dp";
> +
> +		rockchip,grf = <&grf>;
> +		resets = <&cru 111>;
> +		reset-names = "dp";
> +
> +		status = "disabled";
> +
> +		ports {
> +			edp_in: port {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				edp_in_vopb: endpoint@0 {
> +					reg = <0>;
> +					remote-endpoint = <&vopb_out_edp>;
> +				};
> +				edp_in_vopl: endpoint@1 {
> +					reg = <1>;
> +					remote-endpoint = <&vopl_out_edp>;
> +				};
> +			};
> +
> +			edp_out: port@1 {
> +				reg = <1>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				edp_out_panel: endpoint {
> +					reg = <0>;
> +					remote-endpoint = <&panel_in_edp>
> +				};
> +			};
> +		};
> +	};
> +
just a nit right now, because "git am" mentioned it:

git am \[PATCH\ v4\ 08_16\]\ drm_rockchip_dp_add\ rockchip\ platform\ dp\ 
driver.mbox 
[...]/linux-rockchip/.git/rebase-apply/patch:108: new blank line at EOF.
+

meaning you're adding an empty line at the end :-)


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
@ 2015-09-01 14:24     ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 14:24 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel

Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
> Rockchip have three clocks for dp controller, we leave pclk_edp
> to analogix_dp driver control, and keep the sclk_edp_24m and
> sclk_edp in platform driver.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Remove some deprecated DT properties in rockchip dp document.
> 
> Changes in v3:
> - Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
>   dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
>   core driver which name to "dp", and leave "pclk_edp" to rockchip dp
> platform driver which name to "pclk".
> - Take Heiko suggest, add devicetree binding document.
> - Take Heiko suggest, remove "rockchip,panel" DT property, take use of
> remote point to get panel node.
> - Add the new function point analogix_dp_platdata.get_modes init.
> 
> Changes in v2:
> - Take Heiko suggest, get panel node with remote-endpoint method,
>   and create devicetree binding for driver.
> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>   leave those clock to rockchip dp phy driver.
> 
>  .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
>  drivers/gpu/drm/rockchip/Kconfig                   |   9 +
>  drivers/gpu/drm/rockchip/Makefile                  |   1 +
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389
> +++++++++++++++++++++ 4 files changed, 473 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt create
> mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> 
> diff --git
> a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt new file
> mode 100644
> index 0000000..502483e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> @@ -0,0 +1,74 @@
> +Rockchip RK3288 specific extensions to the Analogix Display Port
> +================================
> +
> +Required properties:
> +- compatible: "rockchip,rk3288-edp";
> +
> +- reg: physical base address of the controller and length
> +
> +- clocks: from common clock binding: handle to dp clock.
> +	  of memory mapped region.
> +
> +- clock-names: from common clock binding:
> +	       Required elements: "dp" "pclk"
> +
> +- resets: Must contain an entry for each entry in reset-names.
> +	  See ../reset/reset.txt for details.
> +
> +- reset-names: Must include the name "dp"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +
> +- ports: contain a port node with endpoint definitions as defined in
> +  Documentation/devicetree/bindings/media/video-interfaces.txt.
> +
> +
> +For the below properties, please refer to Analogix DP binding document:
> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> +- phys (required)
> +- phy-names (required)
> +- hpd-gpios (optional)
> +---------------------------------------------------------------------------
> ---- +
> +Example:
> +	dp-controller: dp@ff970000 {
> +		compatible = "rockchip,rk3288-dp";
> +		reg = <0xff970000 0x4000>;
> +		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
> +		clock-names = "dp", "pclk";
> +		phys = <&dp_phy>;
> +		phy-names = "dp";
> +
> +		rockchip,grf = <&grf>;
> +		resets = <&cru 111>;
> +		reset-names = "dp";
> +
> +		status = "disabled";
> +
> +		ports {
> +			edp_in: port {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				edp_in_vopb: endpoint@0 {
> +					reg = <0>;
> +					remote-endpoint = <&vopb_out_edp>;
> +				};
> +				edp_in_vopl: endpoint@1 {
> +					reg = <1>;
> +					remote-endpoint = <&vopl_out_edp>;
> +				};
> +			};
> +
> +			edp_out: port@1 {
> +				reg = <1>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				edp_out_panel: endpoint {
> +					reg = <0>;
> +					remote-endpoint = <&panel_in_edp>
> +				};
> +			};
> +		};
> +	};
> +
just a nit right now, because "git am" mentioned it:

git am \[PATCH\ v4\ 08_16\]\ drm_rockchip_dp_add\ rockchip\ platform\ dp\ 
driver.mbox 
[...]/linux-rockchip/.git/rebase-apply/patch:108: new blank line at EOF.
+

meaning you're adding an empty line at the end :-)


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
@ 2015-09-01 14:24     ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 14:24 UTC (permalink / raw)
  To: linux-arm-kernel

Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
> Rockchip have three clocks for dp controller, we leave pclk_edp
> to analogix_dp driver control, and keep the sclk_edp_24m and
> sclk_edp in platform driver.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Remove some deprecated DT properties in rockchip dp document.
> 
> Changes in v3:
> - Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
>   dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
>   core driver which name to "dp", and leave "pclk_edp" to rockchip dp
> platform driver which name to "pclk".
> - Take Heiko suggest, add devicetree binding document.
> - Take Heiko suggest, remove "rockchip,panel" DT property, take use of
> remote point to get panel node.
> - Add the new function point analogix_dp_platdata.get_modes init.
> 
> Changes in v2:
> - Take Heiko suggest, get panel node with remote-endpoint method,
>   and create devicetree binding for driver.
> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>   leave those clock to rockchip dp phy driver.
> 
>  .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
>  drivers/gpu/drm/rockchip/Kconfig                   |   9 +
>  drivers/gpu/drm/rockchip/Makefile                  |   1 +
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389
> +++++++++++++++++++++ 4 files changed, 473 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt create
> mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> 
> diff --git
> a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt new file
> mode 100644
> index 0000000..502483e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> @@ -0,0 +1,74 @@
> +Rockchip RK3288 specific extensions to the Analogix Display Port
> +================================
> +
> +Required properties:
> +- compatible: "rockchip,rk3288-edp";
> +
> +- reg: physical base address of the controller and length
> +
> +- clocks: from common clock binding: handle to dp clock.
> +	  of memory mapped region.
> +
> +- clock-names: from common clock binding:
> +	       Required elements: "dp" "pclk"
> +
> +- resets: Must contain an entry for each entry in reset-names.
> +	  See ../reset/reset.txt for details.
> +
> +- reset-names: Must include the name "dp"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +
> +- ports: contain a port node with endpoint definitions as defined in
> +  Documentation/devicetree/bindings/media/video-interfaces.txt.
> +
> +
> +For the below properties, please refer to Analogix DP binding document:
> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> +- phys (required)
> +- phy-names (required)
> +- hpd-gpios (optional)
> +---------------------------------------------------------------------------
> ---- +
> +Example:
> +	dp-controller: dp at ff970000 {
> +		compatible = "rockchip,rk3288-dp";
> +		reg = <0xff970000 0x4000>;
> +		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
> +		clock-names = "dp", "pclk";
> +		phys = <&dp_phy>;
> +		phy-names = "dp";
> +
> +		rockchip,grf = <&grf>;
> +		resets = <&cru 111>;
> +		reset-names = "dp";
> +
> +		status = "disabled";
> +
> +		ports {
> +			edp_in: port {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				edp_in_vopb: endpoint at 0 {
> +					reg = <0>;
> +					remote-endpoint = <&vopb_out_edp>;
> +				};
> +				edp_in_vopl: endpoint at 1 {
> +					reg = <1>;
> +					remote-endpoint = <&vopl_out_edp>;
> +				};
> +			};
> +
> +			edp_out: port at 1 {
> +				reg = <1>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				edp_out_panel: endpoint {
> +					reg = <0>;
> +					remote-endpoint = <&panel_in_edp>
> +				};
> +			};
> +		};
> +	};
> +
just a nit right now, because "git am" mentioned it:

git am \[PATCH\ v4\ 08_16\]\ drm_rockchip_dp_add\ rockchip\ platform\ dp\ 
driver.mbox 
[...]/linux-rockchip/.git/rebase-apply/patch:108: new blank line at EOF.
+

meaning you're adding an empty line at the end :-)


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
  2015-09-01 14:24     ` Heiko Stuebner
@ 2015-09-01 14:48       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01 14:48 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, Daniel Kurtz,
	Doug Anderson, Sean Paul, ajaynumb, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, robherring2, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel,
	s.infradead.org

Hi Heiko,

在 2015/9/1 22:24, Heiko Stuebner 写道:
> Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
>> Rockchip have three clocks for dp controller, we leave pclk_edp
>> to analogix_dp driver control, and keep the sclk_edp_24m and
>> sclk_edp in platform driver.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Remove some deprecated DT properties in rockchip dp document.
>>
>> Changes in v3:
>> - Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
>>    dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
>>    core driver which name to "dp", and leave "pclk_edp" to rockchip dp
>> platform driver which name to "pclk".
>> - Take Heiko suggest, add devicetree binding document.
>> - Take Heiko suggest, remove "rockchip,panel" DT property, take use of
>> remote point to get panel node.
>> - Add the new function point analogix_dp_platdata.get_modes init.
>>
>> Changes in v2:
>> - Take Heiko suggest, get panel node with remote-endpoint method,
>>    and create devicetree binding for driver.
>> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>>    leave those clock to rockchip dp phy driver.
>>
>>   .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
>>   drivers/gpu/drm/rockchip/Kconfig                   |   9 +
>>   drivers/gpu/drm/rockchip/Makefile                  |   1 +
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389
>> +++++++++++++++++++++ 4 files changed, 473 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt create
>> mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>
>> diff --git
>> a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt new file
>> mode 100644
>> index 0000000..502483e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> @@ -0,0 +1,74 @@
>> +Rockchip RK3288 specific extensions to the Analogix Display Port
>> +================================
>> +
>> +Required properties:
>> +- compatible: "rockchip,rk3288-edp";
>> +
>> +- reg: physical base address of the controller and length
>> +
>> +- clocks: from common clock binding: handle to dp clock.
>> +	  of memory mapped region.
>> +
>> +- clock-names: from common clock binding:
>> +	       Required elements: "dp" "pclk"
>> +
>> +- resets: Must contain an entry for each entry in reset-names.
>> +	  See ../reset/reset.txt for details.
>> +
>> +- reset-names: Must include the name "dp"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>> +
>> +- ports: contain a port node with endpoint definitions as defined in
>> +  Documentation/devicetree/bindings/media/video-interfaces.txt.
>> +
>> +
>> +For the below properties, please refer to Analogix DP binding document:
>> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> +- phys (required)
>> +- phy-names (required)
>> +- hpd-gpios (optional)
>> +---------------------------------------------------------------------------
>> ---- +
>> +Example:
>> +	dp-controller: dp@ff970000 {
>> +		compatible = "rockchip,rk3288-dp";
>> +		reg = <0xff970000 0x4000>;
>> +		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
>> +		clock-names = "dp", "pclk";
>> +		phys = <&dp_phy>;
>> +		phy-names = "dp";
>> +
>> +		rockchip,grf = <&grf>;
>> +		resets = <&cru 111>;
>> +		reset-names = "dp";
>> +
>> +		status = "disabled";
>> +
>> +		ports {
>> +			edp_in: port {
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				edp_in_vopb: endpoint@0 {
>> +					reg = <0>;
>> +					remote-endpoint = <&vopb_out_edp>;
>> +				};
>> +				edp_in_vopl: endpoint@1 {
>> +					reg = <1>;
>> +					remote-endpoint = <&vopl_out_edp>;
>> +				};
>> +			};
>> +
>> +			edp_out: port@1 {
>> +				reg = <1>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				edp_out_panel: endpoint {
>> +					reg = <0>;
>> +					remote-endpoint = <&panel_in_edp>
>> +				};
>> +			};
>> +		};
>> +	};
>> +
> just a nit right now, because "git am" mentioned it:
>
> git am \[PATCH\ v4\ 08_16\]\ drm_rockchip_dp_add\ rockchip\ platform\ dp\
> driver.mbox
> [...]/linux-rockchip/.git/rebase-apply/patch:108: new blank line at EOF.
> +
>
> meaning you're adding an empty line at the end :-)

Oh, thanks, I have saw this too when I apply this on linux-next
branch, but I haven't see the log very careful at that time, and
".git/rebase-apply/patch" just empty, so I just go ahead and
forget to fix this one.

Thanks for your remind,
  - Yakir

>
> Heiko
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
@ 2015-09-01 14:48       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-01 14:48 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King,
	Daniel Kurtz, Doug Anderson, Sean Paul,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt-sgV2jX0FEOL9JmXXK+q4OQ,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	dri-devel-PD4FTy7X32lNgt0PjOBp93rCq3LdnpKM

Hi Heiko,

在 2015/9/1 22:24, Heiko Stuebner 写道:
> Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
>> Rockchip have three clocks for dp controller, we leave pclk_edp
>> to analogix_dp driver control, and keep the sclk_edp_24m and
>> sclk_edp in platform driver.
>>
>> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>> Changes in v4:
>> - Remove some deprecated DT properties in rockchip dp document.
>>
>> Changes in v3:
>> - Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
>>    dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
>>    core driver which name to "dp", and leave "pclk_edp" to rockchip dp
>> platform driver which name to "pclk".
>> - Take Heiko suggest, add devicetree binding document.
>> - Take Heiko suggest, remove "rockchip,panel" DT property, take use of
>> remote point to get panel node.
>> - Add the new function point analogix_dp_platdata.get_modes init.
>>
>> Changes in v2:
>> - Take Heiko suggest, get panel node with remote-endpoint method,
>>    and create devicetree binding for driver.
>> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>>    leave those clock to rockchip dp phy driver.
>>
>>   .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
>>   drivers/gpu/drm/rockchip/Kconfig                   |   9 +
>>   drivers/gpu/drm/rockchip/Makefile                  |   1 +
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389
>> +++++++++++++++++++++ 4 files changed, 473 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt create
>> mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>
>> diff --git
>> a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt new file
>> mode 100644
>> index 0000000..502483e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> @@ -0,0 +1,74 @@
>> +Rockchip RK3288 specific extensions to the Analogix Display Port
>> +================================
>> +
>> +Required properties:
>> +- compatible: "rockchip,rk3288-edp";
>> +
>> +- reg: physical base address of the controller and length
>> +
>> +- clocks: from common clock binding: handle to dp clock.
>> +	  of memory mapped region.
>> +
>> +- clock-names: from common clock binding:
>> +	       Required elements: "dp" "pclk"
>> +
>> +- resets: Must contain an entry for each entry in reset-names.
>> +	  See ../reset/reset.txt for details.
>> +
>> +- reset-names: Must include the name "dp"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>> +
>> +- ports: contain a port node with endpoint definitions as defined in
>> +  Documentation/devicetree/bindings/media/video-interfaces.txt.
>> +
>> +
>> +For the below properties, please refer to Analogix DP binding document:
>> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> +- phys (required)
>> +- phy-names (required)
>> +- hpd-gpios (optional)
>> +---------------------------------------------------------------------------
>> ---- +
>> +Example:
>> +	dp-controller: dp@ff970000 {
>> +		compatible = "rockchip,rk3288-dp";
>> +		reg = <0xff970000 0x4000>;
>> +		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
>> +		clock-names = "dp", "pclk";
>> +		phys = <&dp_phy>;
>> +		phy-names = "dp";
>> +
>> +		rockchip,grf = <&grf>;
>> +		resets = <&cru 111>;
>> +		reset-names = "dp";
>> +
>> +		status = "disabled";
>> +
>> +		ports {
>> +			edp_in: port {
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				edp_in_vopb: endpoint@0 {
>> +					reg = <0>;
>> +					remote-endpoint = <&vopb_out_edp>;
>> +				};
>> +				edp_in_vopl: endpoint@1 {
>> +					reg = <1>;
>> +					remote-endpoint = <&vopl_out_edp>;
>> +				};
>> +			};
>> +
>> +			edp_out: port@1 {
>> +				reg = <1>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				edp_out_panel: endpoint {
>> +					reg = <0>;
>> +					remote-endpoint = <&panel_in_edp>
>> +				};
>> +			};
>> +		};
>> +	};
>> +
> just a nit right now, because "git am" mentioned it:
>
> git am \[PATCH\ v4\ 08_16\]\ drm_rockchip_dp_add\ rockchip\ platform\ dp\
> driver.mbox
> [...]/linux-rockchip/.git/rebase-apply/patch:108: new blank line at EOF.
> +
>
> meaning you're adding an empty line at the end :-)

Oh, thanks, I have saw this too when I apply this on linux-next
branch, but I haven't see the log very careful at that time, and
".git/rebase-apply/patch" just empty, so I just go ahead and
forget to fix this one.

Thanks for your remind,
  - Yakir

>
> Heiko
>
>
>


--
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
  2015-09-01  6:04   ` Yakir Yang
  (?)
@ 2015-09-01 16:51     ` Heiko Stuebner
  -1 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 16:51 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Kishon suggest, add commit message, and remove the redundant
>   rockchip_dp_phy_init() function, move those code to probe() method.
>   And remove driver .owner number.
> 
> Changes in v3:
> - Take Heiko suggest, add rockchip dp phy driver,
>   collect the phy clocks and power control.
> 
> Changes in v2: None
> 
>  .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++
>  drivers/phy/Kconfig                                |   7 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-rockchip-dp.c                      | 166
> +++++++++++++++++++++ 4 files changed, 200 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt create mode
> 100644 drivers/phy/phy-rockchip-dp.c
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt new file mode
> 100644
> index 0000000..5de1088
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> @@ -0,0 +1,26 @@
> +Rockchip Soc Seroes Display Port PHY
> +------------------------------------
> +
> +Required properties:
> +- compatible : should be one of the following supported values:
> +	 - "rockchip.rk3288-dp-phy"
> +
> +- reg : a list of registers used by phy driver

nodes do not necessarily need to have a regs property. You can do all 
operations via the grf syscon already.


> +- clocks: from common clock binding: handle to dp clock.
> +	of memory mapped region.
> +- clock-names: from common clock binding:
> +	Required elements: "sclk_dp" "sclk_dp_24m"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +- #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Example:
> +
> +edp_phy: phy@ff770274 {

edp_phy: edp-phy {


> +	compatilble = "rockchip,rk3288-dp-phy";
> +	reg = <0xff770274 4>;

no regs property

> +	rockchip,grf = <&grf>;
> +	clocks = <&cru SCLK_EDP_24M>;
> +	clock-names = "24m";
> +	#phy-cells = <0>;
> +}
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573..8f2bc4f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>  	help
>  	  Enable this to support the Rockchip USB 2.0 PHY.
> 
> +config PHY_ROCKCHIP_DP
> +	tristate "Rockchip Display Port PHY Driver"
> +	depends on ARCH_ROCKCHIP && OF
> +	select GENERIC_PHY
> +	help
> +	  Enable this to support the Rockchip Display Port PHY.
> +
>  config PHY_ST_SPEAR1310_MIPHY
>  	tristate "ST SPEAR1310-MIPHY driver"
>  	select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a5b18c1..e281f35 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+=
> phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
>  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
>  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
>  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..e9a726e
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,166 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12                   0x0274
> +#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
> +
> +#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
> +#define DP_PHY_SIDDQ_ON                 0
> +#define DP_PHY_SIDDQ_OFF                BIT(5)
> +
> +struct rockchip_dp_phy {
> +	struct device  *dev;
> +	struct regmap  *grf;
> +	void __iomem   *regs;
> +	struct clk     *phy_24m;
> +};
> +
> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
> +{
> +	int ret = 0;
> +
> +	ret = clk_set_rate(dp->phy_24m, 24000000);
> +	if (ret < 0) {
> +		dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = clk_prepare_enable(dp->phy_24m);
> +	if (ret < 0) {
> +		dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
> +{
> +	clk_disable_unprepare(dp->phy_24m);
> +
> +	return 0;
> +}
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> +
> +	if (enable) {
> +		rockchip_dp_phy_clk_enable(dp);
> +		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
> +	} else {
> +		rockchip_dp_phy_clk_disable(dp);
> +		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_dp_phy_power_on(struct phy *phy)
> +{
> +	return rockchip_set_phy_state(phy, true);
> +}
> +
> +static int rockchip_dp_phy_power_off(struct phy *phy)
> +{
> +	return rockchip_set_phy_state(phy, false);
> +}
> +
> +static struct phy_ops rockchip_dp_phy_ops = {

static const struct ...

see 4a9e5ca1a54a ("phy: Constify struct phy_ops variables")


> +	.power_on	= rockchip_dp_phy_power_on,
> +	.power_off	= rockchip_dp_phy_power_off,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	struct phy_provider *phy_provider;
> +	struct rockchip_dp_phy *dp;
> +	struct resource *res;
> +	struct phy *phy;
> +	int ret;
> +

I guess this could profit from a

if (!np)
	return -ENODEV;

> +	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
> +	if (IS_ERR(dp))
> +		return -ENOMEM;
> +
> +	dp->dev = dev;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	dp->regs = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(dp->regs))
> +		return PTR_ERR(dp->regs);
> +
> +	dp->phy_24m = devm_clk_get(dev, "24m");
> +	if (IS_ERR(dp->phy_24m)) {
> +		dev_err(dev, "cannot get clock 24m\n");
> +		return PTR_ERR(dp->phy_24m);
> +	}
> +
> +	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
> +	if (IS_ERR(dp->grf)) {
> +		dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
> +		return PTR_ERR(dp->grf);
> +	}
> +
> +	ret = regmap_write(dp->grf, GRF_SOC_CON12,
> +			   GRF_EDP_REF_CLK_SEL_INTER |
> +			   (GRF_EDP_REF_CLK_SEL_INTER << 16));
> +	if (ret != 0) {
> +		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
> +		return ret;
> +	}
> +
> +	phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);

hmm, where did you find 4 params for devm_phy_create? Shouldn't this be

	phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);

instead - and also include the phy dt-node as 2nd parameter?


Heiko

> +	if (IS_ERR(phy)) {
> +		dev_err(dev, "failed to create phy\n");
> +		return PTR_ERR(phy);
> +	}
> +	phy_set_drvdata(phy, dp);
> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> +	return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
> +	{ .compatible = "rockchip,rk3288-dp-phy" },
> +	{}
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
> +
> +static struct platform_driver rockchip_dp_phy_driver = {
> +	.probe		= rockchip_dp_phy_probe,
> +	.driver		= {
> +		.name	= "rockchip-dp-phy",
> +		.of_match_table = rockchip_dp_phy_dt_ids,
> +	},
> +};
> +
> +module_platform_driver(rockchip_dp_phy_driver);
> +
> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
> +MODULE_LICENSE("GPL v2");


^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-01 16:51     ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 16:51 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel

Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Kishon suggest, add commit message, and remove the redundant
>   rockchip_dp_phy_init() function, move those code to probe() method.
>   And remove driver .owner number.
> 
> Changes in v3:
> - Take Heiko suggest, add rockchip dp phy driver,
>   collect the phy clocks and power control.
> 
> Changes in v2: None
> 
>  .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++
>  drivers/phy/Kconfig                                |   7 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-rockchip-dp.c                      | 166
> +++++++++++++++++++++ 4 files changed, 200 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt create mode
> 100644 drivers/phy/phy-rockchip-dp.c
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt new file mode
> 100644
> index 0000000..5de1088
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> @@ -0,0 +1,26 @@
> +Rockchip Soc Seroes Display Port PHY
> +------------------------------------
> +
> +Required properties:
> +- compatible : should be one of the following supported values:
> +	 - "rockchip.rk3288-dp-phy"
> +
> +- reg : a list of registers used by phy driver

nodes do not necessarily need to have a regs property. You can do all 
operations via the grf syscon already.


> +- clocks: from common clock binding: handle to dp clock.
> +	of memory mapped region.
> +- clock-names: from common clock binding:
> +	Required elements: "sclk_dp" "sclk_dp_24m"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +- #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Example:
> +
> +edp_phy: phy@ff770274 {

edp_phy: edp-phy {


> +	compatilble = "rockchip,rk3288-dp-phy";
> +	reg = <0xff770274 4>;

no regs property

> +	rockchip,grf = <&grf>;
> +	clocks = <&cru SCLK_EDP_24M>;
> +	clock-names = "24m";
> +	#phy-cells = <0>;
> +}
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573..8f2bc4f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>  	help
>  	  Enable this to support the Rockchip USB 2.0 PHY.
> 
> +config PHY_ROCKCHIP_DP
> +	tristate "Rockchip Display Port PHY Driver"
> +	depends on ARCH_ROCKCHIP && OF
> +	select GENERIC_PHY
> +	help
> +	  Enable this to support the Rockchip Display Port PHY.
> +
>  config PHY_ST_SPEAR1310_MIPHY
>  	tristate "ST SPEAR1310-MIPHY driver"
>  	select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a5b18c1..e281f35 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+=
> phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
>  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
>  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
>  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..e9a726e
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,166 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12                   0x0274
> +#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
> +
> +#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
> +#define DP_PHY_SIDDQ_ON                 0
> +#define DP_PHY_SIDDQ_OFF                BIT(5)
> +
> +struct rockchip_dp_phy {
> +	struct device  *dev;
> +	struct regmap  *grf;
> +	void __iomem   *regs;
> +	struct clk     *phy_24m;
> +};
> +
> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
> +{
> +	int ret = 0;
> +
> +	ret = clk_set_rate(dp->phy_24m, 24000000);
> +	if (ret < 0) {
> +		dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = clk_prepare_enable(dp->phy_24m);
> +	if (ret < 0) {
> +		dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
> +{
> +	clk_disable_unprepare(dp->phy_24m);
> +
> +	return 0;
> +}
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> +
> +	if (enable) {
> +		rockchip_dp_phy_clk_enable(dp);
> +		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
> +	} else {
> +		rockchip_dp_phy_clk_disable(dp);
> +		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_dp_phy_power_on(struct phy *phy)
> +{
> +	return rockchip_set_phy_state(phy, true);
> +}
> +
> +static int rockchip_dp_phy_power_off(struct phy *phy)
> +{
> +	return rockchip_set_phy_state(phy, false);
> +}
> +
> +static struct phy_ops rockchip_dp_phy_ops = {

static const struct ...

see 4a9e5ca1a54a ("phy: Constify struct phy_ops variables")


> +	.power_on	= rockchip_dp_phy_power_on,
> +	.power_off	= rockchip_dp_phy_power_off,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	struct phy_provider *phy_provider;
> +	struct rockchip_dp_phy *dp;
> +	struct resource *res;
> +	struct phy *phy;
> +	int ret;
> +

I guess this could profit from a

if (!np)
	return -ENODEV;

> +	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
> +	if (IS_ERR(dp))
> +		return -ENOMEM;
> +
> +	dp->dev = dev;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	dp->regs = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(dp->regs))
> +		return PTR_ERR(dp->regs);
> +
> +	dp->phy_24m = devm_clk_get(dev, "24m");
> +	if (IS_ERR(dp->phy_24m)) {
> +		dev_err(dev, "cannot get clock 24m\n");
> +		return PTR_ERR(dp->phy_24m);
> +	}
> +
> +	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
> +	if (IS_ERR(dp->grf)) {
> +		dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
> +		return PTR_ERR(dp->grf);
> +	}
> +
> +	ret = regmap_write(dp->grf, GRF_SOC_CON12,
> +			   GRF_EDP_REF_CLK_SEL_INTER |
> +			   (GRF_EDP_REF_CLK_SEL_INTER << 16));
> +	if (ret != 0) {
> +		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
> +		return ret;
> +	}
> +
> +	phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);

hmm, where did you find 4 params for devm_phy_create? Shouldn't this be

	phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);

instead - and also include the phy dt-node as 2nd parameter?


Heiko

> +	if (IS_ERR(phy)) {
> +		dev_err(dev, "failed to create phy\n");
> +		return PTR_ERR(phy);
> +	}
> +	phy_set_drvdata(phy, dp);
> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> +	return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
> +	{ .compatible = "rockchip,rk3288-dp-phy" },
> +	{}
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
> +
> +static struct platform_driver rockchip_dp_phy_driver = {
> +	.probe		= rockchip_dp_phy_probe,
> +	.driver		= {
> +		.name	= "rockchip-dp-phy",
> +		.of_match_table = rockchip_dp_phy_dt_ids,
> +	},
> +};
> +
> +module_platform_driver(rockchip_dp_phy_driver);
> +
> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
> +MODULE_LICENSE("GPL v2");

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-01 16:51     ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 16:51 UTC (permalink / raw)
  To: linux-arm-kernel

Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Kishon suggest, add commit message, and remove the redundant
>   rockchip_dp_phy_init() function, move those code to probe() method.
>   And remove driver .owner number.
> 
> Changes in v3:
> - Take Heiko suggest, add rockchip dp phy driver,
>   collect the phy clocks and power control.
> 
> Changes in v2: None
> 
>  .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++
>  drivers/phy/Kconfig                                |   7 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-rockchip-dp.c                      | 166
> +++++++++++++++++++++ 4 files changed, 200 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt create mode
> 100644 drivers/phy/phy-rockchip-dp.c
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt new file mode
> 100644
> index 0000000..5de1088
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> @@ -0,0 +1,26 @@
> +Rockchip Soc Seroes Display Port PHY
> +------------------------------------
> +
> +Required properties:
> +- compatible : should be one of the following supported values:
> +	 - "rockchip.rk3288-dp-phy"
> +
> +- reg : a list of registers used by phy driver

nodes do not necessarily need to have a regs property. You can do all 
operations via the grf syscon already.


> +- clocks: from common clock binding: handle to dp clock.
> +	of memory mapped region.
> +- clock-names: from common clock binding:
> +	Required elements: "sclk_dp" "sclk_dp_24m"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +- #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Example:
> +
> +edp_phy: phy at ff770274 {

edp_phy: edp-phy {


> +	compatilble = "rockchip,rk3288-dp-phy";
> +	reg = <0xff770274 4>;

no regs property

> +	rockchip,grf = <&grf>;
> +	clocks = <&cru SCLK_EDP_24M>;
> +	clock-names = "24m";
> +	#phy-cells = <0>;
> +}
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573..8f2bc4f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>  	help
>  	  Enable this to support the Rockchip USB 2.0 PHY.
> 
> +config PHY_ROCKCHIP_DP
> +	tristate "Rockchip Display Port PHY Driver"
> +	depends on ARCH_ROCKCHIP && OF
> +	select GENERIC_PHY
> +	help
> +	  Enable this to support the Rockchip Display Port PHY.
> +
>  config PHY_ST_SPEAR1310_MIPHY
>  	tristate "ST SPEAR1310-MIPHY driver"
>  	select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a5b18c1..e281f35 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+=
> phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
>  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
>  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
>  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..e9a726e
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,166 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12                   0x0274
> +#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
> +
> +#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
> +#define DP_PHY_SIDDQ_ON                 0
> +#define DP_PHY_SIDDQ_OFF                BIT(5)
> +
> +struct rockchip_dp_phy {
> +	struct device  *dev;
> +	struct regmap  *grf;
> +	void __iomem   *regs;
> +	struct clk     *phy_24m;
> +};
> +
> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
> +{
> +	int ret = 0;
> +
> +	ret = clk_set_rate(dp->phy_24m, 24000000);
> +	if (ret < 0) {
> +		dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = clk_prepare_enable(dp->phy_24m);
> +	if (ret < 0) {
> +		dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
> +{
> +	clk_disable_unprepare(dp->phy_24m);
> +
> +	return 0;
> +}
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> +
> +	if (enable) {
> +		rockchip_dp_phy_clk_enable(dp);
> +		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
> +	} else {
> +		rockchip_dp_phy_clk_disable(dp);
> +		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_dp_phy_power_on(struct phy *phy)
> +{
> +	return rockchip_set_phy_state(phy, true);
> +}
> +
> +static int rockchip_dp_phy_power_off(struct phy *phy)
> +{
> +	return rockchip_set_phy_state(phy, false);
> +}
> +
> +static struct phy_ops rockchip_dp_phy_ops = {

static const struct ...

see 4a9e5ca1a54a ("phy: Constify struct phy_ops variables")


> +	.power_on	= rockchip_dp_phy_power_on,
> +	.power_off	= rockchip_dp_phy_power_off,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	struct phy_provider *phy_provider;
> +	struct rockchip_dp_phy *dp;
> +	struct resource *res;
> +	struct phy *phy;
> +	int ret;
> +

I guess this could profit from a

if (!np)
	return -ENODEV;

> +	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
> +	if (IS_ERR(dp))
> +		return -ENOMEM;
> +
> +	dp->dev = dev;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	dp->regs = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(dp->regs))
> +		return PTR_ERR(dp->regs);
> +
> +	dp->phy_24m = devm_clk_get(dev, "24m");
> +	if (IS_ERR(dp->phy_24m)) {
> +		dev_err(dev, "cannot get clock 24m\n");
> +		return PTR_ERR(dp->phy_24m);
> +	}
> +
> +	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
> +	if (IS_ERR(dp->grf)) {
> +		dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
> +		return PTR_ERR(dp->grf);
> +	}
> +
> +	ret = regmap_write(dp->grf, GRF_SOC_CON12,
> +			   GRF_EDP_REF_CLK_SEL_INTER |
> +			   (GRF_EDP_REF_CLK_SEL_INTER << 16));
> +	if (ret != 0) {
> +		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
> +		return ret;
> +	}
> +
> +	phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);

hmm, where did you find 4 params for devm_phy_create? Shouldn't this be

	phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);

instead - and also include the phy dt-node as 2nd parameter?


Heiko

> +	if (IS_ERR(phy)) {
> +		dev_err(dev, "failed to create phy\n");
> +		return PTR_ERR(phy);
> +	}
> +	phy_set_drvdata(phy, dp);
> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> +	return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
> +	{ .compatible = "rockchip,rk3288-dp-phy" },
> +	{}
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
> +
> +static struct platform_driver rockchip_dp_phy_driver = {
> +	.probe		= rockchip_dp_phy_probe,
> +	.driver		= {
> +		.name	= "rockchip-dp-phy",
> +		.of_match_table = rockchip_dp_phy_dt_ids,
> +	},
> +};
> +
> +module_platform_driver(rockchip_dp_phy_driver);
> +
> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
> +MODULE_LICENSE("GPL v2");

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-01 20:46     ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 20:46 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
> Split the dp core driver from exynos directory to bridge
> directory, and rename the core driver to analogix_dp_*,
> leave the platform code to analogix_dp-exynos.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>

[...]

> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index bed0252..7d62f22 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

[...]

>  	connector->polled = DRM_CONNECTOR_POLL_HPD;
> 
>  	ret = drm_connector_init(dp->drm_dev, connector,
> -				 &exynos_dp_connector_funcs,
> +				 &analogix_dp_connector_funcs,
>  				 DRM_MODE_CONNECTOR_eDP);
>  	if (ret) {
>  		DRM_ERROR("Failed to initialize connector with drm\n");
>  		return ret;
>  	}
> 
> -	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
> +	drm_connector_helper_add(connector,
> +				 &analogix_dp_connector_helper_funcs);
>  	drm_connector_register(connector);

this should only run on exynos, as we're doing all our connector registration 
in the core driver after all components are bound, so I guess something like 
the following is needed:

       if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
               drm_connector_register(connector);



>  	drm_mode_connector_attach_encoder(connector, encoder);
> 

[...]

> @@ -1301,7 +1239,10 @@ static int exynos_dp_bind(struct device *dev, struct
> device *master, void *data) if (IS_ERR(dp->reg_base))
>  		return PTR_ERR(dp->reg_base);
> 
> -	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
> +	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
> +	if (gpio_is_valid(dp->hpd_gpio))

this should be !gpio_is_valid ... i.e. only check the old property if the new 
one is _not_ valid


> +		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
> +						 "samsung,hpd-gpio", 0);
> 
>  	if (gpio_is_valid(dp->hpd_gpio)) {
>  		/*


^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-01 20:46     ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 20:46 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Krzysztof Kozlowski, David Airlie,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Andrzej Hajda,
	Gustavo Padovan, architt-sgV2jX0FEOL9JmXXK+q4OQ,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Russell King, Thierry Reding,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Inki Dae, joe-6d6DIl74uiNBDgjK7y7TUQ, Rob Herring,
	dianders-F7+t8E8rja9Wk0Htik3J/w,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Yao,
	Jingoo Han, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kyungmin

Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
> Split the dp core driver from exynos directory to bridge
> directory, and rename the core driver to analogix_dp_*,
> leave the platform code to analogix_dp-exynos.
> 
> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

[...]

> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index bed0252..7d62f22 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

[...]

>  	connector->polled = DRM_CONNECTOR_POLL_HPD;
> 
>  	ret = drm_connector_init(dp->drm_dev, connector,
> -				 &exynos_dp_connector_funcs,
> +				 &analogix_dp_connector_funcs,
>  				 DRM_MODE_CONNECTOR_eDP);
>  	if (ret) {
>  		DRM_ERROR("Failed to initialize connector with drm\n");
>  		return ret;
>  	}
> 
> -	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
> +	drm_connector_helper_add(connector,
> +				 &analogix_dp_connector_helper_funcs);
>  	drm_connector_register(connector);

this should only run on exynos, as we're doing all our connector registration 
in the core driver after all components are bound, so I guess something like 
the following is needed:

       if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
               drm_connector_register(connector);



>  	drm_mode_connector_attach_encoder(connector, encoder);
> 

[...]

> @@ -1301,7 +1239,10 @@ static int exynos_dp_bind(struct device *dev, struct
> device *master, void *data) if (IS_ERR(dp->reg_base))
>  		return PTR_ERR(dp->reg_base);
> 
> -	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
> +	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
> +	if (gpio_is_valid(dp->hpd_gpio))

this should be !gpio_is_valid ... i.e. only check the old property if the new 
one is _not_ valid


> +		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
> +						 "samsung,hpd-gpio", 0);
> 
>  	if (gpio_is_valid(dp->hpd_gpio)) {
>  		/*

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-01 20:46     ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 20:46 UTC (permalink / raw)
  To: linux-arm-kernel

Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
> Split the dp core driver from exynos directory to bridge
> directory, and rename the core driver to analogix_dp_*,
> leave the platform code to analogix_dp-exynos.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>

[...]

> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index bed0252..7d62f22 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

[...]

>  	connector->polled = DRM_CONNECTOR_POLL_HPD;
> 
>  	ret = drm_connector_init(dp->drm_dev, connector,
> -				 &exynos_dp_connector_funcs,
> +				 &analogix_dp_connector_funcs,
>  				 DRM_MODE_CONNECTOR_eDP);
>  	if (ret) {
>  		DRM_ERROR("Failed to initialize connector with drm\n");
>  		return ret;
>  	}
> 
> -	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
> +	drm_connector_helper_add(connector,
> +				 &analogix_dp_connector_helper_funcs);
>  	drm_connector_register(connector);

this should only run on exynos, as we're doing all our connector registration 
in the core driver after all components are bound, so I guess something like 
the following is needed:

       if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
               drm_connector_register(connector);



>  	drm_mode_connector_attach_encoder(connector, encoder);
> 

[...]

> @@ -1301,7 +1239,10 @@ static int exynos_dp_bind(struct device *dev, struct
> device *master, void *data) if (IS_ERR(dp->reg_base))
>  		return PTR_ERR(dp->reg_base);
> 
> -	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
> +	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
> +	if (gpio_is_valid(dp->hpd_gpio))

this should be !gpio_is_valid ... i.e. only check the old property if the new 
one is _not_ valid


> +		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
> +						 "samsung,hpd-gpio", 0);
> 
>  	if (gpio_is_valid(dp->hpd_gpio)) {
>  		/*

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
  2015-09-01 16:51     ` Heiko Stuebner
  (?)
@ 2015-09-01 20:58       ` Heiko Stuebner
  -1 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 20:58 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Hi Yakir,

small nit more below

Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
> > +- clocks: from common clock binding: handle to dp clock.
> > +	of memory mapped region.
> > +- clock-names: from common clock binding:
> > +	Required elements: "sclk_dp" "sclk_dp_24m"
> > +
> > +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> > +- #phy-cells : from the generic PHY bindings, must be 0;
> > +
> > +Example:
> > +
> > +edp_phy: phy@ff770274 {
> 
> edp_phy: edp-phy {
> 
> > +	compatilble = "rockchip,rk3288-dp-phy";

typo: compatible


^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-01 20:58       ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 20:58 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel

Hi Yakir,

small nit more below

Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
> > +- clocks: from common clock binding: handle to dp clock.
> > +	of memory mapped region.
> > +- clock-names: from common clock binding:
> > +	Required elements: "sclk_dp" "sclk_dp_24m"
> > +
> > +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> > +- #phy-cells : from the generic PHY bindings, must be 0;
> > +
> > +Example:
> > +
> > +edp_phy: phy@ff770274 {
> 
> edp_phy: edp-phy {
> 
> > +	compatilble = "rockchip,rk3288-dp-phy";

typo: compatible

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-01 20:58       ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 20:58 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Yakir,

small nit more below

Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
> > +- clocks: from common clock binding: handle to dp clock.
> > +	of memory mapped region.
> > +- clock-names: from common clock binding:
> > +	Required elements: "sclk_dp" "sclk_dp_24m"
> > +
> > +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> > +- #phy-cells : from the generic PHY bindings, must be 0;
> > +
> > +Example:
> > +
> > +edp_phy: phy at ff770274 {
> 
> edp_phy: edp-phy {
> 
> > +	compatilble = "rockchip,rk3288-dp-phy";

typo: compatible

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
  2015-09-01  6:01   ` Yakir Yang
  (?)
@ 2015-09-01 21:00     ` Heiko Stuebner
  -1 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 21:00 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Hi Yakir,

Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
> Rockchip have three clocks for dp controller, we leave pclk_edp
> to analogix_dp driver control, and keep the sclk_edp_24m and
> sclk_edp in platform driver.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Remove some deprecated DT properties in rockchip dp document.
> 
> Changes in v3:
> - Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
>   dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
>   core driver which name to "dp", and leave "pclk_edp" to rockchip dp
> platform driver which name to "pclk".
> - Take Heiko suggest, add devicetree binding document.
> - Take Heiko suggest, remove "rockchip,panel" DT property, take use of
> remote point to get panel node.
> - Add the new function point analogix_dp_platdata.get_modes init.
> 
> Changes in v2:
> - Take Heiko suggest, get panel node with remote-endpoint method,
>   and create devicetree binding for driver.
> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>   leave those clock to rockchip dp phy driver.
> 
>  .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
>  drivers/gpu/drm/rockchip/Kconfig                   |   9 +
>  drivers/gpu/drm/rockchip/Makefile                  |   1 +
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389
> +++++++++++++++++++++ 4 files changed, 473 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt create
> mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> 
> diff --git
> a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt new file
> mode 100644
> index 0000000..502483e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> @@ -0,0 +1,74 @@
> +Rockchip RK3288 specific extensions to the Analogix Display Port
> +================================
> +
> +Required properties:
> +- compatible: "rockchip,rk3288-edp";
> +
> +- reg: physical base address of the controller and length
> +
> +- clocks: from common clock binding: handle to dp clock.
> +	  of memory mapped region.
> +
> +- clock-names: from common clock binding:
> +	       Required elements: "dp" "pclk"
> +
> +- resets: Must contain an entry for each entry in reset-names.
> +	  See ../reset/reset.txt for details.
> +
> +- reset-names: Must include the name "dp"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +
> +- ports: contain a port node with endpoint definitions as defined in
> +  Documentation/devicetree/bindings/media/video-interfaces.txt.
> +
> +
> +For the below properties, please refer to Analogix DP binding document:
> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> +- phys (required)
> +- phy-names (required)
> +- hpd-gpios (optional)
> +---------------------------------------------------------------------------
> ---- +
> +Example:
> +	dp-controller: dp@ff970000 {
> +		compatible = "rockchip,rk3288-dp";
> +		reg = <0xff970000 0x4000>;
> +		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
> +		clock-names = "dp", "pclk";
> +		phys = <&dp_phy>;
> +		phy-names = "dp";
> +
> +		rockchip,grf = <&grf>;
> +		resets = <&cru 111>;
> +		reset-names = "dp";
> +
> +		status = "disabled";
> +
> +		ports {

#address-cells = <1>;
#size-cells = <0>;

> +			edp_in: port {

edp_in: port@0
	reg = <0>;

> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				edp_in_vopb: endpoint@0 {
> +					reg = <0>;
> +					remote-endpoint = <&vopb_out_edp>;
> +				};
> +				edp_in_vopl: endpoint@1 {
> +					reg = <1>;
> +					remote-endpoint = <&vopl_out_edp>;
> +				};
> +			};
> +
> +			edp_out: port@1 {
> +				reg = <1>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				edp_out_panel: endpoint {
> +					reg = <0>;
> +					remote-endpoint = <&panel_in_edp>
> +				};
> +			};
> +		};
> +	};
> +
> diff --git a/drivers/gpu/drm/rockchip/Kconfig
> b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..c2ba945 100644
> --- a/drivers/gpu/drm/rockchip/Kconfig
> +++ b/drivers/gpu/drm/rockchip/Kconfig
> @@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
>  	  for the Synopsys DesignWare HDMI driver. If you want to
>  	  enable HDMI on RK3288 based SoC, you should selet this
>  	  option.
> +
> +config ROCKCHIP_ANALOGIX_DP
> +        tristate "Rockchip specific extensions for Analogix DP driver"
> +        depends on DRM_ROCKCHIP
> +        select DRM_ANALOGIX_DP
> +        help
> +	  This selects support for Rockchip SoC specific extensions
> +	  for the Analogix Core DP driver. If you want to enable DP
> +	  on RK3288 based SoC, you should selet this option.
> diff --git a/drivers/gpu/drm/rockchip/Makefile
> b/drivers/gpu/drm/rockchip/Makefile index f3d8a19..8ad01fb 100644
> --- a/drivers/gpu/drm/rockchip/Makefile
> +++ b/drivers/gpu/drm/rockchip/Makefile
> @@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
> rockchip_drm_fbdev.o \ rockchip_drm_gem.o
> 
>  obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
> +obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
> 
>  obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c new file mode 100644
> index 0000000..cebff9e
> --- /dev/null
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -0,0 +1,389 @@
> +/*
> + * Rockchip SoC DP (Display Port) interface driver.
> + *
> + * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
> + * Author: Andy Yan <andy.yan@rock-chips.com>
> + *         Yakir Yang <ykk@rock-chips.com>
> + *         Jeff Chen <jeff.chen@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +#include <drm/drmP.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_dp_helper.h>
> +
> +#include <linux/component.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_graph.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/clk.h>
> +
> +#include <video/of_videomode.h>
> +#include <video/videomode.h>
> +
> +#include <drm/bridge/analogix_dp.h>
> +
> +#include "rockchip_drm_drv.h"
> +#include "rockchip_drm_vop.h"
> +
> +#define encoder_to_dp(c) \
> +		container_of(c, struct rockchip_dp_device, encoder)
> +
> +#define plat_data_to_dp(pd) \
> +		container_of(pd, struct rockchip_dp_device, plat_data)
> +
> +/* dp grf register offset */
> +#define GRF_GPIO7B_IOMUX                        0x0070
> +#define GPIO7B3_SEL_MASK                        (0x03 << 6)
> +#define GPIO7B3_SEL_EDP_HOTPLUG                 BIT(7)

please remove, see comment near pre_init


> +
> +#define GRF_SOC_CON6                            0x025c
> +#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
> +#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
> +#define GRF_EDP_SEL_VOP_BIG                     0
> +
> +struct rockchip_dp_device {
> +	struct drm_device        *drm_dev;
> +	struct device            *dev;
> +	struct drm_encoder       encoder;
> +	struct drm_display_mode  mode;
> +
> +	struct clk               *pclk;
> +	struct regmap            *grf;
> +	struct reset_control     *rst;
> +
> +	struct analogix_dp_plat_data plat_data;
> +};
> +
> +static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
> +{
> +	u32 val;
> +	int ret;
> +
> +	val = GPIO7B3_SEL_EDP_HOTPLUG | (GPIO7B3_SEL_MASK << 16);
> +	ret = regmap_write(dp->grf, GRF_GPIO7B_IOMUX, val);

this is just a regular pinctrl setting. Please don't write onto other 
components registers. Use a regular pinctrl setting in the devicetree instead.


> +	if (ret != 0) {
> +		dev_err(dp->dev, "Could not config GRF edp hpd: %d\n", ret);
> +		return ret;
> +	}
> +
> +	reset_control_assert(dp->rst);
> +	usleep_range(10, 20);
> +	reset_control_deassert(dp->rst);
> +
> +	return 0;
> +}


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
@ 2015-09-01 21:00     ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 21:00 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel

Hi Yakir,

Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
> Rockchip have three clocks for dp controller, we leave pclk_edp
> to analogix_dp driver control, and keep the sclk_edp_24m and
> sclk_edp in platform driver.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Remove some deprecated DT properties in rockchip dp document.
> 
> Changes in v3:
> - Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
>   dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
>   core driver which name to "dp", and leave "pclk_edp" to rockchip dp
> platform driver which name to "pclk".
> - Take Heiko suggest, add devicetree binding document.
> - Take Heiko suggest, remove "rockchip,panel" DT property, take use of
> remote point to get panel node.
> - Add the new function point analogix_dp_platdata.get_modes init.
> 
> Changes in v2:
> - Take Heiko suggest, get panel node with remote-endpoint method,
>   and create devicetree binding for driver.
> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>   leave those clock to rockchip dp phy driver.
> 
>  .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
>  drivers/gpu/drm/rockchip/Kconfig                   |   9 +
>  drivers/gpu/drm/rockchip/Makefile                  |   1 +
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389
> +++++++++++++++++++++ 4 files changed, 473 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt create
> mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> 
> diff --git
> a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt new file
> mode 100644
> index 0000000..502483e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> @@ -0,0 +1,74 @@
> +Rockchip RK3288 specific extensions to the Analogix Display Port
> +================================
> +
> +Required properties:
> +- compatible: "rockchip,rk3288-edp";
> +
> +- reg: physical base address of the controller and length
> +
> +- clocks: from common clock binding: handle to dp clock.
> +	  of memory mapped region.
> +
> +- clock-names: from common clock binding:
> +	       Required elements: "dp" "pclk"
> +
> +- resets: Must contain an entry for each entry in reset-names.
> +	  See ../reset/reset.txt for details.
> +
> +- reset-names: Must include the name "dp"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +
> +- ports: contain a port node with endpoint definitions as defined in
> +  Documentation/devicetree/bindings/media/video-interfaces.txt.
> +
> +
> +For the below properties, please refer to Analogix DP binding document:
> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> +- phys (required)
> +- phy-names (required)
> +- hpd-gpios (optional)
> +---------------------------------------------------------------------------
> ---- +
> +Example:
> +	dp-controller: dp@ff970000 {
> +		compatible = "rockchip,rk3288-dp";
> +		reg = <0xff970000 0x4000>;
> +		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
> +		clock-names = "dp", "pclk";
> +		phys = <&dp_phy>;
> +		phy-names = "dp";
> +
> +		rockchip,grf = <&grf>;
> +		resets = <&cru 111>;
> +		reset-names = "dp";
> +
> +		status = "disabled";
> +
> +		ports {

#address-cells = <1>;
#size-cells = <0>;

> +			edp_in: port {

edp_in: port@0
	reg = <0>;

> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				edp_in_vopb: endpoint@0 {
> +					reg = <0>;
> +					remote-endpoint = <&vopb_out_edp>;
> +				};
> +				edp_in_vopl: endpoint@1 {
> +					reg = <1>;
> +					remote-endpoint = <&vopl_out_edp>;
> +				};
> +			};
> +
> +			edp_out: port@1 {
> +				reg = <1>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				edp_out_panel: endpoint {
> +					reg = <0>;
> +					remote-endpoint = <&panel_in_edp>
> +				};
> +			};
> +		};
> +	};
> +
> diff --git a/drivers/gpu/drm/rockchip/Kconfig
> b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..c2ba945 100644
> --- a/drivers/gpu/drm/rockchip/Kconfig
> +++ b/drivers/gpu/drm/rockchip/Kconfig
> @@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
>  	  for the Synopsys DesignWare HDMI driver. If you want to
>  	  enable HDMI on RK3288 based SoC, you should selet this
>  	  option.
> +
> +config ROCKCHIP_ANALOGIX_DP
> +        tristate "Rockchip specific extensions for Analogix DP driver"
> +        depends on DRM_ROCKCHIP
> +        select DRM_ANALOGIX_DP
> +        help
> +	  This selects support for Rockchip SoC specific extensions
> +	  for the Analogix Core DP driver. If you want to enable DP
> +	  on RK3288 based SoC, you should selet this option.
> diff --git a/drivers/gpu/drm/rockchip/Makefile
> b/drivers/gpu/drm/rockchip/Makefile index f3d8a19..8ad01fb 100644
> --- a/drivers/gpu/drm/rockchip/Makefile
> +++ b/drivers/gpu/drm/rockchip/Makefile
> @@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
> rockchip_drm_fbdev.o \ rockchip_drm_gem.o
> 
>  obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
> +obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
> 
>  obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c new file mode 100644
> index 0000000..cebff9e
> --- /dev/null
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -0,0 +1,389 @@
> +/*
> + * Rockchip SoC DP (Display Port) interface driver.
> + *
> + * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
> + * Author: Andy Yan <andy.yan@rock-chips.com>
> + *         Yakir Yang <ykk@rock-chips.com>
> + *         Jeff Chen <jeff.chen@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +#include <drm/drmP.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_dp_helper.h>
> +
> +#include <linux/component.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_graph.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/clk.h>
> +
> +#include <video/of_videomode.h>
> +#include <video/videomode.h>
> +
> +#include <drm/bridge/analogix_dp.h>
> +
> +#include "rockchip_drm_drv.h"
> +#include "rockchip_drm_vop.h"
> +
> +#define encoder_to_dp(c) \
> +		container_of(c, struct rockchip_dp_device, encoder)
> +
> +#define plat_data_to_dp(pd) \
> +		container_of(pd, struct rockchip_dp_device, plat_data)
> +
> +/* dp grf register offset */
> +#define GRF_GPIO7B_IOMUX                        0x0070
> +#define GPIO7B3_SEL_MASK                        (0x03 << 6)
> +#define GPIO7B3_SEL_EDP_HOTPLUG                 BIT(7)

please remove, see comment near pre_init


> +
> +#define GRF_SOC_CON6                            0x025c
> +#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
> +#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
> +#define GRF_EDP_SEL_VOP_BIG                     0
> +
> +struct rockchip_dp_device {
> +	struct drm_device        *drm_dev;
> +	struct device            *dev;
> +	struct drm_encoder       encoder;
> +	struct drm_display_mode  mode;
> +
> +	struct clk               *pclk;
> +	struct regmap            *grf;
> +	struct reset_control     *rst;
> +
> +	struct analogix_dp_plat_data plat_data;
> +};
> +
> +static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
> +{
> +	u32 val;
> +	int ret;
> +
> +	val = GPIO7B3_SEL_EDP_HOTPLUG | (GPIO7B3_SEL_MASK << 16);
> +	ret = regmap_write(dp->grf, GRF_GPIO7B_IOMUX, val);

this is just a regular pinctrl setting. Please don't write onto other 
components registers. Use a regular pinctrl setting in the devicetree instead.


> +	if (ret != 0) {
> +		dev_err(dp->dev, "Could not config GRF edp hpd: %d\n", ret);
> +		return ret;
> +	}
> +
> +	reset_control_assert(dp->rst);
> +	usleep_range(10, 20);
> +	reset_control_deassert(dp->rst);
> +
> +	return 0;
> +}


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
@ 2015-09-01 21:00     ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 21:00 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Yakir,

Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
> Rockchip have three clocks for dp controller, we leave pclk_edp
> to analogix_dp driver control, and keep the sclk_edp_24m and
> sclk_edp in platform driver.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Remove some deprecated DT properties in rockchip dp document.
> 
> Changes in v3:
> - Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
>   dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
>   core driver which name to "dp", and leave "pclk_edp" to rockchip dp
> platform driver which name to "pclk".
> - Take Heiko suggest, add devicetree binding document.
> - Take Heiko suggest, remove "rockchip,panel" DT property, take use of
> remote point to get panel node.
> - Add the new function point analogix_dp_platdata.get_modes init.
> 
> Changes in v2:
> - Take Heiko suggest, get panel node with remote-endpoint method,
>   and create devicetree binding for driver.
> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>   leave those clock to rockchip dp phy driver.
> 
>  .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
>  drivers/gpu/drm/rockchip/Kconfig                   |   9 +
>  drivers/gpu/drm/rockchip/Makefile                  |   1 +
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389
> +++++++++++++++++++++ 4 files changed, 473 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt create
> mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> 
> diff --git
> a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt new file
> mode 100644
> index 0000000..502483e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> @@ -0,0 +1,74 @@
> +Rockchip RK3288 specific extensions to the Analogix Display Port
> +================================
> +
> +Required properties:
> +- compatible: "rockchip,rk3288-edp";
> +
> +- reg: physical base address of the controller and length
> +
> +- clocks: from common clock binding: handle to dp clock.
> +	  of memory mapped region.
> +
> +- clock-names: from common clock binding:
> +	       Required elements: "dp" "pclk"
> +
> +- resets: Must contain an entry for each entry in reset-names.
> +	  See ../reset/reset.txt for details.
> +
> +- reset-names: Must include the name "dp"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +
> +- ports: contain a port node with endpoint definitions as defined in
> +  Documentation/devicetree/bindings/media/video-interfaces.txt.
> +
> +
> +For the below properties, please refer to Analogix DP binding document:
> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> +- phys (required)
> +- phy-names (required)
> +- hpd-gpios (optional)
> +---------------------------------------------------------------------------
> ---- +
> +Example:
> +	dp-controller: dp at ff970000 {
> +		compatible = "rockchip,rk3288-dp";
> +		reg = <0xff970000 0x4000>;
> +		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
> +		clock-names = "dp", "pclk";
> +		phys = <&dp_phy>;
> +		phy-names = "dp";
> +
> +		rockchip,grf = <&grf>;
> +		resets = <&cru 111>;
> +		reset-names = "dp";
> +
> +		status = "disabled";
> +
> +		ports {

#address-cells = <1>;
#size-cells = <0>;

> +			edp_in: port {

edp_in: port at 0
	reg = <0>;

> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				edp_in_vopb: endpoint at 0 {
> +					reg = <0>;
> +					remote-endpoint = <&vopb_out_edp>;
> +				};
> +				edp_in_vopl: endpoint at 1 {
> +					reg = <1>;
> +					remote-endpoint = <&vopl_out_edp>;
> +				};
> +			};
> +
> +			edp_out: port at 1 {
> +				reg = <1>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				edp_out_panel: endpoint {
> +					reg = <0>;
> +					remote-endpoint = <&panel_in_edp>
> +				};
> +			};
> +		};
> +	};
> +
> diff --git a/drivers/gpu/drm/rockchip/Kconfig
> b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..c2ba945 100644
> --- a/drivers/gpu/drm/rockchip/Kconfig
> +++ b/drivers/gpu/drm/rockchip/Kconfig
> @@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
>  	  for the Synopsys DesignWare HDMI driver. If you want to
>  	  enable HDMI on RK3288 based SoC, you should selet this
>  	  option.
> +
> +config ROCKCHIP_ANALOGIX_DP
> +        tristate "Rockchip specific extensions for Analogix DP driver"
> +        depends on DRM_ROCKCHIP
> +        select DRM_ANALOGIX_DP
> +        help
> +	  This selects support for Rockchip SoC specific extensions
> +	  for the Analogix Core DP driver. If you want to enable DP
> +	  on RK3288 based SoC, you should selet this option.
> diff --git a/drivers/gpu/drm/rockchip/Makefile
> b/drivers/gpu/drm/rockchip/Makefile index f3d8a19..8ad01fb 100644
> --- a/drivers/gpu/drm/rockchip/Makefile
> +++ b/drivers/gpu/drm/rockchip/Makefile
> @@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
> rockchip_drm_fbdev.o \ rockchip_drm_gem.o
> 
>  obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
> +obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
> 
>  obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c new file mode 100644
> index 0000000..cebff9e
> --- /dev/null
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -0,0 +1,389 @@
> +/*
> + * Rockchip SoC DP (Display Port) interface driver.
> + *
> + * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
> + * Author: Andy Yan <andy.yan@rock-chips.com>
> + *         Yakir Yang <ykk@rock-chips.com>
> + *         Jeff Chen <jeff.chen@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +#include <drm/drmP.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_dp_helper.h>
> +
> +#include <linux/component.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_graph.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/clk.h>
> +
> +#include <video/of_videomode.h>
> +#include <video/videomode.h>
> +
> +#include <drm/bridge/analogix_dp.h>
> +
> +#include "rockchip_drm_drv.h"
> +#include "rockchip_drm_vop.h"
> +
> +#define encoder_to_dp(c) \
> +		container_of(c, struct rockchip_dp_device, encoder)
> +
> +#define plat_data_to_dp(pd) \
> +		container_of(pd, struct rockchip_dp_device, plat_data)
> +
> +/* dp grf register offset */
> +#define GRF_GPIO7B_IOMUX                        0x0070
> +#define GPIO7B3_SEL_MASK                        (0x03 << 6)
> +#define GPIO7B3_SEL_EDP_HOTPLUG                 BIT(7)

please remove, see comment near pre_init


> +
> +#define GRF_SOC_CON6                            0x025c
> +#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
> +#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
> +#define GRF_EDP_SEL_VOP_BIG                     0
> +
> +struct rockchip_dp_device {
> +	struct drm_device        *drm_dev;
> +	struct device            *dev;
> +	struct drm_encoder       encoder;
> +	struct drm_display_mode  mode;
> +
> +	struct clk               *pclk;
> +	struct regmap            *grf;
> +	struct reset_control     *rst;
> +
> +	struct analogix_dp_plat_data plat_data;
> +};
> +
> +static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
> +{
> +	u32 val;
> +	int ret;
> +
> +	val = GPIO7B3_SEL_EDP_HOTPLUG | (GPIO7B3_SEL_MASK << 16);
> +	ret = regmap_write(dp->grf, GRF_GPIO7B_IOMUX, val);

this is just a regular pinctrl setting. Please don't write onto other 
components registers. Use a regular pinctrl setting in the devicetree instead.


> +	if (ret != 0) {
> +		dev_err(dp->dev, "Could not config GRF edp hpd: %d\n", ret);
> +		return ret;
> +	}
> +
> +	reset_control_assert(dp->rst);
> +	usleep_range(10, 20);
> +	reset_control_deassert(dp->rst);
> +
> +	return 0;
> +}


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
@ 2015-09-01 21:00     ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 21:00 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel, Mark Yao

Hi Yakir,

Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
> From: Mark Yao <yzq@rock-chips.com>
> 
> Add bpc and color mode setting in rockchip_drm_vop driver, so
> connector could try to use the edid drm_display_info to config
> vop output mode.
> 
> Signed-off-by: Mark Yao <yzq@rock-chips.com>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 46
> +++++++++++++++++++------ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |
>  2 +-
>  drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 33 ++++++++++++++++--
>  4 files changed, 68 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index cebff9e..efea045
> 100644
> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -11,11 +11,6 @@
>   * Free Software Foundation; either version 2 of the License, or (at your
>   * option) any later version.
>   */
> -#include <drm/drmP.h>
> -#include <drm/drm_crtc_helper.h>
> -#include <drm/drm_panel.h>
> -#include <drm/drm_of.h>
> -#include <drm/drm_dp_helper.h>
> 
>  #include <linux/component.h>
>  #include <linux/mfd/syscon.h>
> @@ -27,6 +22,13 @@
>  #include <video/of_videomode.h>
>  #include <video/videomode.h>
> 
> +#include <drm/drmP.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_dp_helper.h>
> +
>  #include <drm/bridge/analogix_dp.h>
> 
>  #include "rockchip_drm_drv.h"
> @@ -125,20 +127,44 @@ static void rockchip_dp_drm_encoder_mode_set(struct
> drm_encoder *encoder, /* do nothing */
>  }
> 
> +static drm_connector *rockchip_dp_get_connector(struct rockchip_dp_device

missing a "struct" -> static struct drm_connector


> *dp) +{
> +	struct drm_connector *connector;
> +	struct drm_device *drm_dev = dp->drm_dev;
> +
> +	drm_for_each_connector(connector, drm_dev) {
> +		if (connector->encoder != &dp->encoder)
> +			return connector;
> +	}
> +
> +	return NULL;
> +}
> +
>  static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
>  {
>  	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
> +	struct drm_connector *connector;
> +	int ret = 0;
>  	u32 val;
> -	int ret;
> 
> -	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
> -					    DRM_MODE_CONNECTOR_eDP,
> -					    ROCKCHIP_OUT_MODE_AAAA);
> -	if (ret < 0) {
> +	connector = rockchip_dp_get_connector(dp);
> +	if (!connector) {
> +		DRM_ERROR("Failed to get connector by encoder[%p]\n", encoder);
> +		return;
> +	}
> +
> +	if (connector->display_info.color_formats | DRM_COLOR_FORMAT_RGB444)
> +		ret = rockchip_drm_crtc_mode_config(
> +			encoder->crtc, DRM_MODE_CONNECTOR_eDP,
> +			connector->display_info.bpc, DRM_COLOR_FORMAT_RGB444);
> +	if (!ret) {
>  		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
>  		return;
>  	}
> 
> +	connector->display_info.bpc = ret;
> +	connector->display_info.color_formats = DRM_COLOR_FORMAT_RGB444;
> +
>  	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
>  	if (ret < 0)
>  		return;
> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 80d6fc8..428a3c1 100644
> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> @@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct
> drm_encoder *encoder) static void dw_hdmi_rockchip_encoder_prepare(struct
> drm_encoder *encoder) {
>  	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
> -				      ROCKCHIP_OUT_MODE_AAAA);
> +				      10, DRM_COLOR_FORMAT_RGB444);
>  }
> 
>  static struct drm_encoder_helper_funcs
> dw_hdmi_rockchip_encoder_helper_funcs = { diff --git
> a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index dc4e5f0..ef1d7fb 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> @@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device
> *dev, int pipe); int rockchip_drm_encoder_get_mux_id(struct device_node
> *node,
>  				    struct drm_encoder *encoder);
>  int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int
> connector_type, -				  int out_mode);
> +				  int bpc, int color);
>  int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
>  				   struct device *dev);
>  void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> @@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
> {
> 
>  int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
>  				  int connector_type,
> -				  int out_mode)
> +				  int bpc, int color)
>  {
>  	struct vop *vop = to_vop(crtc);
> -
>  	vop->connector_type = connector_type;
>  	vop->connector_out_mode = out_mode;

this line should probably go away, as the source var "out_mode" does not exist 
in the function params any more, making the compilation break, and is set 
below anyway.


Heiko

> 
> -	return 0;
> +	/*
> +	 * RK3288 vop only support RGB Color output.
> +	 */
> +	if (color != DRM_COLOR_FORMAT_RGB444) {
> +		DRM_ERROR("Only support output RGB444, not support%d\n",
> +			  color);
> +		return -EINVAL;
> +	}
> +
> +	/*
> +	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
> +	 * bpc, 5 or 6?
> +	 *
> +	 */
> +	if (bpc >= 10) {
> +		bpc = 10;
> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
> +	} else if (bpc >= 8) {
> +		bpc = 8;
> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
> +	} else if (bpc >= 6) {
> +		bpc = 6;
> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
> +	} else {
> +		DRM_ERROR("unsupport bpc %d\n", bpc);
> +		return -EINVAL;
> +	}
> +
> +	return bpc;
>  }
>  EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);


^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
@ 2015-09-01 21:00     ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 21:00 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King,
	djkurtz-F7+t8E8rja9Wk0Htik3J/w, dianders-F7+t8E8rja9Wk0Htik3J/w,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt-sgV2jX0FEOL9JmXXK+q4OQ,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel

Hi Yakir,

Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
> From: Mark Yao <yzq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> 
> Add bpc and color mode setting in rockchip_drm_vop driver, so
> connector could try to use the edid drm_display_info to config
> vop output mode.
> 
> Signed-off-by: Mark Yao <yzq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 46
> +++++++++++++++++++------ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |
>  2 +-
>  drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 33 ++++++++++++++++--
>  4 files changed, 68 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index cebff9e..efea045
> 100644
> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -11,11 +11,6 @@
>   * Free Software Foundation; either version 2 of the License, or (at your
>   * option) any later version.
>   */
> -#include <drm/drmP.h>
> -#include <drm/drm_crtc_helper.h>
> -#include <drm/drm_panel.h>
> -#include <drm/drm_of.h>
> -#include <drm/drm_dp_helper.h>
> 
>  #include <linux/component.h>
>  #include <linux/mfd/syscon.h>
> @@ -27,6 +22,13 @@
>  #include <video/of_videomode.h>
>  #include <video/videomode.h>
> 
> +#include <drm/drmP.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_dp_helper.h>
> +
>  #include <drm/bridge/analogix_dp.h>
> 
>  #include "rockchip_drm_drv.h"
> @@ -125,20 +127,44 @@ static void rockchip_dp_drm_encoder_mode_set(struct
> drm_encoder *encoder, /* do nothing */
>  }
> 
> +static drm_connector *rockchip_dp_get_connector(struct rockchip_dp_device

missing a "struct" -> static struct drm_connector


> *dp) +{
> +	struct drm_connector *connector;
> +	struct drm_device *drm_dev = dp->drm_dev;
> +
> +	drm_for_each_connector(connector, drm_dev) {
> +		if (connector->encoder != &dp->encoder)
> +			return connector;
> +	}
> +
> +	return NULL;
> +}
> +
>  static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
>  {
>  	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
> +	struct drm_connector *connector;
> +	int ret = 0;
>  	u32 val;
> -	int ret;
> 
> -	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
> -					    DRM_MODE_CONNECTOR_eDP,
> -					    ROCKCHIP_OUT_MODE_AAAA);
> -	if (ret < 0) {
> +	connector = rockchip_dp_get_connector(dp);
> +	if (!connector) {
> +		DRM_ERROR("Failed to get connector by encoder[%p]\n", encoder);
> +		return;
> +	}
> +
> +	if (connector->display_info.color_formats | DRM_COLOR_FORMAT_RGB444)
> +		ret = rockchip_drm_crtc_mode_config(
> +			encoder->crtc, DRM_MODE_CONNECTOR_eDP,
> +			connector->display_info.bpc, DRM_COLOR_FORMAT_RGB444);
> +	if (!ret) {
>  		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
>  		return;
>  	}
> 
> +	connector->display_info.bpc = ret;
> +	connector->display_info.color_formats = DRM_COLOR_FORMAT_RGB444;
> +
>  	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
>  	if (ret < 0)
>  		return;
> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 80d6fc8..428a3c1 100644
> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> @@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct
> drm_encoder *encoder) static void dw_hdmi_rockchip_encoder_prepare(struct
> drm_encoder *encoder) {
>  	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
> -				      ROCKCHIP_OUT_MODE_AAAA);
> +				      10, DRM_COLOR_FORMAT_RGB444);
>  }
> 
>  static struct drm_encoder_helper_funcs
> dw_hdmi_rockchip_encoder_helper_funcs = { diff --git
> a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index dc4e5f0..ef1d7fb 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> @@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device
> *dev, int pipe); int rockchip_drm_encoder_get_mux_id(struct device_node
> *node,
>  				    struct drm_encoder *encoder);
>  int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int
> connector_type, -				  int out_mode);
> +				  int bpc, int color);
>  int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
>  				   struct device *dev);
>  void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> @@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
> {
> 
>  int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
>  				  int connector_type,
> -				  int out_mode)
> +				  int bpc, int color)
>  {
>  	struct vop *vop = to_vop(crtc);
> -
>  	vop->connector_type = connector_type;
>  	vop->connector_out_mode = out_mode;

this line should probably go away, as the source var "out_mode" does not exist 
in the function params any more, making the compilation break, and is set 
below anyway.


Heiko

> 
> -	return 0;
> +	/*
> +	 * RK3288 vop only support RGB Color output.
> +	 */
> +	if (color != DRM_COLOR_FORMAT_RGB444) {
> +		DRM_ERROR("Only support output RGB444, not support%d\n",
> +			  color);
> +		return -EINVAL;
> +	}
> +
> +	/*
> +	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
> +	 * bpc, 5 or 6?
> +	 *
> +	 */
> +	if (bpc >= 10) {
> +		bpc = 10;
> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
> +	} else if (bpc >= 8) {
> +		bpc = 8;
> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
> +	} else if (bpc >= 6) {
> +		bpc = 6;
> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
> +	} else {
> +		DRM_ERROR("unsupport bpc %d\n", bpc);
> +		return -EINVAL;
> +	}
> +
> +	return bpc;
>  }
>  EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
@ 2015-09-01 21:00     ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 21:00 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Yakir,

Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
> From: Mark Yao <yzq@rock-chips.com>
> 
> Add bpc and color mode setting in rockchip_drm_vop driver, so
> connector could try to use the edid drm_display_info to config
> vop output mode.
> 
> Signed-off-by: Mark Yao <yzq@rock-chips.com>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 46
> +++++++++++++++++++------ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |
>  2 +-
>  drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 33 ++++++++++++++++--
>  4 files changed, 68 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index cebff9e..efea045
> 100644
> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -11,11 +11,6 @@
>   * Free Software Foundation; either version 2 of the License, or (at your
>   * option) any later version.
>   */
> -#include <drm/drmP.h>
> -#include <drm/drm_crtc_helper.h>
> -#include <drm/drm_panel.h>
> -#include <drm/drm_of.h>
> -#include <drm/drm_dp_helper.h>
> 
>  #include <linux/component.h>
>  #include <linux/mfd/syscon.h>
> @@ -27,6 +22,13 @@
>  #include <video/of_videomode.h>
>  #include <video/videomode.h>
> 
> +#include <drm/drmP.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_dp_helper.h>
> +
>  #include <drm/bridge/analogix_dp.h>
> 
>  #include "rockchip_drm_drv.h"
> @@ -125,20 +127,44 @@ static void rockchip_dp_drm_encoder_mode_set(struct
> drm_encoder *encoder, /* do nothing */
>  }
> 
> +static drm_connector *rockchip_dp_get_connector(struct rockchip_dp_device

missing a "struct" -> static struct drm_connector


> *dp) +{
> +	struct drm_connector *connector;
> +	struct drm_device *drm_dev = dp->drm_dev;
> +
> +	drm_for_each_connector(connector, drm_dev) {
> +		if (connector->encoder != &dp->encoder)
> +			return connector;
> +	}
> +
> +	return NULL;
> +}
> +
>  static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
>  {
>  	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
> +	struct drm_connector *connector;
> +	int ret = 0;
>  	u32 val;
> -	int ret;
> 
> -	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
> -					    DRM_MODE_CONNECTOR_eDP,
> -					    ROCKCHIP_OUT_MODE_AAAA);
> -	if (ret < 0) {
> +	connector = rockchip_dp_get_connector(dp);
> +	if (!connector) {
> +		DRM_ERROR("Failed to get connector by encoder[%p]\n", encoder);
> +		return;
> +	}
> +
> +	if (connector->display_info.color_formats | DRM_COLOR_FORMAT_RGB444)
> +		ret = rockchip_drm_crtc_mode_config(
> +			encoder->crtc, DRM_MODE_CONNECTOR_eDP,
> +			connector->display_info.bpc, DRM_COLOR_FORMAT_RGB444);
> +	if (!ret) {
>  		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
>  		return;
>  	}
> 
> +	connector->display_info.bpc = ret;
> +	connector->display_info.color_formats = DRM_COLOR_FORMAT_RGB444;
> +
>  	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
>  	if (ret < 0)
>  		return;
> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 80d6fc8..428a3c1 100644
> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> @@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct
> drm_encoder *encoder) static void dw_hdmi_rockchip_encoder_prepare(struct
> drm_encoder *encoder) {
>  	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
> -				      ROCKCHIP_OUT_MODE_AAAA);
> +				      10, DRM_COLOR_FORMAT_RGB444);
>  }
> 
>  static struct drm_encoder_helper_funcs
> dw_hdmi_rockchip_encoder_helper_funcs = { diff --git
> a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index dc4e5f0..ef1d7fb 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> @@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device
> *dev, int pipe); int rockchip_drm_encoder_get_mux_id(struct device_node
> *node,
>  				    struct drm_encoder *encoder);
>  int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int
> connector_type, -				  int out_mode);
> +				  int bpc, int color);
>  int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
>  				   struct device *dev);
>  void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> @@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
> {
> 
>  int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
>  				  int connector_type,
> -				  int out_mode)
> +				  int bpc, int color)
>  {
>  	struct vop *vop = to_vop(crtc);
> -
>  	vop->connector_type = connector_type;
>  	vop->connector_out_mode = out_mode;

this line should probably go away, as the source var "out_mode" does not exist 
in the function params any more, making the compilation break, and is set 
below anyway.


Heiko

> 
> -	return 0;
> +	/*
> +	 * RK3288 vop only support RGB Color output.
> +	 */
> +	if (color != DRM_COLOR_FORMAT_RGB444) {
> +		DRM_ERROR("Only support output RGB444, not support%d\n",
> +			  color);
> +		return -EINVAL;
> +	}
> +
> +	/*
> +	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
> +	 * bpc, 5 or 6?
> +	 *
> +	 */
> +	if (bpc >= 10) {
> +		bpc = 10;
> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
> +	} else if (bpc >= 8) {
> +		bpc = 8;
> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
> +	} else if (bpc >= 6) {
> +		bpc = 6;
> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
> +	} else {
> +		DRM_ERROR("unsupport bpc %d\n", bpc);
> +		return -EINVAL;
> +	}
> +
> +	return bpc;
>  }
>  EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver
@ 2015-09-01 21:47   ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 21:47 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Hi Yakir,

Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>    The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM ;)
> 
> Beyond that, there are three light registers setting differents bewteen
> exynos and rk3288.
> 1. RK3288 have five special pll resigters which not indicata in exynos
>    dp controller.
> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>    between rk3288 and exynos.
> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>    register).
> 
> I have verified this series on two kinds of rockchip platform board, one
> is rk3288 sdk board which connect with a 2K display port monitor, the other
> is google jerry chromebook which connect with a eDP screen "cnm,n116bgeea2",
> both of them works rightlly.

it looks like during the rebase something did go wrong and I found some issues 
I mentioned in the replies to individual patches.

I did prepare a branch based on mainline [0] with both the old and the new edp 
driver - rk3288_veyron_defconfig build both drivers into the image.

While the old driver still works, I wasn't able to make the new one work yet 
... the drm core does find the connector, but not that anything is connected 
to it. I'll try to dig deeper tomorrow, but maybe you'll see anything 
interesting before then.


Heiko

[0] https://github.com/mmind/linux-rockchip/tree/tmp/edp-with-veyron


^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver
@ 2015-09-01 21:47   ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 21:47 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Krzysztof Kozlowski, David Airlie,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Andrzej Hajda,
	Gustavo Padovan, architt-sgV2jX0FEOL9JmXXK+q4OQ,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Russell King, Thierry Reding,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Inki Dae, joe-6d6DIl74uiNBDgjK7y7TUQ, Rob Herring,
	dianders-F7+t8E8rja9Wk0Htik3J/w,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Yao,
	Jingoo Han, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kyungmin

Hi Yakir,

Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>    The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM ;)
> 
> Beyond that, there are three light registers setting differents bewteen
> exynos and rk3288.
> 1. RK3288 have five special pll resigters which not indicata in exynos
>    dp controller.
> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>    between rk3288 and exynos.
> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>    register).
> 
> I have verified this series on two kinds of rockchip platform board, one
> is rk3288 sdk board which connect with a 2K display port monitor, the other
> is google jerry chromebook which connect with a eDP screen "cnm,n116bgeea2",
> both of them works rightlly.

it looks like during the rebase something did go wrong and I found some issues 
I mentioned in the replies to individual patches.

I did prepare a branch based on mainline [0] with both the old and the new edp 
driver - rk3288_veyron_defconfig build both drivers into the image.

While the old driver still works, I wasn't able to make the new one work yet 
... the drm core does find the connector, but not that anything is connected 
to it. I'll try to dig deeper tomorrow, but maybe you'll see anything 
interesting before then.


Heiko

[0] https://github.com/mmind/linux-rockchip/tree/tmp/edp-with-veyron

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 0/16] Add Analogix Core Display Port Driver
@ 2015-09-01 21:47   ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-01 21:47 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Yakir,

Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>    The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM ;)
> 
> Beyond that, there are three light registers setting differents bewteen
> exynos and rk3288.
> 1. RK3288 have five special pll resigters which not indicata in exynos
>    dp controller.
> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>    between rk3288 and exynos.
> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>    register).
> 
> I have verified this series on two kinds of rockchip platform board, one
> is rk3288 sdk board which connect with a 2K display port monitor, the other
> is google jerry chromebook which connect with a eDP screen "cnm,n116bgeea2",
> both of them works rightlly.

it looks like during the rebase something did go wrong and I found some issues 
I mentioned in the replies to individual patches.

I did prepare a branch based on mainline [0] with both the old and the new edp 
driver - rk3288_veyron_defconfig build both drivers into the image.

While the old driver still works, I wasn't able to make the new one work yet 
... the drm core does find the connector, but not that anything is connected 
to it. I'll try to dig deeper tomorrow, but maybe you'll see anything 
interesting before then.


Heiko

[0] https://github.com/mmind/linux-rockchip/tree/tmp/edp-with-veyron

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
  2015-09-01 16:51     ` Heiko Stuebner
@ 2015-09-02  1:02       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02  1:02 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel, s.infradead.org

Hi Heiko,

在 09/02/2015 12:51 AM, Heiko Stuebner 写道:
> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you want DP works rightly on rockchip platform,
>> then you should select both of them.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Kishon suggest, add commit message, and remove the redundant
>>    rockchip_dp_phy_init() function, move those code to probe() method.
>>    And remove driver .owner number.
>>
>> Changes in v3:
>> - Take Heiko suggest, add rockchip dp phy driver,
>>    collect the phy clocks and power control.
>>
>> Changes in v2: None
>>
>>   .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++
>>   drivers/phy/Kconfig                                |   7 +
>>   drivers/phy/Makefile                               |   1 +
>>   drivers/phy/phy-rockchip-dp.c                      | 166
>> +++++++++++++++++++++ 4 files changed, 200 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt create mode
>> 100644 drivers/phy/phy-rockchip-dp.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt new file mode
>> 100644
>> index 0000000..5de1088
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> @@ -0,0 +1,26 @@
>> +Rockchip Soc Seroes Display Port PHY
>> +------------------------------------
>> +
>> +Required properties:
>> +- compatible : should be one of the following supported values:
>> +	 - "rockchip.rk3288-dp-phy"
>> +
>> +- reg : a list of registers used by phy driver
> nodes do not necessarily need to have a regs property. You can do all
> operations via the grf syscon already.

Oh, yes, the dp phy power register is belong to GRF filed, thanks.

>
>> +- clocks: from common clock binding: handle to dp clock.
>> +	of memory mapped region.
>> +- clock-names: from common clock binding:
>> +	Required elements: "sclk_dp" "sclk_dp_24m"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>> +- #phy-cells : from the generic PHY bindings, must be 0;
>> +
>> +Example:
>> +
>> +edp_phy: phy@ff770274 {
> edp_phy: edp-phy {

Done,

>
>
>> +	compatilble = "rockchip,rk3288-dp-phy";
>> +	reg = <0xff770274 4>;
> no regs property

Done

>> +	rockchip,grf = <&grf>;
>> +	clocks = <&cru SCLK_EDP_24M>;
>> +	clock-names = "24m";
>> +	#phy-cells = <0>;
>> +}
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 47da573..8f2bc4f 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>>   	help
>>   	  Enable this to support the Rockchip USB 2.0 PHY.
>>
>> +config PHY_ROCKCHIP_DP
>> +	tristate "Rockchip Display Port PHY Driver"
>> +	depends on ARCH_ROCKCHIP && OF
>> +	select GENERIC_PHY
>> +	help
>> +	  Enable this to support the Rockchip Display Port PHY.
>> +
>>   config PHY_ST_SPEAR1310_MIPHY
>>   	tristate "ST SPEAR1310-MIPHY driver"
>>   	select GENERIC_PHY
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a5b18c1..e281f35 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+=
>> phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>> +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
>>   obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
>> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
>> new file mode 100644
>> index 0000000..e9a726e
>> --- /dev/null
>> +++ b/drivers/phy/phy-rockchip-dp.c
>> @@ -0,0 +1,166 @@
>> +/*
>> + * Rockchip DP PHY driver
>> + *
>> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
>> + * Author: Yakir Yang <ykk@@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define GRF_SOC_CON12                   0x0274
>> +#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
>> +
>> +#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
>> +#define DP_PHY_SIDDQ_ON                 0
>> +#define DP_PHY_SIDDQ_OFF                BIT(5)
>> +
>> +struct rockchip_dp_phy {
>> +	struct device  *dev;
>> +	struct regmap  *grf;
>> +	void __iomem   *regs;
>> +	struct clk     *phy_24m;
>> +};
>> +
>> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
>> +{
>> +	int ret = 0;
>> +
>> +	ret = clk_set_rate(dp->phy_24m, 24000000);
>> +	if (ret < 0) {
>> +		dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	ret = clk_prepare_enable(dp->phy_24m);
>> +	if (ret < 0) {
>> +		dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
>> +{
>> +	clk_disable_unprepare(dp->phy_24m);
>> +
>> +	return 0;
>> +}
>> +
>> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
>> +{
>> +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
>> +
>> +	if (enable) {
>> +		rockchip_dp_phy_clk_enable(dp);
>> +		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
>> +	} else {
>> +		rockchip_dp_phy_clk_disable(dp);
>> +		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static int rockchip_dp_phy_power_on(struct phy *phy)
>> +{
>> +	return rockchip_set_phy_state(phy, true);
>> +}
>> +
>> +static int rockchip_dp_phy_power_off(struct phy *phy)
>> +{
>> +	return rockchip_set_phy_state(phy, false);
>> +}
>> +
>> +static struct phy_ops rockchip_dp_phy_ops = {
> static const struct ...
>
> see 4a9e5ca1a54a ("phy: Constify struct phy_ops variables")

Done, thanks

>
>> +	.power_on	= rockchip_dp_phy_power_on,
>> +	.power_off	= rockchip_dp_phy_power_off,
>> +	.owner		= THIS_MODULE,
>> +};
>> +
>> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	struct device_node *np = dev->of_node;
>> +	struct phy_provider *phy_provider;
>> +	struct rockchip_dp_phy *dp;
>> +	struct resource *res;
>> +	struct phy *phy;
>> +	int ret;
>> +
> I guess this could profit from a
>
> if (!np)
> 	return -ENODEV;

Hmm... so we are avoiding the no of_device case,

Done,

>> +	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
>> +	if (IS_ERR(dp))
>> +		return -ENOMEM;
>> +
>> +	dp->dev = dev;
>> +
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	dp->regs = devm_ioremap_resource(dev, res);
>> +	if (IS_ERR(dp->regs))
>> +		return PTR_ERR(dp->regs);
>> +
>> +	dp->phy_24m = devm_clk_get(dev, "24m");
>> +	if (IS_ERR(dp->phy_24m)) {
>> +		dev_err(dev, "cannot get clock 24m\n");
>> +		return PTR_ERR(dp->phy_24m);
>> +	}
>> +
>> +	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
>> +	if (IS_ERR(dp->grf)) {
>> +		dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
>> +		return PTR_ERR(dp->grf);
>> +	}
>> +
>> +	ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> +			   GRF_EDP_REF_CLK_SEL_INTER |
>> +			   (GRF_EDP_REF_CLK_SEL_INTER << 16));
>> +	if (ret != 0) {
>> +		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	phy = devm(dev, NULL, &rockchip_dp_phy_ops, NULL);
> hmm, where did you find 4 params for devm_phy_create? Shouldn't this be
>
> 	phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
>
> instead - and also include the phy dt-node as 2nd parameter?

Oh,  :-(=

I used to test the driver on chrome-3.14 branch, I always back the drm 
head file,
so there would be no drm conflict. But phy driver is missed, the 4 
params is come
from kernel-3.14.

Thanks for your redmind,
- Yakir

>
> Heiko
>
>> +	if (IS_ERR(phy)) {
>> +		dev_err(dev, "failed to create phy\n");
>> +		return PTR_ERR(phy);
>> +	}
>> +	phy_set_drvdata(phy, dp);
>> +
>> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> +
>> +	return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
>> +	{ .compatible = "rockchip,rk3288-dp-phy" },
>> +	{}
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
>> +
>> +static struct platform_driver rockchip_dp_phy_driver = {
>> +	.probe		= rockchip_dp_phy_probe,
>> +	.driver		= {
>> +		.name	= "rockchip-dp-phy",
>> +		.of_match_table = rockchip_dp_phy_dt_ids,
>> +	},
>> +};
>> +
>> +module_platform_driver(rockchip_dp_phy_driver);
>> +
>> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
>> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
>> +MODULE_LICENSE("GPL v2");
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-02  1:02       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02  1:02 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Krzysztof Kozlowski, s.infradead.org-SAd4IJPOV+0bIzgrwE/FjQ,
	David Airlie, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	Andrzej Hajda, Gustavo Padovan, architt-sgV2jX0FEOL9JmXXK+q4OQ,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Russell King, Thierry Reding,
	linux-arm-kernel-ggaV8SP1K3vehVd/f8ENTg,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Inki Dae, joe-6d6DIl74uiNBDgjK7y7TUQ, Rob Herring,
	dianders-F7+t8E8rja9Wk0Htik3J/w, Mark Yao, Jingoo Han,
	linux-kernel-u79uwXL29Tb/PtFMR13I2A

Hi Heiko,

在 09/02/2015 12:51 AM, Heiko Stuebner 写道:
> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you want DP works rightly on rockchip platform,
>> then you should select both of them.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Kishon suggest, add commit message, and remove the redundant
>>    rockchip_dp_phy_init() function, move those code to probe() method.
>>    And remove driver .owner number.
>>
>> Changes in v3:
>> - Take Heiko suggest, add rockchip dp phy driver,
>>    collect the phy clocks and power control.
>>
>> Changes in v2: None
>>
>>   .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++
>>   drivers/phy/Kconfig                                |   7 +
>>   drivers/phy/Makefile                               |   1 +
>>   drivers/phy/phy-rockchip-dp.c                      | 166
>> +++++++++++++++++++++ 4 files changed, 200 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt create mode
>> 100644 drivers/phy/phy-rockchip-dp.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt new file mode
>> 100644
>> index 0000000..5de1088
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> @@ -0,0 +1,26 @@
>> +Rockchip Soc Seroes Display Port PHY
>> +------------------------------------
>> +
>> +Required properties:
>> +- compatible : should be one of the following supported values:
>> +	 - "rockchip.rk3288-dp-phy"
>> +
>> +- reg : a list of registers used by phy driver
> nodes do not necessarily need to have a regs property. You can do all
> operations via the grf syscon already.

Oh, yes, the dp phy power register is belong to GRF filed, thanks.

>
>> +- clocks: from common clock binding: handle to dp clock.
>> +	of memory mapped region.
>> +- clock-names: from common clock binding:
>> +	Required elements: "sclk_dp" "sclk_dp_24m"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>> +- #phy-cells : from the generic PHY bindings, must be 0;
>> +
>> +Example:
>> +
>> +edp_phy: phy@ff770274 {
> edp_phy: edp-phy {

Done,

>
>
>> +	compatilble = "rockchip,rk3288-dp-phy";
>> +	reg = <0xff770274 4>;
> no regs property

Done

>> +	rockchip,grf = <&grf>;
>> +	clocks = <&cru SCLK_EDP_24M>;
>> +	clock-names = "24m";
>> +	#phy-cells = <0>;
>> +}
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 47da573..8f2bc4f 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>>   	help
>>   	  Enable this to support the Rockchip USB 2.0 PHY.
>>
>> +config PHY_ROCKCHIP_DP
>> +	tristate "Rockchip Display Port PHY Driver"
>> +	depends on ARCH_ROCKCHIP && OF
>> +	select GENERIC_PHY
>> +	help
>> +	  Enable this to support the Rockchip Display Port PHY.
>> +
>>   config PHY_ST_SPEAR1310_MIPHY
>>   	tristate "ST SPEAR1310-MIPHY driver"
>>   	select GENERIC_PHY
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a5b18c1..e281f35 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+=
>> phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>> +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
>>   obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
>> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
>> new file mode 100644
>> index 0000000..e9a726e
>> --- /dev/null
>> +++ b/drivers/phy/phy-rockchip-dp.c
>> @@ -0,0 +1,166 @@
>> +/*
>> + * Rockchip DP PHY driver
>> + *
>> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
>> + * Author: Yakir Yang <ykk@@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define GRF_SOC_CON12                   0x0274
>> +#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
>> +
>> +#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
>> +#define DP_PHY_SIDDQ_ON                 0
>> +#define DP_PHY_SIDDQ_OFF                BIT(5)
>> +
>> +struct rockchip_dp_phy {
>> +	struct device  *dev;
>> +	struct regmap  *grf;
>> +	void __iomem   *regs;
>> +	struct clk     *phy_24m;
>> +};
>> +
>> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
>> +{
>> +	int ret = 0;
>> +
>> +	ret = clk_set_rate(dp->phy_24m, 24000000);
>> +	if (ret < 0) {
>> +		dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	ret = clk_prepare_enable(dp->phy_24m);
>> +	if (ret < 0) {
>> +		dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
>> +{
>> +	clk_disable_unprepare(dp->phy_24m);
>> +
>> +	return 0;
>> +}
>> +
>> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
>> +{
>> +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
>> +
>> +	if (enable) {
>> +		rockchip_dp_phy_clk_enable(dp);
>> +		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
>> +	} else {
>> +		rockchip_dp_phy_clk_disable(dp);
>> +		writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static int rockchip_dp_phy_power_on(struct phy *phy)
>> +{
>> +	return rockchip_set_phy_state(phy, true);
>> +}
>> +
>> +static int rockchip_dp_phy_power_off(struct phy *phy)
>> +{
>> +	return rockchip_set_phy_state(phy, false);
>> +}
>> +
>> +static struct phy_ops rockchip_dp_phy_ops = {
> static const struct ...
>
> see 4a9e5ca1a54a ("phy: Constify struct phy_ops variables")

Done, thanks

>
>> +	.power_on	= rockchip_dp_phy_power_on,
>> +	.power_off	= rockchip_dp_phy_power_off,
>> +	.owner		= THIS_MODULE,
>> +};
>> +
>> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	struct device_node *np = dev->of_node;
>> +	struct phy_provider *phy_provider;
>> +	struct rockchip_dp_phy *dp;
>> +	struct resource *res;
>> +	struct phy *phy;
>> +	int ret;
>> +
> I guess this could profit from a
>
> if (!np)
> 	return -ENODEV;

Hmm... so we are avoiding the no of_device case,

Done,

>> +	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
>> +	if (IS_ERR(dp))
>> +		return -ENOMEM;
>> +
>> +	dp->dev = dev;
>> +
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	dp->regs = devm_ioremap_resource(dev, res);
>> +	if (IS_ERR(dp->regs))
>> +		return PTR_ERR(dp->regs);
>> +
>> +	dp->phy_24m = devm_clk_get(dev, "24m");
>> +	if (IS_ERR(dp->phy_24m)) {
>> +		dev_err(dev, "cannot get clock 24m\n");
>> +		return PTR_ERR(dp->phy_24m);
>> +	}
>> +
>> +	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
>> +	if (IS_ERR(dp->grf)) {
>> +		dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
>> +		return PTR_ERR(dp->grf);
>> +	}
>> +
>> +	ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> +			   GRF_EDP_REF_CLK_SEL_INTER |
>> +			   (GRF_EDP_REF_CLK_SEL_INTER << 16));
>> +	if (ret != 0) {
>> +		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	phy = devm(dev, NULL, &rockchip_dp_phy_ops, NULL);
> hmm, where did you find 4 params for devm_phy_create? Shouldn't this be
>
> 	phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
>
> instead - and also include the phy dt-node as 2nd parameter?

Oh,  :-(=

I used to test the driver on chrome-3.14 branch, I always back the drm 
head file,
so there would be no drm conflict. But phy driver is missed, the 4 
params is come
from kernel-3.14.

Thanks for your redmind,
- Yakir

>
> Heiko
>
>> +	if (IS_ERR(phy)) {
>> +		dev_err(dev, "failed to create phy\n");
>> +		return PTR_ERR(phy);
>> +	}
>> +	phy_set_drvdata(phy, dp);
>> +
>> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> +
>> +	return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
>> +	{ .compatible = "rockchip,rk3288-dp-phy" },
>> +	{}
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
>> +
>> +static struct platform_driver rockchip_dp_phy_driver = {
>> +	.probe		= rockchip_dp_phy_probe,
>> +	.driver		= {
>> +		.name	= "rockchip-dp-phy",
>> +		.of_match_table = rockchip_dp_phy_dt_ids,
>> +	},
>> +};
>> +
>> +module_platform_driver(rockchip_dp_phy_driver);
>> +
>> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
>> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
>> +MODULE_LICENSE("GPL v2");
>
>
>



_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
  2015-09-01 20:46     ` Heiko Stuebner
@ 2015-09-02  1:45       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02  1:45 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel, s.infradead.org

Heiko,

在 09/02/2015 04:46 AM, Heiko Stuebner 写道:
> Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code to analogix_dp-exynos.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> [...]
>
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
>> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
>> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index bed0252..7d62f22 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> [...]
>
>>   	connector->polled = DRM_CONNECTOR_POLL_HPD;
>>
>>   	ret = drm_connector_init(dp->drm_dev, connector,
>> -				 &exynos_dp_connector_funcs,
>> +				 &analogix_dp_connector_funcs,
>>   				 DRM_MODE_CONNECTOR_eDP);
>>   	if (ret) {
>>   		DRM_ERROR("Failed to initialize connector with drm\n");
>>   		return ret;
>>   	}
>>
>> -	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
>> +	drm_connector_helper_add(connector,
>> +				 &analogix_dp_connector_helper_funcs);
>>   	drm_connector_register(connector);
> this should only run on exynos, as we're doing all our connector registration
> in the core driver after all components are bound, so I guess something like
> the following is needed:
>
>         if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
>                 drm_connector_register(connector);
>

Oh, good catch, thanks

>
>>   	drm_mode_connector_attach_encoder(connector, encoder);
>>
> [...]
>
>> @@ -1301,7 +1239,10 @@ static int exynos_dp_bind(struct device *dev, struct
>> device *master, void *data) if (IS_ERR(dp->reg_base))
>>   		return PTR_ERR(dp->reg_base);
>>
>> -	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
>> +	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
>> +	if (gpio_is_valid(dp->hpd_gpio))
> this should be !gpio_is_valid ... i.e. only check the old property if the new
> one is _not_ valid

Oh, much appreciate  ;)

- Yakir

>
>> +		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
>> +						 "samsung,hpd-gpio", 0);
>>
>>   	if (gpio_is_valid(dp->hpd_gpio)) {
>>   		/*
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-02  1:45       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02  1:45 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel

Heiko,

在 09/02/2015 04:46 AM, Heiko Stuebner 写道:
> Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code to analogix_dp-exynos.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> [...]
>
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
>> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
>> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index bed0252..7d62f22 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> [...]
>
>>   	connector->polled = DRM_CONNECTOR_POLL_HPD;
>>
>>   	ret = drm_connector_init(dp->drm_dev, connector,
>> -				 &exynos_dp_connector_funcs,
>> +				 &analogix_dp_connector_funcs,
>>   				 DRM_MODE_CONNECTOR_eDP);
>>   	if (ret) {
>>   		DRM_ERROR("Failed to initialize connector with drm\n");
>>   		return ret;
>>   	}
>>
>> -	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
>> +	drm_connector_helper_add(connector,
>> +				 &analogix_dp_connector_helper_funcs);
>>   	drm_connector_register(connector);
> this should only run on exynos, as we're doing all our connector registration
> in the core driver after all components are bound, so I guess something like
> the following is needed:
>
>         if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
>                 drm_connector_register(connector);
>

Oh, good catch, thanks

>
>>   	drm_mode_connector_attach_encoder(connector, encoder);
>>
> [...]
>
>> @@ -1301,7 +1239,10 @@ static int exynos_dp_bind(struct device *dev, struct
>> device *master, void *data) if (IS_ERR(dp->reg_base))
>>   		return PTR_ERR(dp->reg_base);
>>
>> -	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
>> +	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
>> +	if (gpio_is_valid(dp->hpd_gpio))
> this should be !gpio_is_valid ... i.e. only check the old property if the new
> one is _not_ valid

Oh, much appreciate  ;)

- Yakir

>
>> +		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
>> +						 "samsung,hpd-gpio", 0);
>>
>>   	if (gpio_is_valid(dp->hpd_gpio)) {
>>   		/*
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
  2015-09-01 20:58       ` Heiko Stuebner
@ 2015-09-02  1:46         ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02  1:46 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel, s.infradead.org

Hi Heiko,

在 09/02/2015 04:58 AM, Heiko Stuebner 写道:
> Hi Yakir,
>
> small nit more below
>
> Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
>> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
>>> +- clocks: from common clock binding: handle to dp clock.
>>> +	of memory mapped region.
>>> +- clock-names: from common clock binding:
>>> +	Required elements: "sclk_dp" "sclk_dp_24m"
>>> +
>>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>>> +- #phy-cells : from the generic PHY bindings, must be 0;
>>> +
>>> +Example:
>>> +
>>> +edp_phy: phy@ff770274 {
>> edp_phy: edp-phy {
>>
>>> +	compatilble = "rockchip,rk3288-dp-phy";
> typo: compatible

Aha, thanks.

- Yakir
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-02  1:46         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02  1:46 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King,
	djkurtz-F7+t8E8rja9Wk0Htik3J/w, dianders-F7+t8E8rja9Wk0Htik3J/w,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt-sgV2jX0FEOL9JmXXK+q4OQ,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel

Hi Heiko,

在 09/02/2015 04:58 AM, Heiko Stuebner 写道:
> Hi Yakir,
>
> small nit more below
>
> Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
>> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
>>> +- clocks: from common clock binding: handle to dp clock.
>>> +	of memory mapped region.
>>> +- clock-names: from common clock binding:
>>> +	Required elements: "sclk_dp" "sclk_dp_24m"
>>> +
>>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>>> +- #phy-cells : from the generic PHY bindings, must be 0;
>>> +
>>> +Example:
>>> +
>>> +edp_phy: phy@ff770274 {
>> edp_phy: edp-phy {
>>
>>> +	compatilble = "rockchip,rk3288-dp-phy";
> typo: compatible

Aha, thanks.

- Yakir
>
>
>


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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
  2015-09-01 21:00     ` Heiko Stuebner
@ 2015-09-02  1:52       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02  1:52 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel, s.infradead.org

Hi Heiko,

在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
>> Rockchip have three clocks for dp controller, we leave pclk_edp
>> to analogix_dp driver control, and keep the sclk_edp_24m and
>> sclk_edp in platform driver.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Remove some deprecated DT properties in rockchip dp document.
>>
>> Changes in v3:
>> - Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
>>    dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
>>    core driver which name to "dp", and leave "pclk_edp" to rockchip dp
>> platform driver which name to "pclk".
>> - Take Heiko suggest, add devicetree binding document.
>> - Take Heiko suggest, remove "rockchip,panel" DT property, take use of
>> remote point to get panel node.
>> - Add the new function point analogix_dp_platdata.get_modes init.
>>
>> Changes in v2:
>> - Take Heiko suggest, get panel node with remote-endpoint method,
>>    and create devicetree binding for driver.
>> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>>    leave those clock to rockchip dp phy driver.
>>
>>   .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
>>   drivers/gpu/drm/rockchip/Kconfig                   |   9 +
>>   drivers/gpu/drm/rockchip/Makefile                  |   1 +
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389
>> +++++++++++++++++++++ 4 files changed, 473 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt create
>> mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>
>> diff --git
>> a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt new file
>> mode 100644
>> index 0000000..502483e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> @@ -0,0 +1,74 @@
>> +Rockchip RK3288 specific extensions to the Analogix Display Port
>> +================================
>> +
>> +Required properties:
>> +- compatible: "rockchip,rk3288-edp";
>> +
>> +- reg: physical base address of the controller and length
>> +
>> +- clocks: from common clock binding: handle to dp clock.
>> +	  of memory mapped region.
>> +
>> +- clock-names: from common clock binding:
>> +	       Required elements: "dp" "pclk"
>> +
>> +- resets: Must contain an entry for each entry in reset-names.
>> +	  See ../reset/reset.txt for details.
>> +
>> +- reset-names: Must include the name "dp"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>> +
>> +- ports: contain a port node with endpoint definitions as defined in
>> +  Documentation/devicetree/bindings/media/video-interfaces.txt.
>> +
>> +
>> +For the below properties, please refer to Analogix DP binding document:
>> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> +- phys (required)
>> +- phy-names (required)
>> +- hpd-gpios (optional)
>> +---------------------------------------------------------------------------
>> ---- +
>> +Example:
>> +	dp-controller: dp@ff970000 {
>> +		compatible = "rockchip,rk3288-dp";
>> +		reg = <0xff970000 0x4000>;
>> +		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
>> +		clock-names = "dp", "pclk";
>> +		phys = <&dp_phy>;
>> +		phy-names = "dp";
>> +
>> +		rockchip,grf = <&grf>;
>> +		resets = <&cru 111>;
>> +		reset-names = "dp";
>> +
>> +		status = "disabled";
>> +
>> +		ports {
> #address-cells = <1>;
> #size-cells = <0>;

Done,

>> +			edp_in: port {
> edp_in: port@0
> 	reg = <0>;

Done,

>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				edp_in_vopb: endpoint@0 {
>> +					reg = <0>;
>> +					remote-endpoint = <&vopb_out_edp>;
>> +				};
>> +				edp_in_vopl: endpoint@1 {
>> +					reg = <1>;
>> +					remote-endpoint = <&vopl_out_edp>;
>> +				};
>> +			};
>> +
>> +			edp_out: port@1 {
>> +				reg = <1>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				edp_out_panel: endpoint {
>> +					reg = <0>;
>> +					remote-endpoint = <&panel_in_edp>
>> +				};
>> +			};
>> +		};
>> +	};
>> +
>> diff --git a/drivers/gpu/drm/rockchip/Kconfig
>> b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..c2ba945 100644
>> --- a/drivers/gpu/drm/rockchip/Kconfig
>> +++ b/drivers/gpu/drm/rockchip/Kconfig
>> @@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
>>   	  for the Synopsys DesignWare HDMI driver. If you want to
>>   	  enable HDMI on RK3288 based SoC, you should selet this
>>   	  option.
>> +
>> +config ROCKCHIP_ANALOGIX_DP
>> +        tristate "Rockchip specific extensions for Analogix DP driver"
>> +        depends on DRM_ROCKCHIP
>> +        select DRM_ANALOGIX_DP
>> +        help
>> +	  This selects support for Rockchip SoC specific extensions
>> +	  for the Analogix Core DP driver. If you want to enable DP
>> +	  on RK3288 based SoC, you should selet this option.
>> diff --git a/drivers/gpu/drm/rockchip/Makefile
>> b/drivers/gpu/drm/rockchip/Makefile index f3d8a19..8ad01fb 100644
>> --- a/drivers/gpu/drm/rockchip/Makefile
>> +++ b/drivers/gpu/drm/rockchip/Makefile
>> @@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
>> rockchip_drm_fbdev.o \ rockchip_drm_gem.o
>>
>>   obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
>> +obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
>>
>>   obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c new file mode 100644
>> index 0000000..cebff9e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -0,0 +1,389 @@
>> +/*
>> + * Rockchip SoC DP (Display Port) interface driver.
>> + *
>> + * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
>> + * Author: Andy Yan <andy.yan@rock-chips.com>
>> + *         Yakir Yang <ykk@rock-chips.com>
>> + *         Jeff Chen <jeff.chen@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License as published by the
>> + * Free Software Foundation; either version 2 of the License, or (at your
>> + * option) any later version.
>> + */
>> +#include <drm/drmP.h>
>> +#include <drm/drm_crtc_helper.h>
>> +#include <drm/drm_panel.h>
>> +#include <drm/drm_of.h>
>> +#include <drm/drm_dp_helper.h>
>> +
>> +#include <linux/component.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/of_graph.h>
>> +#include <linux/regmap.h>
>> +#include <linux/reset.h>
>> +#include <linux/clk.h>
>> +
>> +#include <video/of_videomode.h>
>> +#include <video/videomode.h>
>> +
>> +#include <drm/bridge/analogix_dp.h>
>> +
>> +#include "rockchip_drm_drv.h"
>> +#include "rockchip_drm_vop.h"
>> +
>> +#define encoder_to_dp(c) \
>> +		container_of(c, struct rockchip_dp_device, encoder)
>> +
>> +#define plat_data_to_dp(pd) \
>> +		container_of(pd, struct rockchip_dp_device, plat_data)
>> +
>> +/* dp grf register offset */
>> +#define GRF_GPIO7B_IOMUX                        0x0070
>> +#define GPIO7B3_SEL_MASK                        (0x03 << 6)
>> +#define GPIO7B3_SEL_EDP_HOTPLUG                 BIT(7)
> please remove, see comment near pre_init

Okay,

>
>> +
>> +#define GRF_SOC_CON6                            0x025c
>> +#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
>> +#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
>> +#define GRF_EDP_SEL_VOP_BIG                     0
>> +
>> +struct rockchip_dp_device {
>> +	struct drm_device        *drm_dev;
>> +	struct device            *dev;
>> +	struct drm_encoder       encoder;
>> +	struct drm_display_mode  mode;
>> +
>> +	struct clk               *pclk;
>> +	struct regmap            *grf;
>> +	struct reset_control     *rst;
>> +
>> +	struct analogix_dp_plat_data plat_data;
>> +};
>> +
>> +static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
>> +{
>> +	u32 val;
>> +	int ret;
>> +
>> +	val = GPIO7B3_SEL_EDP_HOTPLUG | (GPIO7B3_SEL_MASK << 16);
>> +	ret = regmap_write(dp->grf, GRF_GPIO7B_IOMUX, val);
> this is just a regular pinctrl setting. Please don't write onto other
> components registers. Use a regular pinctrl setting in the devicetree instead.

Okay,

Thanks,
- Yakir

>
>> +	if (ret != 0) {
>> +		dev_err(dp->dev, "Could not config GRF edp hpd: %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	reset_control_assert(dp->rst);
>> +	usleep_range(10, 20);
>> +	reset_control_deassert(dp->rst);
>> +
>> +	return 0;
>> +}
>
> Heiko
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver
@ 2015-09-02  1:52       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02  1:52 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel

Hi Heiko,

在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
>> Rockchip have three clocks for dp controller, we leave pclk_edp
>> to analogix_dp driver control, and keep the sclk_edp_24m and
>> sclk_edp in platform driver.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Remove some deprecated DT properties in rockchip dp document.
>>
>> Changes in v3:
>> - Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
>>    dp phy driver which name to "24m", and leave "sclk_edp" to analogix dp
>>    core driver which name to "dp", and leave "pclk_edp" to rockchip dp
>> platform driver which name to "pclk".
>> - Take Heiko suggest, add devicetree binding document.
>> - Take Heiko suggest, remove "rockchip,panel" DT property, take use of
>> remote point to get panel node.
>> - Add the new function point analogix_dp_platdata.get_modes init.
>>
>> Changes in v2:
>> - Take Heiko suggest, get panel node with remote-endpoint method,
>>    and create devicetree binding for driver.
>> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>>    leave those clock to rockchip dp phy driver.
>>
>>   .../bindings/video/analogix_dp-rockchip.txt        |  74 ++++
>>   drivers/gpu/drm/rockchip/Kconfig                   |   9 +
>>   drivers/gpu/drm/rockchip/Makefile                  |   1 +
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    | 389
>> +++++++++++++++++++++ 4 files changed, 473 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt create
>> mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>
>> diff --git
>> a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt new file
>> mode 100644
>> index 0000000..502483e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> @@ -0,0 +1,74 @@
>> +Rockchip RK3288 specific extensions to the Analogix Display Port
>> +================================
>> +
>> +Required properties:
>> +- compatible: "rockchip,rk3288-edp";
>> +
>> +- reg: physical base address of the controller and length
>> +
>> +- clocks: from common clock binding: handle to dp clock.
>> +	  of memory mapped region.
>> +
>> +- clock-names: from common clock binding:
>> +	       Required elements: "dp" "pclk"
>> +
>> +- resets: Must contain an entry for each entry in reset-names.
>> +	  See ../reset/reset.txt for details.
>> +
>> +- reset-names: Must include the name "dp"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>> +
>> +- ports: contain a port node with endpoint definitions as defined in
>> +  Documentation/devicetree/bindings/media/video-interfaces.txt.
>> +
>> +
>> +For the below properties, please refer to Analogix DP binding document:
>> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> +- phys (required)
>> +- phy-names (required)
>> +- hpd-gpios (optional)
>> +---------------------------------------------------------------------------
>> ---- +
>> +Example:
>> +	dp-controller: dp@ff970000 {
>> +		compatible = "rockchip,rk3288-dp";
>> +		reg = <0xff970000 0x4000>;
>> +		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
>> +		clock-names = "dp", "pclk";
>> +		phys = <&dp_phy>;
>> +		phy-names = "dp";
>> +
>> +		rockchip,grf = <&grf>;
>> +		resets = <&cru 111>;
>> +		reset-names = "dp";
>> +
>> +		status = "disabled";
>> +
>> +		ports {
> #address-cells = <1>;
> #size-cells = <0>;

Done,

>> +			edp_in: port {
> edp_in: port@0
> 	reg = <0>;

Done,

>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				edp_in_vopb: endpoint@0 {
>> +					reg = <0>;
>> +					remote-endpoint = <&vopb_out_edp>;
>> +				};
>> +				edp_in_vopl: endpoint@1 {
>> +					reg = <1>;
>> +					remote-endpoint = <&vopl_out_edp>;
>> +				};
>> +			};
>> +
>> +			edp_out: port@1 {
>> +				reg = <1>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				edp_out_panel: endpoint {
>> +					reg = <0>;
>> +					remote-endpoint = <&panel_in_edp>
>> +				};
>> +			};
>> +		};
>> +	};
>> +
>> diff --git a/drivers/gpu/drm/rockchip/Kconfig
>> b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..c2ba945 100644
>> --- a/drivers/gpu/drm/rockchip/Kconfig
>> +++ b/drivers/gpu/drm/rockchip/Kconfig
>> @@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
>>   	  for the Synopsys DesignWare HDMI driver. If you want to
>>   	  enable HDMI on RK3288 based SoC, you should selet this
>>   	  option.
>> +
>> +config ROCKCHIP_ANALOGIX_DP
>> +        tristate "Rockchip specific extensions for Analogix DP driver"
>> +        depends on DRM_ROCKCHIP
>> +        select DRM_ANALOGIX_DP
>> +        help
>> +	  This selects support for Rockchip SoC specific extensions
>> +	  for the Analogix Core DP driver. If you want to enable DP
>> +	  on RK3288 based SoC, you should selet this option.
>> diff --git a/drivers/gpu/drm/rockchip/Makefile
>> b/drivers/gpu/drm/rockchip/Makefile index f3d8a19..8ad01fb 100644
>> --- a/drivers/gpu/drm/rockchip/Makefile
>> +++ b/drivers/gpu/drm/rockchip/Makefile
>> @@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
>> rockchip_drm_fbdev.o \ rockchip_drm_gem.o
>>
>>   obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
>> +obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
>>
>>   obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c new file mode 100644
>> index 0000000..cebff9e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -0,0 +1,389 @@
>> +/*
>> + * Rockchip SoC DP (Display Port) interface driver.
>> + *
>> + * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
>> + * Author: Andy Yan <andy.yan@rock-chips.com>
>> + *         Yakir Yang <ykk@rock-chips.com>
>> + *         Jeff Chen <jeff.chen@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License as published by the
>> + * Free Software Foundation; either version 2 of the License, or (at your
>> + * option) any later version.
>> + */
>> +#include <drm/drmP.h>
>> +#include <drm/drm_crtc_helper.h>
>> +#include <drm/drm_panel.h>
>> +#include <drm/drm_of.h>
>> +#include <drm/drm_dp_helper.h>
>> +
>> +#include <linux/component.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/of_graph.h>
>> +#include <linux/regmap.h>
>> +#include <linux/reset.h>
>> +#include <linux/clk.h>
>> +
>> +#include <video/of_videomode.h>
>> +#include <video/videomode.h>
>> +
>> +#include <drm/bridge/analogix_dp.h>
>> +
>> +#include "rockchip_drm_drv.h"
>> +#include "rockchip_drm_vop.h"
>> +
>> +#define encoder_to_dp(c) \
>> +		container_of(c, struct rockchip_dp_device, encoder)
>> +
>> +#define plat_data_to_dp(pd) \
>> +		container_of(pd, struct rockchip_dp_device, plat_data)
>> +
>> +/* dp grf register offset */
>> +#define GRF_GPIO7B_IOMUX                        0x0070
>> +#define GPIO7B3_SEL_MASK                        (0x03 << 6)
>> +#define GPIO7B3_SEL_EDP_HOTPLUG                 BIT(7)
> please remove, see comment near pre_init

Okay,

>
>> +
>> +#define GRF_SOC_CON6                            0x025c
>> +#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
>> +#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
>> +#define GRF_EDP_SEL_VOP_BIG                     0
>> +
>> +struct rockchip_dp_device {
>> +	struct drm_device        *drm_dev;
>> +	struct device            *dev;
>> +	struct drm_encoder       encoder;
>> +	struct drm_display_mode  mode;
>> +
>> +	struct clk               *pclk;
>> +	struct regmap            *grf;
>> +	struct reset_control     *rst;
>> +
>> +	struct analogix_dp_plat_data plat_data;
>> +};
>> +
>> +static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
>> +{
>> +	u32 val;
>> +	int ret;
>> +
>> +	val = GPIO7B3_SEL_EDP_HOTPLUG | (GPIO7B3_SEL_MASK << 16);
>> +	ret = regmap_write(dp->grf, GRF_GPIO7B_IOMUX, val);
> this is just a regular pinctrl setting. Please don't write onto other
> components registers. Use a regular pinctrl setting in the devicetree instead.

Okay,

Thanks,
- Yakir

>
>> +	if (ret != 0) {
>> +		dev_err(dp->dev, "Could not config GRF edp hpd: %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	reset_control_assert(dp->rst);
>> +	usleep_range(10, 20);
>> +	reset_control_deassert(dp->rst);
>> +
>> +	return 0;
>> +}
>
> Heiko
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
  2015-09-01 21:00     ` Heiko Stuebner
@ 2015-09-02  2:06       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02  2:06 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel, s.infradead.org, Mark Yao

Hi Heiko,

在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
>> From: Mark Yao <yzq@rock-chips.com>
>>
>> Add bpc and color mode setting in rockchip_drm_vop driver, so
>> connector could try to use the edid drm_display_info to config
>> vop output mode.
>>
>> Signed-off-by: Mark Yao <yzq@rock-chips.com>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 46
>> +++++++++++++++++++------ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |
>>   2 +-
>>   drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
>>   drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 33 ++++++++++++++++--
>>   4 files changed, 68 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index cebff9e..efea045
>> 100644
>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -11,11 +11,6 @@
>>    * Free Software Foundation; either version 2 of the License, or (at your
>>    * option) any later version.
>>    */
>> -#include <drm/drmP.h>
>> -#include <drm/drm_crtc_helper.h>
>> -#include <drm/drm_panel.h>
>> -#include <drm/drm_of.h>
>> -#include <drm/drm_dp_helper.h>
>>
>>   #include <linux/component.h>
>>   #include <linux/mfd/syscon.h>
>> @@ -27,6 +22,13 @@
>>   #include <video/of_videomode.h>
>>   #include <video/videomode.h>
>>
>> +#include <drm/drmP.h>
>> +#include <drm/drm_crtc.h>
>> +#include <drm/drm_crtc_helper.h>
>> +#include <drm/drm_panel.h>
>> +#include <drm/drm_of.h>
>> +#include <drm/drm_dp_helper.h>
>> +
>>   #include <drm/bridge/analogix_dp.h>
>>
>>   #include "rockchip_drm_drv.h"
>> @@ -125,20 +127,44 @@ static void rockchip_dp_drm_encoder_mode_set(struct
>> drm_encoder *encoder, /* do nothing */
>>   }
>>
>> +static drm_connector *rockchip_dp_get_connector(struct rockchip_dp_device
> missing a "struct" -> static struct drm_connector

What the hell mistake I make in v5  :-(

Thanks a lot, I would fix this as soon as possible

>
>> *dp) +{
>> +	struct drm_connector *connector;
>> +	struct drm_device *drm_dev = dp->drm_dev;
>> +
>> +	drm_for_each_connector(connector, drm_dev) {
>> +		if (connector->encoder != &dp->encoder)
>> +			return connector;
>> +	}
>> +
>> +	return NULL;
>> +}
>> +
>>   static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
>>   {
>>   	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
>> +	struct drm_connector *connector;
>> +	int ret = 0;
>>   	u32 val;
>> -	int ret;
>>
>> -	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
>> -					    DRM_MODE_CONNECTOR_eDP,
>> -					    ROCKCHIP_OUT_MODE_AAAA);
>> -	if (ret < 0) {
>> +	connector = rockchip_dp_get_connector(dp);
>> +	if (!connector) {
>> +		DRM_ERROR("Failed to get connector by encoder[%p]\n", encoder);
>> +		return;
>> +	}
>> +
>> +	if (connector->display_info.color_formats | DRM_COLOR_FORMAT_RGB444)
>> +		ret = rockchip_drm_crtc_mode_config(
>> +			encoder->crtc, DRM_MODE_CONNECTOR_eDP,
>> +			connector->display_info.bpc, DRM_COLOR_FORMAT_RGB444);
>> +	if (!ret) {
>>   		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
>>   		return;
>>   	}
>>
>> +	connector->display_info.bpc = ret;
>> +	connector->display_info.color_formats = DRM_COLOR_FORMAT_RGB444;
>> +
>>   	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
>>   	if (ret < 0)
>>   		return;
>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>> b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 80d6fc8..428a3c1 100644
>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>> @@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct
>> drm_encoder *encoder) static void dw_hdmi_rockchip_encoder_prepare(struct
>> drm_encoder *encoder) {
>>   	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
>> -				      ROCKCHIP_OUT_MODE_AAAA);
>> +				      10, DRM_COLOR_FORMAT_RGB444);
>>   }
>>
>>   static struct drm_encoder_helper_funcs
>> dw_hdmi_rockchip_encoder_helper_funcs = { diff --git
>> a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
>> b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index dc4e5f0..ef1d7fb 100644
>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
>> @@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device
>> *dev, int pipe); int rockchip_drm_encoder_get_mux_id(struct device_node
>> *node,
>>   				    struct drm_encoder *encoder);
>>   int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int
>> connector_type, -				  int out_mode);
>> +				  int bpc, int color);
>>   int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
>>   				   struct device *dev);
>>   void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
>> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> @@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
>> {
>>
>>   int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
>>   				  int connector_type,
>> -				  int out_mode)
>> +				  int bpc, int color)
>>   {
>>   	struct vop *vop = to_vop(crtc);
>> -
>>   	vop->connector_type = connector_type;
>>   	vop->connector_out_mode = out_mode;
> this line should probably go away, as the source var "out_mode" does not exist
> in the function params any more, making the compilation break, and is set
> below anyway.

Sorry for the failed, there are must be a problem when I backport those code
to chrome-3.14 to verify.

Thanks a lot, I would update next version soon.
- Yakir

>
> Heiko
>
>> -	return 0;
>> +	/*
>> +	 * RK3288 vop only support RGB Color output.
>> +	 */
>> +	if (color != DRM_COLOR_FORMAT_RGB444) {
>> +		DRM_ERROR("Only support output RGB444, not support%d\n",
>> +			  color);
>> +		return -EINVAL;
>> +	}
>> +
>> +	/*
>> +	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
>> +	 * bpc, 5 or 6?
>> +	 *
>> +	 */
>> +	if (bpc >= 10) {
>> +		bpc = 10;
>> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
>> +	} else if (bpc >= 8) {
>> +		bpc = 8;
>> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
>> +	} else if (bpc >= 6) {
>> +		bpc = 6;
>> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
>> +	} else {
>> +		DRM_ERROR("unsupport bpc %d\n", bpc);
>> +		return -EINVAL;
>> +	}
>> +
>> +	return bpc;
>>   }
>>   EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
@ 2015-09-02  2:06       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02  2:06 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel

Hi Heiko,

在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
>> From: Mark Yao <yzq@rock-chips.com>
>>
>> Add bpc and color mode setting in rockchip_drm_vop driver, so
>> connector could try to use the edid drm_display_info to config
>> vop output mode.
>>
>> Signed-off-by: Mark Yao <yzq@rock-chips.com>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 46
>> +++++++++++++++++++------ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |
>>   2 +-
>>   drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
>>   drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 33 ++++++++++++++++--
>>   4 files changed, 68 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index cebff9e..efea045
>> 100644
>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -11,11 +11,6 @@
>>    * Free Software Foundation; either version 2 of the License, or (at your
>>    * option) any later version.
>>    */
>> -#include <drm/drmP.h>
>> -#include <drm/drm_crtc_helper.h>
>> -#include <drm/drm_panel.h>
>> -#include <drm/drm_of.h>
>> -#include <drm/drm_dp_helper.h>
>>
>>   #include <linux/component.h>
>>   #include <linux/mfd/syscon.h>
>> @@ -27,6 +22,13 @@
>>   #include <video/of_videomode.h>
>>   #include <video/videomode.h>
>>
>> +#include <drm/drmP.h>
>> +#include <drm/drm_crtc.h>
>> +#include <drm/drm_crtc_helper.h>
>> +#include <drm/drm_panel.h>
>> +#include <drm/drm_of.h>
>> +#include <drm/drm_dp_helper.h>
>> +
>>   #include <drm/bridge/analogix_dp.h>
>>
>>   #include "rockchip_drm_drv.h"
>> @@ -125,20 +127,44 @@ static void rockchip_dp_drm_encoder_mode_set(struct
>> drm_encoder *encoder, /* do nothing */
>>   }
>>
>> +static drm_connector *rockchip_dp_get_connector(struct rockchip_dp_device
> missing a "struct" -> static struct drm_connector

What the hell mistake I make in v5  :-(

Thanks a lot, I would fix this as soon as possible

>
>> *dp) +{
>> +	struct drm_connector *connector;
>> +	struct drm_device *drm_dev = dp->drm_dev;
>> +
>> +	drm_for_each_connector(connector, drm_dev) {
>> +		if (connector->encoder != &dp->encoder)
>> +			return connector;
>> +	}
>> +
>> +	return NULL;
>> +}
>> +
>>   static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
>>   {
>>   	struct rockchip_dp_device *dp = encoder_to_dp(encoder);
>> +	struct drm_connector *connector;
>> +	int ret = 0;
>>   	u32 val;
>> -	int ret;
>>
>> -	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
>> -					    DRM_MODE_CONNECTOR_eDP,
>> -					    ROCKCHIP_OUT_MODE_AAAA);
>> -	if (ret < 0) {
>> +	connector = rockchip_dp_get_connector(dp);
>> +	if (!connector) {
>> +		DRM_ERROR("Failed to get connector by encoder[%p]\n", encoder);
>> +		return;
>> +	}
>> +
>> +	if (connector->display_info.color_formats | DRM_COLOR_FORMAT_RGB444)
>> +		ret = rockchip_drm_crtc_mode_config(
>> +			encoder->crtc, DRM_MODE_CONNECTOR_eDP,
>> +			connector->display_info.bpc, DRM_COLOR_FORMAT_RGB444);
>> +	if (!ret) {
>>   		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
>>   		return;
>>   	}
>>
>> +	connector->display_info.bpc = ret;
>> +	connector->display_info.color_formats = DRM_COLOR_FORMAT_RGB444;
>> +
>>   	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
>>   	if (ret < 0)
>>   		return;
>> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>> b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 80d6fc8..428a3c1 100644
>> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>> @@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct
>> drm_encoder *encoder) static void dw_hdmi_rockchip_encoder_prepare(struct
>> drm_encoder *encoder) {
>>   	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
>> -				      ROCKCHIP_OUT_MODE_AAAA);
>> +				      10, DRM_COLOR_FORMAT_RGB444);
>>   }
>>
>>   static struct drm_encoder_helper_funcs
>> dw_hdmi_rockchip_encoder_helper_funcs = { diff --git
>> a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
>> b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index dc4e5f0..ef1d7fb 100644
>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
>> @@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device
>> *dev, int pipe); int rockchip_drm_encoder_get_mux_id(struct device_node
>> *node,
>>   				    struct drm_encoder *encoder);
>>   int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int
>> connector_type, -				  int out_mode);
>> +				  int bpc, int color);
>>   int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
>>   				   struct device *dev);
>>   void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
>> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> @@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
>> {
>>
>>   int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
>>   				  int connector_type,
>> -				  int out_mode)
>> +				  int bpc, int color)
>>   {
>>   	struct vop *vop = to_vop(crtc);
>> -
>>   	vop->connector_type = connector_type;
>>   	vop->connector_out_mode = out_mode;
> this line should probably go away, as the source var "out_mode" does not exist
> in the function params any more, making the compilation break, and is set
> below anyway.

Sorry for the failed, there are must be a problem when I backport those code
to chrome-3.14 to verify.

Thanks a lot, I would update next version soon.
- Yakir

>
> Heiko
>
>> -	return 0;
>> +	/*
>> +	 * RK3288 vop only support RGB Color output.
>> +	 */
>> +	if (color != DRM_COLOR_FORMAT_RGB444) {
>> +		DRM_ERROR("Only support output RGB444, not support%d\n",
>> +			  color);
>> +		return -EINVAL;
>> +	}
>> +
>> +	/*
>> +	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
>> +	 * bpc, 5 or 6?
>> +	 *
>> +	 */
>> +	if (bpc >= 10) {
>> +		bpc = 10;
>> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
>> +	} else if (bpc >= 8) {
>> +		bpc = 8;
>> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
>> +	} else if (bpc >= 6) {
>> +		bpc = 6;
>> +		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
>> +	} else {
>> +		DRM_ERROR("unsupport bpc %d\n", bpc);
>> +		return -EINVAL;
>> +	}
>> +
>> +	return bpc;
>>   }
>>   EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver
  2015-09-01 21:47   ` Heiko Stuebner
@ 2015-09-02  2:15     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02  2:15 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel, s.infradead.org

Hi Heiko,

在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I split the common
>> code into bridge directory, then rk3288 and exynos only need to keep
>> some platform code. Cause I can't find the exact IP name of exynos dp
>> controller, so I decide to name dp core driver with "analogix" which I
>> find in rk3288 eDP TRM ;)
>>
>> Beyond that, there are three light registers setting differents bewteen
>> exynos and rk3288.
>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>     dp controller.
>> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>>     between rk3288 and exynos.
>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>>     register).
>>
>> I have verified this series on two kinds of rockchip platform board, one
>> is rk3288 sdk board which connect with a 2K display port monitor, the other
>> is google jerry chromebook which connect with a eDP screen "cnm,n116bgeea2",
>> both of them works rightlly.
> it looks like during the rebase something did go wrong and I found some issues
> I mentioned in the replies to individual patches.
>
> I did prepare a branch based on mainline [0] with both the old and the new edp
> driver - rk3288_veyron_defconfig build both drivers into the image.
>
> While the old driver still works, I wasn't able to make the new one work yet
> ... the drm core does find the connector, but not that anything is connected
> to it. I'll try to dig deeper tomorrow, but maybe you'll see anything
> interesting before then.

Many thanks for your comment and debug, I would rebase on your
"edp-with-veyron" branch and fix the broken, make sure v6 would
work rightly at least in your side and my side.

- Yakir

>
> Heiko
>
> [0] https://github.com/mmind/linux-rockchip/tree/tmp/edp-with-veyron
>
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver
@ 2015-09-02  2:15     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02  2:15 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Thierry Reding, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel

Hi Heiko,

在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I split the common
>> code into bridge directory, then rk3288 and exynos only need to keep
>> some platform code. Cause I can't find the exact IP name of exynos dp
>> controller, so I decide to name dp core driver with "analogix" which I
>> find in rk3288 eDP TRM ;)
>>
>> Beyond that, there are three light registers setting differents bewteen
>> exynos and rk3288.
>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>     dp controller.
>> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>>     between rk3288 and exynos.
>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>>     register).
>>
>> I have verified this series on two kinds of rockchip platform board, one
>> is rk3288 sdk board which connect with a 2K display port monitor, the other
>> is google jerry chromebook which connect with a eDP screen "cnm,n116bgeea2",
>> both of them works rightlly.
> it looks like during the rebase something did go wrong and I found some issues
> I mentioned in the replies to individual patches.
>
> I did prepare a branch based on mainline [0] with both the old and the new edp
> driver - rk3288_veyron_defconfig build both drivers into the image.
>
> While the old driver still works, I wasn't able to make the new one work yet
> ... the drm core does find the connector, but not that anything is connected
> to it. I'll try to dig deeper tomorrow, but maybe you'll see anything
> interesting before then.

Many thanks for your comment and debug, I would rebase on your
"edp-with-veyron" branch and fix the broken, make sure v6 would
work rightly at least in your side and my side.

- Yakir

>
> Heiko
>
> [0] https://github.com/mmind/linux-rockchip/tree/tmp/edp-with-veyron
>
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
  2015-09-02  2:06       ` Yakir Yang
@ 2015-09-02  8:34         ` Thierry Reding
  -1 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-02  8:34 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel, s.infradead.org, Mark Yao

[-- Attachment #1: Type: text/plain, Size: 2631 bytes --]

On Wed, Sep 02, 2015 at 10:06:36AM +0800, Yakir Yang wrote:
> 在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
> >Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
[...]
> >>diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> >>b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
> >>--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> >>+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> >>@@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
> >>{
> >>
> >>  int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
> >>  				  int connector_type,
> >>-				  int out_mode)
> >>+				  int bpc, int color)
> >>  {
> >>  	struct vop *vop = to_vop(crtc);
> >>-
> >>  	vop->connector_type = connector_type;
> >>  	vop->connector_out_mode = out_mode;
> >this line should probably go away, as the source var "out_mode" does not exist
> >in the function params any more, making the compilation break, and is set
> >below anyway.
> 
> Sorry for the failed, there are must be a problem when I backport those code
> to chrome-3.14 to verify.
> 
> Thanks a lot, I would update next version soon.

*sigh*

I get the feeling that you're going about upstreaming the wrong way. If
you post patches to upstream mailing lists and you expect people to
apply those patches, then your target is the upstream kernel. So you
should be basing all of your work on top of a recent release candidate
directly from Linus or some recent version of linux-next.

Your current approach is already making people waste time trying to
build the patches and fail because you've been testing on something
other than mainline or linux-next.

At the very least your code must compile when applied against a recent
upstream tree. I would also expect you to make sure the code works at
runtime, though, contrary to build testing, not everybody will be able
to verify that you've actually done so. It is ultimately your platform
maintainer's (i.e. Heiko's) responsibility to ensure that because they
will get to deal with user complaints if people can't run an upstream
kernel on the devices.

I realize that the upstream kernel isn't what's going to end up in
products later on, but that doesn't change the fact that you're
submitting code for inclusion in the mainline tree. If you need to
backport code to some ChromeOS tree, then that should be done after
you've verified that things build and run upstream. Doing so makes life
a lot easier for your upstream maintainers, and that in turn makes it
more likely to get your code merged.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
@ 2015-09-02  8:34         ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-02  8:34 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree

[-- Attachment #1: Type: text/plain, Size: 2631 bytes --]

On Wed, Sep 02, 2015 at 10:06:36AM +0800, Yakir Yang wrote:
> 在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
> >Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
[...]
> >>diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> >>b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
> >>--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> >>+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> >>@@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
> >>{
> >>
> >>  int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
> >>  				  int connector_type,
> >>-				  int out_mode)
> >>+				  int bpc, int color)
> >>  {
> >>  	struct vop *vop = to_vop(crtc);
> >>-
> >>  	vop->connector_type = connector_type;
> >>  	vop->connector_out_mode = out_mode;
> >this line should probably go away, as the source var "out_mode" does not exist
> >in the function params any more, making the compilation break, and is set
> >below anyway.
> 
> Sorry for the failed, there are must be a problem when I backport those code
> to chrome-3.14 to verify.
> 
> Thanks a lot, I would update next version soon.

*sigh*

I get the feeling that you're going about upstreaming the wrong way. If
you post patches to upstream mailing lists and you expect people to
apply those patches, then your target is the upstream kernel. So you
should be basing all of your work on top of a recent release candidate
directly from Linus or some recent version of linux-next.

Your current approach is already making people waste time trying to
build the patches and fail because you've been testing on something
other than mainline or linux-next.

At the very least your code must compile when applied against a recent
upstream tree. I would also expect you to make sure the code works at
runtime, though, contrary to build testing, not everybody will be able
to verify that you've actually done so. It is ultimately your platform
maintainer's (i.e. Heiko's) responsibility to ensure that because they
will get to deal with user complaints if people can't run an upstream
kernel on the devices.

I realize that the upstream kernel isn't what's going to end up in
products later on, but that doesn't change the fact that you're
submitting code for inclusion in the mainline tree. If you need to
backport code to some ChromeOS tree, then that should be done after
you've verified that things build and run upstream. Doing so makes life
a lot easier for your upstream maintainers, and that in turn makes it
more likely to get your code merged.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
@ 2015-09-02 10:02           ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02 10:02 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Heiko Stuebner, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel, s.infradead.org, Mark Yao

Thierry,

在 2015/9/2 16:34, Thierry Reding 写道:
> On Wed, Sep 02, 2015 at 10:06:36AM +0800, Yakir Yang wrote:
>> 在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
>>> Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
> [...]
>>>> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>>>> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
>>>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>>>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>>>> @@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
>>>> {
>>>>
>>>>   int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
>>>>   				  int connector_type,
>>>> -				  int out_mode)
>>>> +				  int bpc, int color)
>>>>   {
>>>>   	struct vop *vop = to_vop(crtc);
>>>> -
>>>>   	vop->connector_type = connector_type;
>>>>   	vop->connector_out_mode = out_mode;
>>> this line should probably go away, as the source var "out_mode" does not exist
>>> in the function params any more, making the compilation break, and is set
>>> below anyway.
>> Sorry for the failed, there are must be a problem when I backport those code
>> to chrome-3.14 to verify.
>>
>> Thanks a lot, I would update next version soon.
> *sigh*
>
> I get the feeling that you're going about upstreaming the wrong way. If
> you post patches to upstream mailing lists and you expect people to
> apply those patches, then your target is the upstream kernel. So you
> should be basing all of your work on top of a recent release candidate
> directly from Linus or some recent version of linux-next.

Yeah, do feel I am in the wrong way now. I used to write my patch on
linux-next branch, then backport some head file to productor kernel,
so I can check compiled failed. After that, I backport the dp driver code
to normal productor kernel, start to debug the function.

So I used to ensure no compiled failed on upstrean kernel, actually it's
also hard to ensure, cause I just backport head file. Not even debug the
function on upstream kernel.

> Your current approach is already making people waste time trying to
> build the patches and fail because you've been testing on something
> other than mainline or linux-next.
>
> At the very least your code must compile when applied against a recent
> upstream tree. I would also expect you to make sure the code works at
> runtime, though, contrary to build testing, not everybody will be able
> to verify that you've actually done so. It is ultimately your platform
> maintainer's (i.e. Heiko's) responsibility to ensure that because they
> will get to deal with user complaints if people can't run an upstream
> kernel on the devices.

Oh, first time to know this rule. So I should work on Heiko's github
kernel branch at the first time to start send upstream.

> I realize that the upstream kernel isn't what's going to end up in
> products later on, but that doesn't change the fact that you're
> submitting code for inclusion in the mainline tree. If you need to
> backport code to some ChromeOS tree, then that should be done after
> you've verified that things build and run upstream. Doing so makes life
> a lot easier for your upstream maintainers, and that in turn makes it
> more likely to get your code merged.

Feel free now, I would correct those in bellow version. Thanks
for your remind (or maybe complain :-D ).

- Yakir
> Thierry



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
@ 2015-09-02 10:02           ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-02 10:02 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Heiko Stuebner, Jingoo Han, Inki Dae, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King,
	djkurtz-F7+t8E8rja9Wk0Htik3J/w, dianders-F7+t8E8rja9Wk0Htik3J/w,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt-sgV2jX0FEOL9JmXXK+q4OQ,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel

Thierry,

在 2015/9/2 16:34, Thierry Reding 写道:
> On Wed, Sep 02, 2015 at 10:06:36AM +0800, Yakir Yang wrote:
>> 在 09/02/2015 05:00 AM, Heiko Stuebner 写道:
>>> Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
> [...]
>>>> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>>>> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 34b78e7..5d7f9b6 100644
>>>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>>>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>>>> @@ -811,14 +811,41 @@ static const struct drm_plane_funcs vop_plane_funcs =
>>>> {
>>>>
>>>>   int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
>>>>   				  int connector_type,
>>>> -				  int out_mode)
>>>> +				  int bpc, int color)
>>>>   {
>>>>   	struct vop *vop = to_vop(crtc);
>>>> -
>>>>   	vop->connector_type = connector_type;
>>>>   	vop->connector_out_mode = out_mode;
>>> this line should probably go away, as the source var "out_mode" does not exist
>>> in the function params any more, making the compilation break, and is set
>>> below anyway.
>> Sorry for the failed, there are must be a problem when I backport those code
>> to chrome-3.14 to verify.
>>
>> Thanks a lot, I would update next version soon.
> *sigh*
>
> I get the feeling that you're going about upstreaming the wrong way. If
> you post patches to upstream mailing lists and you expect people to
> apply those patches, then your target is the upstream kernel. So you
> should be basing all of your work on top of a recent release candidate
> directly from Linus or some recent version of linux-next.

Yeah, do feel I am in the wrong way now. I used to write my patch on
linux-next branch, then backport some head file to productor kernel,
so I can check compiled failed. After that, I backport the dp driver code
to normal productor kernel, start to debug the function.

So I used to ensure no compiled failed on upstrean kernel, actually it's
also hard to ensure, cause I just backport head file. Not even debug the
function on upstream kernel.

> Your current approach is already making people waste time trying to
> build the patches and fail because you've been testing on something
> other than mainline or linux-next.
>
> At the very least your code must compile when applied against a recent
> upstream tree. I would also expect you to make sure the code works at
> runtime, though, contrary to build testing, not everybody will be able
> to verify that you've actually done so. It is ultimately your platform
> maintainer's (i.e. Heiko's) responsibility to ensure that because they
> will get to deal with user complaints if people can't run an upstream
> kernel on the devices.

Oh, first time to know this rule. So I should work on Heiko's github
kernel branch at the first time to start send upstream.

> I realize that the upstream kernel isn't what's going to end up in
> products later on, but that doesn't change the fact that you're
> submitting code for inclusion in the mainline tree. If you need to
> backport code to some ChromeOS tree, then that should be done after
> you've verified that things build and run upstream. Doing so makes life
> a lot easier for your upstream maintainers, and that in turn makes it
> more likely to get your code merged.

Feel free now, I would correct those in bellow version. Thanks
for your remind (or maybe complain :-D ).

- Yakir
> Thierry


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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
  2015-09-01  6:04   ` Yakir Yang
  (?)
@ 2015-09-02 13:27     ` Rob Herring
  -1 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-02 13:27 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	Russell King, djkurtz, dianders, seanpaul, Ajay kumar,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Kishon suggest, add commit message, and remove the redundant
>   rockchip_dp_phy_init() function, move those code to probe() method.
>   And remove driver .owner number.
>
> Changes in v3:
> - Take Heiko suggest, add rockchip dp phy driver,
>   collect the phy clocks and power control.
>
> Changes in v2: None
>
>  .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++

It is preferred that you split binding doc's from driver changes.

>  drivers/phy/Kconfig                                |   7 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-rockchip-dp.c                      | 166 +++++++++++++++++++++
>  4 files changed, 200 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>  create mode 100644 drivers/phy/phy-rockchip-dp.c
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> new file mode 100644
> index 0000000..5de1088
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> @@ -0,0 +1,26 @@
> +Rockchip Soc Seroes Display Port PHY
> +------------------------------------
> +
> +Required properties:
> +- compatible : should be one of the following supported values:
> +        - "rockchip.rk3288-dp-phy"
> +
> +- reg : a list of registers used by phy driver

Please state the size of the list and order of what each entry if more than one.

> +- clocks: from common clock binding: handle to dp clock.
> +       of memory mapped region.
> +- clock-names: from common clock binding:
> +       Required elements: "sclk_dp" "sclk_dp_24m"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.

I have no idea what GRF means.

> +- #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Example:
> +
> +edp_phy: phy@ff770274 {
> +       compatilble = "rockchip,rk3288-dp-phy";
> +       reg = <0xff770274 4>;
> +       rockchip,grf = <&grf>;
> +       clocks = <&cru SCLK_EDP_24M>;
> +       clock-names = "24m";
> +       #phy-cells = <0>;
> +}
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573..8f2bc4f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>         help
>           Enable this to support the Rockchip USB 2.0 PHY.
>
> +config PHY_ROCKCHIP_DP
> +       tristate "Rockchip Display Port PHY Driver"
> +       depends on ARCH_ROCKCHIP && OF
> +       select GENERIC_PHY
> +       help
> +         Enable this to support the Rockchip Display Port PHY.
> +
>  config PHY_ST_SPEAR1310_MIPHY
>         tristate "ST SPEAR1310-MIPHY driver"
>         select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a5b18c1..e281f35 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)    += phy-s5pv210-usb2.o
>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)       += phy-exynos5-usbdrd.o
>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)    += phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP)          += phy-rockchip-dp.o
>  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)    += phy-qcom-ipq806x-sata.o
>  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)   += phy-spear1310-miphy.o
>  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)   += phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..e9a726e
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,166 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12                   0x0274
> +#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
> +
> +#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
> +#define DP_PHY_SIDDQ_ON                 0
> +#define DP_PHY_SIDDQ_OFF                BIT(5)
> +
> +struct rockchip_dp_phy {
> +       struct device  *dev;
> +       struct regmap  *grf;
> +       void __iomem   *regs;
> +       struct clk     *phy_24m;
> +};
> +
> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
> +{
> +       int ret = 0;
> +
> +       ret = clk_set_rate(dp->phy_24m, 24000000);

Do you need to do this every time? This can go in probe.

> +       if (ret < 0) {
> +               dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
> +               return ret;
> +       }
> +
> +       ret = clk_prepare_enable(dp->phy_24m);
> +       if (ret < 0) {
> +               dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
> +{
> +       clk_disable_unprepare(dp->phy_24m);
> +
> +       return 0;
> +}
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> +       struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> +
> +       if (enable) {
> +               rockchip_dp_phy_clk_enable(dp);
> +               writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
> +       } else {
> +               rockchip_dp_phy_clk_disable(dp);
> +               writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
> +       }
> +
> +       return 0;
> +}

I would just inline all 3 of these functions. The wrappers don't
doesn't do anything, but add 2 levels of function calls.

> +
> +static int rockchip_dp_phy_power_on(struct phy *phy)
> +{
> +       return rockchip_set_phy_state(phy, true);
> +}
> +
> +static int rockchip_dp_phy_power_off(struct phy *phy)
> +{
> +       return rockchip_set_phy_state(phy, false);
> +}
> +
> +static struct phy_ops rockchip_dp_phy_ops = {
> +       .power_on       = rockchip_dp_phy_power_on,
> +       .power_off      = rockchip_dp_phy_power_off,
> +       .owner          = THIS_MODULE,
> +};
> +
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct device_node *np = dev->of_node;
> +       struct phy_provider *phy_provider;
> +       struct rockchip_dp_phy *dp;
> +       struct resource *res;
> +       struct phy *phy;
> +       int ret;
> +
> +       dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
> +       if (IS_ERR(dp))
> +               return -ENOMEM;
> +
> +       dp->dev = dev;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       dp->regs = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(dp->regs))
> +               return PTR_ERR(dp->regs);
> +
> +       dp->phy_24m = devm_clk_get(dev, "24m");
> +       if (IS_ERR(dp->phy_24m)) {
> +               dev_err(dev, "cannot get clock 24m\n");
> +               return PTR_ERR(dp->phy_24m);
> +       }

The binding says there are 2 clocks.

> +
> +       dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
> +       if (IS_ERR(dp->grf)) {
> +               dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
> +               return PTR_ERR(dp->grf);
> +       }
> +
> +       ret = regmap_write(dp->grf, GRF_SOC_CON12,
> +                          GRF_EDP_REF_CLK_SEL_INTER |
> +                          (GRF_EDP_REF_CLK_SEL_INTER << 16));
> +       if (ret != 0) {
> +               dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
> +               return ret;
> +       }
> +
> +       phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
> +       if (IS_ERR(phy)) {
> +               dev_err(dev, "failed to create phy\n");
> +               return PTR_ERR(phy);
> +       }
> +       phy_set_drvdata(phy, dp);
> +
> +       phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> +       return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
> +       { .compatible = "rockchip,rk3288-dp-phy" },
> +       {}
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
> +
> +static struct platform_driver rockchip_dp_phy_driver = {
> +       .probe          = rockchip_dp_phy_probe,
> +       .driver         = {
> +               .name   = "rockchip-dp-phy",
> +               .of_match_table = rockchip_dp_phy_dt_ids,
> +       },
> +};
> +
> +module_platform_driver(rockchip_dp_phy_driver);
> +
> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.1.2
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-02 13:27     ` Rob Herring
  0 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-02 13:27 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	Russell King, djkurtz, dianders, seanpaul, Ajay kumar,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel

On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Kishon suggest, add commit message, and remove the redundant
>   rockchip_dp_phy_init() function, move those code to probe() method.
>   And remove driver .owner number.
>
> Changes in v3:
> - Take Heiko suggest, add rockchip dp phy driver,
>   collect the phy clocks and power control.
>
> Changes in v2: None
>
>  .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++

It is preferred that you split binding doc's from driver changes.

>  drivers/phy/Kconfig                                |   7 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-rockchip-dp.c                      | 166 +++++++++++++++++++++
>  4 files changed, 200 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>  create mode 100644 drivers/phy/phy-rockchip-dp.c
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> new file mode 100644
> index 0000000..5de1088
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> @@ -0,0 +1,26 @@
> +Rockchip Soc Seroes Display Port PHY
> +------------------------------------
> +
> +Required properties:
> +- compatible : should be one of the following supported values:
> +        - "rockchip.rk3288-dp-phy"
> +
> +- reg : a list of registers used by phy driver

Please state the size of the list and order of what each entry if more than one.

> +- clocks: from common clock binding: handle to dp clock.
> +       of memory mapped region.
> +- clock-names: from common clock binding:
> +       Required elements: "sclk_dp" "sclk_dp_24m"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.

I have no idea what GRF means.

> +- #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Example:
> +
> +edp_phy: phy@ff770274 {
> +       compatilble = "rockchip,rk3288-dp-phy";
> +       reg = <0xff770274 4>;
> +       rockchip,grf = <&grf>;
> +       clocks = <&cru SCLK_EDP_24M>;
> +       clock-names = "24m";
> +       #phy-cells = <0>;
> +}
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573..8f2bc4f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>         help
>           Enable this to support the Rockchip USB 2.0 PHY.
>
> +config PHY_ROCKCHIP_DP
> +       tristate "Rockchip Display Port PHY Driver"
> +       depends on ARCH_ROCKCHIP && OF
> +       select GENERIC_PHY
> +       help
> +         Enable this to support the Rockchip Display Port PHY.
> +
>  config PHY_ST_SPEAR1310_MIPHY
>         tristate "ST SPEAR1310-MIPHY driver"
>         select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a5b18c1..e281f35 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)    += phy-s5pv210-usb2.o
>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)       += phy-exynos5-usbdrd.o
>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)    += phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP)          += phy-rockchip-dp.o
>  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)    += phy-qcom-ipq806x-sata.o
>  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)   += phy-spear1310-miphy.o
>  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)   += phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..e9a726e
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,166 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12                   0x0274
> +#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
> +
> +#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
> +#define DP_PHY_SIDDQ_ON                 0
> +#define DP_PHY_SIDDQ_OFF                BIT(5)
> +
> +struct rockchip_dp_phy {
> +       struct device  *dev;
> +       struct regmap  *grf;
> +       void __iomem   *regs;
> +       struct clk     *phy_24m;
> +};
> +
> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
> +{
> +       int ret = 0;
> +
> +       ret = clk_set_rate(dp->phy_24m, 24000000);

Do you need to do this every time? This can go in probe.

> +       if (ret < 0) {
> +               dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
> +               return ret;
> +       }
> +
> +       ret = clk_prepare_enable(dp->phy_24m);
> +       if (ret < 0) {
> +               dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
> +{
> +       clk_disable_unprepare(dp->phy_24m);
> +
> +       return 0;
> +}
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> +       struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> +
> +       if (enable) {
> +               rockchip_dp_phy_clk_enable(dp);
> +               writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
> +       } else {
> +               rockchip_dp_phy_clk_disable(dp);
> +               writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
> +       }
> +
> +       return 0;
> +}

I would just inline all 3 of these functions. The wrappers don't
doesn't do anything, but add 2 levels of function calls.

> +
> +static int rockchip_dp_phy_power_on(struct phy *phy)
> +{
> +       return rockchip_set_phy_state(phy, true);
> +}
> +
> +static int rockchip_dp_phy_power_off(struct phy *phy)
> +{
> +       return rockchip_set_phy_state(phy, false);
> +}
> +
> +static struct phy_ops rockchip_dp_phy_ops = {
> +       .power_on       = rockchip_dp_phy_power_on,
> +       .power_off      = rockchip_dp_phy_power_off,
> +       .owner          = THIS_MODULE,
> +};
> +
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct device_node *np = dev->of_node;
> +       struct phy_provider *phy_provider;
> +       struct rockchip_dp_phy *dp;
> +       struct resource *res;
> +       struct phy *phy;
> +       int ret;
> +
> +       dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
> +       if (IS_ERR(dp))
> +               return -ENOMEM;
> +
> +       dp->dev = dev;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       dp->regs = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(dp->regs))
> +               return PTR_ERR(dp->regs);
> +
> +       dp->phy_24m = devm_clk_get(dev, "24m");
> +       if (IS_ERR(dp->phy_24m)) {
> +               dev_err(dev, "cannot get clock 24m\n");
> +               return PTR_ERR(dp->phy_24m);
> +       }

The binding says there are 2 clocks.

> +
> +       dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
> +       if (IS_ERR(dp->grf)) {
> +               dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
> +               return PTR_ERR(dp->grf);
> +       }
> +
> +       ret = regmap_write(dp->grf, GRF_SOC_CON12,
> +                          GRF_EDP_REF_CLK_SEL_INTER |
> +                          (GRF_EDP_REF_CLK_SEL_INTER << 16));
> +       if (ret != 0) {
> +               dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
> +               return ret;
> +       }
> +
> +       phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
> +       if (IS_ERR(phy)) {
> +               dev_err(dev, "failed to create phy\n");
> +               return PTR_ERR(phy);
> +       }
> +       phy_set_drvdata(phy, dp);
> +
> +       phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> +       return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
> +       { .compatible = "rockchip,rk3288-dp-phy" },
> +       {}
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
> +
> +static struct platform_driver rockchip_dp_phy_driver = {
> +       .probe          = rockchip_dp_phy_probe,
> +       .driver         = {
> +               .name   = "rockchip-dp-phy",
> +               .of_match_table = rockchip_dp_phy_dt_ids,
> +       },
> +};
> +
> +module_platform_driver(rockchip_dp_phy_driver);
> +
> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.1.2
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-02 13:27     ` Rob Herring
  0 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-02 13:27 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Kishon suggest, add commit message, and remove the redundant
>   rockchip_dp_phy_init() function, move those code to probe() method.
>   And remove driver .owner number.
>
> Changes in v3:
> - Take Heiko suggest, add rockchip dp phy driver,
>   collect the phy clocks and power control.
>
> Changes in v2: None
>
>  .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++

It is preferred that you split binding doc's from driver changes.

>  drivers/phy/Kconfig                                |   7 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-rockchip-dp.c                      | 166 +++++++++++++++++++++
>  4 files changed, 200 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>  create mode 100644 drivers/phy/phy-rockchip-dp.c
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> new file mode 100644
> index 0000000..5de1088
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> @@ -0,0 +1,26 @@
> +Rockchip Soc Seroes Display Port PHY
> +------------------------------------
> +
> +Required properties:
> +- compatible : should be one of the following supported values:
> +        - "rockchip.rk3288-dp-phy"
> +
> +- reg : a list of registers used by phy driver

Please state the size of the list and order of what each entry if more than one.

> +- clocks: from common clock binding: handle to dp clock.
> +       of memory mapped region.
> +- clock-names: from common clock binding:
> +       Required elements: "sclk_dp" "sclk_dp_24m"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.

I have no idea what GRF means.

> +- #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Example:
> +
> +edp_phy: phy at ff770274 {
> +       compatilble = "rockchip,rk3288-dp-phy";
> +       reg = <0xff770274 4>;
> +       rockchip,grf = <&grf>;
> +       clocks = <&cru SCLK_EDP_24M>;
> +       clock-names = "24m";
> +       #phy-cells = <0>;
> +}
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573..8f2bc4f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>         help
>           Enable this to support the Rockchip USB 2.0 PHY.
>
> +config PHY_ROCKCHIP_DP
> +       tristate "Rockchip Display Port PHY Driver"
> +       depends on ARCH_ROCKCHIP && OF
> +       select GENERIC_PHY
> +       help
> +         Enable this to support the Rockchip Display Port PHY.
> +
>  config PHY_ST_SPEAR1310_MIPHY
>         tristate "ST SPEAR1310-MIPHY driver"
>         select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a5b18c1..e281f35 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)    += phy-s5pv210-usb2.o
>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)       += phy-exynos5-usbdrd.o
>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)    += phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP)          += phy-rockchip-dp.o
>  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)    += phy-qcom-ipq806x-sata.o
>  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)   += phy-spear1310-miphy.o
>  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)   += phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..e9a726e
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,166 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12                   0x0274
> +#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
> +
> +#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
> +#define DP_PHY_SIDDQ_ON                 0
> +#define DP_PHY_SIDDQ_OFF                BIT(5)
> +
> +struct rockchip_dp_phy {
> +       struct device  *dev;
> +       struct regmap  *grf;
> +       void __iomem   *regs;
> +       struct clk     *phy_24m;
> +};
> +
> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
> +{
> +       int ret = 0;
> +
> +       ret = clk_set_rate(dp->phy_24m, 24000000);

Do you need to do this every time? This can go in probe.

> +       if (ret < 0) {
> +               dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
> +               return ret;
> +       }
> +
> +       ret = clk_prepare_enable(dp->phy_24m);
> +       if (ret < 0) {
> +               dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
> +{
> +       clk_disable_unprepare(dp->phy_24m);
> +
> +       return 0;
> +}
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> +       struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> +
> +       if (enable) {
> +               rockchip_dp_phy_clk_enable(dp);
> +               writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
> +       } else {
> +               rockchip_dp_phy_clk_disable(dp);
> +               writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
> +       }
> +
> +       return 0;
> +}

I would just inline all 3 of these functions. The wrappers don't
doesn't do anything, but add 2 levels of function calls.

> +
> +static int rockchip_dp_phy_power_on(struct phy *phy)
> +{
> +       return rockchip_set_phy_state(phy, true);
> +}
> +
> +static int rockchip_dp_phy_power_off(struct phy *phy)
> +{
> +       return rockchip_set_phy_state(phy, false);
> +}
> +
> +static struct phy_ops rockchip_dp_phy_ops = {
> +       .power_on       = rockchip_dp_phy_power_on,
> +       .power_off      = rockchip_dp_phy_power_off,
> +       .owner          = THIS_MODULE,
> +};
> +
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct device_node *np = dev->of_node;
> +       struct phy_provider *phy_provider;
> +       struct rockchip_dp_phy *dp;
> +       struct resource *res;
> +       struct phy *phy;
> +       int ret;
> +
> +       dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
> +       if (IS_ERR(dp))
> +               return -ENOMEM;
> +
> +       dp->dev = dev;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       dp->regs = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(dp->regs))
> +               return PTR_ERR(dp->regs);
> +
> +       dp->phy_24m = devm_clk_get(dev, "24m");
> +       if (IS_ERR(dp->phy_24m)) {
> +               dev_err(dev, "cannot get clock 24m\n");
> +               return PTR_ERR(dp->phy_24m);
> +       }

The binding says there are 2 clocks.

> +
> +       dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
> +       if (IS_ERR(dp->grf)) {
> +               dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
> +               return PTR_ERR(dp->grf);
> +       }
> +
> +       ret = regmap_write(dp->grf, GRF_SOC_CON12,
> +                          GRF_EDP_REF_CLK_SEL_INTER |
> +                          (GRF_EDP_REF_CLK_SEL_INTER << 16));
> +       if (ret != 0) {
> +               dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
> +               return ret;
> +       }
> +
> +       phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
> +       if (IS_ERR(phy)) {
> +               dev_err(dev, "failed to create phy\n");
> +               return PTR_ERR(phy);
> +       }
> +       phy_set_drvdata(phy, dp);
> +
> +       phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> +       return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
> +       { .compatible = "rockchip,rk3288-dp-phy" },
> +       {}
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
> +
> +static struct platform_driver rockchip_dp_phy_driver = {
> +       .probe          = rockchip_dp_phy_probe,
> +       .driver         = {
> +               .name   = "rockchip-dp-phy",
> +               .of_match_table = rockchip_dp_phy_dt_ids,
> +       },
> +};
> +
> +module_platform_driver(rockchip_dp_phy_driver);
> +
> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.1.2
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
  2015-09-01  5:49   ` Yakir Yang
  (?)
@ 2015-09-02 14:50     ` Emil Velikov
  -1 siblings, 0 replies; 370+ messages in thread
From: Emil Velikov @ 2015-09-02 14:50 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, ML dri-devel,
	Andrzej Hajda, Gustavo Padovan,
	moderated list:ARM/S5P EXYNOS AR...,
	seanpaul, djkurtz, Kishon Vijay Abraham I, linux-rockchip,
	robherring2, Russell King, devicetree, Pawel Moll, Ian Campbell,
	Rob Herring, dianders, linux-arm-kernel,
	Linux-Kernel@Vger. Kernel. Org, Kyungmin Park, Kumar Gala,
	ajaynumb, Andy Yan

[Dropping the CC list]

Hi Yakir Yang,

On 1 September 2015 at 06:49, Yakir Yang <ykk@rock-chips.com> wrote:
> Split the dp core driver from exynos directory to bridge
> directory, and rename the core driver to analogix_dp_*,
> leave the platform code to analogix_dp-exynos.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
> - Take Archit suggest, create a separate folder for analogix code in bridge/
>
"Take X suggest", is grammatically incorrect. You should use
"suggestion(s)" or alternatively use the following approach.

- Create a separate folder for analogix code in bridge/ (Archit)

Cheers,
Emil

P.S. Why do you resend the whole series (some 10+ patches) when only a
few patches have been changed ? Are all the patches changed whist
missing that information (vX: rebase on top of A)

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-02 14:50     ` Emil Velikov
  0 siblings, 0 replies; 370+ messages in thread
From: Emil Velikov @ 2015-09-02 14:50 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, ML dri-devel,
	Andrzej Hajda, Gustavo Padovan,
	moderated list:ARM/S5P EXYNOS AR...,
	seanpaul, djkurtz, Kishon Vijay Abraham I, linux-rockchip,
	robherring2, Russell King, devicetree, Pawel Moll, Ian Campbell,
	Rob Herring, dianders, linux-arm-kernel, Linu

[Dropping the CC list]

Hi Yakir Yang,

On 1 September 2015 at 06:49, Yakir Yang <ykk@rock-chips.com> wrote:
> Split the dp core driver from exynos directory to bridge
> directory, and rename the core driver to analogix_dp_*,
> leave the platform code to analogix_dp-exynos.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
> - Take Archit suggest, create a separate folder for analogix code in bridge/
>
"Take X suggest", is grammatically incorrect. You should use
"suggestion(s)" or alternatively use the following approach.

- Create a separate folder for analogix code in bridge/ (Archit)

Cheers,
Emil

P.S. Why do you resend the whole series (some 10+ patches) when only a
few patches have been changed ? Are all the patches changed whist
missing that information (vX: rebase on top of A)

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-02 14:50     ` Emil Velikov
  0 siblings, 0 replies; 370+ messages in thread
From: Emil Velikov @ 2015-09-02 14:50 UTC (permalink / raw)
  To: linux-arm-kernel

[Dropping the CC list]

Hi Yakir Yang,

On 1 September 2015 at 06:49, Yakir Yang <ykk@rock-chips.com> wrote:
> Split the dp core driver from exynos directory to bridge
> directory, and rename the core driver to analogix_dp_*,
> leave the platform code to analogix_dp-exynos.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
> - Take Archit suggest, create a separate folder for analogix code in bridge/
>
"Take X suggest", is grammatically incorrect. You should use
"suggestion(s)" or alternatively use the following approach.

- Create a separate folder for analogix code in bridge/ (Archit)

Cheers,
Emil

P.S. Why do you resend the whole series (some 10+ patches) when only a
few patches have been changed ? Are all the patches changed whist
missing that information (vX: rebase on top of A)

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-02 20:17     ` Rob Herring
  0 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-02 20:17 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	Russell King, djkurtz, dianders, seanpaul, Ajay kumar,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> Some edp screen do not have hpd signal, so we can't just return
> failed when hpd plug in detect failed.

This is a property of the panel (or connector perhaps), so this
property should be located there. At least, it is a common issue and
not specific to this chip. We could have an HDMI connector and failed
to hook up HPD for example. A connector node is also where hpd-gpios
should be located instead (and are already defined by
../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
binding, too.

Are there any eDP panels which don't have EDID and need panel details in DT?

Rob

> This is an hardware property, so we need add a devicetree property
> "analogix,need-force-hpd" to indicate this sutiation.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4: None
> Changes in v3:
> - Add "analogix,need-force-hpd" to indicate whether driver need foce
>   hpd when hpd detect failed.
>
> Changes in v2: None
>
>  .../devicetree/bindings/drm/bridge/analogix_dp.txt |  4 ++-
>  .../bindings/video/analogix_dp-rockchip.txt        |  1 +
>  .../devicetree/bindings/video/exynos_dp.txt        |  1 +
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
>  6 files changed, 47 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> index f54dc3e..c310367 100644
> --- a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> +++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> @@ -22,6 +22,9 @@ Required properties for dp-controller:
>                 from general PHY binding: Should be "dp".
>
>  Optional properties for dp-controller:
> +       -analogix,need-force-hpd:
> +               Indicate driver need force hpd when hpd detect failed, this
> +               is used for some eDP screen which don't have hpd signal.
>         -hpd-gpios:
>                 Hotplug detect GPIO.
>                 Indicates which GPIO should be used for hotplug detection
> @@ -31,7 +34,6 @@ Optional properties for dp-controller:
>                 * Documentation/devicetree/bindings/video/exynos_dp.txt
>                 * Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>
> -
>  [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
>  -------------------------------------------------------------------------------
>
> diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> index 502483e..8b9ed7d 100644
> --- a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> @@ -28,6 +28,7 @@ For the below properties, please refer to Analogix DP binding document:
>  - phys (required)
>  - phy-names (required)
>  - hpd-gpios (optional)
> +- analogix,need-force-hpd (optional)
>  -------------------------------------------------------------------------------
>
>  Example:
> diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
> index ea03b3a..4f06e80 100644
> --- a/Documentation/devicetree/bindings/video/exynos_dp.txt
> +++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
> @@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
>         -phys (required)
>         -phy-names (required)
>         -hpd-gpios (optional)
> +       -analogix,need-force-hpd (optional)
>         -video interfaces (optional)
>
>  Deprecated properties for DisplayPort:
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index f7227ec..e6b328a 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -63,15 +63,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
>  {
>         int timeout_loop = 0;
>
> -       while (analogix_dp_get_plug_in_status(dp) != 0) {
> +       while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
> +               if (analogix_dp_get_plug_in_status(dp) == 0)
> +                       return 0;
> +
>                 timeout_loop++;
> -               if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> -                       dev_err(dp->dev, "failed to get hpd plug status\n");
> -                       return -ETIMEDOUT;
> -               }
>                 usleep_range(10, 11);
>         }
>
> +       /*
> +        * Some edp screen do not have hpd signal, so we can't just
> +        * return failed when hpd plug in detect failed, DT property
> +        * "need-force-hpd" would indicate whether driver need this.
> +        */
> +       if (!dp->need_force_hpd)
> +               return -ETIMEDOUT;
> +
> +       /*
> +        * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
> +        * will not work, so we need to give a force hpd action to
> +        * set HPD_STATUS manually.
> +        */
> +       dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
> +
> +       analogix_dp_force_hpd(dp);
> +
> +       if (analogix_dp_get_plug_in_status(dp) != 0) {
> +               dev_err(dp->dev, "failed to get hpd plug in status\n");
> +               return -EINVAL;
> +       }
> +
> +       dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
> +
>         return 0;
>  }
>
> @@ -1287,6 +1310,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>         if (IS_ERR(dp->reg_base))
>                 return PTR_ERR(dp->reg_base);
>
> +       dp->need_force_hpd =
> +               of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
> +
>         dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
>         if (gpio_is_valid(dp->hpd_gpio))
>                 dp->hpd_gpio = of_get_named_gpio(dev->of_node,
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> index d8945e2..6960ab3 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> @@ -160,6 +160,7 @@ struct analogix_dp_device {
>         struct phy              *phy;
>         int                     dpms_mode;
>         int                     hpd_gpio;
> +       bool                    need_force_hpd;
>
>         struct analogix_dp_plat_data *plat_data;
>  };
> @@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
>                                        bool enable);
>  void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
>  void analogix_dp_init_hpd(struct analogix_dp_device *dp);
> +void analogix_dp_force_hpd(struct analogix_dp_device *dp);
>  enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
>  void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
>  void analogix_dp_reset_aux(struct analogix_dp_device *dp);
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index 15346fe..3086afc 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
>         writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
>  }
>
> +void analogix_dp_force_hpd(struct analogix_dp_device *dp)
> +{
> +       u32 reg;
> +
> +       reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
> +       reg = (F_HPD | HPD_CTRL);
> +       writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
> +}
> +
>  enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
>  {
>         u32 reg;
> --
> 2.1.2
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-02 20:17     ` Rob Herring
  0 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-02 20:17 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	Russell King, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	dianders-F7+t8E8rja9Wk0Htik3J/w, seanpaul-F7+t8E8rja9Wk0Htik3J/w,
	Ajay kumar, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I,
	architt-sgV2jX0FEOL9JmXXK+q4OQ, dri-devel

On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
> Some edp screen do not have hpd signal, so we can't just return
> failed when hpd plug in detect failed.

This is a property of the panel (or connector perhaps), so this
property should be located there. At least, it is a common issue and
not specific to this chip. We could have an HDMI connector and failed
to hook up HPD for example. A connector node is also where hpd-gpios
should be located instead (and are already defined by
../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
binding, too.

Are there any eDP panels which don't have EDID and need panel details in DT?

Rob

> This is an hardware property, so we need add a devicetree property
> "analogix,need-force-hpd" to indicate this sutiation.
>
> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> Changes in v4: None
> Changes in v3:
> - Add "analogix,need-force-hpd" to indicate whether driver need foce
>   hpd when hpd detect failed.
>
> Changes in v2: None
>
>  .../devicetree/bindings/drm/bridge/analogix_dp.txt |  4 ++-
>  .../bindings/video/analogix_dp-rockchip.txt        |  1 +
>  .../devicetree/bindings/video/exynos_dp.txt        |  1 +
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
>  6 files changed, 47 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> index f54dc3e..c310367 100644
> --- a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> +++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> @@ -22,6 +22,9 @@ Required properties for dp-controller:
>                 from general PHY binding: Should be "dp".
>
>  Optional properties for dp-controller:
> +       -analogix,need-force-hpd:
> +               Indicate driver need force hpd when hpd detect failed, this
> +               is used for some eDP screen which don't have hpd signal.
>         -hpd-gpios:
>                 Hotplug detect GPIO.
>                 Indicates which GPIO should be used for hotplug detection
> @@ -31,7 +34,6 @@ Optional properties for dp-controller:
>                 * Documentation/devicetree/bindings/video/exynos_dp.txt
>                 * Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>
> -
>  [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
>  -------------------------------------------------------------------------------
>
> diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> index 502483e..8b9ed7d 100644
> --- a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> @@ -28,6 +28,7 @@ For the below properties, please refer to Analogix DP binding document:
>  - phys (required)
>  - phy-names (required)
>  - hpd-gpios (optional)
> +- analogix,need-force-hpd (optional)
>  -------------------------------------------------------------------------------
>
>  Example:
> diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
> index ea03b3a..4f06e80 100644
> --- a/Documentation/devicetree/bindings/video/exynos_dp.txt
> +++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
> @@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
>         -phys (required)
>         -phy-names (required)
>         -hpd-gpios (optional)
> +       -analogix,need-force-hpd (optional)
>         -video interfaces (optional)
>
>  Deprecated properties for DisplayPort:
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index f7227ec..e6b328a 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -63,15 +63,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
>  {
>         int timeout_loop = 0;
>
> -       while (analogix_dp_get_plug_in_status(dp) != 0) {
> +       while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
> +               if (analogix_dp_get_plug_in_status(dp) == 0)
> +                       return 0;
> +
>                 timeout_loop++;
> -               if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> -                       dev_err(dp->dev, "failed to get hpd plug status\n");
> -                       return -ETIMEDOUT;
> -               }
>                 usleep_range(10, 11);
>         }
>
> +       /*
> +        * Some edp screen do not have hpd signal, so we can't just
> +        * return failed when hpd plug in detect failed, DT property
> +        * "need-force-hpd" would indicate whether driver need this.
> +        */
> +       if (!dp->need_force_hpd)
> +               return -ETIMEDOUT;
> +
> +       /*
> +        * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
> +        * will not work, so we need to give a force hpd action to
> +        * set HPD_STATUS manually.
> +        */
> +       dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
> +
> +       analogix_dp_force_hpd(dp);
> +
> +       if (analogix_dp_get_plug_in_status(dp) != 0) {
> +               dev_err(dp->dev, "failed to get hpd plug in status\n");
> +               return -EINVAL;
> +       }
> +
> +       dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
> +
>         return 0;
>  }
>
> @@ -1287,6 +1310,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>         if (IS_ERR(dp->reg_base))
>                 return PTR_ERR(dp->reg_base);
>
> +       dp->need_force_hpd =
> +               of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
> +
>         dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
>         if (gpio_is_valid(dp->hpd_gpio))
>                 dp->hpd_gpio = of_get_named_gpio(dev->of_node,
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> index d8945e2..6960ab3 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> @@ -160,6 +160,7 @@ struct analogix_dp_device {
>         struct phy              *phy;
>         int                     dpms_mode;
>         int                     hpd_gpio;
> +       bool                    need_force_hpd;
>
>         struct analogix_dp_plat_data *plat_data;
>  };
> @@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
>                                        bool enable);
>  void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
>  void analogix_dp_init_hpd(struct analogix_dp_device *dp);
> +void analogix_dp_force_hpd(struct analogix_dp_device *dp);
>  enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
>  void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
>  void analogix_dp_reset_aux(struct analogix_dp_device *dp);
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index 15346fe..3086afc 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
>         writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
>  }
>
> +void analogix_dp_force_hpd(struct analogix_dp_device *dp)
> +{
> +       u32 reg;
> +
> +       reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
> +       reg = (F_HPD | HPD_CTRL);
> +       writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
> +}
> +
>  enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
>  {
>         u32 reg;
> --
> 2.1.2
>
>
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-02 20:17     ` Rob Herring
  0 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-02 20:17 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> Some edp screen do not have hpd signal, so we can't just return
> failed when hpd plug in detect failed.

This is a property of the panel (or connector perhaps), so this
property should be located there. At least, it is a common issue and
not specific to this chip. We could have an HDMI connector and failed
to hook up HPD for example. A connector node is also where hpd-gpios
should be located instead (and are already defined by
../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
binding, too.

Are there any eDP panels which don't have EDID and need panel details in DT?

Rob

> This is an hardware property, so we need add a devicetree property
> "analogix,need-force-hpd" to indicate this sutiation.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4: None
> Changes in v3:
> - Add "analogix,need-force-hpd" to indicate whether driver need foce
>   hpd when hpd detect failed.
>
> Changes in v2: None
>
>  .../devicetree/bindings/drm/bridge/analogix_dp.txt |  4 ++-
>  .../bindings/video/analogix_dp-rockchip.txt        |  1 +
>  .../devicetree/bindings/video/exynos_dp.txt        |  1 +
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
>  6 files changed, 47 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> index f54dc3e..c310367 100644
> --- a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> +++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> @@ -22,6 +22,9 @@ Required properties for dp-controller:
>                 from general PHY binding: Should be "dp".
>
>  Optional properties for dp-controller:
> +       -analogix,need-force-hpd:
> +               Indicate driver need force hpd when hpd detect failed, this
> +               is used for some eDP screen which don't have hpd signal.
>         -hpd-gpios:
>                 Hotplug detect GPIO.
>                 Indicates which GPIO should be used for hotplug detection
> @@ -31,7 +34,6 @@ Optional properties for dp-controller:
>                 * Documentation/devicetree/bindings/video/exynos_dp.txt
>                 * Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>
> -
>  [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
>  -------------------------------------------------------------------------------
>
> diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> index 502483e..8b9ed7d 100644
> --- a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
> @@ -28,6 +28,7 @@ For the below properties, please refer to Analogix DP binding document:
>  - phys (required)
>  - phy-names (required)
>  - hpd-gpios (optional)
> +- analogix,need-force-hpd (optional)
>  -------------------------------------------------------------------------------
>
>  Example:
> diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
> index ea03b3a..4f06e80 100644
> --- a/Documentation/devicetree/bindings/video/exynos_dp.txt
> +++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
> @@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
>         -phys (required)
>         -phy-names (required)
>         -hpd-gpios (optional)
> +       -analogix,need-force-hpd (optional)
>         -video interfaces (optional)
>
>  Deprecated properties for DisplayPort:
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index f7227ec..e6b328a 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -63,15 +63,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
>  {
>         int timeout_loop = 0;
>
> -       while (analogix_dp_get_plug_in_status(dp) != 0) {
> +       while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
> +               if (analogix_dp_get_plug_in_status(dp) == 0)
> +                       return 0;
> +
>                 timeout_loop++;
> -               if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> -                       dev_err(dp->dev, "failed to get hpd plug status\n");
> -                       return -ETIMEDOUT;
> -               }
>                 usleep_range(10, 11);
>         }
>
> +       /*
> +        * Some edp screen do not have hpd signal, so we can't just
> +        * return failed when hpd plug in detect failed, DT property
> +        * "need-force-hpd" would indicate whether driver need this.
> +        */
> +       if (!dp->need_force_hpd)
> +               return -ETIMEDOUT;
> +
> +       /*
> +        * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
> +        * will not work, so we need to give a force hpd action to
> +        * set HPD_STATUS manually.
> +        */
> +       dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
> +
> +       analogix_dp_force_hpd(dp);
> +
> +       if (analogix_dp_get_plug_in_status(dp) != 0) {
> +               dev_err(dp->dev, "failed to get hpd plug in status\n");
> +               return -EINVAL;
> +       }
> +
> +       dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
> +
>         return 0;
>  }
>
> @@ -1287,6 +1310,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>         if (IS_ERR(dp->reg_base))
>                 return PTR_ERR(dp->reg_base);
>
> +       dp->need_force_hpd =
> +               of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
> +
>         dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
>         if (gpio_is_valid(dp->hpd_gpio))
>                 dp->hpd_gpio = of_get_named_gpio(dev->of_node,
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> index d8945e2..6960ab3 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> @@ -160,6 +160,7 @@ struct analogix_dp_device {
>         struct phy              *phy;
>         int                     dpms_mode;
>         int                     hpd_gpio;
> +       bool                    need_force_hpd;
>
>         struct analogix_dp_plat_data *plat_data;
>  };
> @@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
>                                        bool enable);
>  void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
>  void analogix_dp_init_hpd(struct analogix_dp_device *dp);
> +void analogix_dp_force_hpd(struct analogix_dp_device *dp);
>  enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
>  void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
>  void analogix_dp_reset_aux(struct analogix_dp_device *dp);
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index 15346fe..3086afc 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
>         writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
>  }
>
> +void analogix_dp_force_hpd(struct analogix_dp_device *dp)
> +{
> +       u32 reg;
> +
> +       reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
> +       reg = (F_HPD | HPD_CTRL);
> +       writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
> +}
> +
>  enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
>  {
>         u32 reg;
> --
> 2.1.2
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 07/16] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
  2015-09-01  6:01   ` Yakir Yang
@ 2015-09-03  0:01     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-03  0:01 UTC (permalink / raw)
  To: Yakir Yang, Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

On 01.09.2015 15:01, Yakir Yang wrote:
> After exynos_dp have been splited the common IP code into analogix_dp driver,
s/splited/split/

> the analogix_dp driver have deprecated some samsung platform properties which

s/samsung/Samsung/

> could be dynamic parsed from EDID/MODE/DPCD message, so this is an update for

s/dynamic/dynamically/

> exynos DTS file for dp-controller.
/exynos/Exynos/

> 
> Beside analogix_dp have provide the backward compatibility, so there are no
> bisectability break that make this change in a separate patch.

It took me some time to figure out the meaning of this sentence... Did
you want to say that backward compatibility is fully preserved?

You are removing samsung,dynamic-range and samsung,ycbcr-coeff. I would
assume that now:
1. on all these board these values would be parsed from EDID/MODE/DPCD
message?
2. everything would work as previously?
Am I understanding it correctly?

The patch itself looks good.

Best regards,
Krzysztof


> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Krzysztof suggest, separate all DTS changes to a separate patch.
> 
> Changes in v3: None
> Changes in v2: None
> 
>  arch/arm/boot/dts/exynos5250-arndale.dts   | 2 --
>  arch/arm/boot/dts/exynos5250-smdk5250.dts  | 2 --
>  arch/arm/boot/dts/exynos5250-snow.dts      | 4 +---
>  arch/arm/boot/dts/exynos5250-spring.dts    | 4 +---
>  arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
>  arch/arm/boot/dts/exynos5420-smdk5420.dts  | 2 --
>  arch/arm/boot/dts/exynos5800-peach-pi.dts  | 4 +---
>  7 files changed, 4 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
> index db3f65f..4636862 100644
> --- a/arch/arm/boot/dts/exynos5250-arndale.dts
> +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
> @@ -124,8 +124,6 @@
>  &dp {
>  	status = "okay";
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x0a>;
>  	samsung,lane-count = <4>;
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index c625e71..cd424d6 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -80,8 +80,6 @@
>  
>  &dp {
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x0a>;
>  	samsung,lane-count = <4>;
> diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
> index 0720caa..242b621 100644
> --- a/arch/arm/boot/dts/exynos5250-snow.dts
> +++ b/arch/arm/boot/dts/exynos5250-snow.dts
> @@ -244,12 +244,10 @@
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&dp_hpd>;
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x0a>;
>  	samsung,lane-count = <2>;
> -	samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
> +	hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
>  
>  	ports {
>  		port@0 {
> diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
> index c1edd6d..91881d7 100644
> --- a/arch/arm/boot/dts/exynos5250-spring.dts
> +++ b/arch/arm/boot/dts/exynos5250-spring.dts
> @@ -74,12 +74,10 @@
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&dp_hpd_gpio>;
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x0a>;
>  	samsung,lane-count = <1>;
> -	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
> +	hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
>  };
>  
>  &ehci {
> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> index 8f4d76c..7433683 100644
> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> @@ -148,12 +148,10 @@
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&dp_hpd_gpio>;
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x06>;
>  	samsung,lane-count = <2>;
> -	samsung,hpd-gpio = <&gpx2 6 0>;
> +	hpd-gpio = <&gpx2 6 0>;
>  
>  	ports {
>  		port@0 {
> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> index 98871f9..b3df3c1 100644
> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> @@ -92,8 +92,6 @@
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&dp_hpd>;
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x0a>;
>  	samsung,lane-count = <4>;
> diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> index 7d5b386..b89bff5 100644
> --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
> +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> @@ -142,12 +142,10 @@
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&dp_hpd_gpio>;
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x0a>;
>  	samsung,lane-count = <2>;
> -	samsung,hpd-gpio = <&gpx2 6 0>;
> +	hpd-gpios = <&gpx2 6 0>;
>  	panel = <&panel>;
>  };
>  
> 


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 07/16] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
@ 2015-09-03  0:01     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-03  0:01 UTC (permalink / raw)
  To: linux-arm-kernel

On 01.09.2015 15:01, Yakir Yang wrote:
> After exynos_dp have been splited the common IP code into analogix_dp driver,
s/splited/split/

> the analogix_dp driver have deprecated some samsung platform properties which

s/samsung/Samsung/

> could be dynamic parsed from EDID/MODE/DPCD message, so this is an update for

s/dynamic/dynamically/

> exynos DTS file for dp-controller.
/exynos/Exynos/

> 
> Beside analogix_dp have provide the backward compatibility, so there are no
> bisectability break that make this change in a separate patch.

It took me some time to figure out the meaning of this sentence... Did
you want to say that backward compatibility is fully preserved?

You are removing samsung,dynamic-range and samsung,ycbcr-coeff. I would
assume that now:
1. on all these board these values would be parsed from EDID/MODE/DPCD
message?
2. everything would work as previously?
Am I understanding it correctly?

The patch itself looks good.

Best regards,
Krzysztof


> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Krzysztof suggest, separate all DTS changes to a separate patch.
> 
> Changes in v3: None
> Changes in v2: None
> 
>  arch/arm/boot/dts/exynos5250-arndale.dts   | 2 --
>  arch/arm/boot/dts/exynos5250-smdk5250.dts  | 2 --
>  arch/arm/boot/dts/exynos5250-snow.dts      | 4 +---
>  arch/arm/boot/dts/exynos5250-spring.dts    | 4 +---
>  arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
>  arch/arm/boot/dts/exynos5420-smdk5420.dts  | 2 --
>  arch/arm/boot/dts/exynos5800-peach-pi.dts  | 4 +---
>  7 files changed, 4 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
> index db3f65f..4636862 100644
> --- a/arch/arm/boot/dts/exynos5250-arndale.dts
> +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
> @@ -124,8 +124,6 @@
>  &dp {
>  	status = "okay";
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x0a>;
>  	samsung,lane-count = <4>;
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> index c625e71..cd424d6 100644
> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -80,8 +80,6 @@
>  
>  &dp {
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x0a>;
>  	samsung,lane-count = <4>;
> diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
> index 0720caa..242b621 100644
> --- a/arch/arm/boot/dts/exynos5250-snow.dts
> +++ b/arch/arm/boot/dts/exynos5250-snow.dts
> @@ -244,12 +244,10 @@
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&dp_hpd>;
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x0a>;
>  	samsung,lane-count = <2>;
> -	samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
> +	hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
>  
>  	ports {
>  		port at 0 {
> diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
> index c1edd6d..91881d7 100644
> --- a/arch/arm/boot/dts/exynos5250-spring.dts
> +++ b/arch/arm/boot/dts/exynos5250-spring.dts
> @@ -74,12 +74,10 @@
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&dp_hpd_gpio>;
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x0a>;
>  	samsung,lane-count = <1>;
> -	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
> +	hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
>  };
>  
>  &ehci {
> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> index 8f4d76c..7433683 100644
> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> @@ -148,12 +148,10 @@
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&dp_hpd_gpio>;
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x06>;
>  	samsung,lane-count = <2>;
> -	samsung,hpd-gpio = <&gpx2 6 0>;
> +	hpd-gpio = <&gpx2 6 0>;
>  
>  	ports {
>  		port at 0 {
> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> index 98871f9..b3df3c1 100644
> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> @@ -92,8 +92,6 @@
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&dp_hpd>;
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x0a>;
>  	samsung,lane-count = <4>;
> diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> index 7d5b386..b89bff5 100644
> --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
> +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
> @@ -142,12 +142,10 @@
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&dp_hpd_gpio>;
>  	samsung,color-space = <0>;
> -	samsung,dynamic-range = <0>;
> -	samsung,ycbcr-coeff = <0>;
>  	samsung,color-depth = <1>;
>  	samsung,link-rate = <0x0a>;
>  	samsung,lane-count = <2>;
> -	samsung,hpd-gpio = <&gpx2 6 0>;
> +	hpd-gpios = <&gpx2 6 0>;
>  	panel = <&panel>;
>  };
>  
> 

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 01/16] drm: exynos/dp: fix code style
  2015-09-01  5:46   ` Yakir Yang
@ 2015-09-03  0:21     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-03  0:21 UTC (permalink / raw)
  To: Yakir Yang, Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

On 01.09.2015 14:46, Yakir Yang wrote:
> After run "checkpatch.pl -f --subjective" command, I see there
> are lots of alignment problem in exynos_dp driver, so let just
> fix them.

Hi,

Warnings from checkpatch are not a reason for a commit. Reason for a
commit could be for example an unreadable code, violation of
coding-style leading to decrease in code maintainability or just
improving the code readability so it will be easier to review and
maintain it.

You do not make commits because some tool tells you that. We do not
listen to machines :) ... If that would be the case, the commit could be
made automatically, without human interaction. Such automated commit
could be even easily tested by the machine by comparing object files.

Especially that you enabled "subjective" rule. This is not a valid
motivation for a commit.

Please rephrase this to sensible reason and convince that change is
worth the effort.

> 
> - Take Romain suggest, rebase on linux-next branch

That comment seems unrelated to the commit. Please remove it.

> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Take Joe Preches advise, improved commit message more readable, and
>   avoid using some uncommon style like bellow:
>   -  retval = exynos_dp_read_bytes_from_i2c(...
> 				...)
>   +  retval =
>   +  exynos_dp_read_bytes_from_i2c(......);
> 
>  drivers/gpu/drm/exynos/exynos_dp_core.c | 226 ++++++++++++++++----------------
>  drivers/gpu/drm/exynos/exynos_dp_core.h |  54 ++++----
>  drivers/gpu/drm/exynos/exynos_dp_reg.c  | 106 +++++++--------
>  3 files changed, 188 insertions(+), 198 deletions(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
> index d66ade0..266f7f7 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
> @@ -115,8 +115,8 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  
>  	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
>  	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> -				EDID_EXTENSION_FLAG,
> -				&extend_block);
> +					      EDID_EXTENSION_FLAG,
> +					      &extend_block);
>  	if (retval)
>  		return retval;
>  
> @@ -124,10 +124,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>  
>  		/* Read EDID data */
> -		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> -						EDID_HEADER_PATTERN,
> -						EDID_BLOCK_LENGTH,
> -						&edid[EDID_HEADER_PATTERN]);
> +		retval = exynos_dp_read_bytes_from_i2c(
> +					dp, I2C_EDID_DEVICE_ADDR,
> +					EDID_HEADER_PATTERN,
> +					EDID_BLOCK_LENGTH,
> +					&edid[EDID_HEADER_PATTERN]);
>  		if (retval != 0) {
>  			dev_err(dp->dev, "EDID Read failed!\n");
>  			return -EIO;
> @@ -139,11 +140,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  		}
>  
>  		/* Read additional EDID data */
> -		retval = exynos_dp_read_bytes_from_i2c(dp,
> -				I2C_EDID_DEVICE_ADDR,
> -				EDID_BLOCK_LENGTH,
> -				EDID_BLOCK_LENGTH,
> -				&edid[EDID_BLOCK_LENGTH]);
> +		retval = exynos_dp_read_bytes_from_i2c(
> +					dp, I2C_EDID_DEVICE_ADDR,
> +					EDID_BLOCK_LENGTH,
> +					EDID_BLOCK_LENGTH,
> +					&edid[EDID_BLOCK_LENGTH]);
>  		if (retval != 0) {
>  			dev_err(dp->dev, "EDID Read failed!\n");
>  			return -EIO;
> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  		}
>  
>  		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
> -					&test_vector);
> +					      &test_vector);
>  		if (test_vector & DP_TEST_LINK_EDID_READ) {
> -			exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TEST_EDID_CHECKSUM,
> +			exynos_dp_write_byte_to_dpcd(
> +				dp, DP_TEST_EDID_CHECKSUM,
>  				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
> -			exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TEST_RESPONSE,
> +			exynos_dp_write_byte_to_dpcd(
> +				dp, DP_TEST_RESPONSE,
>  				DP_TEST_EDID_CHECKSUM_WRITE);

To me, missing argument after opening parenthesis, looks worse. I would
prefer:

			exynos_dp_write_byte_to_dpcd(dp,

Why you moved the 'dp' argument to new line?

>  		}
>  	} else {
>  		dev_info(dp->dev, "EDID data does not include any extensions.\n");
>  
>  		/* Read EDID data */
> -		retval = exynos_dp_read_bytes_from_i2c(dp,
> -				I2C_EDID_DEVICE_ADDR,
> -				EDID_HEADER_PATTERN,
> -				EDID_BLOCK_LENGTH,
> -				&edid[EDID_HEADER_PATTERN]);
> +		retval = exynos_dp_read_bytes_from_i2c(
> +				dp, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
> +				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);

ditto

>  		if (retval != 0) {
>  			dev_err(dp->dev, "EDID Read failed!\n");
>  			return -EIO;
> @@ -183,16 +182,15 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  			return -EIO;
>  		}
>  
> -		exynos_dp_read_byte_from_dpcd(dp,
> -			DP_TEST_REQUEST,
> -			&test_vector);
> +		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
> +					      &test_vector);
>  		if (test_vector & DP_TEST_LINK_EDID_READ) {
> -			exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TEST_EDID_CHECKSUM,
> -				edid[EDID_CHECKSUM]);
> -			exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TEST_RESPONSE,
> -				DP_TEST_EDID_CHECKSUM_WRITE);
> +			exynos_dp_write_byte_to_dpcd(
> +					dp, DP_TEST_EDID_CHECKSUM,
> +					edid[EDID_CHECKSUM]);
> +			exynos_dp_write_byte_to_dpcd(
> +					dp, DP_TEST_RESPONSE,
> +					DP_TEST_EDID_CHECKSUM_WRITE);

ditto

>  		}
>  	}
>  
> @@ -207,8 +205,7 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
>  	int retval;
>  
>  	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
> -	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
> -				12, buf);
> +	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
>  	if (retval)
>  		return retval;
>  
> @@ -223,7 +220,7 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
>  }
>  
>  static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
> -						bool enable)
> +						 bool enable)
>  {
>  	u8 data;
>  
> @@ -231,11 +228,11 @@ static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
>  
>  	if (enable)
>  		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
> -			DP_LANE_COUNT_ENHANCED_FRAME_EN |
> -			DPCD_LANE_COUNT_SET(data));
> +					     DP_LANE_COUNT_ENHANCED_FRAME_EN |
> +					     DPCD_LANE_COUNT_SET(data));
>  	else
>  		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
> -			DPCD_LANE_COUNT_SET(data));
> +					     DPCD_LANE_COUNT_SET(data));
>  }
>  
>  static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
> @@ -262,13 +259,12 @@ static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
>  {
>  	exynos_dp_set_training_pattern(dp, DP_NONE);
>  
> -	exynos_dp_write_byte_to_dpcd(dp,
> -		DP_TRAINING_PATTERN_SET,
> -		DP_TRAINING_PATTERN_DISABLE);
> +	exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
> +				     DP_TRAINING_PATTERN_DISABLE);
>  }
>  
>  static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
> -					int pre_emphasis, int lane)
> +						 int pre_emphasis, int lane)
>  {
>  	switch (lane) {
>  	case 0:
> @@ -308,15 +304,14 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>  	/* Setup RX configuration */
>  	buf[0] = dp->link_train.link_rate;
>  	buf[1] = dp->link_train.lane_count;
> -	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
> -				2, buf);
> +	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
>  	if (retval)
>  		return retval;
>  
>  	/* Set TX pre-emphasis to minimum */
>  	for (lane = 0; lane < lane_count; lane++)
> -		exynos_dp_set_lane_lane_pre_emphasis(dp,
> -			PRE_EMPHASIS_LEVEL_0, lane);
> +		exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0,
> +						     lane);
>  
>  	/* Wait for PLL lock */
>  	pll_tries = 0;
> @@ -334,9 +329,9 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>  	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
>  
>  	/* Set RX training pattern */
> -	retval = exynos_dp_write_byte_to_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
> +	retval = exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
> +					      DP_LINK_SCRAMBLING_DISABLE |
> +					      DP_TRAINING_PATTERN_1);
>  	if (retval)
>  		return retval;
>  
> @@ -345,7 +340,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>  			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
>  
>  	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
> -			lane_count, buf);
> +					       lane_count, buf);
>  
>  	return retval;
>  }
> @@ -353,7 +348,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>  static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
>  {
>  	int shift = (lane & 1) * 4;
> -	u8 link_value = link_status[lane>>1];
> +	u8 link_value = link_status[lane >> 1];
>  
>  	return (link_value >> shift) & 0xf;
>  }
> @@ -372,7 +367,7 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
>  }
>  
>  static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
> -				int lane_count)
> +				   int lane_count)
>  {
>  	int lane;
>  	u8 lane_status;
> @@ -391,10 +386,10 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
>  }
>  
>  static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
> -							int lane)
> +							  int lane)
>  {
>  	int shift = (lane & 1) * 4;
> -	u8 link_value = adjust_request[lane>>1];
> +	u8 link_value = adjust_request[lane >> 1];
>  
>  	return (link_value >> shift) & 0x3;
>  }
> @@ -404,13 +399,13 @@ static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
>  					int lane)
>  {
>  	int shift = (lane & 1) * 4;
> -	u8 link_value = adjust_request[lane>>1];
> +	u8 link_value = adjust_request[lane >> 1];
>  
>  	return ((link_value >> shift) & 0xc) >> 2;
>  }
>  
>  static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
> -					u8 training_lane_set, int lane)
> +					     u8 training_lane_set, int lane)
>  {
>  	switch (lane) {
>  	case 0:
> @@ -430,9 +425,8 @@ static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
>  	}
>  }
>  
> -static unsigned int exynos_dp_get_lane_link_training(
> -				struct exynos_dp_device *dp,
> -				int lane)
> +static unsigned int
> +exynos_dp_get_lane_link_training(struct exynos_dp_device *dp, int lane)
>  {
>  	u32 reg;
>  
> @@ -466,7 +460,7 @@ static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
>  }
>  
>  static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
> -					u8 adjust_request[2])
> +					       u8 adjust_request[2])
>  {
>  	int lane, lane_count;
>  	u8 voltage_swing, pre_emphasis, training_lane;
> @@ -499,13 +493,13 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>  
>  	lane_count = dp->link_train.lane_count;
>  
> -	retval =  exynos_dp_read_bytes_from_dpcd(dp,
> -			DP_LANE0_1_STATUS, 2, link_status);
> +	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
> +						 2, link_status);
>  	if (retval)
>  		return retval;
>  
> -	retval =  exynos_dp_read_bytes_from_dpcd(dp,
> -			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
> +	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
> +						 2, adjust_request);
>  	if (retval)
>  		return retval;
>  
> @@ -513,8 +507,8 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>  		/* set training pattern 2 for EQ */
>  		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
>  
> -		retval = exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TRAINING_PATTERN_SET,
> +		retval = exynos_dp_write_byte_to_dpcd(
> +				dp, DP_TRAINING_PATTERN_SET,
>  				DP_LINK_SCRAMBLING_DISABLE |
>  				DP_TRAINING_PATTERN_2);

ditto

>  		if (retval)
> @@ -552,11 +546,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>  	exynos_dp_get_adjust_training_lane(dp, adjust_request);
>  
>  	for (lane = 0; lane < lane_count; lane++)
> -		exynos_dp_set_lane_link_training(dp,
> -			dp->link_train.training_lane[lane], lane);
> +		exynos_dp_set_lane_link_training(
> +				dp, dp->link_train.training_lane[lane], lane);
>  
> -	retval = exynos_dp_write_bytes_to_dpcd(dp,
> -			DP_TRAINING_LANE0_SET, lane_count,
> +	retval = exynos_dp_write_bytes_to_dpcd(
> +			dp, DP_TRAINING_LANE0_SET, lane_count,
>  			dp->link_train.training_lane);

ditto

>  	if (retval)
>  		return retval;
> @@ -574,8 +568,8 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>  
>  	lane_count = dp->link_train.lane_count;
>  
> -	retval = exynos_dp_read_bytes_from_dpcd(dp,
> -			DP_LANE0_1_STATUS, 2, link_status);
> +	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
> +						2, link_status);
>  	if (retval)
>  		return retval;
>  
> @@ -584,13 +578,13 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>  		return -EIO;
>  	}
>  
> -	retval = exynos_dp_read_bytes_from_dpcd(dp,
> -			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
> +	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
> +						2, adjust_request);
>  	if (retval)
>  		return retval;
>  
> -	retval = exynos_dp_read_byte_from_dpcd(dp,
> -			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
> +	retval = exynos_dp_read_byte_from_dpcd(dp, DP_LANE_ALIGN_STATUS_UPDATED,
> +					       &link_align);
>  	if (retval)
>  		return retval;
>  
> @@ -629,17 +623,18 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>  	}
>  
>  	for (lane = 0; lane < lane_count; lane++)
> -		exynos_dp_set_lane_link_training(dp,
> -			dp->link_train.training_lane[lane], lane);
> +		exynos_dp_set_lane_link_training(
> +				dp, dp->link_train.training_lane[lane], lane);

ditto

>  
>  	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
> -			lane_count, dp->link_train.training_lane);
> +					       lane_count,
> +					       dp->link_train.training_lane);
>  
>  	return retval;
>  }
>  
>  static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
> -					u8 *bandwidth)
> +					   u8 *bandwidth)
>  {
>  	u8 data;
>  
> @@ -652,7 +647,7 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
>  }
>  
>  static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
> -					u8 *lane_count)
> +					    u8 *lane_count)
>  {
>  	u8 data;
>  
> @@ -665,8 +660,8 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
>  }
>  
>  static void exynos_dp_init_training(struct exynos_dp_device *dp,
> -			enum link_lane_count_type max_lane,
> -			enum link_rate_type max_rate)
> +				    enum link_lane_count_type max_lane,
> +				    enum link_rate_type max_rate)
>  {
>  	/*
>  	 * MACRO_RST must be applied after the PLL_LOCK to avoid
> @@ -679,7 +674,7 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
>  	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
>  
>  	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
> -	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
> +	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
>  		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
>  			dp->link_train.link_rate);
>  		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
> @@ -739,8 +734,7 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
>  }
>  
>  static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
> -				u32 count,
> -				u32 bwtype)
> +				    u32 count, u32 bwtype)
>  {
>  	int i;
>  	int retval;
> @@ -828,21 +822,19 @@ static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
>  	if (enable) {
>  		exynos_dp_enable_scrambling(dp);
>  
> -		exynos_dp_read_byte_from_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			&data);
> -		exynos_dp_write_byte_to_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
> +		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
> +					      &data);
> +		exynos_dp_write_byte_to_dpcd(
> +				dp, DP_TRAINING_PATTERN_SET,
> +				(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));

ditto

>  	} else {
>  		exynos_dp_disable_scrambling(dp);
>  
> -		exynos_dp_read_byte_from_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			&data);
> -		exynos_dp_write_byte_to_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
> +		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
> +					      &data);
> +		exynos_dp_write_byte_to_dpcd(
> +				dp, DP_TRAINING_PATTERN_SET,
> +				(u8)(data | DP_LINK_SCRAMBLING_DISABLE));

ditto

>  	}
>  }
>  
> @@ -913,7 +905,7 @@ static void exynos_dp_commit(struct drm_encoder *encoder)
>  	}
>  
>  	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
> -					dp->video_info->link_rate);
> +				       dp->video_info->link_rate);
>  	if (ret) {
>  		dev_err(dp->dev, "unable to do link train\n");
>  		return;
> @@ -941,8 +933,8 @@ static void exynos_dp_commit(struct drm_encoder *encoder)
>  	exynos_dp_start_video(dp);
>  }
>  
> -static enum drm_connector_status exynos_dp_detect(
> -				struct drm_connector *connector, bool force)
> +static enum drm_connector_status
> +exynos_dp_detect(struct drm_connector *connector, bool force)
>  {
>  	return connector_status_connected;
>  }
> @@ -990,8 +982,8 @@ static int exynos_dp_get_modes(struct drm_connector *connector)
>  	return 1;
>  }
>  
> -static struct drm_encoder *exynos_dp_best_encoder(
> -			struct drm_connector *connector)
> +static struct drm_encoder *
> +exynos_dp_best_encoder(struct drm_connector *connector)
>  {
>  	struct exynos_dp_device *dp = ctx_from_connector(connector);
>  
> @@ -1005,7 +997,7 @@ static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
>  
>  /* returns the number of bridges attached */
>  static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
> -		struct drm_encoder *encoder)
> +					struct drm_encoder *encoder)
>  {
>  	int ret;
>  
> @@ -1036,7 +1028,8 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
>  	connector->polled = DRM_CONNECTOR_POLL_HPD;
>  
>  	ret = drm_connector_init(dp->drm_dev, connector,
> -			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
> +				 &exynos_dp_connector_funcs,
> +				 DRM_MODE_CONNECTOR_eDP);
>  	if (ret) {
>  		DRM_ERROR("Failed to initialize connector with drm\n");
>  		return ret;
> @@ -1139,8 +1132,8 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
>  	struct device_node *dp_node = dev->of_node;
>  	struct video_info *dp_video_config;
>  
> -	dp_video_config = devm_kzalloc(dev,
> -				sizeof(*dp_video_config), GFP_KERNEL);
> +	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
> +				       GFP_KERNEL);
>  	if (!dp_video_config)
>  		return ERR_PTR(-ENOMEM);
>  
> @@ -1154,37 +1147,37 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
>  		of_property_read_bool(dp_node, "interlaced");
>  
>  	if (of_property_read_u32(dp_node, "samsung,color-space",
> -				&dp_video_config->color_space)) {
> +				 &dp_video_config->color_space)) {
>  		dev_err(dev, "failed to get color-space\n");
>  		return ERR_PTR(-EINVAL);
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
> -				&dp_video_config->dynamic_range)) {
> +				 &dp_video_config->dynamic_range)) {
>  		dev_err(dev, "failed to get dynamic-range\n");
>  		return ERR_PTR(-EINVAL);
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> -				&dp_video_config->ycbcr_coeff)) {
> +				 &dp_video_config->ycbcr_coeff)) {
>  		dev_err(dev, "failed to get ycbcr-coeff\n");
>  		return ERR_PTR(-EINVAL);
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,color-depth",
> -				&dp_video_config->color_depth)) {
> +				 &dp_video_config->color_depth)) {
>  		dev_err(dev, "failed to get color-depth\n");
>  		return ERR_PTR(-EINVAL);
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,link-rate",
> -				&dp_video_config->link_rate)) {
> +				 &dp_video_config->link_rate)) {
>  		dev_err(dev, "failed to get link-rate\n");
>  		return ERR_PTR(-EINVAL);
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,lane-count",
> -				&dp_video_config->lane_count)) {
> +				 &dp_video_config->lane_count)) {
>  		dev_err(dev, "failed to get lane-count\n");
>  		return ERR_PTR(-EINVAL);
>  	}
> @@ -1197,7 +1190,7 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
>  	int ret;
>  
>  	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
> -			OF_USE_NATIVE_MODE);
> +			       OF_USE_NATIVE_MODE);
>  	if (ret) {
>  		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
>  		return ret;
> @@ -1294,7 +1287,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>  	exynos_dp_init_dp(dp);
>  
>  	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
> -			irq_flags, "exynos-dp", dp);
> +			       irq_flags, "exynos-dp", dp);
>  	if (ret) {
>  		dev_err(&pdev->dev, "failed to request irq\n");
>  		return ret;
> @@ -1328,7 +1321,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>  }
>  
>  static void exynos_dp_unbind(struct device *dev, struct device *master,
> -				void *data)
> +			     void *data)
>  {
>  	struct exynos_dp_device *dp = dev_get_drvdata(dev);
>  
> @@ -1347,7 +1340,7 @@ static int exynos_dp_probe(struct platform_device *pdev)
>  	struct exynos_dp_device *dp;
>  
>  	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
> -				GFP_KERNEL);
> +			  GFP_KERNEL);
>  	if (!dp)
>  		return -ENOMEM;
>  
> @@ -1369,8 +1362,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
>  			of_node_put(bridge_node);
>  			if (!dp->bridge)
>  				return -EPROBE_DEFER;
> -		} else
> +		} else {
>  			return -EPROBE_DEFER;
> +		}
>  	}
>  
>  	return component_add(&pdev->dev, &exynos_dp_ops);
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
> index e413b6f..71f2b86 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.h
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
> @@ -179,8 +179,8 @@ void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
>  enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
>  void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
>  void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
> -				enum analog_power_block block,
> -				bool enable);
> +				     enum analog_power_block block,
> +				     bool enable);
>  void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
>  void exynos_dp_init_hpd(struct exynos_dp_device *dp);
>  enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
> @@ -191,50 +191,50 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
>  void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
>  int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
>  int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned char data);
> +				 unsigned int reg_addr,
> +				 unsigned char data);
>  int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned char *data);
> +				  unsigned int reg_addr,
> +				  unsigned char *data);
>  int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char data[]);
> +				  unsigned int reg_addr,
> +				  unsigned int count,
> +				  unsigned char data[]);
>  int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char data[]);
> +				   unsigned int reg_addr,
> +				   unsigned int count,
> +				   unsigned char data[]);
>  int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
>  				unsigned int device_addr,
>  				unsigned int reg_addr);
>  int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr,
> -				unsigned int *data);
> +				 unsigned int device_addr,
> +				 unsigned int reg_addr,
> +				 unsigned int *data);
>  int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char edid[]);
> +				  unsigned int device_addr,
> +				  unsigned int reg_addr,
> +				  unsigned int count,
> +				  unsigned char edid[]);
>  void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
>  void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
>  void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
>  void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
>  void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
>  void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
> -				 enum pattern_set pattern);
> +				    enum pattern_set pattern);
>  void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>  void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>  void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>  void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>  void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
> -				u32 training_lane);
> +				       u32 training_lane);
>  void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
> -				u32 training_lane);
> +				       u32 training_lane);
>  void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
> -				u32 training_lane);
> +				       u32 training_lane);
>  void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
> -				u32 training_lane);
> +				       u32 training_lane);
>  u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
>  u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
>  u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
> @@ -245,9 +245,9 @@ void exynos_dp_init_video(struct exynos_dp_device *dp);
>  void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
>  int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
>  void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
> -			enum clock_recovery_m_value_type type,
> -			u32 m_value,
> -			u32 n_value);
> +			       enum clock_recovery_m_value_type type,
> +			       u32 m_value,
> +			       u32 n_value);
>  void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
>  void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
>  void exynos_dp_start_video(struct exynos_dp_device *dp);
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
> index c1f87a2..5aff19a 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp_reg.c
> @@ -202,8 +202,8 @@ void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
>  }
>  
>  void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
> -				enum analog_power_block block,
> -				bool enable)
> +				     enum analog_power_block block,
> +				     bool enable)
>  {
>  	u32 reg;
>  
> @@ -399,8 +399,8 @@ void exynos_dp_init_aux(struct exynos_dp_device *dp)
>  	exynos_dp_reset_aux(dp);
>  
>  	/* Disable AUX transaction H/W retry */
> -	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
> -		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> +	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
> +	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
>  	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
>  
>  	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
> @@ -483,8 +483,8 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
>  }
>  
>  int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned char data)
> +				 unsigned int reg_addr,
> +				 unsigned char data)
>  {
>  	u32 reg;
>  	int i;
> @@ -519,17 +519,16 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
>  		retval = exynos_dp_start_aux_transaction(dp);
>  		if (retval == 0)
>  			break;
> -		else
> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -				__func__);
> +
> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
>  	}
>  
>  	return retval;
>  }
>  
>  int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned char *data)
> +				  unsigned int reg_addr,
> +				  unsigned char *data)
>  {
>  	u32 reg;
>  	int i;
> @@ -560,9 +559,8 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
>  		retval = exynos_dp_start_aux_transaction(dp);
>  		if (retval == 0)
>  			break;
> -		else
> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -				__func__);
> +
> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
>  	}
>  
>  	/* Read data buffer */
> @@ -573,9 +571,9 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
>  }
>  
>  int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char data[])
> +				  unsigned int reg_addr,
> +				  unsigned int count,
> +				  unsigned char data[])
>  {
>  	u32 reg;
>  	unsigned int start_offset;
> @@ -625,9 +623,9 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
>  			retval = exynos_dp_start_aux_transaction(dp);
>  			if (retval == 0)
>  				break;
> -			else
> -				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -					__func__);
> +
> +			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> +				__func__);
>  		}
>  
>  		start_offset += cur_data_count;
> @@ -637,9 +635,9 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
>  }
>  
>  int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char data[])
> +				   unsigned int reg_addr,
> +				   unsigned int count,
> +				   unsigned char data[])
>  {
>  	u32 reg;
>  	unsigned int start_offset;
> @@ -683,9 +681,9 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
>  			retval = exynos_dp_start_aux_transaction(dp);
>  			if (retval == 0)
>  				break;
> -			else
> -				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -					__func__);
> +
> +			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> +				__func__);
>  		}
>  
>  		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
> @@ -736,9 +734,9 @@ int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
>  }
>  
>  int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr,
> -				unsigned int *data)
> +				 unsigned int device_addr,
> +				 unsigned int reg_addr,
> +				 unsigned int *data)
>  {
>  	u32 reg;
>  	int i;
> @@ -767,9 +765,8 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
>  		retval = exynos_dp_start_aux_transaction(dp);
>  		if (retval == 0)
>  			break;
> -		else
> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -				__func__);
> +
> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
>  	}
>  
>  	/* Read data */
> @@ -780,10 +777,10 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
>  }
>  
>  int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char edid[])
> +				  unsigned int device_addr,
> +				  unsigned int reg_addr,
> +				  unsigned int count,
> +				  unsigned char edid[])
>  {
>  	u32 reg;
>  	unsigned int i, j;
> @@ -807,8 +804,8 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
>  			 * request without sending address
>  			 */
>  			if (!defer)
> -				retval = exynos_dp_select_i2c_device(dp,
> -						device_addr, reg_addr + i);
> +				retval = exynos_dp_select_i2c_device(
> +						dp, device_addr, reg_addr + i);

ditto

Best regards,
Krzysztof

>  			else
>  				defer = 0;
>  
> @@ -819,24 +816,23 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
>  				 * If Bit 3 is 0, I2C transaction.
>  				 */
>  				reg = AUX_LENGTH(16) |
> -					AUX_TX_COMM_I2C_TRANSACTION |
> -					AUX_TX_COMM_READ;
> +				      AUX_TX_COMM_I2C_TRANSACTION |
> +				      AUX_TX_COMM_READ;
>  				writel(reg, dp->reg_base +
> -					EXYNOS_DP_AUX_CH_CTL_1);
> +				       EXYNOS_DP_AUX_CH_CTL_1);
>  
>  				/* Start AUX transaction */
>  				retval = exynos_dp_start_aux_transaction(dp);
>  				if (retval == 0)
>  					break;
> -				else
> -					dev_dbg(dp->dev,
> -						"%s: Aux Transaction fail!\n",
> -						__func__);
> +
> +				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> +					__func__);
>  			}
>  			/* Check if Rx sends defer */
>  			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
>  			if (reg == AUX_RX_COMM_AUX_DEFER ||
> -				reg == AUX_RX_COMM_I2C_DEFER) {
> +			    reg == AUX_RX_COMM_I2C_DEFER) {
>  				dev_err(dp->dev, "Defer: %d\n\n", reg);
>  				defer = 1;
>  			}
> @@ -901,7 +897,7 @@ void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
>  }
>  
>  void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
> -				 enum pattern_set pattern)
> +				    enum pattern_set pattern)
>  {
>  	u32 reg;
>  
> @@ -974,7 +970,7 @@ void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
>  }
>  
>  void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
> -					u32 training_lane)
> +				       u32 training_lane)
>  {
>  	u32 reg;
>  
> @@ -983,7 +979,7 @@ void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
>  }
>  
>  void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
> -					u32 training_lane)
> +				       u32 training_lane)
>  {
>  	u32 reg;
>  
> @@ -992,7 +988,7 @@ void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
>  }
>  
>  void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
> -					u32 training_lane)
> +				       u32 training_lane)
>  {
>  	u32 reg;
>  
> @@ -1001,7 +997,7 @@ void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
>  }
>  
>  void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
> -					u32 training_lane)
> +				       u32 training_lane)
>  {
>  	u32 reg;
>  
> @@ -1125,9 +1121,9 @@ int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
>  }
>  
>  void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
> -		enum clock_recovery_m_value_type type,
> -		u32 m_value,
> -		u32 n_value)
> +			       enum clock_recovery_m_value_type type,
> +			       u32 m_value,
> +			       u32 n_value)
>  {
>  	u32 reg;
>  
> @@ -1221,7 +1217,7 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
>  	u32 reg;
>  
>  	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
> -	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
> +	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
>  	reg |= MASTER_VID_FUNC_EN_N;
>  	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
>  
> 


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 01/16] drm: exynos/dp: fix code style
@ 2015-09-03  0:21     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-03  0:21 UTC (permalink / raw)
  To: linux-arm-kernel

On 01.09.2015 14:46, Yakir Yang wrote:
> After run "checkpatch.pl -f --subjective" command, I see there
> are lots of alignment problem in exynos_dp driver, so let just
> fix them.

Hi,

Warnings from checkpatch are not a reason for a commit. Reason for a
commit could be for example an unreadable code, violation of
coding-style leading to decrease in code maintainability or just
improving the code readability so it will be easier to review and
maintain it.

You do not make commits because some tool tells you that. We do not
listen to machines :) ... If that would be the case, the commit could be
made automatically, without human interaction. Such automated commit
could be even easily tested by the machine by comparing object files.

Especially that you enabled "subjective" rule. This is not a valid
motivation for a commit.

Please rephrase this to sensible reason and convince that change is
worth the effort.

> 
> - Take Romain suggest, rebase on linux-next branch

That comment seems unrelated to the commit. Please remove it.

> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Take Joe Preches advise, improved commit message more readable, and
>   avoid using some uncommon style like bellow:
>   -  retval = exynos_dp_read_bytes_from_i2c(...
> 				...)
>   +  retval =
>   +  exynos_dp_read_bytes_from_i2c(......);
> 
>  drivers/gpu/drm/exynos/exynos_dp_core.c | 226 ++++++++++++++++----------------
>  drivers/gpu/drm/exynos/exynos_dp_core.h |  54 ++++----
>  drivers/gpu/drm/exynos/exynos_dp_reg.c  | 106 +++++++--------
>  3 files changed, 188 insertions(+), 198 deletions(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
> index d66ade0..266f7f7 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
> @@ -115,8 +115,8 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  
>  	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
>  	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> -				EDID_EXTENSION_FLAG,
> -				&extend_block);
> +					      EDID_EXTENSION_FLAG,
> +					      &extend_block);
>  	if (retval)
>  		return retval;
>  
> @@ -124,10 +124,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>  
>  		/* Read EDID data */
> -		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> -						EDID_HEADER_PATTERN,
> -						EDID_BLOCK_LENGTH,
> -						&edid[EDID_HEADER_PATTERN]);
> +		retval = exynos_dp_read_bytes_from_i2c(
> +					dp, I2C_EDID_DEVICE_ADDR,
> +					EDID_HEADER_PATTERN,
> +					EDID_BLOCK_LENGTH,
> +					&edid[EDID_HEADER_PATTERN]);
>  		if (retval != 0) {
>  			dev_err(dp->dev, "EDID Read failed!\n");
>  			return -EIO;
> @@ -139,11 +140,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  		}
>  
>  		/* Read additional EDID data */
> -		retval = exynos_dp_read_bytes_from_i2c(dp,
> -				I2C_EDID_DEVICE_ADDR,
> -				EDID_BLOCK_LENGTH,
> -				EDID_BLOCK_LENGTH,
> -				&edid[EDID_BLOCK_LENGTH]);
> +		retval = exynos_dp_read_bytes_from_i2c(
> +					dp, I2C_EDID_DEVICE_ADDR,
> +					EDID_BLOCK_LENGTH,
> +					EDID_BLOCK_LENGTH,
> +					&edid[EDID_BLOCK_LENGTH]);
>  		if (retval != 0) {
>  			dev_err(dp->dev, "EDID Read failed!\n");
>  			return -EIO;
> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  		}
>  
>  		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
> -					&test_vector);
> +					      &test_vector);
>  		if (test_vector & DP_TEST_LINK_EDID_READ) {
> -			exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TEST_EDID_CHECKSUM,
> +			exynos_dp_write_byte_to_dpcd(
> +				dp, DP_TEST_EDID_CHECKSUM,
>  				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
> -			exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TEST_RESPONSE,
> +			exynos_dp_write_byte_to_dpcd(
> +				dp, DP_TEST_RESPONSE,
>  				DP_TEST_EDID_CHECKSUM_WRITE);

To me, missing argument after opening parenthesis, looks worse. I would
prefer:

			exynos_dp_write_byte_to_dpcd(dp,

Why you moved the 'dp' argument to new line?

>  		}
>  	} else {
>  		dev_info(dp->dev, "EDID data does not include any extensions.\n");
>  
>  		/* Read EDID data */
> -		retval = exynos_dp_read_bytes_from_i2c(dp,
> -				I2C_EDID_DEVICE_ADDR,
> -				EDID_HEADER_PATTERN,
> -				EDID_BLOCK_LENGTH,
> -				&edid[EDID_HEADER_PATTERN]);
> +		retval = exynos_dp_read_bytes_from_i2c(
> +				dp, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
> +				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);

ditto

>  		if (retval != 0) {
>  			dev_err(dp->dev, "EDID Read failed!\n");
>  			return -EIO;
> @@ -183,16 +182,15 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  			return -EIO;
>  		}
>  
> -		exynos_dp_read_byte_from_dpcd(dp,
> -			DP_TEST_REQUEST,
> -			&test_vector);
> +		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
> +					      &test_vector);
>  		if (test_vector & DP_TEST_LINK_EDID_READ) {
> -			exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TEST_EDID_CHECKSUM,
> -				edid[EDID_CHECKSUM]);
> -			exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TEST_RESPONSE,
> -				DP_TEST_EDID_CHECKSUM_WRITE);
> +			exynos_dp_write_byte_to_dpcd(
> +					dp, DP_TEST_EDID_CHECKSUM,
> +					edid[EDID_CHECKSUM]);
> +			exynos_dp_write_byte_to_dpcd(
> +					dp, DP_TEST_RESPONSE,
> +					DP_TEST_EDID_CHECKSUM_WRITE);

ditto

>  		}
>  	}
>  
> @@ -207,8 +205,7 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
>  	int retval;
>  
>  	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
> -	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
> -				12, buf);
> +	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
>  	if (retval)
>  		return retval;
>  
> @@ -223,7 +220,7 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
>  }
>  
>  static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
> -						bool enable)
> +						 bool enable)
>  {
>  	u8 data;
>  
> @@ -231,11 +228,11 @@ static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
>  
>  	if (enable)
>  		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
> -			DP_LANE_COUNT_ENHANCED_FRAME_EN |
> -			DPCD_LANE_COUNT_SET(data));
> +					     DP_LANE_COUNT_ENHANCED_FRAME_EN |
> +					     DPCD_LANE_COUNT_SET(data));
>  	else
>  		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
> -			DPCD_LANE_COUNT_SET(data));
> +					     DPCD_LANE_COUNT_SET(data));
>  }
>  
>  static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
> @@ -262,13 +259,12 @@ static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
>  {
>  	exynos_dp_set_training_pattern(dp, DP_NONE);
>  
> -	exynos_dp_write_byte_to_dpcd(dp,
> -		DP_TRAINING_PATTERN_SET,
> -		DP_TRAINING_PATTERN_DISABLE);
> +	exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
> +				     DP_TRAINING_PATTERN_DISABLE);
>  }
>  
>  static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
> -					int pre_emphasis, int lane)
> +						 int pre_emphasis, int lane)
>  {
>  	switch (lane) {
>  	case 0:
> @@ -308,15 +304,14 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>  	/* Setup RX configuration */
>  	buf[0] = dp->link_train.link_rate;
>  	buf[1] = dp->link_train.lane_count;
> -	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
> -				2, buf);
> +	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
>  	if (retval)
>  		return retval;
>  
>  	/* Set TX pre-emphasis to minimum */
>  	for (lane = 0; lane < lane_count; lane++)
> -		exynos_dp_set_lane_lane_pre_emphasis(dp,
> -			PRE_EMPHASIS_LEVEL_0, lane);
> +		exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0,
> +						     lane);
>  
>  	/* Wait for PLL lock */
>  	pll_tries = 0;
> @@ -334,9 +329,9 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>  	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
>  
>  	/* Set RX training pattern */
> -	retval = exynos_dp_write_byte_to_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
> +	retval = exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
> +					      DP_LINK_SCRAMBLING_DISABLE |
> +					      DP_TRAINING_PATTERN_1);
>  	if (retval)
>  		return retval;
>  
> @@ -345,7 +340,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>  			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
>  
>  	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
> -			lane_count, buf);
> +					       lane_count, buf);
>  
>  	return retval;
>  }
> @@ -353,7 +348,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>  static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
>  {
>  	int shift = (lane & 1) * 4;
> -	u8 link_value = link_status[lane>>1];
> +	u8 link_value = link_status[lane >> 1];
>  
>  	return (link_value >> shift) & 0xf;
>  }
> @@ -372,7 +367,7 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
>  }
>  
>  static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
> -				int lane_count)
> +				   int lane_count)
>  {
>  	int lane;
>  	u8 lane_status;
> @@ -391,10 +386,10 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
>  }
>  
>  static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
> -							int lane)
> +							  int lane)
>  {
>  	int shift = (lane & 1) * 4;
> -	u8 link_value = adjust_request[lane>>1];
> +	u8 link_value = adjust_request[lane >> 1];
>  
>  	return (link_value >> shift) & 0x3;
>  }
> @@ -404,13 +399,13 @@ static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
>  					int lane)
>  {
>  	int shift = (lane & 1) * 4;
> -	u8 link_value = adjust_request[lane>>1];
> +	u8 link_value = adjust_request[lane >> 1];
>  
>  	return ((link_value >> shift) & 0xc) >> 2;
>  }
>  
>  static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
> -					u8 training_lane_set, int lane)
> +					     u8 training_lane_set, int lane)
>  {
>  	switch (lane) {
>  	case 0:
> @@ -430,9 +425,8 @@ static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
>  	}
>  }
>  
> -static unsigned int exynos_dp_get_lane_link_training(
> -				struct exynos_dp_device *dp,
> -				int lane)
> +static unsigned int
> +exynos_dp_get_lane_link_training(struct exynos_dp_device *dp, int lane)
>  {
>  	u32 reg;
>  
> @@ -466,7 +460,7 @@ static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
>  }
>  
>  static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
> -					u8 adjust_request[2])
> +					       u8 adjust_request[2])
>  {
>  	int lane, lane_count;
>  	u8 voltage_swing, pre_emphasis, training_lane;
> @@ -499,13 +493,13 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>  
>  	lane_count = dp->link_train.lane_count;
>  
> -	retval =  exynos_dp_read_bytes_from_dpcd(dp,
> -			DP_LANE0_1_STATUS, 2, link_status);
> +	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
> +						 2, link_status);
>  	if (retval)
>  		return retval;
>  
> -	retval =  exynos_dp_read_bytes_from_dpcd(dp,
> -			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
> +	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
> +						 2, adjust_request);
>  	if (retval)
>  		return retval;
>  
> @@ -513,8 +507,8 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>  		/* set training pattern 2 for EQ */
>  		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
>  
> -		retval = exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TRAINING_PATTERN_SET,
> +		retval = exynos_dp_write_byte_to_dpcd(
> +				dp, DP_TRAINING_PATTERN_SET,
>  				DP_LINK_SCRAMBLING_DISABLE |
>  				DP_TRAINING_PATTERN_2);

ditto

>  		if (retval)
> @@ -552,11 +546,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>  	exynos_dp_get_adjust_training_lane(dp, adjust_request);
>  
>  	for (lane = 0; lane < lane_count; lane++)
> -		exynos_dp_set_lane_link_training(dp,
> -			dp->link_train.training_lane[lane], lane);
> +		exynos_dp_set_lane_link_training(
> +				dp, dp->link_train.training_lane[lane], lane);
>  
> -	retval = exynos_dp_write_bytes_to_dpcd(dp,
> -			DP_TRAINING_LANE0_SET, lane_count,
> +	retval = exynos_dp_write_bytes_to_dpcd(
> +			dp, DP_TRAINING_LANE0_SET, lane_count,
>  			dp->link_train.training_lane);

ditto

>  	if (retval)
>  		return retval;
> @@ -574,8 +568,8 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>  
>  	lane_count = dp->link_train.lane_count;
>  
> -	retval = exynos_dp_read_bytes_from_dpcd(dp,
> -			DP_LANE0_1_STATUS, 2, link_status);
> +	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
> +						2, link_status);
>  	if (retval)
>  		return retval;
>  
> @@ -584,13 +578,13 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>  		return -EIO;
>  	}
>  
> -	retval = exynos_dp_read_bytes_from_dpcd(dp,
> -			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
> +	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
> +						2, adjust_request);
>  	if (retval)
>  		return retval;
>  
> -	retval = exynos_dp_read_byte_from_dpcd(dp,
> -			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
> +	retval = exynos_dp_read_byte_from_dpcd(dp, DP_LANE_ALIGN_STATUS_UPDATED,
> +					       &link_align);
>  	if (retval)
>  		return retval;
>  
> @@ -629,17 +623,18 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>  	}
>  
>  	for (lane = 0; lane < lane_count; lane++)
> -		exynos_dp_set_lane_link_training(dp,
> -			dp->link_train.training_lane[lane], lane);
> +		exynos_dp_set_lane_link_training(
> +				dp, dp->link_train.training_lane[lane], lane);

ditto

>  
>  	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
> -			lane_count, dp->link_train.training_lane);
> +					       lane_count,
> +					       dp->link_train.training_lane);
>  
>  	return retval;
>  }
>  
>  static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
> -					u8 *bandwidth)
> +					   u8 *bandwidth)
>  {
>  	u8 data;
>  
> @@ -652,7 +647,7 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
>  }
>  
>  static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
> -					u8 *lane_count)
> +					    u8 *lane_count)
>  {
>  	u8 data;
>  
> @@ -665,8 +660,8 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
>  }
>  
>  static void exynos_dp_init_training(struct exynos_dp_device *dp,
> -			enum link_lane_count_type max_lane,
> -			enum link_rate_type max_rate)
> +				    enum link_lane_count_type max_lane,
> +				    enum link_rate_type max_rate)
>  {
>  	/*
>  	 * MACRO_RST must be applied after the PLL_LOCK to avoid
> @@ -679,7 +674,7 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
>  	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
>  
>  	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
> -	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
> +	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
>  		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
>  			dp->link_train.link_rate);
>  		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
> @@ -739,8 +734,7 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
>  }
>  
>  static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
> -				u32 count,
> -				u32 bwtype)
> +				    u32 count, u32 bwtype)
>  {
>  	int i;
>  	int retval;
> @@ -828,21 +822,19 @@ static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
>  	if (enable) {
>  		exynos_dp_enable_scrambling(dp);
>  
> -		exynos_dp_read_byte_from_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			&data);
> -		exynos_dp_write_byte_to_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
> +		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
> +					      &data);
> +		exynos_dp_write_byte_to_dpcd(
> +				dp, DP_TRAINING_PATTERN_SET,
> +				(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));

ditto

>  	} else {
>  		exynos_dp_disable_scrambling(dp);
>  
> -		exynos_dp_read_byte_from_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			&data);
> -		exynos_dp_write_byte_to_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
> +		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
> +					      &data);
> +		exynos_dp_write_byte_to_dpcd(
> +				dp, DP_TRAINING_PATTERN_SET,
> +				(u8)(data | DP_LINK_SCRAMBLING_DISABLE));

ditto

>  	}
>  }
>  
> @@ -913,7 +905,7 @@ static void exynos_dp_commit(struct drm_encoder *encoder)
>  	}
>  
>  	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
> -					dp->video_info->link_rate);
> +				       dp->video_info->link_rate);
>  	if (ret) {
>  		dev_err(dp->dev, "unable to do link train\n");
>  		return;
> @@ -941,8 +933,8 @@ static void exynos_dp_commit(struct drm_encoder *encoder)
>  	exynos_dp_start_video(dp);
>  }
>  
> -static enum drm_connector_status exynos_dp_detect(
> -				struct drm_connector *connector, bool force)
> +static enum drm_connector_status
> +exynos_dp_detect(struct drm_connector *connector, bool force)
>  {
>  	return connector_status_connected;
>  }
> @@ -990,8 +982,8 @@ static int exynos_dp_get_modes(struct drm_connector *connector)
>  	return 1;
>  }
>  
> -static struct drm_encoder *exynos_dp_best_encoder(
> -			struct drm_connector *connector)
> +static struct drm_encoder *
> +exynos_dp_best_encoder(struct drm_connector *connector)
>  {
>  	struct exynos_dp_device *dp = ctx_from_connector(connector);
>  
> @@ -1005,7 +997,7 @@ static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
>  
>  /* returns the number of bridges attached */
>  static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
> -		struct drm_encoder *encoder)
> +					struct drm_encoder *encoder)
>  {
>  	int ret;
>  
> @@ -1036,7 +1028,8 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
>  	connector->polled = DRM_CONNECTOR_POLL_HPD;
>  
>  	ret = drm_connector_init(dp->drm_dev, connector,
> -			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
> +				 &exynos_dp_connector_funcs,
> +				 DRM_MODE_CONNECTOR_eDP);
>  	if (ret) {
>  		DRM_ERROR("Failed to initialize connector with drm\n");
>  		return ret;
> @@ -1139,8 +1132,8 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
>  	struct device_node *dp_node = dev->of_node;
>  	struct video_info *dp_video_config;
>  
> -	dp_video_config = devm_kzalloc(dev,
> -				sizeof(*dp_video_config), GFP_KERNEL);
> +	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
> +				       GFP_KERNEL);
>  	if (!dp_video_config)
>  		return ERR_PTR(-ENOMEM);
>  
> @@ -1154,37 +1147,37 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
>  		of_property_read_bool(dp_node, "interlaced");
>  
>  	if (of_property_read_u32(dp_node, "samsung,color-space",
> -				&dp_video_config->color_space)) {
> +				 &dp_video_config->color_space)) {
>  		dev_err(dev, "failed to get color-space\n");
>  		return ERR_PTR(-EINVAL);
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
> -				&dp_video_config->dynamic_range)) {
> +				 &dp_video_config->dynamic_range)) {
>  		dev_err(dev, "failed to get dynamic-range\n");
>  		return ERR_PTR(-EINVAL);
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> -				&dp_video_config->ycbcr_coeff)) {
> +				 &dp_video_config->ycbcr_coeff)) {
>  		dev_err(dev, "failed to get ycbcr-coeff\n");
>  		return ERR_PTR(-EINVAL);
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,color-depth",
> -				&dp_video_config->color_depth)) {
> +				 &dp_video_config->color_depth)) {
>  		dev_err(dev, "failed to get color-depth\n");
>  		return ERR_PTR(-EINVAL);
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,link-rate",
> -				&dp_video_config->link_rate)) {
> +				 &dp_video_config->link_rate)) {
>  		dev_err(dev, "failed to get link-rate\n");
>  		return ERR_PTR(-EINVAL);
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,lane-count",
> -				&dp_video_config->lane_count)) {
> +				 &dp_video_config->lane_count)) {
>  		dev_err(dev, "failed to get lane-count\n");
>  		return ERR_PTR(-EINVAL);
>  	}
> @@ -1197,7 +1190,7 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
>  	int ret;
>  
>  	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
> -			OF_USE_NATIVE_MODE);
> +			       OF_USE_NATIVE_MODE);
>  	if (ret) {
>  		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
>  		return ret;
> @@ -1294,7 +1287,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>  	exynos_dp_init_dp(dp);
>  
>  	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
> -			irq_flags, "exynos-dp", dp);
> +			       irq_flags, "exynos-dp", dp);
>  	if (ret) {
>  		dev_err(&pdev->dev, "failed to request irq\n");
>  		return ret;
> @@ -1328,7 +1321,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>  }
>  
>  static void exynos_dp_unbind(struct device *dev, struct device *master,
> -				void *data)
> +			     void *data)
>  {
>  	struct exynos_dp_device *dp = dev_get_drvdata(dev);
>  
> @@ -1347,7 +1340,7 @@ static int exynos_dp_probe(struct platform_device *pdev)
>  	struct exynos_dp_device *dp;
>  
>  	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
> -				GFP_KERNEL);
> +			  GFP_KERNEL);
>  	if (!dp)
>  		return -ENOMEM;
>  
> @@ -1369,8 +1362,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
>  			of_node_put(bridge_node);
>  			if (!dp->bridge)
>  				return -EPROBE_DEFER;
> -		} else
> +		} else {
>  			return -EPROBE_DEFER;
> +		}
>  	}
>  
>  	return component_add(&pdev->dev, &exynos_dp_ops);
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
> index e413b6f..71f2b86 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.h
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
> @@ -179,8 +179,8 @@ void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
>  enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
>  void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
>  void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
> -				enum analog_power_block block,
> -				bool enable);
> +				     enum analog_power_block block,
> +				     bool enable);
>  void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
>  void exynos_dp_init_hpd(struct exynos_dp_device *dp);
>  enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
> @@ -191,50 +191,50 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
>  void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
>  int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
>  int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned char data);
> +				 unsigned int reg_addr,
> +				 unsigned char data);
>  int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned char *data);
> +				  unsigned int reg_addr,
> +				  unsigned char *data);
>  int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char data[]);
> +				  unsigned int reg_addr,
> +				  unsigned int count,
> +				  unsigned char data[]);
>  int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char data[]);
> +				   unsigned int reg_addr,
> +				   unsigned int count,
> +				   unsigned char data[]);
>  int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
>  				unsigned int device_addr,
>  				unsigned int reg_addr);
>  int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr,
> -				unsigned int *data);
> +				 unsigned int device_addr,
> +				 unsigned int reg_addr,
> +				 unsigned int *data);
>  int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char edid[]);
> +				  unsigned int device_addr,
> +				  unsigned int reg_addr,
> +				  unsigned int count,
> +				  unsigned char edid[]);
>  void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
>  void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
>  void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
>  void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
>  void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
>  void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
> -				 enum pattern_set pattern);
> +				    enum pattern_set pattern);
>  void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>  void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>  void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>  void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>  void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
> -				u32 training_lane);
> +				       u32 training_lane);
>  void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
> -				u32 training_lane);
> +				       u32 training_lane);
>  void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
> -				u32 training_lane);
> +				       u32 training_lane);
>  void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
> -				u32 training_lane);
> +				       u32 training_lane);
>  u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
>  u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
>  u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
> @@ -245,9 +245,9 @@ void exynos_dp_init_video(struct exynos_dp_device *dp);
>  void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
>  int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
>  void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
> -			enum clock_recovery_m_value_type type,
> -			u32 m_value,
> -			u32 n_value);
> +			       enum clock_recovery_m_value_type type,
> +			       u32 m_value,
> +			       u32 n_value);
>  void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
>  void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
>  void exynos_dp_start_video(struct exynos_dp_device *dp);
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
> index c1f87a2..5aff19a 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp_reg.c
> @@ -202,8 +202,8 @@ void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
>  }
>  
>  void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
> -				enum analog_power_block block,
> -				bool enable)
> +				     enum analog_power_block block,
> +				     bool enable)
>  {
>  	u32 reg;
>  
> @@ -399,8 +399,8 @@ void exynos_dp_init_aux(struct exynos_dp_device *dp)
>  	exynos_dp_reset_aux(dp);
>  
>  	/* Disable AUX transaction H/W retry */
> -	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
> -		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> +	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
> +	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
>  	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
>  
>  	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
> @@ -483,8 +483,8 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
>  }
>  
>  int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned char data)
> +				 unsigned int reg_addr,
> +				 unsigned char data)
>  {
>  	u32 reg;
>  	int i;
> @@ -519,17 +519,16 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
>  		retval = exynos_dp_start_aux_transaction(dp);
>  		if (retval == 0)
>  			break;
> -		else
> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -				__func__);
> +
> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
>  	}
>  
>  	return retval;
>  }
>  
>  int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned char *data)
> +				  unsigned int reg_addr,
> +				  unsigned char *data)
>  {
>  	u32 reg;
>  	int i;
> @@ -560,9 +559,8 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
>  		retval = exynos_dp_start_aux_transaction(dp);
>  		if (retval == 0)
>  			break;
> -		else
> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -				__func__);
> +
> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
>  	}
>  
>  	/* Read data buffer */
> @@ -573,9 +571,9 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
>  }
>  
>  int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char data[])
> +				  unsigned int reg_addr,
> +				  unsigned int count,
> +				  unsigned char data[])
>  {
>  	u32 reg;
>  	unsigned int start_offset;
> @@ -625,9 +623,9 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
>  			retval = exynos_dp_start_aux_transaction(dp);
>  			if (retval == 0)
>  				break;
> -			else
> -				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -					__func__);
> +
> +			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> +				__func__);
>  		}
>  
>  		start_offset += cur_data_count;
> @@ -637,9 +635,9 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
>  }
>  
>  int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char data[])
> +				   unsigned int reg_addr,
> +				   unsigned int count,
> +				   unsigned char data[])
>  {
>  	u32 reg;
>  	unsigned int start_offset;
> @@ -683,9 +681,9 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
>  			retval = exynos_dp_start_aux_transaction(dp);
>  			if (retval == 0)
>  				break;
> -			else
> -				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -					__func__);
> +
> +			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> +				__func__);
>  		}
>  
>  		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
> @@ -736,9 +734,9 @@ int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
>  }
>  
>  int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr,
> -				unsigned int *data)
> +				 unsigned int device_addr,
> +				 unsigned int reg_addr,
> +				 unsigned int *data)
>  {
>  	u32 reg;
>  	int i;
> @@ -767,9 +765,8 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
>  		retval = exynos_dp_start_aux_transaction(dp);
>  		if (retval == 0)
>  			break;
> -		else
> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -				__func__);
> +
> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
>  	}
>  
>  	/* Read data */
> @@ -780,10 +777,10 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
>  }
>  
>  int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char edid[])
> +				  unsigned int device_addr,
> +				  unsigned int reg_addr,
> +				  unsigned int count,
> +				  unsigned char edid[])
>  {
>  	u32 reg;
>  	unsigned int i, j;
> @@ -807,8 +804,8 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
>  			 * request without sending address
>  			 */
>  			if (!defer)
> -				retval = exynos_dp_select_i2c_device(dp,
> -						device_addr, reg_addr + i);
> +				retval = exynos_dp_select_i2c_device(
> +						dp, device_addr, reg_addr + i);

ditto

Best regards,
Krzysztof

>  			else
>  				defer = 0;
>  
> @@ -819,24 +816,23 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
>  				 * If Bit 3 is 0, I2C transaction.
>  				 */
>  				reg = AUX_LENGTH(16) |
> -					AUX_TX_COMM_I2C_TRANSACTION |
> -					AUX_TX_COMM_READ;
> +				      AUX_TX_COMM_I2C_TRANSACTION |
> +				      AUX_TX_COMM_READ;
>  				writel(reg, dp->reg_base +
> -					EXYNOS_DP_AUX_CH_CTL_1);
> +				       EXYNOS_DP_AUX_CH_CTL_1);
>  
>  				/* Start AUX transaction */
>  				retval = exynos_dp_start_aux_transaction(dp);
>  				if (retval == 0)
>  					break;
> -				else
> -					dev_dbg(dp->dev,
> -						"%s: Aux Transaction fail!\n",
> -						__func__);
> +
> +				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> +					__func__);
>  			}
>  			/* Check if Rx sends defer */
>  			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
>  			if (reg == AUX_RX_COMM_AUX_DEFER ||
> -				reg == AUX_RX_COMM_I2C_DEFER) {
> +			    reg == AUX_RX_COMM_I2C_DEFER) {
>  				dev_err(dp->dev, "Defer: %d\n\n", reg);
>  				defer = 1;
>  			}
> @@ -901,7 +897,7 @@ void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
>  }
>  
>  void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
> -				 enum pattern_set pattern)
> +				    enum pattern_set pattern)
>  {
>  	u32 reg;
>  
> @@ -974,7 +970,7 @@ void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
>  }
>  
>  void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
> -					u32 training_lane)
> +				       u32 training_lane)
>  {
>  	u32 reg;
>  
> @@ -983,7 +979,7 @@ void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
>  }
>  
>  void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
> -					u32 training_lane)
> +				       u32 training_lane)
>  {
>  	u32 reg;
>  
> @@ -992,7 +988,7 @@ void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
>  }
>  
>  void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
> -					u32 training_lane)
> +				       u32 training_lane)
>  {
>  	u32 reg;
>  
> @@ -1001,7 +997,7 @@ void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
>  }
>  
>  void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
> -					u32 training_lane)
> +				       u32 training_lane)
>  {
>  	u32 reg;
>  
> @@ -1125,9 +1121,9 @@ int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
>  }
>  
>  void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
> -		enum clock_recovery_m_value_type type,
> -		u32 m_value,
> -		u32 n_value)
> +			       enum clock_recovery_m_value_type type,
> +			       u32 m_value,
> +			       u32 n_value)
>  {
>  	u32 reg;
>  
> @@ -1221,7 +1217,7 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
>  	u32 reg;
>  
>  	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
> -	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
> +	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
>  	reg |= MASTER_VID_FUNC_EN_N;
>  	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
>  
> 

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
  2015-09-01  5:49   ` Yakir Yang
@ 2015-09-03  0:58     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-03  0:58 UTC (permalink / raw)
  To: Yakir Yang, Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

On 01.09.2015 14:49, Yakir Yang wrote:
> Split the dp core driver from exynos directory to bridge
> directory, and rename the core driver to analogix_dp_*,
> leave the platform code to analogix_dp-exynos.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
> - Take Archit suggest, create a separate folder for analogix code in bridge/
> 
> Changes in v3:
> - Take Thierry Reding suggest, move exynos's video_timing code
>   to analogix_dp-exynos platform driver, add get_modes method
>   to struct analogix_dp_plat_data.
> - Take Heiko suggest, rename some "samsung*" dts propery to "analogix*".
> 
> Changes in v2:
> - Take Jingoo Han suggest, remove new copyright
> - Fix compiled failed dut to analogix_dp_device misspell
> 
>  drivers/gpu/drm/bridge/Kconfig                     |    2 +
>  drivers/gpu/drm/bridge/Makefile                    |    1 +
>  drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
>  drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
>  .../analogix/analogix_dp_core.c}                   |  817 ++++++-------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  283 +++++
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1265 ++++++++++++++++++++
>  .../analogix/analogix_dp_reg.h}                    |  258 ++--
>  drivers/gpu/drm/exynos/Kconfig                     |    3 +-
>  drivers/gpu/drm/exynos/Makefile                    |    2 +-
>  drivers/gpu/drm/exynos/exynos_dp.c                 |  306 +++++
>  drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 -----
>  drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1259 -------------------
>  include/drm/bridge/analogix_dp.h                   |   24 +
>  14 files changed, 2357 insertions(+), 2150 deletions(-)
>  create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
>  create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
>  rename drivers/gpu/drm/{exynos/exynos_dp_core.c => bridge/analogix/analogix_dp_core.c} (50%)
>  create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>  create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>  rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (64%)
>  create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
>  delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
>  delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
>  create mode 100644 include/drm/bridge/analogix_dp.h
> 
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 2de52a5..7b5b77a 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -29,4 +29,6 @@ config DRM_PARADE_PS8622
>  	---help---
>  	  Parade eDP-LVDS bridge chip driver.
>  
> +source "drivers/gpu/drm/bridge/analogix/Kconfig"
> +
>  endmenu
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index e2eef1c..5366c6b 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -3,3 +3,4 @@ ccflags-y := -Iinclude/drm
>  obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o
>  obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
>  obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
> diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
> new file mode 100644
> index 0000000..5ff6551
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
> @@ -0,0 +1,4 @@
> +config DRM_ANALOGIX_DP
> +	tristate
> +	depends on DRM
> +	select DRM_KMS_HELPER
> diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
> new file mode 100644
> index 0000000..9107b86
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> similarity index 50%
> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index bed0252..7d62f22 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -1,14 +1,14 @@
>  /*
> - * Samsung SoC DP (Display Port) interface driver.
> - *
> - * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> - * Author: Jingoo Han <jg1.han@samsung.com>
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms of the GNU General Public License as published by the
> - * Free Software Foundation; either version 2 of the License, or (at your
> - * option) any later version.
> - */
> +* Analogix DP (Display Port) core interface driver.
> +*
> +* Copyright (C) 2012 Samsung Electronics Co., Ltd.
> +* Author: Jingoo Han <jg1.han@samsung.com>
> +*
> +* This program is free software; you can redistribute it and/or modify it
> +* under the terms of the GNU General Public License as published by the
> +* Free Software Foundation; either version 2 of the License, or (at your
> +* option) any later version.
> +*/
>  
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
> @@ -18,12 +18,9 @@
>  #include <linux/interrupt.h>
>  #include <linux/of.h>
>  #include <linux/of_gpio.h>
> -#include <linux/of_graph.h>
>  #include <linux/gpio.h>
>  #include <linux/component.h>
>  #include <linux/phy/phy.h>
> -#include <video/of_display_timing.h>
> -#include <video/of_videomode.h>
>  
>  #include <drm/drmP.h>
>  #include <drm/drm_crtc.h>
> @@ -31,52 +28,42 @@
>  #include <drm/drm_atomic_helper.h>
>  #include <drm/drm_panel.h>
>  
> -#include "exynos_dp_core.h"
> -#include "exynos_drm_crtc.h"
> +#include <drm/bridge/analogix_dp.h>
>  
> -#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
> -					connector)
> +#include "analogix_dp_core.h"
>  
> -static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
> -{
> -	return to_exynos_crtc(dp->encoder.crtc);
> -}
> -
> -static inline struct exynos_dp_device *encoder_to_dp(
> -						struct drm_encoder *e)
> -{
> -	return container_of(e, struct exynos_dp_device, encoder);
> -}
> +#define connector_to_dp(c) \
> +	container_of(c, struct analogix_dp_device, connector)
>  
>  struct bridge_init {
>  	struct i2c_client *client;
>  	struct device_node *node;
>  };
>  
> -static void exynos_dp_init_dp(struct exynos_dp_device *dp)
> +static void analogix_dp_init_dp(struct analogix_dp_device *dp)
>  {
> -	exynos_dp_reset(dp);
> +	analogix_dp_reset(dp);
>  
> -	exynos_dp_swreset(dp);
> +	analogix_dp_swreset(dp);
>  
> -	exynos_dp_init_analog_param(dp);
> -	exynos_dp_init_interrupt(dp);
> +	analogix_dp_init_analog_param(dp);
> +	analogix_dp_init_interrupt(dp);
>  
>  	/* SW defined function Normal operation */
> -	exynos_dp_enable_sw_function(dp);
> +	analogix_dp_enable_sw_function(dp);
>  
> -	exynos_dp_config_interrupt(dp);
> -	exynos_dp_init_analog_func(dp);
> +	analogix_dp_config_interrupt(dp);
> +	analogix_dp_init_analog_func(dp);
>  
> -	exynos_dp_init_hpd(dp);
> -	exynos_dp_init_aux(dp);
> +	analogix_dp_init_hpd(dp);
> +	analogix_dp_init_aux(dp);
>  }
>  
> -static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
> +static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
>  {
>  	int timeout_loop = 0;
>  
> -	while (exynos_dp_get_plug_in_status(dp) != 0) {
> +	while (analogix_dp_get_plug_in_status(dp) != 0) {
>  		timeout_loop++;
>  		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
>  			dev_err(dp->dev, "failed to get hpd plug status\n");
> @@ -88,7 +75,7 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
>  	return 0;
>  }
>  
> -static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
> +static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
>  {
>  	int i;
>  	unsigned char sum = 0;
> @@ -99,7 +86,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
>  	return sum;
>  }
>  
> -static int exynos_dp_read_edid(struct exynos_dp_device *dp)
> +static int analogix_dp_read_edid(struct analogix_dp_device *dp)
>  {
>  	unsigned char edid[EDID_BLOCK_LENGTH * 2];
>  	unsigned int extend_block = 0;
> @@ -114,9 +101,9 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  	 */
>  
>  	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
> -	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> -					      EDID_EXTENSION_FLAG,
> -					      &extend_block);
> +	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> +						EDID_EXTENSION_FLAG,
> +						&extend_block);

Hi,

What was the point of patch 1 (checkpatch -f --subjective) if you
have to re-align the parameters again? It's meaningless.

I could understand that idea if this patch touched only first
line - name of the function. This would result in small
and effective diff, like:

-	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+	retval = SAME_LEGNTH____byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 					      EDID_EXTENSION_FLAG,

But this is not the case. The reviewer have to look at 6 lines
of changes instead of two. You fixed the alignment just for two
patches and then you re-written it. It's meaningless.

Nope. Please drop all changes from patch 1 which:  
(all conditions apply):
1. change alignment,
2. are immediately changed in next patches (e.g. like here),

and fix the alignment while renaming the function.

This is actually another point for not accepting commits where
the reason is "checkpatch told me".



>  	if (retval)
>  		return retval;
>  
> @@ -124,7 +111,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>  
>  		/* Read EDID data */
> -		retval = exynos_dp_read_bytes_from_i2c(
> +		retval = analogix_dp_read_bytes_from_i2c(
>  					dp, I2C_EDID_DEVICE_ADDR,
>  					EDID_HEADER_PATTERN,
>  					EDID_BLOCK_LENGTH,
> @@ -133,14 +120,14 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)

(...)

> @@ -871,218 +862,204 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
>  	return IRQ_HANDLED;
>  }
>  
> -static void exynos_dp_hotplug(struct work_struct *work)
> +static void analogix_dp_hotplug(struct work_struct *work)
>  {
> -	struct exynos_dp_device *dp;
> +	struct analogix_dp_device *dp;
>  
> -	dp = container_of(work, struct exynos_dp_device, hotplug_work);
> +	dp = container_of(work, struct analogix_dp_device, hotplug_work);
>  
>  	if (dp->drm_dev)
>  		drm_helper_hpd_irq_event(dp->drm_dev);
>  }
>  
> -static void exynos_dp_commit(struct drm_encoder *encoder)
> +static void analogix_dp_commit(struct analogix_dp_device *dp)
>  {
> -	struct exynos_dp_device *dp = encoder_to_dp(encoder);
>  	int ret;
>  
>  	/* Keep the panel disabled while we configure video */
> -	if (dp->panel) {
> -		if (drm_panel_disable(dp->panel))
> +	if (dp->plat_data && dp->plat_data->panel) {
> +		if (drm_panel_disable(dp->plat_data->panel))
>  			DRM_ERROR("failed to disable the panel\n");
>  	}
>  
> -	ret = exynos_dp_detect_hpd(dp);
> +	ret = analogix_dp_detect_hpd(dp);
>  	if (ret) {
>  		/* Cable has been disconnected, we're done */
>  		return;
>  	}
>  
> -	ret = exynos_dp_handle_edid(dp);
> +	ret = analogix_dp_handle_edid(dp);
>  	if (ret) {
>  		dev_err(dp->dev, "unable to handle edid\n");
>  		return;
>  	}
>  
> -	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
> -				       dp->video_info->link_rate);
> +	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
> +					 dp->video_info->link_rate);
>  	if (ret) {
>  		dev_err(dp->dev, "unable to do link train\n");
>  		return;
>  	}
>  
> -	exynos_dp_enable_scramble(dp, 1);
> -	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
> -	exynos_dp_enable_enhanced_mode(dp, 1);
> +	analogix_dp_enable_scramble(dp, 1);
> +	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
> +	analogix_dp_enable_enhanced_mode(dp, 1);
>  
> -	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
> -	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
> +	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
> +	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
>  
> -	exynos_dp_init_video(dp);
> -	ret = exynos_dp_config_video(dp);
> +	analogix_dp_init_video(dp);
> +	ret = analogix_dp_config_video(dp);
>  	if (ret)
>  		dev_err(dp->dev, "unable to config video\n");
>  
>  	/* Safe to enable the panel now */
> -	if (dp->panel) {
> -		if (drm_panel_enable(dp->panel))
> +	if (dp->plat_data && dp->plat_data->panel) {
> +		if (drm_panel_enable(dp->plat_data->panel))
>  			DRM_ERROR("failed to enable the panel\n");
>  	}
>  
>  	/* Enable video */
> -	exynos_dp_start_video(dp);
> +	analogix_dp_start_video(dp);
>  }
>  
>  static enum drm_connector_status
> -exynos_dp_detect(struct drm_connector *connector, bool force)
> +analogix_dp_detect(struct drm_connector *connector, bool force)
>  {
>  	return connector_status_connected;
>  }
>  
> -static void exynos_dp_connector_destroy(struct drm_connector *connector)
> +static void analogix_dp_connector_destroy(struct drm_connector *connector)
>  {
>  	drm_connector_unregister(connector);
>  	drm_connector_cleanup(connector);
>  }
>  
> -static struct drm_connector_funcs exynos_dp_connector_funcs = {
> +static struct drm_connector_funcs analogix_dp_connector_funcs = {
>  	.dpms = drm_atomic_helper_connector_dpms,
>  	.fill_modes = drm_helper_probe_single_connector_modes,
> -	.detect = exynos_dp_detect,
> -	.destroy = exynos_dp_connector_destroy,
> +	.detect = analogix_dp_detect,
> +	.destroy = analogix_dp_connector_destroy,
>  	.reset = drm_atomic_helper_connector_reset,
>  	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
>  	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>  };
>  
> -static int exynos_dp_get_modes(struct drm_connector *connector)
> +static int analogix_dp_get_modes(struct drm_connector *connector)
>  {
> -	struct exynos_dp_device *dp = ctx_from_connector(connector);
> -	struct drm_display_mode *mode;
> -
> -	if (dp->panel)
> -		return drm_panel_get_modes(dp->panel);
> +	struct analogix_dp_device *dp = connector_to_dp(connector);
> +	struct analogix_dp_plat_data *plat_data = dp->plat_data;
> +	int num_modes = 0;
>  
> -	mode = drm_mode_create(connector->dev);
> -	if (!mode) {
> -		DRM_ERROR("failed to create a new display mode.\n");
> -		return 0;
> -	}
> -
> -	drm_display_mode_from_videomode(&dp->priv.vm, mode);
> -	mode->width_mm = dp->priv.width_mm;
> -	mode->height_mm = dp->priv.height_mm;
> -	connector->display_info.width_mm = mode->width_mm;
> -	connector->display_info.height_mm = mode->height_mm;
> +	if (plat_data && plat_data->panel)
> +		num_modes += drm_panel_get_modes(plat_data->panel);
>  
> -	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
> -	drm_mode_set_name(mode);
> -	drm_mode_probed_add(connector, mode);
> +	if (plat_data && plat_data->get_modes)
> +		 num_modes += plat_data->get_modes(plat_data, connector);
>  
> -	return 1;
> +	return num_modes;
>  }
>  
>  static struct drm_encoder *
> -exynos_dp_best_encoder(struct drm_connector *connector)
> +analogix_dp_best_encoder(struct drm_connector *connector)
>  {
> -	struct exynos_dp_device *dp = ctx_from_connector(connector);
> +	struct analogix_dp_device *dp = connector_to_dp(connector);
>  
> -	return &dp->encoder;
> +	return dp->encoder;
>  }
>  
> -static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
> -	.get_modes = exynos_dp_get_modes,
> -	.best_encoder = exynos_dp_best_encoder,
> +static struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
> +	.get_modes = analogix_dp_get_modes,
> +	.best_encoder = analogix_dp_best_encoder,
>  };
>  
> -/* returns the number of bridges attached */
> -static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
> -					struct drm_encoder *encoder)
> -{
> -	int ret;
> -
> -	encoder->bridge->next = dp->ptn_bridge;
> -	dp->ptn_bridge->encoder = encoder;
> -	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
> -	if (ret) {
> -		DRM_ERROR("Failed to attach bridge to drm\n");
> -		return ret;
> -	}
> -
> -	return 0;
> -}
> -
> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>  {
> -	struct exynos_dp_device *dp = bridge->driver_private;
> -	struct drm_encoder *encoder = &dp->encoder;
> +	struct analogix_dp_device *dp = bridge->driver_private;
> +	struct drm_encoder *encoder = dp->encoder;
>  	struct drm_connector *connector = &dp->connector;
>  	int ret;
>  
> -	/* Pre-empt DP connector creation if there's a bridge */
> -	if (dp->ptn_bridge) {
> -		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
> -		if (!ret)
> -			return 0;
> +	if (!bridge->encoder) {
> +		DRM_ERROR("Parent encoder object not found");
> +		return -ENODEV;
>  	}
>  
> +	encoder->bridge = bridge;
> +
>  	connector->polled = DRM_CONNECTOR_POLL_HPD;
>  
>  	ret = drm_connector_init(dp->drm_dev, connector,
> -				 &exynos_dp_connector_funcs,
> +				 &analogix_dp_connector_funcs,
>  				 DRM_MODE_CONNECTOR_eDP);
>  	if (ret) {
>  		DRM_ERROR("Failed to initialize connector with drm\n");
>  		return ret;
>  	}
>  
> -	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
> +	drm_connector_helper_add(connector,
> +				 &analogix_dp_connector_helper_funcs);
>  	drm_connector_register(connector);
>  	drm_mode_connector_attach_encoder(connector, encoder);
>  
> -	if (dp->panel)
> -		ret = drm_panel_attach(dp->panel, &dp->connector);
> +	if (dp->plat_data && dp->plat_data->panel) {
> +		ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
> +		if (ret) {
> +			DRM_ERROR("Failed to attach panel\n");
> +			return ret;
> +		}
> +	}
> +
> +	/*
> +	 * This should be the end of attach function, caused
> +	 * we should ensure dp bridge could attach first.
> +	 */
> +	 if (dp->plat_data && dp->plat_data->attach) {
> +		 ret = dp->plat_data->attach(dp->plat_data, bridge);
> +		 if (ret) {
> +			 DRM_ERROR("Failed at platform attch func\n");

Two new error paths appeared here and above. Don't you have to
cleanup something? I don't know, just wondering...

(...)

> @@ -1345,22 +1286,9 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>  	disable_irq(dp->irq);
>  
>  	dp->drm_dev = drm_dev;
> +	dp->encoder = encoder;
>  
> -	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
> -						  EXYNOS_DISPLAY_TYPE_LCD);
> -	if (pipe < 0)
> -		return pipe;
> -
> -	encoder->possible_crtcs = 1 << pipe;
> -
> -	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
> -
> -	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
> -			 DRM_MODE_ENCODER_TMDS);
> -
> -	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
> -
> -	ret = exynos_dp_create_connector(encoder);
> +	ret = analogix_dp_create_bridge(drm_dev, dp);
>  	if (ret) {
>  		DRM_ERROR("failed to create connector ret = %d\n", ret);
>  		drm_encoder_cleanup(encoder);
> @@ -1369,103 +1297,36 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>  
>  	return 0;
>  }
> +EXPORT_SYMBOL_GPL(analogix_dp_bind);

Ooo, a new export symbol. I suppose it is necessary for the split
but the commit message does not mention exporting
anything nor the reason for doing it. Could you extend the commit
message describing more tha changes here and rationale for it?

(...)

> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> new file mode 100644
> index 0000000..b879d8c
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -0,0 +1,1265 @@
> +/*
> + * Analogix DP (Display port) core register interface driver.
> + *
> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> + * Author: Jingoo Han <jg1.han@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/delay.h>
> +#include <linux/gpio.h>
> +
> +#include "analogix_dp_core.h"
> +#include "analogix_dp_reg.h"
> +
> +#define COMMON_INT_MASK_1	0
> +#define COMMON_INT_MASK_2	0
> +#define COMMON_INT_MASK_3	0
> +#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
> +#define INT_STA_MASK		INT_HPD
> +
> +void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
> +{
> +	u32 reg;
> +
> +	if (enable) {
> +		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> +		reg |= HDCP_VIDEO_MUTE;
> +		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> +	} else {
> +		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> +		reg &= ~HDCP_VIDEO_MUTE;
> +		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> +	}
> +}
> +
> +void analogix_dp_stop_video(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> +	reg &= ~VIDEO_EN;
> +	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> +}
> +
> +void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
> +{
> +	u32 reg;
> +
> +	if (enable)
> +		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
> +			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
> +	else
> +		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
> +			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;

Here and in few other places with new code: no alignment?

You spent some time fixing these in patch 1, so I would assume
that new code already comes after "checkpatch -f --subjective".
That's actually the only valid reason for using checkpatch - new code.
However my mail reader could corrupt the output so maybe this is aligned?

Code seems fine after looking at it but review was rather shallow.
I don't know the Exynos DP driver.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-03  0:58     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-03  0:58 UTC (permalink / raw)
  To: linux-arm-kernel

On 01.09.2015 14:49, Yakir Yang wrote:
> Split the dp core driver from exynos directory to bridge
> directory, and rename the core driver to analogix_dp_*,
> leave the platform code to analogix_dp-exynos.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
> - Take Archit suggest, create a separate folder for analogix code in bridge/
> 
> Changes in v3:
> - Take Thierry Reding suggest, move exynos's video_timing code
>   to analogix_dp-exynos platform driver, add get_modes method
>   to struct analogix_dp_plat_data.
> - Take Heiko suggest, rename some "samsung*" dts propery to "analogix*".
> 
> Changes in v2:
> - Take Jingoo Han suggest, remove new copyright
> - Fix compiled failed dut to analogix_dp_device misspell
> 
>  drivers/gpu/drm/bridge/Kconfig                     |    2 +
>  drivers/gpu/drm/bridge/Makefile                    |    1 +
>  drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
>  drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
>  .../analogix/analogix_dp_core.c}                   |  817 ++++++-------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  283 +++++
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1265 ++++++++++++++++++++
>  .../analogix/analogix_dp_reg.h}                    |  258 ++--
>  drivers/gpu/drm/exynos/Kconfig                     |    3 +-
>  drivers/gpu/drm/exynos/Makefile                    |    2 +-
>  drivers/gpu/drm/exynos/exynos_dp.c                 |  306 +++++
>  drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 -----
>  drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1259 -------------------
>  include/drm/bridge/analogix_dp.h                   |   24 +
>  14 files changed, 2357 insertions(+), 2150 deletions(-)
>  create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
>  create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
>  rename drivers/gpu/drm/{exynos/exynos_dp_core.c => bridge/analogix/analogix_dp_core.c} (50%)
>  create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>  create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>  rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (64%)
>  create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
>  delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
>  delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
>  create mode 100644 include/drm/bridge/analogix_dp.h
> 
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 2de52a5..7b5b77a 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -29,4 +29,6 @@ config DRM_PARADE_PS8622
>  	---help---
>  	  Parade eDP-LVDS bridge chip driver.
>  
> +source "drivers/gpu/drm/bridge/analogix/Kconfig"
> +
>  endmenu
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index e2eef1c..5366c6b 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -3,3 +3,4 @@ ccflags-y := -Iinclude/drm
>  obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o
>  obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
>  obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
> diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
> new file mode 100644
> index 0000000..5ff6551
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
> @@ -0,0 +1,4 @@
> +config DRM_ANALOGIX_DP
> +	tristate
> +	depends on DRM
> +	select DRM_KMS_HELPER
> diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
> new file mode 100644
> index 0000000..9107b86
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> similarity index 50%
> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index bed0252..7d62f22 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -1,14 +1,14 @@
>  /*
> - * Samsung SoC DP (Display Port) interface driver.
> - *
> - * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> - * Author: Jingoo Han <jg1.han@samsung.com>
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms of the GNU General Public License as published by the
> - * Free Software Foundation; either version 2 of the License, or (at your
> - * option) any later version.
> - */
> +* Analogix DP (Display Port) core interface driver.
> +*
> +* Copyright (C) 2012 Samsung Electronics Co., Ltd.
> +* Author: Jingoo Han <jg1.han@samsung.com>
> +*
> +* This program is free software; you can redistribute it and/or modify it
> +* under the terms of the GNU General Public License as published by the
> +* Free Software Foundation; either version 2 of the License, or (at your
> +* option) any later version.
> +*/
>  
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
> @@ -18,12 +18,9 @@
>  #include <linux/interrupt.h>
>  #include <linux/of.h>
>  #include <linux/of_gpio.h>
> -#include <linux/of_graph.h>
>  #include <linux/gpio.h>
>  #include <linux/component.h>
>  #include <linux/phy/phy.h>
> -#include <video/of_display_timing.h>
> -#include <video/of_videomode.h>
>  
>  #include <drm/drmP.h>
>  #include <drm/drm_crtc.h>
> @@ -31,52 +28,42 @@
>  #include <drm/drm_atomic_helper.h>
>  #include <drm/drm_panel.h>
>  
> -#include "exynos_dp_core.h"
> -#include "exynos_drm_crtc.h"
> +#include <drm/bridge/analogix_dp.h>
>  
> -#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
> -					connector)
> +#include "analogix_dp_core.h"
>  
> -static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
> -{
> -	return to_exynos_crtc(dp->encoder.crtc);
> -}
> -
> -static inline struct exynos_dp_device *encoder_to_dp(
> -						struct drm_encoder *e)
> -{
> -	return container_of(e, struct exynos_dp_device, encoder);
> -}
> +#define connector_to_dp(c) \
> +	container_of(c, struct analogix_dp_device, connector)
>  
>  struct bridge_init {
>  	struct i2c_client *client;
>  	struct device_node *node;
>  };
>  
> -static void exynos_dp_init_dp(struct exynos_dp_device *dp)
> +static void analogix_dp_init_dp(struct analogix_dp_device *dp)
>  {
> -	exynos_dp_reset(dp);
> +	analogix_dp_reset(dp);
>  
> -	exynos_dp_swreset(dp);
> +	analogix_dp_swreset(dp);
>  
> -	exynos_dp_init_analog_param(dp);
> -	exynos_dp_init_interrupt(dp);
> +	analogix_dp_init_analog_param(dp);
> +	analogix_dp_init_interrupt(dp);
>  
>  	/* SW defined function Normal operation */
> -	exynos_dp_enable_sw_function(dp);
> +	analogix_dp_enable_sw_function(dp);
>  
> -	exynos_dp_config_interrupt(dp);
> -	exynos_dp_init_analog_func(dp);
> +	analogix_dp_config_interrupt(dp);
> +	analogix_dp_init_analog_func(dp);
>  
> -	exynos_dp_init_hpd(dp);
> -	exynos_dp_init_aux(dp);
> +	analogix_dp_init_hpd(dp);
> +	analogix_dp_init_aux(dp);
>  }
>  
> -static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
> +static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
>  {
>  	int timeout_loop = 0;
>  
> -	while (exynos_dp_get_plug_in_status(dp) != 0) {
> +	while (analogix_dp_get_plug_in_status(dp) != 0) {
>  		timeout_loop++;
>  		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
>  			dev_err(dp->dev, "failed to get hpd plug status\n");
> @@ -88,7 +75,7 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
>  	return 0;
>  }
>  
> -static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
> +static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
>  {
>  	int i;
>  	unsigned char sum = 0;
> @@ -99,7 +86,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
>  	return sum;
>  }
>  
> -static int exynos_dp_read_edid(struct exynos_dp_device *dp)
> +static int analogix_dp_read_edid(struct analogix_dp_device *dp)
>  {
>  	unsigned char edid[EDID_BLOCK_LENGTH * 2];
>  	unsigned int extend_block = 0;
> @@ -114,9 +101,9 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  	 */
>  
>  	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
> -	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> -					      EDID_EXTENSION_FLAG,
> -					      &extend_block);
> +	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> +						EDID_EXTENSION_FLAG,
> +						&extend_block);

Hi,

What was the point of patch 1 (checkpatch -f --subjective) if you
have to re-align the parameters again? It's meaningless.

I could understand that idea if this patch touched only first
line - name of the function. This would result in small
and effective diff, like:

-	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+	retval = SAME_LEGNTH____byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 					      EDID_EXTENSION_FLAG,

But this is not the case. The reviewer have to look at 6 lines
of changes instead of two. You fixed the alignment just for two
patches and then you re-written it. It's meaningless.

Nope. Please drop all changes from patch 1 which:  
(all conditions apply):
1. change alignment,
2. are immediately changed in next patches (e.g. like here),

and fix the alignment while renaming the function.

This is actually another point for not accepting commits where
the reason is "checkpatch told me".



>  	if (retval)
>  		return retval;
>  
> @@ -124,7 +111,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>  		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>  
>  		/* Read EDID data */
> -		retval = exynos_dp_read_bytes_from_i2c(
> +		retval = analogix_dp_read_bytes_from_i2c(
>  					dp, I2C_EDID_DEVICE_ADDR,
>  					EDID_HEADER_PATTERN,
>  					EDID_BLOCK_LENGTH,
> @@ -133,14 +120,14 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)

(...)

> @@ -871,218 +862,204 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
>  	return IRQ_HANDLED;
>  }
>  
> -static void exynos_dp_hotplug(struct work_struct *work)
> +static void analogix_dp_hotplug(struct work_struct *work)
>  {
> -	struct exynos_dp_device *dp;
> +	struct analogix_dp_device *dp;
>  
> -	dp = container_of(work, struct exynos_dp_device, hotplug_work);
> +	dp = container_of(work, struct analogix_dp_device, hotplug_work);
>  
>  	if (dp->drm_dev)
>  		drm_helper_hpd_irq_event(dp->drm_dev);
>  }
>  
> -static void exynos_dp_commit(struct drm_encoder *encoder)
> +static void analogix_dp_commit(struct analogix_dp_device *dp)
>  {
> -	struct exynos_dp_device *dp = encoder_to_dp(encoder);
>  	int ret;
>  
>  	/* Keep the panel disabled while we configure video */
> -	if (dp->panel) {
> -		if (drm_panel_disable(dp->panel))
> +	if (dp->plat_data && dp->plat_data->panel) {
> +		if (drm_panel_disable(dp->plat_data->panel))
>  			DRM_ERROR("failed to disable the panel\n");
>  	}
>  
> -	ret = exynos_dp_detect_hpd(dp);
> +	ret = analogix_dp_detect_hpd(dp);
>  	if (ret) {
>  		/* Cable has been disconnected, we're done */
>  		return;
>  	}
>  
> -	ret = exynos_dp_handle_edid(dp);
> +	ret = analogix_dp_handle_edid(dp);
>  	if (ret) {
>  		dev_err(dp->dev, "unable to handle edid\n");
>  		return;
>  	}
>  
> -	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
> -				       dp->video_info->link_rate);
> +	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
> +					 dp->video_info->link_rate);
>  	if (ret) {
>  		dev_err(dp->dev, "unable to do link train\n");
>  		return;
>  	}
>  
> -	exynos_dp_enable_scramble(dp, 1);
> -	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
> -	exynos_dp_enable_enhanced_mode(dp, 1);
> +	analogix_dp_enable_scramble(dp, 1);
> +	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
> +	analogix_dp_enable_enhanced_mode(dp, 1);
>  
> -	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
> -	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
> +	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
> +	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
>  
> -	exynos_dp_init_video(dp);
> -	ret = exynos_dp_config_video(dp);
> +	analogix_dp_init_video(dp);
> +	ret = analogix_dp_config_video(dp);
>  	if (ret)
>  		dev_err(dp->dev, "unable to config video\n");
>  
>  	/* Safe to enable the panel now */
> -	if (dp->panel) {
> -		if (drm_panel_enable(dp->panel))
> +	if (dp->plat_data && dp->plat_data->panel) {
> +		if (drm_panel_enable(dp->plat_data->panel))
>  			DRM_ERROR("failed to enable the panel\n");
>  	}
>  
>  	/* Enable video */
> -	exynos_dp_start_video(dp);
> +	analogix_dp_start_video(dp);
>  }
>  
>  static enum drm_connector_status
> -exynos_dp_detect(struct drm_connector *connector, bool force)
> +analogix_dp_detect(struct drm_connector *connector, bool force)
>  {
>  	return connector_status_connected;
>  }
>  
> -static void exynos_dp_connector_destroy(struct drm_connector *connector)
> +static void analogix_dp_connector_destroy(struct drm_connector *connector)
>  {
>  	drm_connector_unregister(connector);
>  	drm_connector_cleanup(connector);
>  }
>  
> -static struct drm_connector_funcs exynos_dp_connector_funcs = {
> +static struct drm_connector_funcs analogix_dp_connector_funcs = {
>  	.dpms = drm_atomic_helper_connector_dpms,
>  	.fill_modes = drm_helper_probe_single_connector_modes,
> -	.detect = exynos_dp_detect,
> -	.destroy = exynos_dp_connector_destroy,
> +	.detect = analogix_dp_detect,
> +	.destroy = analogix_dp_connector_destroy,
>  	.reset = drm_atomic_helper_connector_reset,
>  	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
>  	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>  };
>  
> -static int exynos_dp_get_modes(struct drm_connector *connector)
> +static int analogix_dp_get_modes(struct drm_connector *connector)
>  {
> -	struct exynos_dp_device *dp = ctx_from_connector(connector);
> -	struct drm_display_mode *mode;
> -
> -	if (dp->panel)
> -		return drm_panel_get_modes(dp->panel);
> +	struct analogix_dp_device *dp = connector_to_dp(connector);
> +	struct analogix_dp_plat_data *plat_data = dp->plat_data;
> +	int num_modes = 0;
>  
> -	mode = drm_mode_create(connector->dev);
> -	if (!mode) {
> -		DRM_ERROR("failed to create a new display mode.\n");
> -		return 0;
> -	}
> -
> -	drm_display_mode_from_videomode(&dp->priv.vm, mode);
> -	mode->width_mm = dp->priv.width_mm;
> -	mode->height_mm = dp->priv.height_mm;
> -	connector->display_info.width_mm = mode->width_mm;
> -	connector->display_info.height_mm = mode->height_mm;
> +	if (plat_data && plat_data->panel)
> +		num_modes += drm_panel_get_modes(plat_data->panel);
>  
> -	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
> -	drm_mode_set_name(mode);
> -	drm_mode_probed_add(connector, mode);
> +	if (plat_data && plat_data->get_modes)
> +		 num_modes += plat_data->get_modes(plat_data, connector);
>  
> -	return 1;
> +	return num_modes;
>  }
>  
>  static struct drm_encoder *
> -exynos_dp_best_encoder(struct drm_connector *connector)
> +analogix_dp_best_encoder(struct drm_connector *connector)
>  {
> -	struct exynos_dp_device *dp = ctx_from_connector(connector);
> +	struct analogix_dp_device *dp = connector_to_dp(connector);
>  
> -	return &dp->encoder;
> +	return dp->encoder;
>  }
>  
> -static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
> -	.get_modes = exynos_dp_get_modes,
> -	.best_encoder = exynos_dp_best_encoder,
> +static struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
> +	.get_modes = analogix_dp_get_modes,
> +	.best_encoder = analogix_dp_best_encoder,
>  };
>  
> -/* returns the number of bridges attached */
> -static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
> -					struct drm_encoder *encoder)
> -{
> -	int ret;
> -
> -	encoder->bridge->next = dp->ptn_bridge;
> -	dp->ptn_bridge->encoder = encoder;
> -	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
> -	if (ret) {
> -		DRM_ERROR("Failed to attach bridge to drm\n");
> -		return ret;
> -	}
> -
> -	return 0;
> -}
> -
> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>  {
> -	struct exynos_dp_device *dp = bridge->driver_private;
> -	struct drm_encoder *encoder = &dp->encoder;
> +	struct analogix_dp_device *dp = bridge->driver_private;
> +	struct drm_encoder *encoder = dp->encoder;
>  	struct drm_connector *connector = &dp->connector;
>  	int ret;
>  
> -	/* Pre-empt DP connector creation if there's a bridge */
> -	if (dp->ptn_bridge) {
> -		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
> -		if (!ret)
> -			return 0;
> +	if (!bridge->encoder) {
> +		DRM_ERROR("Parent encoder object not found");
> +		return -ENODEV;
>  	}
>  
> +	encoder->bridge = bridge;
> +
>  	connector->polled = DRM_CONNECTOR_POLL_HPD;
>  
>  	ret = drm_connector_init(dp->drm_dev, connector,
> -				 &exynos_dp_connector_funcs,
> +				 &analogix_dp_connector_funcs,
>  				 DRM_MODE_CONNECTOR_eDP);
>  	if (ret) {
>  		DRM_ERROR("Failed to initialize connector with drm\n");
>  		return ret;
>  	}
>  
> -	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
> +	drm_connector_helper_add(connector,
> +				 &analogix_dp_connector_helper_funcs);
>  	drm_connector_register(connector);
>  	drm_mode_connector_attach_encoder(connector, encoder);
>  
> -	if (dp->panel)
> -		ret = drm_panel_attach(dp->panel, &dp->connector);
> +	if (dp->plat_data && dp->plat_data->panel) {
> +		ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
> +		if (ret) {
> +			DRM_ERROR("Failed to attach panel\n");
> +			return ret;
> +		}
> +	}
> +
> +	/*
> +	 * This should be the end of attach function, caused
> +	 * we should ensure dp bridge could attach first.
> +	 */
> +	 if (dp->plat_data && dp->plat_data->attach) {
> +		 ret = dp->plat_data->attach(dp->plat_data, bridge);
> +		 if (ret) {
> +			 DRM_ERROR("Failed at platform attch func\n");

Two new error paths appeared here and above. Don't you have to
cleanup something? I don't know, just wondering...

(...)

> @@ -1345,22 +1286,9 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>  	disable_irq(dp->irq);
>  
>  	dp->drm_dev = drm_dev;
> +	dp->encoder = encoder;
>  
> -	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
> -						  EXYNOS_DISPLAY_TYPE_LCD);
> -	if (pipe < 0)
> -		return pipe;
> -
> -	encoder->possible_crtcs = 1 << pipe;
> -
> -	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
> -
> -	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
> -			 DRM_MODE_ENCODER_TMDS);
> -
> -	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
> -
> -	ret = exynos_dp_create_connector(encoder);
> +	ret = analogix_dp_create_bridge(drm_dev, dp);
>  	if (ret) {
>  		DRM_ERROR("failed to create connector ret = %d\n", ret);
>  		drm_encoder_cleanup(encoder);
> @@ -1369,103 +1297,36 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>  
>  	return 0;
>  }
> +EXPORT_SYMBOL_GPL(analogix_dp_bind);

Ooo, a new export symbol. I suppose it is necessary for the split
but the commit message does not mention exporting
anything nor the reason for doing it. Could you extend the commit
message describing more tha changes here and rationale for it?

(...)

> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> new file mode 100644
> index 0000000..b879d8c
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -0,0 +1,1265 @@
> +/*
> + * Analogix DP (Display port) core register interface driver.
> + *
> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> + * Author: Jingoo Han <jg1.han@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/delay.h>
> +#include <linux/gpio.h>
> +
> +#include "analogix_dp_core.h"
> +#include "analogix_dp_reg.h"
> +
> +#define COMMON_INT_MASK_1	0
> +#define COMMON_INT_MASK_2	0
> +#define COMMON_INT_MASK_3	0
> +#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
> +#define INT_STA_MASK		INT_HPD
> +
> +void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
> +{
> +	u32 reg;
> +
> +	if (enable) {
> +		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> +		reg |= HDCP_VIDEO_MUTE;
> +		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> +	} else {
> +		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> +		reg &= ~HDCP_VIDEO_MUTE;
> +		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> +	}
> +}
> +
> +void analogix_dp_stop_video(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> +	reg &= ~VIDEO_EN;
> +	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> +}
> +
> +void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
> +{
> +	u32 reg;
> +
> +	if (enable)
> +		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
> +			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
> +	else
> +		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
> +			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;

Here and in few other places with new code: no alignment?

You spent some time fixing these in patch 1, so I would assume
that new code already comes after "checkpatch -f --subjective".
That's actually the only valid reason for using checkpatch - new code.
However my mail reader could corrupt the output so maybe this is aligned?

Code seems fine after looking at it but review was rather shallow.
I don't know the Exynos DP driver.

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
  2015-09-02 13:27     ` Rob Herring
  (?)
@ 2015-09-03  3:25       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  3:25 UTC (permalink / raw)
  To: Rob Herring
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	Russell King, djkurtz, dianders, seanpaul, Ajay kumar,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Rob,

在 09/02/2015 09:27 PM, Rob Herring 写道:
> On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you want DP works rightly on rockchip platform,
>> then you should select both of them.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Kishon suggest, add commit message, and remove the redundant
>>    rockchip_dp_phy_init() function, move those code to probe() method.
>>    And remove driver .owner number.
>>
>> Changes in v3:
>> - Take Heiko suggest, add rockchip dp phy driver,
>>    collect the phy clocks and power control.
>>
>> Changes in v2: None
>>
>>   .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++
> It is preferred that you split binding doc's from driver changes.

Okay, done.

>>   drivers/phy/Kconfig                                |   7 +
>>   drivers/phy/Makefile                               |   1 +
>>   drivers/phy/phy-rockchip-dp.c                      | 166 +++++++++++++++++++++
>>   4 files changed, 200 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>>   create mode 100644 drivers/phy/phy-rockchip-dp.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> new file mode 100644
>> index 0000000..5de1088
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> @@ -0,0 +1,26 @@
>> +Rockchip Soc Seroes Display Port PHY
>> +------------------------------------
>> +
>> +Required properties:
>> +- compatible : should be one of the following supported values:
>> +        - "rockchip.rk3288-dp-phy"
>> +
>> +- reg : a list of registers used by phy driver
> Please state the size of the list and order of what each entry if more than one.

Just like Heiko remind, I don't need the reg number anymore,
"rockchip,grf" is enough for this driver.

Anyway thanks :-)

>> +- clocks: from common clock binding: handle to dp clock.
>> +       of memory mapped region.
>> +- clock-names: from common clock binding:
>> +       Required elements: "sclk_dp" "sclk_dp_24m"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> I have no idea what GRF means.

GRF is an module of our IC chip, the full name is General Register Files.
I would rather to pick some words from our TRM.

The general register file will be used to do static set by software, which
is composed of many registers for system control.

>
>> +- #phy-cells : from the generic PHY bindings, must be 0;
>> +
>> +Example:
>> +
>> +edp_phy: phy@ff770274 {
>> +       compatilble = "rockchip,rk3288-dp-phy";
>> +       reg = <0xff770274 4>;
>> +       rockchip,grf = <&grf>;
>> +       clocks = <&cru SCLK_EDP_24M>;
>> +       clock-names = "24m";
>> +       #phy-cells = <0>;
>> +}
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 47da573..8f2bc4f 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>>          help
>>            Enable this to support the Rockchip USB 2.0 PHY.
>>
>> +config PHY_ROCKCHIP_DP
>> +       tristate "Rockchip Display Port PHY Driver"
>> +       depends on ARCH_ROCKCHIP && OF
>> +       select GENERIC_PHY
>> +       help
>> +         Enable this to support the Rockchip Display Port PHY.
>> +
>>   config PHY_ST_SPEAR1310_MIPHY
>>          tristate "ST SPEAR1310-MIPHY driver"
>>          select GENERIC_PHY
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a5b18c1..e281f35 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)    += phy-s5pv210-usb2.o
>>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)       += phy-exynos5-usbdrd.o
>>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)    += phy-qcom-apq8064-sata.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>> +obj-$(CONFIG_PHY_ROCKCHIP_DP)          += phy-rockchip-dp.o
>>   obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)    += phy-qcom-ipq806x-sata.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)   += phy-spear1310-miphy.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)   += phy-spear1340-miphy.o
>> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
>> new file mode 100644
>> index 0000000..e9a726e
>> --- /dev/null
>> +++ b/drivers/phy/phy-rockchip-dp.c
>> @@ -0,0 +1,166 @@
>> +/*
>> + * Rockchip DP PHY driver
>> + *
>> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
>> + * Author: Yakir Yang <ykk@@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define GRF_SOC_CON12                   0x0274
>> +#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
>> +
>> +#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
>> +#define DP_PHY_SIDDQ_ON                 0
>> +#define DP_PHY_SIDDQ_OFF                BIT(5)
>> +
>> +struct rockchip_dp_phy {
>> +       struct device  *dev;
>> +       struct regmap  *grf;
>> +       void __iomem   *regs;
>> +       struct clk     *phy_24m;
>> +};
>> +
>> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
>> +{
>> +       int ret = 0;
>> +
>> +       ret = clk_set_rate(dp->phy_24m, 24000000);
> Do you need to do this every time? This can go in probe.

Yeah, it could move to probe, thanks.

>> +       if (ret < 0) {
>> +               dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
>> +               return ret;
>> +       }
>> +
>> +       ret = clk_prepare_enable(dp->phy_24m);
>> +       if (ret < 0) {
>> +               dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
>> +               return ret;
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
>> +{
>> +       clk_disable_unprepare(dp->phy_24m);
>> +
>> +       return 0;
>> +}
>> +
>> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
>> +{
>> +       struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
>> +
>> +       if (enable) {
>> +               rockchip_dp_phy_clk_enable(dp);
>> +               writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
>> +       } else {
>> +               rockchip_dp_phy_clk_disable(dp);
>> +               writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
>> +       }
>> +
>> +       return 0;
>> +}
> I would just inline all 3 of these functions. The wrappers don't
> doesn't do anything, but add 2 levels of function calls.

After move clk_set_rate to probe, I would rather to remove those
wrappers just operate in power_on/power_off directly.  :)

>
>> +
>> +static int rockchip_dp_phy_power_on(struct phy *phy)
>> +{
>> +       return rockchip_set_phy_state(phy, true);
>> +}
>> +
>> +static int rockchip_dp_phy_power_off(struct phy *phy)
>> +{
>> +       return rockchip_set_phy_state(phy, false);
>> +}
>> +
>> +static struct phy_ops rockchip_dp_phy_ops = {
>> +       .power_on       = rockchip_dp_phy_power_on,
>> +       .power_off      = rockchip_dp_phy_power_off,
>> +       .owner          = THIS_MODULE,
>> +};
>> +
>> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
>> +{
>> +       struct device *dev = &pdev->dev;
>> +       struct device_node *np = dev->of_node;
>> +       struct phy_provider *phy_provider;
>> +       struct rockchip_dp_phy *dp;
>> +       struct resource *res;
>> +       struct phy *phy;
>> +       int ret;
>> +
>> +       dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
>> +       if (IS_ERR(dp))
>> +               return -ENOMEM;
>> +
>> +       dp->dev = dev;
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +       dp->regs = devm_ioremap_resource(dev, res);
>> +       if (IS_ERR(dp->regs))
>> +               return PTR_ERR(dp->regs);
>> +
>> +       dp->phy_24m = devm_clk_get(dev, "24m");
>> +       if (IS_ERR(dp->phy_24m)) {
>> +               dev_err(dev, "cannot get clock 24m\n");
>> +               return PTR_ERR(dp->phy_24m);
>> +       }
> The binding says there are 2 clocks.

Oh... Document have been little bit old. I used to handle
two kinds of clocks in phy driver in v2, and take Thierry
and Heiko suggest to reduce to one clock in v3, but forget
to improved the Document at the same time.

+- clock-names: from common clock binding:
+       Required elements: "sclk_dp" "sclk_dp_24m"

should be

+- clock-names: from common clock binding:
+       Required elements: "24m"

Thanks for your point out.

>> +
>> +       dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
>> +       if (IS_ERR(dp->grf)) {
>> +               dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
>> +               return PTR_ERR(dp->grf);
>> +       }
>> +
>> +       ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> +                          GRF_EDP_REF_CLK_SEL_INTER |
>> +                          (GRF_EDP_REF_CLK_SEL_INTER << 16));
>> +       if (ret != 0) {
>> +               dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
>> +               return ret;
>> +       }
>> +
>> +       phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
>> +       if (IS_ERR(phy)) {
>> +               dev_err(dev, "failed to create phy\n");
>> +               return PTR_ERR(phy);
>> +       }
>> +       phy_set_drvdata(phy, dp);
>> +
>> +       phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> +
>> +       return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
>> +       { .compatible = "rockchip,rk3288-dp-phy" },
>> +       {}
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
>> +
>> +static struct platform_driver rockchip_dp_phy_driver = {
>> +       .probe          = rockchip_dp_phy_probe,
>> +       .driver         = {
>> +               .name   = "rockchip-dp-phy",
>> +               .of_match_table = rockchip_dp_phy_dt_ids,
>> +       },
>> +};
>> +
>> +module_platform_driver(rockchip_dp_phy_driver);
>> +
>> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
>> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
>> +MODULE_LICENSE("GPL v2");
>> --
>> 2.1.2
>>
>>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-03  3:25       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  3:25 UTC (permalink / raw)
  To: Rob Herring
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	Russell King, djkurtz, dianders, seanpaul, Ajay kumar,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel

Hi Rob,

在 09/02/2015 09:27 PM, Rob Herring 写道:
> On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you want DP works rightly on rockchip platform,
>> then you should select both of them.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Kishon suggest, add commit message, and remove the redundant
>>    rockchip_dp_phy_init() function, move those code to probe() method.
>>    And remove driver .owner number.
>>
>> Changes in v3:
>> - Take Heiko suggest, add rockchip dp phy driver,
>>    collect the phy clocks and power control.
>>
>> Changes in v2: None
>>
>>   .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++
> It is preferred that you split binding doc's from driver changes.

Okay, done.

>>   drivers/phy/Kconfig                                |   7 +
>>   drivers/phy/Makefile                               |   1 +
>>   drivers/phy/phy-rockchip-dp.c                      | 166 +++++++++++++++++++++
>>   4 files changed, 200 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>>   create mode 100644 drivers/phy/phy-rockchip-dp.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> new file mode 100644
>> index 0000000..5de1088
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> @@ -0,0 +1,26 @@
>> +Rockchip Soc Seroes Display Port PHY
>> +------------------------------------
>> +
>> +Required properties:
>> +- compatible : should be one of the following supported values:
>> +        - "rockchip.rk3288-dp-phy"
>> +
>> +- reg : a list of registers used by phy driver
> Please state the size of the list and order of what each entry if more than one.

Just like Heiko remind, I don't need the reg number anymore,
"rockchip,grf" is enough for this driver.

Anyway thanks :-)

>> +- clocks: from common clock binding: handle to dp clock.
>> +       of memory mapped region.
>> +- clock-names: from common clock binding:
>> +       Required elements: "sclk_dp" "sclk_dp_24m"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> I have no idea what GRF means.

GRF is an module of our IC chip, the full name is General Register Files.
I would rather to pick some words from our TRM.

The general register file will be used to do static set by software, which
is composed of many registers for system control.

>
>> +- #phy-cells : from the generic PHY bindings, must be 0;
>> +
>> +Example:
>> +
>> +edp_phy: phy@ff770274 {
>> +       compatilble = "rockchip,rk3288-dp-phy";
>> +       reg = <0xff770274 4>;
>> +       rockchip,grf = <&grf>;
>> +       clocks = <&cru SCLK_EDP_24M>;
>> +       clock-names = "24m";
>> +       #phy-cells = <0>;
>> +}
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 47da573..8f2bc4f 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>>          help
>>            Enable this to support the Rockchip USB 2.0 PHY.
>>
>> +config PHY_ROCKCHIP_DP
>> +       tristate "Rockchip Display Port PHY Driver"
>> +       depends on ARCH_ROCKCHIP && OF
>> +       select GENERIC_PHY
>> +       help
>> +         Enable this to support the Rockchip Display Port PHY.
>> +
>>   config PHY_ST_SPEAR1310_MIPHY
>>          tristate "ST SPEAR1310-MIPHY driver"
>>          select GENERIC_PHY
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a5b18c1..e281f35 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)    += phy-s5pv210-usb2.o
>>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)       += phy-exynos5-usbdrd.o
>>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)    += phy-qcom-apq8064-sata.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>> +obj-$(CONFIG_PHY_ROCKCHIP_DP)          += phy-rockchip-dp.o
>>   obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)    += phy-qcom-ipq806x-sata.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)   += phy-spear1310-miphy.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)   += phy-spear1340-miphy.o
>> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
>> new file mode 100644
>> index 0000000..e9a726e
>> --- /dev/null
>> +++ b/drivers/phy/phy-rockchip-dp.c
>> @@ -0,0 +1,166 @@
>> +/*
>> + * Rockchip DP PHY driver
>> + *
>> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
>> + * Author: Yakir Yang <ykk@@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define GRF_SOC_CON12                   0x0274
>> +#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
>> +
>> +#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
>> +#define DP_PHY_SIDDQ_ON                 0
>> +#define DP_PHY_SIDDQ_OFF                BIT(5)
>> +
>> +struct rockchip_dp_phy {
>> +       struct device  *dev;
>> +       struct regmap  *grf;
>> +       void __iomem   *regs;
>> +       struct clk     *phy_24m;
>> +};
>> +
>> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
>> +{
>> +       int ret = 0;
>> +
>> +       ret = clk_set_rate(dp->phy_24m, 24000000);
> Do you need to do this every time? This can go in probe.

Yeah, it could move to probe, thanks.

>> +       if (ret < 0) {
>> +               dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
>> +               return ret;
>> +       }
>> +
>> +       ret = clk_prepare_enable(dp->phy_24m);
>> +       if (ret < 0) {
>> +               dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
>> +               return ret;
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
>> +{
>> +       clk_disable_unprepare(dp->phy_24m);
>> +
>> +       return 0;
>> +}
>> +
>> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
>> +{
>> +       struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
>> +
>> +       if (enable) {
>> +               rockchip_dp_phy_clk_enable(dp);
>> +               writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
>> +       } else {
>> +               rockchip_dp_phy_clk_disable(dp);
>> +               writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
>> +       }
>> +
>> +       return 0;
>> +}
> I would just inline all 3 of these functions. The wrappers don't
> doesn't do anything, but add 2 levels of function calls.

After move clk_set_rate to probe, I would rather to remove those
wrappers just operate in power_on/power_off directly.  :)

>
>> +
>> +static int rockchip_dp_phy_power_on(struct phy *phy)
>> +{
>> +       return rockchip_set_phy_state(phy, true);
>> +}
>> +
>> +static int rockchip_dp_phy_power_off(struct phy *phy)
>> +{
>> +       return rockchip_set_phy_state(phy, false);
>> +}
>> +
>> +static struct phy_ops rockchip_dp_phy_ops = {
>> +       .power_on       = rockchip_dp_phy_power_on,
>> +       .power_off      = rockchip_dp_phy_power_off,
>> +       .owner          = THIS_MODULE,
>> +};
>> +
>> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
>> +{
>> +       struct device *dev = &pdev->dev;
>> +       struct device_node *np = dev->of_node;
>> +       struct phy_provider *phy_provider;
>> +       struct rockchip_dp_phy *dp;
>> +       struct resource *res;
>> +       struct phy *phy;
>> +       int ret;
>> +
>> +       dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
>> +       if (IS_ERR(dp))
>> +               return -ENOMEM;
>> +
>> +       dp->dev = dev;
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +       dp->regs = devm_ioremap_resource(dev, res);
>> +       if (IS_ERR(dp->regs))
>> +               return PTR_ERR(dp->regs);
>> +
>> +       dp->phy_24m = devm_clk_get(dev, "24m");
>> +       if (IS_ERR(dp->phy_24m)) {
>> +               dev_err(dev, "cannot get clock 24m\n");
>> +               return PTR_ERR(dp->phy_24m);
>> +       }
> The binding says there are 2 clocks.

Oh... Document have been little bit old. I used to handle
two kinds of clocks in phy driver in v2, and take Thierry
and Heiko suggest to reduce to one clock in v3, but forget
to improved the Document at the same time.

+- clock-names: from common clock binding:
+       Required elements: "sclk_dp" "sclk_dp_24m"

should be

+- clock-names: from common clock binding:
+       Required elements: "24m"

Thanks for your point out.

>> +
>> +       dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
>> +       if (IS_ERR(dp->grf)) {
>> +               dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
>> +               return PTR_ERR(dp->grf);
>> +       }
>> +
>> +       ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> +                          GRF_EDP_REF_CLK_SEL_INTER |
>> +                          (GRF_EDP_REF_CLK_SEL_INTER << 16));
>> +       if (ret != 0) {
>> +               dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
>> +               return ret;
>> +       }
>> +
>> +       phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
>> +       if (IS_ERR(phy)) {
>> +               dev_err(dev, "failed to create phy\n");
>> +               return PTR_ERR(phy);
>> +       }
>> +       phy_set_drvdata(phy, dp);
>> +
>> +       phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> +
>> +       return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
>> +       { .compatible = "rockchip,rk3288-dp-phy" },
>> +       {}
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
>> +
>> +static struct platform_driver rockchip_dp_phy_driver = {
>> +       .probe          = rockchip_dp_phy_probe,
>> +       .driver         = {
>> +               .name   = "rockchip-dp-phy",
>> +               .of_match_table = rockchip_dp_phy_dt_ids,
>> +       },
>> +};
>> +
>> +module_platform_driver(rockchip_dp_phy_driver);
>> +
>> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
>> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
>> +MODULE_LICENSE("GPL v2");
>> --
>> 2.1.2
>>
>>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-03  3:25       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  3:25 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Rob,

? 09/02/2015 09:27 PM, Rob Herring ??:
> On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you want DP works rightly on rockchip platform,
>> then you should select both of them.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Kishon suggest, add commit message, and remove the redundant
>>    rockchip_dp_phy_init() function, move those code to probe() method.
>>    And remove driver .owner number.
>>
>> Changes in v3:
>> - Take Heiko suggest, add rockchip dp phy driver,
>>    collect the phy clocks and power control.
>>
>> Changes in v2: None
>>
>>   .../devicetree/bindings/phy/rockchip-dp-phy.txt    |  26 ++++
> It is preferred that you split binding doc's from driver changes.

Okay, done.

>>   drivers/phy/Kconfig                                |   7 +
>>   drivers/phy/Makefile                               |   1 +
>>   drivers/phy/phy-rockchip-dp.c                      | 166 +++++++++++++++++++++
>>   4 files changed, 200 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>>   create mode 100644 drivers/phy/phy-rockchip-dp.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> new file mode 100644
>> index 0000000..5de1088
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> @@ -0,0 +1,26 @@
>> +Rockchip Soc Seroes Display Port PHY
>> +------------------------------------
>> +
>> +Required properties:
>> +- compatible : should be one of the following supported values:
>> +        - "rockchip.rk3288-dp-phy"
>> +
>> +- reg : a list of registers used by phy driver
> Please state the size of the list and order of what each entry if more than one.

Just like Heiko remind, I don't need the reg number anymore,
"rockchip,grf" is enough for this driver.

Anyway thanks :-)

>> +- clocks: from common clock binding: handle to dp clock.
>> +       of memory mapped region.
>> +- clock-names: from common clock binding:
>> +       Required elements: "sclk_dp" "sclk_dp_24m"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> I have no idea what GRF means.

GRF is an module of our IC chip, the full name is General Register Files.
I would rather to pick some words from our TRM.

The general register file will be used to do static set by software, which
is composed of many registers for system control.

>
>> +- #phy-cells : from the generic PHY bindings, must be 0;
>> +
>> +Example:
>> +
>> +edp_phy: phy at ff770274 {
>> +       compatilble = "rockchip,rk3288-dp-phy";
>> +       reg = <0xff770274 4>;
>> +       rockchip,grf = <&grf>;
>> +       clocks = <&cru SCLK_EDP_24M>;
>> +       clock-names = "24m";
>> +       #phy-cells = <0>;
>> +}
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 47da573..8f2bc4f 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>>          help
>>            Enable this to support the Rockchip USB 2.0 PHY.
>>
>> +config PHY_ROCKCHIP_DP
>> +       tristate "Rockchip Display Port PHY Driver"
>> +       depends on ARCH_ROCKCHIP && OF
>> +       select GENERIC_PHY
>> +       help
>> +         Enable this to support the Rockchip Display Port PHY.
>> +
>>   config PHY_ST_SPEAR1310_MIPHY
>>          tristate "ST SPEAR1310-MIPHY driver"
>>          select GENERIC_PHY
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a5b18c1..e281f35 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)    += phy-s5pv210-usb2.o
>>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)       += phy-exynos5-usbdrd.o
>>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)    += phy-qcom-apq8064-sata.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>> +obj-$(CONFIG_PHY_ROCKCHIP_DP)          += phy-rockchip-dp.o
>>   obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)    += phy-qcom-ipq806x-sata.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)   += phy-spear1310-miphy.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)   += phy-spear1340-miphy.o
>> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
>> new file mode 100644
>> index 0000000..e9a726e
>> --- /dev/null
>> +++ b/drivers/phy/phy-rockchip-dp.c
>> @@ -0,0 +1,166 @@
>> +/*
>> + * Rockchip DP PHY driver
>> + *
>> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
>> + * Author: Yakir Yang <ykk@@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define GRF_SOC_CON12                   0x0274
>> +#define GRF_EDP_REF_CLK_SEL_INTER       BIT(4)
>> +
>> +#define DP_PHY_SIDDQ_WRITE_EN           BIT(21)
>> +#define DP_PHY_SIDDQ_ON                 0
>> +#define DP_PHY_SIDDQ_OFF                BIT(5)
>> +
>> +struct rockchip_dp_phy {
>> +       struct device  *dev;
>> +       struct regmap  *grf;
>> +       void __iomem   *regs;
>> +       struct clk     *phy_24m;
>> +};
>> +
>> +static int rockchip_dp_phy_clk_enable(struct rockchip_dp_phy *dp)
>> +{
>> +       int ret = 0;
>> +
>> +       ret = clk_set_rate(dp->phy_24m, 24000000);
> Do you need to do this every time? This can go in probe.

Yeah, it could move to probe, thanks.

>> +       if (ret < 0) {
>> +               dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
>> +               return ret;
>> +       }
>> +
>> +       ret = clk_prepare_enable(dp->phy_24m);
>> +       if (ret < 0) {
>> +               dev_err(dp->dev, "cannot enable clock phy_24m %d\n", ret);
>> +               return ret;
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +static int rockchip_dp_phy_clk_disable(struct rockchip_dp_phy *dp)
>> +{
>> +       clk_disable_unprepare(dp->phy_24m);
>> +
>> +       return 0;
>> +}
>> +
>> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
>> +{
>> +       struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
>> +
>> +       if (enable) {
>> +               rockchip_dp_phy_clk_enable(dp);
>> +               writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_ON, dp->regs);
>> +       } else {
>> +               rockchip_dp_phy_clk_disable(dp);
>> +               writel(DP_PHY_SIDDQ_WRITE_EN | DP_PHY_SIDDQ_OFF, dp->regs);
>> +       }
>> +
>> +       return 0;
>> +}
> I would just inline all 3 of these functions. The wrappers don't
> doesn't do anything, but add 2 levels of function calls.

After move clk_set_rate to probe, I would rather to remove those
wrappers just operate in power_on/power_off directly.  :)

>
>> +
>> +static int rockchip_dp_phy_power_on(struct phy *phy)
>> +{
>> +       return rockchip_set_phy_state(phy, true);
>> +}
>> +
>> +static int rockchip_dp_phy_power_off(struct phy *phy)
>> +{
>> +       return rockchip_set_phy_state(phy, false);
>> +}
>> +
>> +static struct phy_ops rockchip_dp_phy_ops = {
>> +       .power_on       = rockchip_dp_phy_power_on,
>> +       .power_off      = rockchip_dp_phy_power_off,
>> +       .owner          = THIS_MODULE,
>> +};
>> +
>> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
>> +{
>> +       struct device *dev = &pdev->dev;
>> +       struct device_node *np = dev->of_node;
>> +       struct phy_provider *phy_provider;
>> +       struct rockchip_dp_phy *dp;
>> +       struct resource *res;
>> +       struct phy *phy;
>> +       int ret;
>> +
>> +       dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
>> +       if (IS_ERR(dp))
>> +               return -ENOMEM;
>> +
>> +       dp->dev = dev;
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +       dp->regs = devm_ioremap_resource(dev, res);
>> +       if (IS_ERR(dp->regs))
>> +               return PTR_ERR(dp->regs);
>> +
>> +       dp->phy_24m = devm_clk_get(dev, "24m");
>> +       if (IS_ERR(dp->phy_24m)) {
>> +               dev_err(dev, "cannot get clock 24m\n");
>> +               return PTR_ERR(dp->phy_24m);
>> +       }
> The binding says there are 2 clocks.

Oh... Document have been little bit old. I used to handle
two kinds of clocks in phy driver in v2, and take Thierry
and Heiko suggest to reduce to one clock in v3, but forget
to improved the Document at the same time.

+- clock-names: from common clock binding:
+       Required elements: "sclk_dp" "sclk_dp_24m"

should be

+- clock-names: from common clock binding:
+       Required elements: "24m"

Thanks for your point out.

>> +
>> +       dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
>> +       if (IS_ERR(dp->grf)) {
>> +               dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
>> +               return PTR_ERR(dp->grf);
>> +       }
>> +
>> +       ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> +                          GRF_EDP_REF_CLK_SEL_INTER |
>> +                          (GRF_EDP_REF_CLK_SEL_INTER << 16));
>> +       if (ret != 0) {
>> +               dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
>> +               return ret;
>> +       }
>> +
>> +       phy = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops, NULL);
>> +       if (IS_ERR(phy)) {
>> +               dev_err(dev, "failed to create phy\n");
>> +               return PTR_ERR(phy);
>> +       }
>> +       phy_set_drvdata(phy, dp);
>> +
>> +       phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> +
>> +       return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
>> +       { .compatible = "rockchip,rk3288-dp-phy" },
>> +       {}
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
>> +
>> +static struct platform_driver rockchip_dp_phy_driver = {
>> +       .probe          = rockchip_dp_phy_probe,
>> +       .driver         = {
>> +               .name   = "rockchip-dp-phy",
>> +               .of_match_table = rockchip_dp_phy_dt_ids,
>> +       },
>> +};
>> +
>> +module_platform_driver(rockchip_dp_phy_driver);
>> +
>> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
>> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
>> +MODULE_LICENSE("GPL v2");
>> --
>> 2.1.2
>>
>>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
  2015-09-02 14:50     ` Emil Velikov
  (?)
@ 2015-09-03  3:55       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  3:55 UTC (permalink / raw)
  To: Emil Velikov
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, ML dri-devel,
	Andrzej Hajda, Gustavo Padovan,
	moderated list:ARM/S5P EXYNOS AR...,
	seanpaul, djkurtz, Kishon Vijay Abraham I, linux-rockchip,
	robherring2, Russell King, devicetree, Pawel Moll, Ian Campbell,
	Rob Herring, dianders, linux-arm-kernel,
	Linux-Kernel@Vger. Kernel. Org, Kyungmin Park, Kumar Gala,
	ajaynumb, Andy Yan

Hi Emil,

在 09/02/2015 10:50 PM, Emil Velikov 写道:
> [Dropping the CC list]

Hmm...Don't understand what this means. If you can explain, that
would be better, so I would not miss your suggest.  :-)

> Hi Yakir Yang,
>
> On 1 September 2015 at 06:49, Yakir Yang <ykk@rock-chips.com> wrote:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code to analogix_dp-exynos.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
>> - Take Archit suggest, create a separate folder for analogix code in bridge/
>>
> "Take X suggest", is grammatically incorrect. You should use
> "suggestion(s)" or alternatively use the following approach.
>
> - Create a separate folder for analogix code in bridge/ (Archit)

Thanks for your correct. I prefer to take the last one  ;)

> Cheers,
> Emil
>
> P.S. Why do you resend the whole series (some 10+ patches) when only a
> few patches have been changed ? Are all the patches changed whist
> missing that information (vX: rebase on top of A)

Yes, those 10+ patches do base on the previous changes, specially when I
rebase my series on the latest linux-next branch.

Besides, I don't know that how to send parts of this series, and keep the
unrelated patches no send. For example if the [v4 03/16] ~ [v4 10/16]
need  update to v5, and [v4 11/16] ~ [v4 16/16] keep in v4.
So should I only send the [v5 03/16]  ~ [v5 10/16], no need to send and
update [v4 11/16] ~ [v4 16/16] to v5 ?

If so I think it would be difficult for guys to comment, cause they 
can't see
the whole series in one reply list .   ;)

Thanks,
- Yakir
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-03  3:55       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  3:55 UTC (permalink / raw)
  To: Emil Velikov
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae, joe,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, ML dri-devel,
	Andrzej Hajda, Gustavo Padovan,
	moderated list:ARM/S5P EXYNOS AR...,
	seanpaul, djkurtz, Kishon Vijay Abraham I, linux-rockchip,
	robherring2, Russell King, devicetree, Pawel Moll, Ian Campbell,
	Rob Herring, dianders, linux-arm-kernel, Linu

Hi Emil,

在 09/02/2015 10:50 PM, Emil Velikov 写道:
> [Dropping the CC list]

Hmm...Don't understand what this means. If you can explain, that
would be better, so I would not miss your suggest.  :-)

> Hi Yakir Yang,
>
> On 1 September 2015 at 06:49, Yakir Yang <ykk@rock-chips.com> wrote:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code to analogix_dp-exynos.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
>> - Take Archit suggest, create a separate folder for analogix code in bridge/
>>
> "Take X suggest", is grammatically incorrect. You should use
> "suggestion(s)" or alternatively use the following approach.
>
> - Create a separate folder for analogix code in bridge/ (Archit)

Thanks for your correct. I prefer to take the last one  ;)

> Cheers,
> Emil
>
> P.S. Why do you resend the whole series (some 10+ patches) when only a
> few patches have been changed ? Are all the patches changed whist
> missing that information (vX: rebase on top of A)

Yes, those 10+ patches do base on the previous changes, specially when I
rebase my series on the latest linux-next branch.

Besides, I don't know that how to send parts of this series, and keep the
unrelated patches no send. For example if the [v4 03/16] ~ [v4 10/16]
need  update to v5, and [v4 11/16] ~ [v4 16/16] keep in v4.
So should I only send the [v5 03/16]  ~ [v5 10/16], no need to send and
update [v4 11/16] ~ [v4 16/16] to v5 ?

If so I think it would be difficult for guys to comment, cause they 
can't see
the whole series in one reply list .   ;)

Thanks,
- Yakir
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-03  3:55       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  3:55 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Emil,

? 09/02/2015 10:50 PM, Emil Velikov ??:
> [Dropping the CC list]

Hmm...Don't understand what this means. If you can explain, that
would be better, so I would not miss your suggest.  :-)

> Hi Yakir Yang,
>
> On 1 September 2015 at 06:49, Yakir Yang <ykk@rock-chips.com> wrote:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code to analogix_dp-exynos.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
>> - Take Archit suggest, create a separate folder for analogix code in bridge/
>>
> "Take X suggest", is grammatically incorrect. You should use
> "suggestion(s)" or alternatively use the following approach.
>
> - Create a separate folder for analogix code in bridge/ (Archit)

Thanks for your correct. I prefer to take the last one  ;)

> Cheers,
> Emil
>
> P.S. Why do you resend the whole series (some 10+ patches) when only a
> few patches have been changed ? Are all the patches changed whist
> missing that information (vX: rebase on top of A)

Yes, those 10+ patches do base on the previous changes, specially when I
rebase my series on the latest linux-next branch.

Besides, I don't know that how to send parts of this series, and keep the
unrelated patches no send. For example if the [v4 03/16] ~ [v4 10/16]
need  update to v5, and [v4 11/16] ~ [v4 16/16] keep in v4.
So should I only send the [v5 03/16]  ~ [v5 10/16], no need to send and
update [v4 11/16] ~ [v4 16/16] to v5 ?

If so I think it would be difficult for guys to comment, cause they 
can't see
the whole series in one reply list .   ;)

Thanks,
- Yakir
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-03  4:27       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  4:27 UTC (permalink / raw)
  To: Rob Herring
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	Russell King, djkurtz, dianders, seanpaul, Ajay kumar,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Rob,

在 09/03/2015 04:17 AM, Rob Herring 写道:
> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>> Some edp screen do not have hpd signal, so we can't just return
>> failed when hpd plug in detect failed.
> This is a property of the panel (or connector perhaps), so this
> property should be located there. At least, it is a common issue and
> not specific to this chip. We could have an HDMI connector and failed
> to hook up HPD for example. A connector node is also where hpd-gpios
> should be located instead (and are already defined by
> ../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
> binding, too.

Yep, I agree with your front point, it is a property of panel, not specific
to eDP controller, so this code should handle in connector logic.

But another question, if we just leave this property to connector,
then we would need to parse this property in analogix_dp-rockchip.c,
and then make an hook in analogix_dp_core.c driver. This is not nice,
and if there are some coming platform which alse want to use analogix_dp
code and meet this "no-hpd" situation,  then they would need duplicate
to parse this property and fill the hook in analogix_dp_core.c driver.
So it's little bit conflict  :-)

Beside I can not understand your example very well. Do you mean
that there are some HDMI monitor which also do not have HPD
signal (just like some eDP panel do not have hpd too), and then
the "hpd-gpios" ? Hmm... I don't know how the "hpd-gpios" want
to help in this case, would you mind show some sample code  :-D

> Are there any eDP panels which don't have EDID and need panel details in DT?

Oh, I think you want to collect some info that belong to panel
property but no indicate in panel EDID message, so those can
be collect in eDP connector binding, is it right ?

As for me, I just meet this "no-hpd" special situation.

- Yakir

>
> Rob
>
>> This is an hardware property, so we need add a devicetree property
>> "analogix,need-force-hpd" to indicate this sutiation.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4: None
>> Changes in v3:
>> - Add "analogix,need-force-hpd" to indicate whether driver need foce
>>    hpd when hpd detect failed.
>>
>> Changes in v2: None
>>
>>   .../devicetree/bindings/drm/bridge/analogix_dp.txt |  4 ++-
>>   .../bindings/video/analogix_dp-rockchip.txt        |  1 +
>>   .../devicetree/bindings/video/exynos_dp.txt        |  1 +
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
>>   6 files changed, 47 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> index f54dc3e..c310367 100644
>> --- a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> +++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> @@ -22,6 +22,9 @@ Required properties for dp-controller:
>>                  from general PHY binding: Should be "dp".
>>
>>   Optional properties for dp-controller:
>> +       -analogix,need-force-hpd:
>> +               Indicate driver need force hpd when hpd detect failed, this
>> +               is used for some eDP screen which don't have hpd signal.
>>          -hpd-gpios:
>>                  Hotplug detect GPIO.
>>                  Indicates which GPIO should be used for hotplug detection
>> @@ -31,7 +34,6 @@ Optional properties for dp-controller:
>>                  * Documentation/devicetree/bindings/video/exynos_dp.txt
>>                  * Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>>
>> -
>>   [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
>>   -------------------------------------------------------------------------------
>>
>> diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> index 502483e..8b9ed7d 100644
>> --- a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> @@ -28,6 +28,7 @@ For the below properties, please refer to Analogix DP binding document:
>>   - phys (required)
>>   - phy-names (required)
>>   - hpd-gpios (optional)
>> +- analogix,need-force-hpd (optional)
>>   -------------------------------------------------------------------------------
>>
>>   Example:
>> diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
>> index ea03b3a..4f06e80 100644
>> --- a/Documentation/devicetree/bindings/video/exynos_dp.txt
>> +++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
>> @@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
>>          -phys (required)
>>          -phy-names (required)
>>          -hpd-gpios (optional)
>> +       -analogix,need-force-hpd (optional)
>>          -video interfaces (optional)
>>
>>   Deprecated properties for DisplayPort:
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index f7227ec..e6b328a 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -63,15 +63,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
>>   {
>>          int timeout_loop = 0;
>>
>> -       while (analogix_dp_get_plug_in_status(dp) != 0) {
>> +       while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
>> +               if (analogix_dp_get_plug_in_status(dp) == 0)
>> +                       return 0;
>> +
>>                  timeout_loop++;
>> -               if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
>> -                       dev_err(dp->dev, "failed to get hpd plug status\n");
>> -                       return -ETIMEDOUT;
>> -               }
>>                  usleep_range(10, 11);
>>          }
>>
>> +       /*
>> +        * Some edp screen do not have hpd signal, so we can't just
>> +        * return failed when hpd plug in detect failed, DT property
>> +        * "need-force-hpd" would indicate whether driver need this.
>> +        */
>> +       if (!dp->need_force_hpd)
>> +               return -ETIMEDOUT;
>> +
>> +       /*
>> +        * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
>> +        * will not work, so we need to give a force hpd action to
>> +        * set HPD_STATUS manually.
>> +        */
>> +       dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
>> +
>> +       analogix_dp_force_hpd(dp);
>> +
>> +       if (analogix_dp_get_plug_in_status(dp) != 0) {
>> +               dev_err(dp->dev, "failed to get hpd plug in status\n");
>> +               return -EINVAL;
>> +       }
>> +
>> +       dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
>> +
>>          return 0;
>>   }
>>
>> @@ -1287,6 +1310,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>>          if (IS_ERR(dp->reg_base))
>>                  return PTR_ERR(dp->reg_base);
>>
>> +       dp->need_force_hpd =
>> +               of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
>> +
>>          dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
>>          if (gpio_is_valid(dp->hpd_gpio))
>>                  dp->hpd_gpio = of_get_named_gpio(dev->of_node,
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> index d8945e2..6960ab3 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> @@ -160,6 +160,7 @@ struct analogix_dp_device {
>>          struct phy              *phy;
>>          int                     dpms_mode;
>>          int                     hpd_gpio;
>> +       bool                    need_force_hpd;
>>
>>          struct analogix_dp_plat_data *plat_data;
>>   };
>> @@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
>>                                         bool enable);
>>   void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
>>   void analogix_dp_init_hpd(struct analogix_dp_device *dp);
>> +void analogix_dp_force_hpd(struct analogix_dp_device *dp);
>>   enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
>>   void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
>>   void analogix_dp_reset_aux(struct analogix_dp_device *dp);
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> index 15346fe..3086afc 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> @@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
>>          writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
>>   }
>>
>> +void analogix_dp_force_hpd(struct analogix_dp_device *dp)
>> +{
>> +       u32 reg;
>> +
>> +       reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
>> +       reg = (F_HPD | HPD_CTRL);
>> +       writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
>> +}
>> +
>>   enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
>>   {
>>          u32 reg;
>> --
>> 2.1.2
>>
>>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-03  4:27       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  4:27 UTC (permalink / raw)
  To: Rob Herring
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	Russell King, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	dianders-F7+t8E8rja9Wk0Htik3J/w, seanpaul-F7+t8E8rja9Wk0Htik3J/w,
	Ajay kumar, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I,
	architt-sgV2jX0FEOL9JmXXK+q4OQ, dri-devel

Hi Rob,

在 09/03/2015 04:17 AM, Rob Herring 写道:
> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
>> Some edp screen do not have hpd signal, so we can't just return
>> failed when hpd plug in detect failed.
> This is a property of the panel (or connector perhaps), so this
> property should be located there. At least, it is a common issue and
> not specific to this chip. We could have an HDMI connector and failed
> to hook up HPD for example. A connector node is also where hpd-gpios
> should be located instead (and are already defined by
> ../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
> binding, too.

Yep, I agree with your front point, it is a property of panel, not specific
to eDP controller, so this code should handle in connector logic.

But another question, if we just leave this property to connector,
then we would need to parse this property in analogix_dp-rockchip.c,
and then make an hook in analogix_dp_core.c driver. This is not nice,
and if there are some coming platform which alse want to use analogix_dp
code and meet this "no-hpd" situation,  then they would need duplicate
to parse this property and fill the hook in analogix_dp_core.c driver.
So it's little bit conflict  :-)

Beside I can not understand your example very well. Do you mean
that there are some HDMI monitor which also do not have HPD
signal (just like some eDP panel do not have hpd too), and then
the "hpd-gpios" ? Hmm... I don't know how the "hpd-gpios" want
to help in this case, would you mind show some sample code  :-D

> Are there any eDP panels which don't have EDID and need panel details in DT?

Oh, I think you want to collect some info that belong to panel
property but no indicate in panel EDID message, so those can
be collect in eDP connector binding, is it right ?

As for me, I just meet this "no-hpd" special situation.

- Yakir

>
> Rob
>
>> This is an hardware property, so we need add a devicetree property
>> "analogix,need-force-hpd" to indicate this sutiation.
>>
>> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>> Changes in v4: None
>> Changes in v3:
>> - Add "analogix,need-force-hpd" to indicate whether driver need foce
>>    hpd when hpd detect failed.
>>
>> Changes in v2: None
>>
>>   .../devicetree/bindings/drm/bridge/analogix_dp.txt |  4 ++-
>>   .../bindings/video/analogix_dp-rockchip.txt        |  1 +
>>   .../devicetree/bindings/video/exynos_dp.txt        |  1 +
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
>>   6 files changed, 47 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> index f54dc3e..c310367 100644
>> --- a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> +++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> @@ -22,6 +22,9 @@ Required properties for dp-controller:
>>                  from general PHY binding: Should be "dp".
>>
>>   Optional properties for dp-controller:
>> +       -analogix,need-force-hpd:
>> +               Indicate driver need force hpd when hpd detect failed, this
>> +               is used for some eDP screen which don't have hpd signal.
>>          -hpd-gpios:
>>                  Hotplug detect GPIO.
>>                  Indicates which GPIO should be used for hotplug detection
>> @@ -31,7 +34,6 @@ Optional properties for dp-controller:
>>                  * Documentation/devicetree/bindings/video/exynos_dp.txt
>>                  * Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>>
>> -
>>   [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
>>   -------------------------------------------------------------------------------
>>
>> diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> index 502483e..8b9ed7d 100644
>> --- a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> @@ -28,6 +28,7 @@ For the below properties, please refer to Analogix DP binding document:
>>   - phys (required)
>>   - phy-names (required)
>>   - hpd-gpios (optional)
>> +- analogix,need-force-hpd (optional)
>>   -------------------------------------------------------------------------------
>>
>>   Example:
>> diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
>> index ea03b3a..4f06e80 100644
>> --- a/Documentation/devicetree/bindings/video/exynos_dp.txt
>> +++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
>> @@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
>>          -phys (required)
>>          -phy-names (required)
>>          -hpd-gpios (optional)
>> +       -analogix,need-force-hpd (optional)
>>          -video interfaces (optional)
>>
>>   Deprecated properties for DisplayPort:
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index f7227ec..e6b328a 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -63,15 +63,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
>>   {
>>          int timeout_loop = 0;
>>
>> -       while (analogix_dp_get_plug_in_status(dp) != 0) {
>> +       while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
>> +               if (analogix_dp_get_plug_in_status(dp) == 0)
>> +                       return 0;
>> +
>>                  timeout_loop++;
>> -               if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
>> -                       dev_err(dp->dev, "failed to get hpd plug status\n");
>> -                       return -ETIMEDOUT;
>> -               }
>>                  usleep_range(10, 11);
>>          }
>>
>> +       /*
>> +        * Some edp screen do not have hpd signal, so we can't just
>> +        * return failed when hpd plug in detect failed, DT property
>> +        * "need-force-hpd" would indicate whether driver need this.
>> +        */
>> +       if (!dp->need_force_hpd)
>> +               return -ETIMEDOUT;
>> +
>> +       /*
>> +        * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
>> +        * will not work, so we need to give a force hpd action to
>> +        * set HPD_STATUS manually.
>> +        */
>> +       dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
>> +
>> +       analogix_dp_force_hpd(dp);
>> +
>> +       if (analogix_dp_get_plug_in_status(dp) != 0) {
>> +               dev_err(dp->dev, "failed to get hpd plug in status\n");
>> +               return -EINVAL;
>> +       }
>> +
>> +       dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
>> +
>>          return 0;
>>   }
>>
>> @@ -1287,6 +1310,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>>          if (IS_ERR(dp->reg_base))
>>                  return PTR_ERR(dp->reg_base);
>>
>> +       dp->need_force_hpd =
>> +               of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
>> +
>>          dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
>>          if (gpio_is_valid(dp->hpd_gpio))
>>                  dp->hpd_gpio = of_get_named_gpio(dev->of_node,
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> index d8945e2..6960ab3 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> @@ -160,6 +160,7 @@ struct analogix_dp_device {
>>          struct phy              *phy;
>>          int                     dpms_mode;
>>          int                     hpd_gpio;
>> +       bool                    need_force_hpd;
>>
>>          struct analogix_dp_plat_data *plat_data;
>>   };
>> @@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
>>                                         bool enable);
>>   void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
>>   void analogix_dp_init_hpd(struct analogix_dp_device *dp);
>> +void analogix_dp_force_hpd(struct analogix_dp_device *dp);
>>   enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
>>   void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
>>   void analogix_dp_reset_aux(struct analogix_dp_device *dp);
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> index 15346fe..3086afc 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> @@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
>>          writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
>>   }
>>
>> +void analogix_dp_force_hpd(struct analogix_dp_device *dp)
>> +{
>> +       u32 reg;
>> +
>> +       reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
>> +       reg = (F_HPD | HPD_CTRL);
>> +       writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
>> +}
>> +
>>   enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
>>   {
>>          u32 reg;
>> --
>> 2.1.2
>>
>>
>
>


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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-03  4:27       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  4:27 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Rob,

? 09/03/2015 04:17 AM, Rob Herring ??:
> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>> Some edp screen do not have hpd signal, so we can't just return
>> failed when hpd plug in detect failed.
> This is a property of the panel (or connector perhaps), so this
> property should be located there. At least, it is a common issue and
> not specific to this chip. We could have an HDMI connector and failed
> to hook up HPD for example. A connector node is also where hpd-gpios
> should be located instead (and are already defined by
> ../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
> binding, too.

Yep, I agree with your front point, it is a property of panel, not specific
to eDP controller, so this code should handle in connector logic.

But another question, if we just leave this property to connector,
then we would need to parse this property in analogix_dp-rockchip.c,
and then make an hook in analogix_dp_core.c driver. This is not nice,
and if there are some coming platform which alse want to use analogix_dp
code and meet this "no-hpd" situation,  then they would need duplicate
to parse this property and fill the hook in analogix_dp_core.c driver.
So it's little bit conflict  :-)

Beside I can not understand your example very well. Do you mean
that there are some HDMI monitor which also do not have HPD
signal (just like some eDP panel do not have hpd too), and then
the "hpd-gpios" ? Hmm... I don't know how the "hpd-gpios" want
to help in this case, would you mind show some sample code  :-D

> Are there any eDP panels which don't have EDID and need panel details in DT?

Oh, I think you want to collect some info that belong to panel
property but no indicate in panel EDID message, so those can
be collect in eDP connector binding, is it right ?

As for me, I just meet this "no-hpd" special situation.

- Yakir

>
> Rob
>
>> This is an hardware property, so we need add a devicetree property
>> "analogix,need-force-hpd" to indicate this sutiation.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4: None
>> Changes in v3:
>> - Add "analogix,need-force-hpd" to indicate whether driver need foce
>>    hpd when hpd detect failed.
>>
>> Changes in v2: None
>>
>>   .../devicetree/bindings/drm/bridge/analogix_dp.txt |  4 ++-
>>   .../bindings/video/analogix_dp-rockchip.txt        |  1 +
>>   .../devicetree/bindings/video/exynos_dp.txt        |  1 +
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
>>   6 files changed, 47 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> index f54dc3e..c310367 100644
>> --- a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> +++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> @@ -22,6 +22,9 @@ Required properties for dp-controller:
>>                  from general PHY binding: Should be "dp".
>>
>>   Optional properties for dp-controller:
>> +       -analogix,need-force-hpd:
>> +               Indicate driver need force hpd when hpd detect failed, this
>> +               is used for some eDP screen which don't have hpd signal.
>>          -hpd-gpios:
>>                  Hotplug detect GPIO.
>>                  Indicates which GPIO should be used for hotplug detection
>> @@ -31,7 +34,6 @@ Optional properties for dp-controller:
>>                  * Documentation/devicetree/bindings/video/exynos_dp.txt
>>                  * Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>>
>> -
>>   [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
>>   -------------------------------------------------------------------------------
>>
>> diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> index 502483e..8b9ed7d 100644
>> --- a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> +++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>> @@ -28,6 +28,7 @@ For the below properties, please refer to Analogix DP binding document:
>>   - phys (required)
>>   - phy-names (required)
>>   - hpd-gpios (optional)
>> +- analogix,need-force-hpd (optional)
>>   -------------------------------------------------------------------------------
>>
>>   Example:
>> diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
>> index ea03b3a..4f06e80 100644
>> --- a/Documentation/devicetree/bindings/video/exynos_dp.txt
>> +++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
>> @@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
>>          -phys (required)
>>          -phy-names (required)
>>          -hpd-gpios (optional)
>> +       -analogix,need-force-hpd (optional)
>>          -video interfaces (optional)
>>
>>   Deprecated properties for DisplayPort:
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index f7227ec..e6b328a 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -63,15 +63,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
>>   {
>>          int timeout_loop = 0;
>>
>> -       while (analogix_dp_get_plug_in_status(dp) != 0) {
>> +       while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
>> +               if (analogix_dp_get_plug_in_status(dp) == 0)
>> +                       return 0;
>> +
>>                  timeout_loop++;
>> -               if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
>> -                       dev_err(dp->dev, "failed to get hpd plug status\n");
>> -                       return -ETIMEDOUT;
>> -               }
>>                  usleep_range(10, 11);
>>          }
>>
>> +       /*
>> +        * Some edp screen do not have hpd signal, so we can't just
>> +        * return failed when hpd plug in detect failed, DT property
>> +        * "need-force-hpd" would indicate whether driver need this.
>> +        */
>> +       if (!dp->need_force_hpd)
>> +               return -ETIMEDOUT;
>> +
>> +       /*
>> +        * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
>> +        * will not work, so we need to give a force hpd action to
>> +        * set HPD_STATUS manually.
>> +        */
>> +       dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
>> +
>> +       analogix_dp_force_hpd(dp);
>> +
>> +       if (analogix_dp_get_plug_in_status(dp) != 0) {
>> +               dev_err(dp->dev, "failed to get hpd plug in status\n");
>> +               return -EINVAL;
>> +       }
>> +
>> +       dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
>> +
>>          return 0;
>>   }
>>
>> @@ -1287,6 +1310,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>>          if (IS_ERR(dp->reg_base))
>>                  return PTR_ERR(dp->reg_base);
>>
>> +       dp->need_force_hpd =
>> +               of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
>> +
>>          dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
>>          if (gpio_is_valid(dp->hpd_gpio))
>>                  dp->hpd_gpio = of_get_named_gpio(dev->of_node,
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> index d8945e2..6960ab3 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> @@ -160,6 +160,7 @@ struct analogix_dp_device {
>>          struct phy              *phy;
>>          int                     dpms_mode;
>>          int                     hpd_gpio;
>> +       bool                    need_force_hpd;
>>
>>          struct analogix_dp_plat_data *plat_data;
>>   };
>> @@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
>>                                         bool enable);
>>   void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
>>   void analogix_dp_init_hpd(struct analogix_dp_device *dp);
>> +void analogix_dp_force_hpd(struct analogix_dp_device *dp);
>>   enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
>>   void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
>>   void analogix_dp_reset_aux(struct analogix_dp_device *dp);
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> index 15346fe..3086afc 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> @@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
>>          writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
>>   }
>>
>> +void analogix_dp_force_hpd(struct analogix_dp_device *dp)
>> +{
>> +       u32 reg;
>> +
>> +       reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
>> +       reg = (F_HPD | HPD_CTRL);
>> +       writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
>> +}
>> +
>>   enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
>>   {
>>          u32 reg;
>> --
>> 2.1.2
>>
>>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 07/16] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
  2015-09-03  0:01     ` Krzysztof Kozlowski
  (?)
@ 2015-09-03  4:51     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  4:51 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, joe, Kukjin Kim, Mark Yao
  Cc: dri-devel, Andrzej Hajda, Gustavo Padovan, linux-samsung-soc,
	seanpaul, djkurtz, Kishon Vijay Abraham I, linux-rockchip,
	robherring2, Russell King, devicetree, Pawel Moll, Ian Campbell,
	Rob Herring, dianders, linux-arm-kernel, linux-kernel,
	Kyungmin Park, Kumar Gala, ajaynumb, Andy Yan


[-- Attachment #1.1: Type: text/plain, Size: 7106 bytes --]

Hi Krzysztof,

在 09/03/2015 08:01 AM, Krzysztof Kozlowski 写道:
> On 01.09.2015 15:01, Yakir Yang wrote:
>> After exynos_dp have been splited the common IP code into analogix_dp driver,
> s/splited/split/

Done  :)
>> the analogix_dp driver have deprecated some samsung platform properties which
> s/samsung/Samsung/

Done,

>> could be dynamic parsed from EDID/MODE/DPCD message, so this is an update for
> s/dynamic/dynamically/
>

thanks,

>> exynos DTS file for dp-controller.
> /exynos/Exynos/

Okay

>> Beside analogix_dp have provide the backward compatibility, so there are no
>> bisectability break that make this change in a separate patch.
> It took me some time to figure out the meaning of this sentence... Did
> you want to say that backward compatibility is fully preserved?

Aha, Yeah, I means I already have provided the backward
compatibility in previous patches, so no kernel broken when
I make this DTS change in separate patch.

> You are removing samsung,dynamic-range and samsung,ycbcr-coeff. I would
> assume that now:
> 1. on all these board these values would be parsed from EDID/MODE/DPCD
> message?
> 2. everything would work as previously?
> Am I understanding it correctly?

Yeah, you are right. I think dynamic-range and ycbcr-coeff can parse from
the vic value of mode, and this works rightly on my side whether the TV and
simple panel (if we ignored the mistake I make in v4 :(  ).

But I do have a concern about the ycbcr-coeff. I just copy the judge 
rule from
dw_hdmi code, and don't understand very well about it, wish some guys could
share some ideas.

   if ((vic == 2) || (vic == 3) || (vic == 6) ||

        (vic == 7) || (vic == 17) || (vic == 18) ||

     (vic == 21) || (vic == 22))

      hdmi->mode_data.colorimetry = eITU601;

     else

     hdmi->mode_data.colorimetry = eITU709;


Beside, most panel timing would not match the cea mode, that's to say panel
timing would get vic to zero in most time. So after the previous rule, 
ycbcr would
set to ITU709 which is "1" in eDP controller. But I see Exynos always 
set 0 to this
bit, so this is the place I am worry about.

- Yakir

> The patch itself looks good.

Thanks.

> Best regards,
> Krzysztof
>
>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Krzysztof suggest, separate all DTS changes to a separate patch.
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>   arch/arm/boot/dts/exynos5250-arndale.dts   | 2 --
>>   arch/arm/boot/dts/exynos5250-smdk5250.dts  | 2 --
>>   arch/arm/boot/dts/exynos5250-snow.dts      | 4 +---
>>   arch/arm/boot/dts/exynos5250-spring.dts    | 4 +---
>>   arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
>>   arch/arm/boot/dts/exynos5420-smdk5420.dts  | 2 --
>>   arch/arm/boot/dts/exynos5800-peach-pi.dts  | 4 +---
>>   7 files changed, 4 insertions(+), 18 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
>> index db3f65f..4636862 100644
>> --- a/arch/arm/boot/dts/exynos5250-arndale.dts
>> +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
>> @@ -124,8 +124,6 @@
>>   &dp {
>>   	status = "okay";
>>   	samsung,color-space = <0>;
>> -	samsung,dynamic-range = <0>;
>> -	samsung,ycbcr-coeff = <0>;
>>   	samsung,color-depth = <1>;
>>   	samsung,link-rate = <0x0a>;
>>   	samsung,lane-count = <4>;
>> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> index c625e71..cd424d6 100644
>> --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> @@ -80,8 +80,6 @@
>>   
>>   &dp {
>>   	samsung,color-space = <0>;
>> -	samsung,dynamic-range = <0>;
>> -	samsung,ycbcr-coeff = <0>;
>>   	samsung,color-depth = <1>;
>>   	samsung,link-rate = <0x0a>;
>>   	samsung,lane-count = <4>;
>> diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
>> index 0720caa..242b621 100644
>> --- a/arch/arm/boot/dts/exynos5250-snow.dts
>> +++ b/arch/arm/boot/dts/exynos5250-snow.dts
>> @@ -244,12 +244,10 @@
>>   	pinctrl-names = "default";
>>   	pinctrl-0 = <&dp_hpd>;
>>   	samsung,color-space = <0>;
>> -	samsung,dynamic-range = <0>;
>> -	samsung,ycbcr-coeff = <0>;
>>   	samsung,color-depth = <1>;
>>   	samsung,link-rate = <0x0a>;
>>   	samsung,lane-count = <2>;
>> -	samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
>> +	hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
>>   
>>   	ports {
>>   		port@0 {
>> diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
>> index c1edd6d..91881d7 100644
>> --- a/arch/arm/boot/dts/exynos5250-spring.dts
>> +++ b/arch/arm/boot/dts/exynos5250-spring.dts
>> @@ -74,12 +74,10 @@
>>   	pinctrl-names = "default";
>>   	pinctrl-0 = <&dp_hpd_gpio>;
>>   	samsung,color-space = <0>;
>> -	samsung,dynamic-range = <0>;
>> -	samsung,ycbcr-coeff = <0>;
>>   	samsung,color-depth = <1>;
>>   	samsung,link-rate = <0x0a>;
>>   	samsung,lane-count = <1>;
>> -	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
>> +	hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
>>   };
>>   
>>   &ehci {
>> diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
>> index 8f4d76c..7433683 100644
>> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
>> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
>> @@ -148,12 +148,10 @@
>>   	pinctrl-names = "default";
>>   	pinctrl-0 = <&dp_hpd_gpio>;
>>   	samsung,color-space = <0>;
>> -	samsung,dynamic-range = <0>;
>> -	samsung,ycbcr-coeff = <0>;
>>   	samsung,color-depth = <1>;
>>   	samsung,link-rate = <0x06>;
>>   	samsung,lane-count = <2>;
>> -	samsung,hpd-gpio = <&gpx2 6 0>;
>> +	hpd-gpio = <&gpx2 6 0>;
>>   
>>   	ports {
>>   		port@0 {
>> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> index 98871f9..b3df3c1 100644
>> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> @@ -92,8 +92,6 @@
>>   	pinctrl-names = "default";
>>   	pinctrl-0 = <&dp_hpd>;
>>   	samsung,color-space = <0>;
>> -	samsung,dynamic-range = <0>;
>> -	samsung,ycbcr-coeff = <0>;
>>   	samsung,color-depth = <1>;
>>   	samsung,link-rate = <0x0a>;
>>   	samsung,lane-count = <4>;
>> diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
>> index 7d5b386..b89bff5 100644
>> --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
>> +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
>> @@ -142,12 +142,10 @@
>>   	pinctrl-names = "default";
>>   	pinctrl-0 = <&dp_hpd_gpio>;
>>   	samsung,color-space = <0>;
>> -	samsung,dynamic-range = <0>;
>> -	samsung,ycbcr-coeff = <0>;
>>   	samsung,color-depth = <1>;
>>   	samsung,link-rate = <0x0a>;
>>   	samsung,lane-count = <2>;
>> -	samsung,hpd-gpio = <&gpx2 6 0>;
>> +	hpd-gpios = <&gpx2 6 0>;
>>   	panel = <&panel>;
>>   };
>>   
>>
>
>
>


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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 01/16] drm: exynos/dp: fix code style
  2015-09-03  0:21     ` Krzysztof Kozlowski
@ 2015-09-03  5:04       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  5:04 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Krzysztof,

在 09/03/2015 08:21 AM, Krzysztof Kozlowski 写道:
> On 01.09.2015 14:46, Yakir Yang wrote:
>> After run "checkpatch.pl -f --subjective" command, I see there
>> are lots of alignment problem in exynos_dp driver, so let just
>> fix them.
> Hi,
>
> Warnings from checkpatch are not a reason for a commit. Reason for a
> commit could be for example an unreadable code, violation of
> coding-style leading to decrease in code maintainability or just
> improving the code readability so it will be easier to review and
> maintain it.
>
> You do not make commits because some tool tells you that. We do not
> listen to machines :) ... If that would be the case, the commit could be
> made automatically, without human interaction. Such automated commit
> could be even easily tested by the machine by comparing object files.
>
> Especially that you enabled "subjective" rule. This is not a valid
> motivation for a commit.
>
> Please rephrase this to sensible reason and convince that change is
> worth the effort.

Oh, nice, thanks for your remind. I would rephrase the commit.

>> - Take Romain suggest, rebase on linux-next branch
> That comment seems unrelated to the commit. Please remove it.

Done,

>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2:
>> - Take Joe Preches advise, improved commit message more readable, and
>>    avoid using some uncommon style like bellow:
>>    -  retval = exynos_dp_read_bytes_from_i2c(...
>> 				...)
>>    +  retval =
>>    +  exynos_dp_read_bytes_from_i2c(......);
>>
>>   drivers/gpu/drm/exynos/exynos_dp_core.c | 226 ++++++++++++++++----------------
>>   drivers/gpu/drm/exynos/exynos_dp_core.h |  54 ++++----
>>   drivers/gpu/drm/exynos/exynos_dp_reg.c  | 106 +++++++--------
>>   3 files changed, 188 insertions(+), 198 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
>> index d66ade0..266f7f7 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
>> @@ -115,8 +115,8 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   
>>   	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
>>   	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>> -				EDID_EXTENSION_FLAG,
>> -				&extend_block);
>> +					      EDID_EXTENSION_FLAG,
>> +					      &extend_block);
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -124,10 +124,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>>   
>>   		/* Read EDID data */
>> -		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>> -						EDID_HEADER_PATTERN,
>> -						EDID_BLOCK_LENGTH,
>> -						&edid[EDID_HEADER_PATTERN]);
>> +		retval = exynos_dp_read_bytes_from_i2c(
>> +					dp, I2C_EDID_DEVICE_ADDR,
>> +					EDID_HEADER_PATTERN,
>> +					EDID_BLOCK_LENGTH,
>> +					&edid[EDID_HEADER_PATTERN]);
>>   		if (retval != 0) {
>>   			dev_err(dp->dev, "EDID Read failed!\n");
>>   			return -EIO;
>> @@ -139,11 +140,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   		}
>>   
>>   		/* Read additional EDID data */
>> -		retval = exynos_dp_read_bytes_from_i2c(dp,
>> -				I2C_EDID_DEVICE_ADDR,
>> -				EDID_BLOCK_LENGTH,
>> -				EDID_BLOCK_LENGTH,
>> -				&edid[EDID_BLOCK_LENGTH]);
>> +		retval = exynos_dp_read_bytes_from_i2c(
>> +					dp, I2C_EDID_DEVICE_ADDR,
>> +					EDID_BLOCK_LENGTH,
>> +					EDID_BLOCK_LENGTH,
>> +					&edid[EDID_BLOCK_LENGTH]);
>>   		if (retval != 0) {
>>   			dev_err(dp->dev, "EDID Read failed!\n");
>>   			return -EIO;
>> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   		}
>>   
>>   		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
>> -					&test_vector);
>> +					      &test_vector);
>>   		if (test_vector & DP_TEST_LINK_EDID_READ) {
>> -			exynos_dp_write_byte_to_dpcd(dp,
>> -				DP_TEST_EDID_CHECKSUM,
>> +			exynos_dp_write_byte_to_dpcd(
>> +				dp, DP_TEST_EDID_CHECKSUM,
>>   				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
>> -			exynos_dp_write_byte_to_dpcd(dp,
>> -				DP_TEST_RESPONSE,
>> +			exynos_dp_write_byte_to_dpcd(
>> +				dp, DP_TEST_RESPONSE,
>>   				DP_TEST_EDID_CHECKSUM_WRITE);
> To me, missing argument after opening parenthesis, looks worse. I would
> prefer:
>
> 			exynos_dp_write_byte_to_dpcd(dp,
>
> Why you moved the 'dp' argument to new line?

Hmm... Just like style tool indicate, no more warning after
that change.

For now, I would like to follow the original style, just improved
some obvious style problem.  :-)

>
>>   		}
>>   	} else {
>>   		dev_info(dp->dev, "EDID data does not include any extensions.\n");
>>   
>>   		/* Read EDID data */
>> -		retval = exynos_dp_read_bytes_from_i2c(dp,
>> -				I2C_EDID_DEVICE_ADDR,
>> -				EDID_HEADER_PATTERN,
>> -				EDID_BLOCK_LENGTH,
>> -				&edid[EDID_HEADER_PATTERN]);
>> +		retval = exynos_dp_read_bytes_from_i2c(
>> +				dp, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
>> +				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
> ditto

Done

>
>>   		if (retval != 0) {
>>   			dev_err(dp->dev, "EDID Read failed!\n");
>>   			return -EIO;
>> @@ -183,16 +182,15 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   			return -EIO;
>>   		}
>>   
>> -		exynos_dp_read_byte_from_dpcd(dp,
>> -			DP_TEST_REQUEST,
>> -			&test_vector);
>> +		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
>> +					      &test_vector);
>>   		if (test_vector & DP_TEST_LINK_EDID_READ) {
>> -			exynos_dp_write_byte_to_dpcd(dp,
>> -				DP_TEST_EDID_CHECKSUM,
>> -				edid[EDID_CHECKSUM]);
>> -			exynos_dp_write_byte_to_dpcd(dp,
>> -				DP_TEST_RESPONSE,
>> -				DP_TEST_EDID_CHECKSUM_WRITE);
>> +			exynos_dp_write_byte_to_dpcd(
>> +					dp, DP_TEST_EDID_CHECKSUM,
>> +					edid[EDID_CHECKSUM]);
>> +			exynos_dp_write_byte_to_dpcd(
>> +					dp, DP_TEST_RESPONSE,
>> +					DP_TEST_EDID_CHECKSUM_WRITE);
> ditto

Done

>
>>   		}
>>   	}
>>   
>> @@ -207,8 +205,7 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
>>   	int retval;
>>   
>>   	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
>> -	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
>> -				12, buf);
>> +	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -223,7 +220,7 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
>>   }
>>   
>>   static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
>> -						bool enable)
>> +						 bool enable)
>>   {
>>   	u8 data;
>>   
>> @@ -231,11 +228,11 @@ static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
>>   
>>   	if (enable)
>>   		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
>> -			DP_LANE_COUNT_ENHANCED_FRAME_EN |
>> -			DPCD_LANE_COUNT_SET(data));
>> +					     DP_LANE_COUNT_ENHANCED_FRAME_EN |
>> +					     DPCD_LANE_COUNT_SET(data));
>>   	else
>>   		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
>> -			DPCD_LANE_COUNT_SET(data));
>> +					     DPCD_LANE_COUNT_SET(data));
>>   }
>>   
>>   static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
>> @@ -262,13 +259,12 @@ static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
>>   {
>>   	exynos_dp_set_training_pattern(dp, DP_NONE);
>>   
>> -	exynos_dp_write_byte_to_dpcd(dp,
>> -		DP_TRAINING_PATTERN_SET,
>> -		DP_TRAINING_PATTERN_DISABLE);
>> +	exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
>> +				     DP_TRAINING_PATTERN_DISABLE);
>>   }
>>   
>>   static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
>> -					int pre_emphasis, int lane)
>> +						 int pre_emphasis, int lane)
>>   {
>>   	switch (lane) {
>>   	case 0:
>> @@ -308,15 +304,14 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>>   	/* Setup RX configuration */
>>   	buf[0] = dp->link_train.link_rate;
>>   	buf[1] = dp->link_train.lane_count;
>> -	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
>> -				2, buf);
>> +	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
>>   	if (retval)
>>   		return retval;
>>   
>>   	/* Set TX pre-emphasis to minimum */
>>   	for (lane = 0; lane < lane_count; lane++)
>> -		exynos_dp_set_lane_lane_pre_emphasis(dp,
>> -			PRE_EMPHASIS_LEVEL_0, lane);
>> +		exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0,
>> +						     lane);
>>   
>>   	/* Wait for PLL lock */
>>   	pll_tries = 0;
>> @@ -334,9 +329,9 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>>   	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
>>   
>>   	/* Set RX training pattern */
>> -	retval = exynos_dp_write_byte_to_dpcd(dp,
>> -			DP_TRAINING_PATTERN_SET,
>> -			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
>> +	retval = exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
>> +					      DP_LINK_SCRAMBLING_DISABLE |
>> +					      DP_TRAINING_PATTERN_1);
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -345,7 +340,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>>   			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
>>   
>>   	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
>> -			lane_count, buf);
>> +					       lane_count, buf);
>>   
>>   	return retval;
>>   }
>> @@ -353,7 +348,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>>   static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
>>   {
>>   	int shift = (lane & 1) * 4;
>> -	u8 link_value = link_status[lane>>1];
>> +	u8 link_value = link_status[lane >> 1];
>>   
>>   	return (link_value >> shift) & 0xf;
>>   }
>> @@ -372,7 +367,7 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
>>   }
>>   
>>   static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
>> -				int lane_count)
>> +				   int lane_count)
>>   {
>>   	int lane;
>>   	u8 lane_status;
>> @@ -391,10 +386,10 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
>>   }
>>   
>>   static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
>> -							int lane)
>> +							  int lane)
>>   {
>>   	int shift = (lane & 1) * 4;
>> -	u8 link_value = adjust_request[lane>>1];
>> +	u8 link_value = adjust_request[lane >> 1];
>>   
>>   	return (link_value >> shift) & 0x3;
>>   }
>> @@ -404,13 +399,13 @@ static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
>>   					int lane)
>>   {
>>   	int shift = (lane & 1) * 4;
>> -	u8 link_value = adjust_request[lane>>1];
>> +	u8 link_value = adjust_request[lane >> 1];
>>   
>>   	return ((link_value >> shift) & 0xc) >> 2;
>>   }
>>   
>>   static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
>> -					u8 training_lane_set, int lane)
>> +					     u8 training_lane_set, int lane)
>>   {
>>   	switch (lane) {
>>   	case 0:
>> @@ -430,9 +425,8 @@ static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
>>   	}
>>   }
>>   
>> -static unsigned int exynos_dp_get_lane_link_training(
>> -				struct exynos_dp_device *dp,
>> -				int lane)
>> +static unsigned int
>> +exynos_dp_get_lane_link_training(struct exynos_dp_device *dp, int lane)
>>   {
>>   	u32 reg;
>>   
>> @@ -466,7 +460,7 @@ static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
>>   }
>>   
>>   static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
>> -					u8 adjust_request[2])
>> +					       u8 adjust_request[2])
>>   {
>>   	int lane, lane_count;
>>   	u8 voltage_swing, pre_emphasis, training_lane;
>> @@ -499,13 +493,13 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>>   
>>   	lane_count = dp->link_train.lane_count;
>>   
>> -	retval =  exynos_dp_read_bytes_from_dpcd(dp,
>> -			DP_LANE0_1_STATUS, 2, link_status);
>> +	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
>> +						 2, link_status);
>>   	if (retval)
>>   		return retval;
>>   
>> -	retval =  exynos_dp_read_bytes_from_dpcd(dp,
>> -			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
>> +	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
>> +						 2, adjust_request);
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -513,8 +507,8 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>>   		/* set training pattern 2 for EQ */
>>   		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
>>   
>> -		retval = exynos_dp_write_byte_to_dpcd(dp,
>> -				DP_TRAINING_PATTERN_SET,
>> +		retval = exynos_dp_write_byte_to_dpcd(
>> +				dp, DP_TRAINING_PATTERN_SET,
>>   				DP_LINK_SCRAMBLING_DISABLE |
>>   				DP_TRAINING_PATTERN_2);
> ditto

Done

>
>>   		if (retval)
>> @@ -552,11 +546,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>>   	exynos_dp_get_adjust_training_lane(dp, adjust_request);
>>   
>>   	for (lane = 0; lane < lane_count; lane++)
>> -		exynos_dp_set_lane_link_training(dp,
>> -			dp->link_train.training_lane[lane], lane);
>> +		exynos_dp_set_lane_link_training(
>> +				dp, dp->link_train.training_lane[lane], lane);
>>   
>> -	retval = exynos_dp_write_bytes_to_dpcd(dp,
>> -			DP_TRAINING_LANE0_SET, lane_count,
>> +	retval = exynos_dp_write_bytes_to_dpcd(
>> +			dp, DP_TRAINING_LANE0_SET, lane_count,
>>   			dp->link_train.training_lane);
> ditto

Done

>
>>   	if (retval)
>>   		return retval;
>> @@ -574,8 +568,8 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>>   
>>   	lane_count = dp->link_train.lane_count;
>>   
>> -	retval = exynos_dp_read_bytes_from_dpcd(dp,
>> -			DP_LANE0_1_STATUS, 2, link_status);
>> +	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
>> +						2, link_status);
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -584,13 +578,13 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>>   		return -EIO;
>>   	}
>>   
>> -	retval = exynos_dp_read_bytes_from_dpcd(dp,
>> -			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
>> +	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
>> +						2, adjust_request);
>>   	if (retval)
>>   		return retval;
>>   
>> -	retval = exynos_dp_read_byte_from_dpcd(dp,
>> -			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
>> +	retval = exynos_dp_read_byte_from_dpcd(dp, DP_LANE_ALIGN_STATUS_UPDATED,
>> +					       &link_align);
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -629,17 +623,18 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>>   	}
>>   
>>   	for (lane = 0; lane < lane_count; lane++)
>> -		exynos_dp_set_lane_link_training(dp,
>> -			dp->link_train.training_lane[lane], lane);
>> +		exynos_dp_set_lane_link_training(
>> +				dp, dp->link_train.training_lane[lane], lane);
> ditto

Done

>
>>   
>>   	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
>> -			lane_count, dp->link_train.training_lane);
>> +					       lane_count,
>> +					       dp->link_train.training_lane);
>>   
>>   	return retval;
>>   }
>>   
>>   static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
>> -					u8 *bandwidth)
>> +					   u8 *bandwidth)
>>   {
>>   	u8 data;
>>   
>> @@ -652,7 +647,7 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
>>   }
>>   
>>   static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
>> -					u8 *lane_count)
>> +					    u8 *lane_count)
>>   {
>>   	u8 data;
>>   
>> @@ -665,8 +660,8 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
>>   }
>>   
>>   static void exynos_dp_init_training(struct exynos_dp_device *dp,
>> -			enum link_lane_count_type max_lane,
>> -			enum link_rate_type max_rate)
>> +				    enum link_lane_count_type max_lane,
>> +				    enum link_rate_type max_rate)
>>   {
>>   	/*
>>   	 * MACRO_RST must be applied after the PLL_LOCK to avoid
>> @@ -679,7 +674,7 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
>>   	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
>>   
>>   	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
>> -	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
>> +	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
>>   		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
>>   			dp->link_train.link_rate);
>>   		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
>> @@ -739,8 +734,7 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
>>   }
>>   
>>   static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
>> -				u32 count,
>> -				u32 bwtype)
>> +				    u32 count, u32 bwtype)
>>   {
>>   	int i;
>>   	int retval;
>> @@ -828,21 +822,19 @@ static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
>>   	if (enable) {
>>   		exynos_dp_enable_scrambling(dp);
>>   
>> -		exynos_dp_read_byte_from_dpcd(dp,
>> -			DP_TRAINING_PATTERN_SET,
>> -			&data);
>> -		exynos_dp_write_byte_to_dpcd(dp,
>> -			DP_TRAINING_PATTERN_SET,
>> -			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
>> +		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
>> +					      &data);
>> +		exynos_dp_write_byte_to_dpcd(
>> +				dp, DP_TRAINING_PATTERN_SET,
>> +				(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
> ditto

Done

>
>>   	} else {
>>   		exynos_dp_disable_scrambling(dp);
>>   
>> -		exynos_dp_read_byte_from_dpcd(dp,
>> -			DP_TRAINING_PATTERN_SET,
>> -			&data);
>> -		exynos_dp_write_byte_to_dpcd(dp,
>> -			DP_TRAINING_PATTERN_SET,
>> -			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
>> +		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
>> +					      &data);
>> +		exynos_dp_write_byte_to_dpcd(
>> +				dp, DP_TRAINING_PATTERN_SET,
>> +				(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
> ditto

Done

>
>>   	}
>>   }
>>   
>> @@ -913,7 +905,7 @@ static void exynos_dp_commit(struct drm_encoder *encoder)
>>   	}
>>   
>>   	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
>> -					dp->video_info->link_rate);
>> +				       dp->video_info->link_rate);
>>   	if (ret) {
>>   		dev_err(dp->dev, "unable to do link train\n");
>>   		return;
>> @@ -941,8 +933,8 @@ static void exynos_dp_commit(struct drm_encoder *encoder)
>>   	exynos_dp_start_video(dp);
>>   }
>>   
>> -static enum drm_connector_status exynos_dp_detect(
>> -				struct drm_connector *connector, bool force)
>> +static enum drm_connector_status
>> +exynos_dp_detect(struct drm_connector *connector, bool force)
>>   {
>>   	return connector_status_connected;
>>   }
>> @@ -990,8 +982,8 @@ static int exynos_dp_get_modes(struct drm_connector *connector)
>>   	return 1;
>>   }
>>   
>> -static struct drm_encoder *exynos_dp_best_encoder(
>> -			struct drm_connector *connector)
>> +static struct drm_encoder *
>> +exynos_dp_best_encoder(struct drm_connector *connector)
>>   {
>>   	struct exynos_dp_device *dp = ctx_from_connector(connector);
>>   
>> @@ -1005,7 +997,7 @@ static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
>>   
>>   /* returns the number of bridges attached */
>>   static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
>> -		struct drm_encoder *encoder)
>> +					struct drm_encoder *encoder)
>>   {
>>   	int ret;
>>   
>> @@ -1036,7 +1028,8 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
>>   	connector->polled = DRM_CONNECTOR_POLL_HPD;
>>   
>>   	ret = drm_connector_init(dp->drm_dev, connector,
>> -			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
>> +				 &exynos_dp_connector_funcs,
>> +				 DRM_MODE_CONNECTOR_eDP);
>>   	if (ret) {
>>   		DRM_ERROR("Failed to initialize connector with drm\n");
>>   		return ret;
>> @@ -1139,8 +1132,8 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
>>   	struct device_node *dp_node = dev->of_node;
>>   	struct video_info *dp_video_config;
>>   
>> -	dp_video_config = devm_kzalloc(dev,
>> -				sizeof(*dp_video_config), GFP_KERNEL);
>> +	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
>> +				       GFP_KERNEL);
>>   	if (!dp_video_config)
>>   		return ERR_PTR(-ENOMEM);
>>   
>> @@ -1154,37 +1147,37 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
>>   		of_property_read_bool(dp_node, "interlaced");
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,color-space",
>> -				&dp_video_config->color_space)) {
>> +				 &dp_video_config->color_space)) {
>>   		dev_err(dev, "failed to get color-space\n");
>>   		return ERR_PTR(-EINVAL);
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
>> -				&dp_video_config->dynamic_range)) {
>> +				 &dp_video_config->dynamic_range)) {
>>   		dev_err(dev, "failed to get dynamic-range\n");
>>   		return ERR_PTR(-EINVAL);
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
>> -				&dp_video_config->ycbcr_coeff)) {
>> +				 &dp_video_config->ycbcr_coeff)) {
>>   		dev_err(dev, "failed to get ycbcr-coeff\n");
>>   		return ERR_PTR(-EINVAL);
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,color-depth",
>> -				&dp_video_config->color_depth)) {
>> +				 &dp_video_config->color_depth)) {
>>   		dev_err(dev, "failed to get color-depth\n");
>>   		return ERR_PTR(-EINVAL);
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,link-rate",
>> -				&dp_video_config->link_rate)) {
>> +				 &dp_video_config->link_rate)) {
>>   		dev_err(dev, "failed to get link-rate\n");
>>   		return ERR_PTR(-EINVAL);
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,lane-count",
>> -				&dp_video_config->lane_count)) {
>> +				 &dp_video_config->lane_count)) {
>>   		dev_err(dev, "failed to get lane-count\n");
>>   		return ERR_PTR(-EINVAL);
>>   	}
>> @@ -1197,7 +1190,7 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
>>   	int ret;
>>   
>>   	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
>> -			OF_USE_NATIVE_MODE);
>> +			       OF_USE_NATIVE_MODE);
>>   	if (ret) {
>>   		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
>>   		return ret;
>> @@ -1294,7 +1287,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>>   	exynos_dp_init_dp(dp);
>>   
>>   	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
>> -			irq_flags, "exynos-dp", dp);
>> +			       irq_flags, "exynos-dp", dp);
>>   	if (ret) {
>>   		dev_err(&pdev->dev, "failed to request irq\n");
>>   		return ret;
>> @@ -1328,7 +1321,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>>   }
>>   
>>   static void exynos_dp_unbind(struct device *dev, struct device *master,
>> -				void *data)
>> +			     void *data)
>>   {
>>   	struct exynos_dp_device *dp = dev_get_drvdata(dev);
>>   
>> @@ -1347,7 +1340,7 @@ static int exynos_dp_probe(struct platform_device *pdev)
>>   	struct exynos_dp_device *dp;
>>   
>>   	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
>> -				GFP_KERNEL);
>> +			  GFP_KERNEL);
>>   	if (!dp)
>>   		return -ENOMEM;
>>   
>> @@ -1369,8 +1362,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
>>   			of_node_put(bridge_node);
>>   			if (!dp->bridge)
>>   				return -EPROBE_DEFER;
>> -		} else
>> +		} else {
>>   			return -EPROBE_DEFER;
>> +		}
>>   	}
>>   
>>   	return component_add(&pdev->dev, &exynos_dp_ops);
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
>> index e413b6f..71f2b86 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.h
>> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
>> @@ -179,8 +179,8 @@ void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
>>   enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
>>   void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
>>   void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
>> -				enum analog_power_block block,
>> -				bool enable);
>> +				     enum analog_power_block block,
>> +				     bool enable);
>>   void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
>>   void exynos_dp_init_hpd(struct exynos_dp_device *dp);
>>   enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
>> @@ -191,50 +191,50 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
>>   void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
>>   int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
>>   int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned char data);
>> +				 unsigned int reg_addr,
>> +				 unsigned char data);
>>   int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned char *data);
>> +				  unsigned int reg_addr,
>> +				  unsigned char *data);
>>   int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned int count,
>> -				unsigned char data[]);
>> +				  unsigned int reg_addr,
>> +				  unsigned int count,
>> +				  unsigned char data[]);
>>   int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned int count,
>> -				unsigned char data[]);
>> +				   unsigned int reg_addr,
>> +				   unsigned int count,
>> +				   unsigned char data[]);
>>   int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
>>   				unsigned int device_addr,
>>   				unsigned int reg_addr);
>>   int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
>> -				unsigned int device_addr,
>> -				unsigned int reg_addr,
>> -				unsigned int *data);
>> +				 unsigned int device_addr,
>> +				 unsigned int reg_addr,
>> +				 unsigned int *data);
>>   int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
>> -				unsigned int device_addr,
>> -				unsigned int reg_addr,
>> -				unsigned int count,
>> -				unsigned char edid[]);
>> +				  unsigned int device_addr,
>> +				  unsigned int reg_addr,
>> +				  unsigned int count,
>> +				  unsigned char edid[]);
>>   void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
>>   void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
>>   void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
>>   void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
>>   void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
>>   void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
>> -				 enum pattern_set pattern);
>> +				    enum pattern_set pattern);
>>   void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>>   void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>>   void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>>   void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>>   void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
>> -				u32 training_lane);
>> +				       u32 training_lane);
>>   void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
>> -				u32 training_lane);
>> +				       u32 training_lane);
>>   void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
>> -				u32 training_lane);
>> +				       u32 training_lane);
>>   void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
>> -				u32 training_lane);
>> +				       u32 training_lane);
>>   u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
>>   u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
>>   u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
>> @@ -245,9 +245,9 @@ void exynos_dp_init_video(struct exynos_dp_device *dp);
>>   void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
>>   int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
>>   void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
>> -			enum clock_recovery_m_value_type type,
>> -			u32 m_value,
>> -			u32 n_value);
>> +			       enum clock_recovery_m_value_type type,
>> +			       u32 m_value,
>> +			       u32 n_value);
>>   void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
>>   void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
>>   void exynos_dp_start_video(struct exynos_dp_device *dp);
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
>> index c1f87a2..5aff19a 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
>> +++ b/drivers/gpu/drm/exynos/exynos_dp_reg.c
>> @@ -202,8 +202,8 @@ void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
>>   }
>>   
>>   void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
>> -				enum analog_power_block block,
>> -				bool enable)
>> +				     enum analog_power_block block,
>> +				     bool enable)
>>   {
>>   	u32 reg;
>>   
>> @@ -399,8 +399,8 @@ void exynos_dp_init_aux(struct exynos_dp_device *dp)
>>   	exynos_dp_reset_aux(dp);
>>   
>>   	/* Disable AUX transaction H/W retry */
>> -	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
>> -		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
>> +	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
>> +	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
>>   	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
>>   
>>   	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
>> @@ -483,8 +483,8 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
>>   }
>>   
>>   int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned char data)
>> +				 unsigned int reg_addr,
>> +				 unsigned char data)
>>   {
>>   	u32 reg;
>>   	int i;
>> @@ -519,17 +519,16 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
>>   		retval = exynos_dp_start_aux_transaction(dp);
>>   		if (retval == 0)
>>   			break;
>> -		else
>> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> -				__func__);
>> +
>> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
>>   	}
>>   
>>   	return retval;
>>   }
>>   
>>   int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned char *data)
>> +				  unsigned int reg_addr,
>> +				  unsigned char *data)
>>   {
>>   	u32 reg;
>>   	int i;
>> @@ -560,9 +559,8 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
>>   		retval = exynos_dp_start_aux_transaction(dp);
>>   		if (retval == 0)
>>   			break;
>> -		else
>> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> -				__func__);
>> +
>> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
>>   	}
>>   
>>   	/* Read data buffer */
>> @@ -573,9 +571,9 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
>>   }
>>   
>>   int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned int count,
>> -				unsigned char data[])
>> +				  unsigned int reg_addr,
>> +				  unsigned int count,
>> +				  unsigned char data[])
>>   {
>>   	u32 reg;
>>   	unsigned int start_offset;
>> @@ -625,9 +623,9 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
>>   			retval = exynos_dp_start_aux_transaction(dp);
>>   			if (retval == 0)
>>   				break;
>> -			else
>> -				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> -					__func__);
>> +
>> +			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> +				__func__);
>>   		}
>>   
>>   		start_offset += cur_data_count;
>> @@ -637,9 +635,9 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
>>   }
>>   
>>   int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned int count,
>> -				unsigned char data[])
>> +				   unsigned int reg_addr,
>> +				   unsigned int count,
>> +				   unsigned char data[])
>>   {
>>   	u32 reg;
>>   	unsigned int start_offset;
>> @@ -683,9 +681,9 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
>>   			retval = exynos_dp_start_aux_transaction(dp);
>>   			if (retval == 0)
>>   				break;
>> -			else
>> -				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> -					__func__);
>> +
>> +			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> +				__func__);
>>   		}
>>   
>>   		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
>> @@ -736,9 +734,9 @@ int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
>>   }
>>   
>>   int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
>> -				unsigned int device_addr,
>> -				unsigned int reg_addr,
>> -				unsigned int *data)
>> +				 unsigned int device_addr,
>> +				 unsigned int reg_addr,
>> +				 unsigned int *data)
>>   {
>>   	u32 reg;
>>   	int i;
>> @@ -767,9 +765,8 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
>>   		retval = exynos_dp_start_aux_transaction(dp);
>>   		if (retval == 0)
>>   			break;
>> -		else
>> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> -				__func__);
>> +
>> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
>>   	}
>>   
>>   	/* Read data */
>> @@ -780,10 +777,10 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
>>   }
>>   
>>   int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
>> -				unsigned int device_addr,
>> -				unsigned int reg_addr,
>> -				unsigned int count,
>> -				unsigned char edid[])
>> +				  unsigned int device_addr,
>> +				  unsigned int reg_addr,
>> +				  unsigned int count,
>> +				  unsigned char edid[])
>>   {
>>   	u32 reg;
>>   	unsigned int i, j;
>> @@ -807,8 +804,8 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
>>   			 * request without sending address
>>   			 */
>>   			if (!defer)
>> -				retval = exynos_dp_select_i2c_device(dp,
>> -						device_addr, reg_addr + i);
>> +				retval = exynos_dp_select_i2c_device(
>> +						dp, device_addr, reg_addr + i);
> ditto

Done

Thanks,
- Yakir

>
> Best regards,
> Krzysztof
>
>>   			else
>>   				defer = 0;
>>   
>> @@ -819,24 +816,23 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
>>   				 * If Bit 3 is 0, I2C transaction.
>>   				 */
>>   				reg = AUX_LENGTH(16) |
>> -					AUX_TX_COMM_I2C_TRANSACTION |
>> -					AUX_TX_COMM_READ;
>> +				      AUX_TX_COMM_I2C_TRANSACTION |
>> +				      AUX_TX_COMM_READ;
>>   				writel(reg, dp->reg_base +
>> -					EXYNOS_DP_AUX_CH_CTL_1);
>> +				       EXYNOS_DP_AUX_CH_CTL_1);
>>   
>>   				/* Start AUX transaction */
>>   				retval = exynos_dp_start_aux_transaction(dp);
>>   				if (retval == 0)
>>   					break;
>> -				else
>> -					dev_dbg(dp->dev,
>> -						"%s: Aux Transaction fail!\n",
>> -						__func__);
>> +
>> +				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> +					__func__);
>>   			}
>>   			/* Check if Rx sends defer */
>>   			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
>>   			if (reg == AUX_RX_COMM_AUX_DEFER ||
>> -				reg == AUX_RX_COMM_I2C_DEFER) {
>> +			    reg == AUX_RX_COMM_I2C_DEFER) {
>>   				dev_err(dp->dev, "Defer: %d\n\n", reg);
>>   				defer = 1;
>>   			}
>> @@ -901,7 +897,7 @@ void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
>>   }
>>   
>>   void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
>> -				 enum pattern_set pattern)
>> +				    enum pattern_set pattern)
>>   {
>>   	u32 reg;
>>   
>> @@ -974,7 +970,7 @@ void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
>>   }
>>   
>>   void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
>> -					u32 training_lane)
>> +				       u32 training_lane)
>>   {
>>   	u32 reg;
>>   
>> @@ -983,7 +979,7 @@ void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
>>   }
>>   
>>   void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
>> -					u32 training_lane)
>> +				       u32 training_lane)
>>   {
>>   	u32 reg;
>>   
>> @@ -992,7 +988,7 @@ void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
>>   }
>>   
>>   void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
>> -					u32 training_lane)
>> +				       u32 training_lane)
>>   {
>>   	u32 reg;
>>   
>> @@ -1001,7 +997,7 @@ void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
>>   }
>>   
>>   void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
>> -					u32 training_lane)
>> +				       u32 training_lane)
>>   {
>>   	u32 reg;
>>   
>> @@ -1125,9 +1121,9 @@ int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
>>   }
>>   
>>   void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
>> -		enum clock_recovery_m_value_type type,
>> -		u32 m_value,
>> -		u32 n_value)
>> +			       enum clock_recovery_m_value_type type,
>> +			       u32 m_value,
>> +			       u32 n_value)
>>   {
>>   	u32 reg;
>>   
>> @@ -1221,7 +1217,7 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
>>   	u32 reg;
>>   
>>   	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
>> -	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
>> +	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
>>   	reg |= MASTER_VID_FUNC_EN_N;
>>   	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
>>   
>>
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 01/16] drm: exynos/dp: fix code style
@ 2015-09-03  5:04       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  5:04 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Krzysztof,

? 09/03/2015 08:21 AM, Krzysztof Kozlowski ??:
> On 01.09.2015 14:46, Yakir Yang wrote:
>> After run "checkpatch.pl -f --subjective" command, I see there
>> are lots of alignment problem in exynos_dp driver, so let just
>> fix them.
> Hi,
>
> Warnings from checkpatch are not a reason for a commit. Reason for a
> commit could be for example an unreadable code, violation of
> coding-style leading to decrease in code maintainability or just
> improving the code readability so it will be easier to review and
> maintain it.
>
> You do not make commits because some tool tells you that. We do not
> listen to machines :) ... If that would be the case, the commit could be
> made automatically, without human interaction. Such automated commit
> could be even easily tested by the machine by comparing object files.
>
> Especially that you enabled "subjective" rule. This is not a valid
> motivation for a commit.
>
> Please rephrase this to sensible reason and convince that change is
> worth the effort.

Oh, nice, thanks for your remind. I would rephrase the commit.

>> - Take Romain suggest, rebase on linux-next branch
> That comment seems unrelated to the commit. Please remove it.

Done,

>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2:
>> - Take Joe Preches advise, improved commit message more readable, and
>>    avoid using some uncommon style like bellow:
>>    -  retval = exynos_dp_read_bytes_from_i2c(...
>> 				...)
>>    +  retval =
>>    +  exynos_dp_read_bytes_from_i2c(......);
>>
>>   drivers/gpu/drm/exynos/exynos_dp_core.c | 226 ++++++++++++++++----------------
>>   drivers/gpu/drm/exynos/exynos_dp_core.h |  54 ++++----
>>   drivers/gpu/drm/exynos/exynos_dp_reg.c  | 106 +++++++--------
>>   3 files changed, 188 insertions(+), 198 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
>> index d66ade0..266f7f7 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
>> @@ -115,8 +115,8 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   
>>   	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
>>   	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>> -				EDID_EXTENSION_FLAG,
>> -				&extend_block);
>> +					      EDID_EXTENSION_FLAG,
>> +					      &extend_block);
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -124,10 +124,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>>   
>>   		/* Read EDID data */
>> -		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>> -						EDID_HEADER_PATTERN,
>> -						EDID_BLOCK_LENGTH,
>> -						&edid[EDID_HEADER_PATTERN]);
>> +		retval = exynos_dp_read_bytes_from_i2c(
>> +					dp, I2C_EDID_DEVICE_ADDR,
>> +					EDID_HEADER_PATTERN,
>> +					EDID_BLOCK_LENGTH,
>> +					&edid[EDID_HEADER_PATTERN]);
>>   		if (retval != 0) {
>>   			dev_err(dp->dev, "EDID Read failed!\n");
>>   			return -EIO;
>> @@ -139,11 +140,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   		}
>>   
>>   		/* Read additional EDID data */
>> -		retval = exynos_dp_read_bytes_from_i2c(dp,
>> -				I2C_EDID_DEVICE_ADDR,
>> -				EDID_BLOCK_LENGTH,
>> -				EDID_BLOCK_LENGTH,
>> -				&edid[EDID_BLOCK_LENGTH]);
>> +		retval = exynos_dp_read_bytes_from_i2c(
>> +					dp, I2C_EDID_DEVICE_ADDR,
>> +					EDID_BLOCK_LENGTH,
>> +					EDID_BLOCK_LENGTH,
>> +					&edid[EDID_BLOCK_LENGTH]);
>>   		if (retval != 0) {
>>   			dev_err(dp->dev, "EDID Read failed!\n");
>>   			return -EIO;
>> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   		}
>>   
>>   		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
>> -					&test_vector);
>> +					      &test_vector);
>>   		if (test_vector & DP_TEST_LINK_EDID_READ) {
>> -			exynos_dp_write_byte_to_dpcd(dp,
>> -				DP_TEST_EDID_CHECKSUM,
>> +			exynos_dp_write_byte_to_dpcd(
>> +				dp, DP_TEST_EDID_CHECKSUM,
>>   				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
>> -			exynos_dp_write_byte_to_dpcd(dp,
>> -				DP_TEST_RESPONSE,
>> +			exynos_dp_write_byte_to_dpcd(
>> +				dp, DP_TEST_RESPONSE,
>>   				DP_TEST_EDID_CHECKSUM_WRITE);
> To me, missing argument after opening parenthesis, looks worse. I would
> prefer:
>
> 			exynos_dp_write_byte_to_dpcd(dp,
>
> Why you moved the 'dp' argument to new line?

Hmm... Just like style tool indicate, no more warning after
that change.

For now, I would like to follow the original style, just improved
some obvious style problem.  :-)

>
>>   		}
>>   	} else {
>>   		dev_info(dp->dev, "EDID data does not include any extensions.\n");
>>   
>>   		/* Read EDID data */
>> -		retval = exynos_dp_read_bytes_from_i2c(dp,
>> -				I2C_EDID_DEVICE_ADDR,
>> -				EDID_HEADER_PATTERN,
>> -				EDID_BLOCK_LENGTH,
>> -				&edid[EDID_HEADER_PATTERN]);
>> +		retval = exynos_dp_read_bytes_from_i2c(
>> +				dp, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
>> +				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
> ditto

Done

>
>>   		if (retval != 0) {
>>   			dev_err(dp->dev, "EDID Read failed!\n");
>>   			return -EIO;
>> @@ -183,16 +182,15 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   			return -EIO;
>>   		}
>>   
>> -		exynos_dp_read_byte_from_dpcd(dp,
>> -			DP_TEST_REQUEST,
>> -			&test_vector);
>> +		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
>> +					      &test_vector);
>>   		if (test_vector & DP_TEST_LINK_EDID_READ) {
>> -			exynos_dp_write_byte_to_dpcd(dp,
>> -				DP_TEST_EDID_CHECKSUM,
>> -				edid[EDID_CHECKSUM]);
>> -			exynos_dp_write_byte_to_dpcd(dp,
>> -				DP_TEST_RESPONSE,
>> -				DP_TEST_EDID_CHECKSUM_WRITE);
>> +			exynos_dp_write_byte_to_dpcd(
>> +					dp, DP_TEST_EDID_CHECKSUM,
>> +					edid[EDID_CHECKSUM]);
>> +			exynos_dp_write_byte_to_dpcd(
>> +					dp, DP_TEST_RESPONSE,
>> +					DP_TEST_EDID_CHECKSUM_WRITE);
> ditto

Done

>
>>   		}
>>   	}
>>   
>> @@ -207,8 +205,7 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
>>   	int retval;
>>   
>>   	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
>> -	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
>> -				12, buf);
>> +	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -223,7 +220,7 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
>>   }
>>   
>>   static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
>> -						bool enable)
>> +						 bool enable)
>>   {
>>   	u8 data;
>>   
>> @@ -231,11 +228,11 @@ static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
>>   
>>   	if (enable)
>>   		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
>> -			DP_LANE_COUNT_ENHANCED_FRAME_EN |
>> -			DPCD_LANE_COUNT_SET(data));
>> +					     DP_LANE_COUNT_ENHANCED_FRAME_EN |
>> +					     DPCD_LANE_COUNT_SET(data));
>>   	else
>>   		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
>> -			DPCD_LANE_COUNT_SET(data));
>> +					     DPCD_LANE_COUNT_SET(data));
>>   }
>>   
>>   static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
>> @@ -262,13 +259,12 @@ static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
>>   {
>>   	exynos_dp_set_training_pattern(dp, DP_NONE);
>>   
>> -	exynos_dp_write_byte_to_dpcd(dp,
>> -		DP_TRAINING_PATTERN_SET,
>> -		DP_TRAINING_PATTERN_DISABLE);
>> +	exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
>> +				     DP_TRAINING_PATTERN_DISABLE);
>>   }
>>   
>>   static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
>> -					int pre_emphasis, int lane)
>> +						 int pre_emphasis, int lane)
>>   {
>>   	switch (lane) {
>>   	case 0:
>> @@ -308,15 +304,14 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>>   	/* Setup RX configuration */
>>   	buf[0] = dp->link_train.link_rate;
>>   	buf[1] = dp->link_train.lane_count;
>> -	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
>> -				2, buf);
>> +	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
>>   	if (retval)
>>   		return retval;
>>   
>>   	/* Set TX pre-emphasis to minimum */
>>   	for (lane = 0; lane < lane_count; lane++)
>> -		exynos_dp_set_lane_lane_pre_emphasis(dp,
>> -			PRE_EMPHASIS_LEVEL_0, lane);
>> +		exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0,
>> +						     lane);
>>   
>>   	/* Wait for PLL lock */
>>   	pll_tries = 0;
>> @@ -334,9 +329,9 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>>   	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
>>   
>>   	/* Set RX training pattern */
>> -	retval = exynos_dp_write_byte_to_dpcd(dp,
>> -			DP_TRAINING_PATTERN_SET,
>> -			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
>> +	retval = exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
>> +					      DP_LINK_SCRAMBLING_DISABLE |
>> +					      DP_TRAINING_PATTERN_1);
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -345,7 +340,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>>   			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
>>   
>>   	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
>> -			lane_count, buf);
>> +					       lane_count, buf);
>>   
>>   	return retval;
>>   }
>> @@ -353,7 +348,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
>>   static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
>>   {
>>   	int shift = (lane & 1) * 4;
>> -	u8 link_value = link_status[lane>>1];
>> +	u8 link_value = link_status[lane >> 1];
>>   
>>   	return (link_value >> shift) & 0xf;
>>   }
>> @@ -372,7 +367,7 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
>>   }
>>   
>>   static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
>> -				int lane_count)
>> +				   int lane_count)
>>   {
>>   	int lane;
>>   	u8 lane_status;
>> @@ -391,10 +386,10 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
>>   }
>>   
>>   static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
>> -							int lane)
>> +							  int lane)
>>   {
>>   	int shift = (lane & 1) * 4;
>> -	u8 link_value = adjust_request[lane>>1];
>> +	u8 link_value = adjust_request[lane >> 1];
>>   
>>   	return (link_value >> shift) & 0x3;
>>   }
>> @@ -404,13 +399,13 @@ static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
>>   					int lane)
>>   {
>>   	int shift = (lane & 1) * 4;
>> -	u8 link_value = adjust_request[lane>>1];
>> +	u8 link_value = adjust_request[lane >> 1];
>>   
>>   	return ((link_value >> shift) & 0xc) >> 2;
>>   }
>>   
>>   static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
>> -					u8 training_lane_set, int lane)
>> +					     u8 training_lane_set, int lane)
>>   {
>>   	switch (lane) {
>>   	case 0:
>> @@ -430,9 +425,8 @@ static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
>>   	}
>>   }
>>   
>> -static unsigned int exynos_dp_get_lane_link_training(
>> -				struct exynos_dp_device *dp,
>> -				int lane)
>> +static unsigned int
>> +exynos_dp_get_lane_link_training(struct exynos_dp_device *dp, int lane)
>>   {
>>   	u32 reg;
>>   
>> @@ -466,7 +460,7 @@ static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
>>   }
>>   
>>   static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
>> -					u8 adjust_request[2])
>> +					       u8 adjust_request[2])
>>   {
>>   	int lane, lane_count;
>>   	u8 voltage_swing, pre_emphasis, training_lane;
>> @@ -499,13 +493,13 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>>   
>>   	lane_count = dp->link_train.lane_count;
>>   
>> -	retval =  exynos_dp_read_bytes_from_dpcd(dp,
>> -			DP_LANE0_1_STATUS, 2, link_status);
>> +	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
>> +						 2, link_status);
>>   	if (retval)
>>   		return retval;
>>   
>> -	retval =  exynos_dp_read_bytes_from_dpcd(dp,
>> -			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
>> +	retval =  exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
>> +						 2, adjust_request);
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -513,8 +507,8 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>>   		/* set training pattern 2 for EQ */
>>   		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
>>   
>> -		retval = exynos_dp_write_byte_to_dpcd(dp,
>> -				DP_TRAINING_PATTERN_SET,
>> +		retval = exynos_dp_write_byte_to_dpcd(
>> +				dp, DP_TRAINING_PATTERN_SET,
>>   				DP_LINK_SCRAMBLING_DISABLE |
>>   				DP_TRAINING_PATTERN_2);
> ditto

Done

>
>>   		if (retval)
>> @@ -552,11 +546,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>>   	exynos_dp_get_adjust_training_lane(dp, adjust_request);
>>   
>>   	for (lane = 0; lane < lane_count; lane++)
>> -		exynos_dp_set_lane_link_training(dp,
>> -			dp->link_train.training_lane[lane], lane);
>> +		exynos_dp_set_lane_link_training(
>> +				dp, dp->link_train.training_lane[lane], lane);
>>   
>> -	retval = exynos_dp_write_bytes_to_dpcd(dp,
>> -			DP_TRAINING_LANE0_SET, lane_count,
>> +	retval = exynos_dp_write_bytes_to_dpcd(
>> +			dp, DP_TRAINING_LANE0_SET, lane_count,
>>   			dp->link_train.training_lane);
> ditto

Done

>
>>   	if (retval)
>>   		return retval;
>> @@ -574,8 +568,8 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>>   
>>   	lane_count = dp->link_train.lane_count;
>>   
>> -	retval = exynos_dp_read_bytes_from_dpcd(dp,
>> -			DP_LANE0_1_STATUS, 2, link_status);
>> +	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS,
>> +						2, link_status);
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -584,13 +578,13 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>>   		return -EIO;
>>   	}
>>   
>> -	retval = exynos_dp_read_bytes_from_dpcd(dp,
>> -			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
>> +	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1,
>> +						2, adjust_request);
>>   	if (retval)
>>   		return retval;
>>   
>> -	retval = exynos_dp_read_byte_from_dpcd(dp,
>> -			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
>> +	retval = exynos_dp_read_byte_from_dpcd(dp, DP_LANE_ALIGN_STATUS_UPDATED,
>> +					       &link_align);
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -629,17 +623,18 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>>   	}
>>   
>>   	for (lane = 0; lane < lane_count; lane++)
>> -		exynos_dp_set_lane_link_training(dp,
>> -			dp->link_train.training_lane[lane], lane);
>> +		exynos_dp_set_lane_link_training(
>> +				dp, dp->link_train.training_lane[lane], lane);
> ditto

Done

>
>>   
>>   	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
>> -			lane_count, dp->link_train.training_lane);
>> +					       lane_count,
>> +					       dp->link_train.training_lane);
>>   
>>   	return retval;
>>   }
>>   
>>   static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
>> -					u8 *bandwidth)
>> +					   u8 *bandwidth)
>>   {
>>   	u8 data;
>>   
>> @@ -652,7 +647,7 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
>>   }
>>   
>>   static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
>> -					u8 *lane_count)
>> +					    u8 *lane_count)
>>   {
>>   	u8 data;
>>   
>> @@ -665,8 +660,8 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
>>   }
>>   
>>   static void exynos_dp_init_training(struct exynos_dp_device *dp,
>> -			enum link_lane_count_type max_lane,
>> -			enum link_rate_type max_rate)
>> +				    enum link_lane_count_type max_lane,
>> +				    enum link_rate_type max_rate)
>>   {
>>   	/*
>>   	 * MACRO_RST must be applied after the PLL_LOCK to avoid
>> @@ -679,7 +674,7 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
>>   	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
>>   
>>   	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
>> -	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
>> +	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
>>   		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
>>   			dp->link_train.link_rate);
>>   		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
>> @@ -739,8 +734,7 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
>>   }
>>   
>>   static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
>> -				u32 count,
>> -				u32 bwtype)
>> +				    u32 count, u32 bwtype)
>>   {
>>   	int i;
>>   	int retval;
>> @@ -828,21 +822,19 @@ static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
>>   	if (enable) {
>>   		exynos_dp_enable_scrambling(dp);
>>   
>> -		exynos_dp_read_byte_from_dpcd(dp,
>> -			DP_TRAINING_PATTERN_SET,
>> -			&data);
>> -		exynos_dp_write_byte_to_dpcd(dp,
>> -			DP_TRAINING_PATTERN_SET,
>> -			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
>> +		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
>> +					      &data);
>> +		exynos_dp_write_byte_to_dpcd(
>> +				dp, DP_TRAINING_PATTERN_SET,
>> +				(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
> ditto

Done

>
>>   	} else {
>>   		exynos_dp_disable_scrambling(dp);
>>   
>> -		exynos_dp_read_byte_from_dpcd(dp,
>> -			DP_TRAINING_PATTERN_SET,
>> -			&data);
>> -		exynos_dp_write_byte_to_dpcd(dp,
>> -			DP_TRAINING_PATTERN_SET,
>> -			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
>> +		exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
>> +					      &data);
>> +		exynos_dp_write_byte_to_dpcd(
>> +				dp, DP_TRAINING_PATTERN_SET,
>> +				(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
> ditto

Done

>
>>   	}
>>   }
>>   
>> @@ -913,7 +905,7 @@ static void exynos_dp_commit(struct drm_encoder *encoder)
>>   	}
>>   
>>   	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
>> -					dp->video_info->link_rate);
>> +				       dp->video_info->link_rate);
>>   	if (ret) {
>>   		dev_err(dp->dev, "unable to do link train\n");
>>   		return;
>> @@ -941,8 +933,8 @@ static void exynos_dp_commit(struct drm_encoder *encoder)
>>   	exynos_dp_start_video(dp);
>>   }
>>   
>> -static enum drm_connector_status exynos_dp_detect(
>> -				struct drm_connector *connector, bool force)
>> +static enum drm_connector_status
>> +exynos_dp_detect(struct drm_connector *connector, bool force)
>>   {
>>   	return connector_status_connected;
>>   }
>> @@ -990,8 +982,8 @@ static int exynos_dp_get_modes(struct drm_connector *connector)
>>   	return 1;
>>   }
>>   
>> -static struct drm_encoder *exynos_dp_best_encoder(
>> -			struct drm_connector *connector)
>> +static struct drm_encoder *
>> +exynos_dp_best_encoder(struct drm_connector *connector)
>>   {
>>   	struct exynos_dp_device *dp = ctx_from_connector(connector);
>>   
>> @@ -1005,7 +997,7 @@ static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
>>   
>>   /* returns the number of bridges attached */
>>   static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
>> -		struct drm_encoder *encoder)
>> +					struct drm_encoder *encoder)
>>   {
>>   	int ret;
>>   
>> @@ -1036,7 +1028,8 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
>>   	connector->polled = DRM_CONNECTOR_POLL_HPD;
>>   
>>   	ret = drm_connector_init(dp->drm_dev, connector,
>> -			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
>> +				 &exynos_dp_connector_funcs,
>> +				 DRM_MODE_CONNECTOR_eDP);
>>   	if (ret) {
>>   		DRM_ERROR("Failed to initialize connector with drm\n");
>>   		return ret;
>> @@ -1139,8 +1132,8 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
>>   	struct device_node *dp_node = dev->of_node;
>>   	struct video_info *dp_video_config;
>>   
>> -	dp_video_config = devm_kzalloc(dev,
>> -				sizeof(*dp_video_config), GFP_KERNEL);
>> +	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
>> +				       GFP_KERNEL);
>>   	if (!dp_video_config)
>>   		return ERR_PTR(-ENOMEM);
>>   
>> @@ -1154,37 +1147,37 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
>>   		of_property_read_bool(dp_node, "interlaced");
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,color-space",
>> -				&dp_video_config->color_space)) {
>> +				 &dp_video_config->color_space)) {
>>   		dev_err(dev, "failed to get color-space\n");
>>   		return ERR_PTR(-EINVAL);
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
>> -				&dp_video_config->dynamic_range)) {
>> +				 &dp_video_config->dynamic_range)) {
>>   		dev_err(dev, "failed to get dynamic-range\n");
>>   		return ERR_PTR(-EINVAL);
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
>> -				&dp_video_config->ycbcr_coeff)) {
>> +				 &dp_video_config->ycbcr_coeff)) {
>>   		dev_err(dev, "failed to get ycbcr-coeff\n");
>>   		return ERR_PTR(-EINVAL);
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,color-depth",
>> -				&dp_video_config->color_depth)) {
>> +				 &dp_video_config->color_depth)) {
>>   		dev_err(dev, "failed to get color-depth\n");
>>   		return ERR_PTR(-EINVAL);
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,link-rate",
>> -				&dp_video_config->link_rate)) {
>> +				 &dp_video_config->link_rate)) {
>>   		dev_err(dev, "failed to get link-rate\n");
>>   		return ERR_PTR(-EINVAL);
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,lane-count",
>> -				&dp_video_config->lane_count)) {
>> +				 &dp_video_config->lane_count)) {
>>   		dev_err(dev, "failed to get lane-count\n");
>>   		return ERR_PTR(-EINVAL);
>>   	}
>> @@ -1197,7 +1190,7 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
>>   	int ret;
>>   
>>   	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
>> -			OF_USE_NATIVE_MODE);
>> +			       OF_USE_NATIVE_MODE);
>>   	if (ret) {
>>   		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
>>   		return ret;
>> @@ -1294,7 +1287,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>>   	exynos_dp_init_dp(dp);
>>   
>>   	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
>> -			irq_flags, "exynos-dp", dp);
>> +			       irq_flags, "exynos-dp", dp);
>>   	if (ret) {
>>   		dev_err(&pdev->dev, "failed to request irq\n");
>>   		return ret;
>> @@ -1328,7 +1321,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>>   }
>>   
>>   static void exynos_dp_unbind(struct device *dev, struct device *master,
>> -				void *data)
>> +			     void *data)
>>   {
>>   	struct exynos_dp_device *dp = dev_get_drvdata(dev);
>>   
>> @@ -1347,7 +1340,7 @@ static int exynos_dp_probe(struct platform_device *pdev)
>>   	struct exynos_dp_device *dp;
>>   
>>   	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
>> -				GFP_KERNEL);
>> +			  GFP_KERNEL);
>>   	if (!dp)
>>   		return -ENOMEM;
>>   
>> @@ -1369,8 +1362,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
>>   			of_node_put(bridge_node);
>>   			if (!dp->bridge)
>>   				return -EPROBE_DEFER;
>> -		} else
>> +		} else {
>>   			return -EPROBE_DEFER;
>> +		}
>>   	}
>>   
>>   	return component_add(&pdev->dev, &exynos_dp_ops);
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
>> index e413b6f..71f2b86 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.h
>> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
>> @@ -179,8 +179,8 @@ void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
>>   enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
>>   void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
>>   void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
>> -				enum analog_power_block block,
>> -				bool enable);
>> +				     enum analog_power_block block,
>> +				     bool enable);
>>   void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
>>   void exynos_dp_init_hpd(struct exynos_dp_device *dp);
>>   enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
>> @@ -191,50 +191,50 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
>>   void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
>>   int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
>>   int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned char data);
>> +				 unsigned int reg_addr,
>> +				 unsigned char data);
>>   int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned char *data);
>> +				  unsigned int reg_addr,
>> +				  unsigned char *data);
>>   int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned int count,
>> -				unsigned char data[]);
>> +				  unsigned int reg_addr,
>> +				  unsigned int count,
>> +				  unsigned char data[]);
>>   int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned int count,
>> -				unsigned char data[]);
>> +				   unsigned int reg_addr,
>> +				   unsigned int count,
>> +				   unsigned char data[]);
>>   int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
>>   				unsigned int device_addr,
>>   				unsigned int reg_addr);
>>   int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
>> -				unsigned int device_addr,
>> -				unsigned int reg_addr,
>> -				unsigned int *data);
>> +				 unsigned int device_addr,
>> +				 unsigned int reg_addr,
>> +				 unsigned int *data);
>>   int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
>> -				unsigned int device_addr,
>> -				unsigned int reg_addr,
>> -				unsigned int count,
>> -				unsigned char edid[]);
>> +				  unsigned int device_addr,
>> +				  unsigned int reg_addr,
>> +				  unsigned int count,
>> +				  unsigned char edid[]);
>>   void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
>>   void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
>>   void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
>>   void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
>>   void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
>>   void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
>> -				 enum pattern_set pattern);
>> +				    enum pattern_set pattern);
>>   void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>>   void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>>   void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>>   void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
>>   void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
>> -				u32 training_lane);
>> +				       u32 training_lane);
>>   void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
>> -				u32 training_lane);
>> +				       u32 training_lane);
>>   void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
>> -				u32 training_lane);
>> +				       u32 training_lane);
>>   void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
>> -				u32 training_lane);
>> +				       u32 training_lane);
>>   u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
>>   u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
>>   u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
>> @@ -245,9 +245,9 @@ void exynos_dp_init_video(struct exynos_dp_device *dp);
>>   void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
>>   int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
>>   void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
>> -			enum clock_recovery_m_value_type type,
>> -			u32 m_value,
>> -			u32 n_value);
>> +			       enum clock_recovery_m_value_type type,
>> +			       u32 m_value,
>> +			       u32 n_value);
>>   void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
>>   void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
>>   void exynos_dp_start_video(struct exynos_dp_device *dp);
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
>> index c1f87a2..5aff19a 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
>> +++ b/drivers/gpu/drm/exynos/exynos_dp_reg.c
>> @@ -202,8 +202,8 @@ void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
>>   }
>>   
>>   void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
>> -				enum analog_power_block block,
>> -				bool enable)
>> +				     enum analog_power_block block,
>> +				     bool enable)
>>   {
>>   	u32 reg;
>>   
>> @@ -399,8 +399,8 @@ void exynos_dp_init_aux(struct exynos_dp_device *dp)
>>   	exynos_dp_reset_aux(dp);
>>   
>>   	/* Disable AUX transaction H/W retry */
>> -	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
>> -		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
>> +	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
>> +	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
>>   	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
>>   
>>   	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
>> @@ -483,8 +483,8 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
>>   }
>>   
>>   int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned char data)
>> +				 unsigned int reg_addr,
>> +				 unsigned char data)
>>   {
>>   	u32 reg;
>>   	int i;
>> @@ -519,17 +519,16 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
>>   		retval = exynos_dp_start_aux_transaction(dp);
>>   		if (retval == 0)
>>   			break;
>> -		else
>> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> -				__func__);
>> +
>> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
>>   	}
>>   
>>   	return retval;
>>   }
>>   
>>   int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned char *data)
>> +				  unsigned int reg_addr,
>> +				  unsigned char *data)
>>   {
>>   	u32 reg;
>>   	int i;
>> @@ -560,9 +559,8 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
>>   		retval = exynos_dp_start_aux_transaction(dp);
>>   		if (retval == 0)
>>   			break;
>> -		else
>> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> -				__func__);
>> +
>> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
>>   	}
>>   
>>   	/* Read data buffer */
>> @@ -573,9 +571,9 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
>>   }
>>   
>>   int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned int count,
>> -				unsigned char data[])
>> +				  unsigned int reg_addr,
>> +				  unsigned int count,
>> +				  unsigned char data[])
>>   {
>>   	u32 reg;
>>   	unsigned int start_offset;
>> @@ -625,9 +623,9 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
>>   			retval = exynos_dp_start_aux_transaction(dp);
>>   			if (retval == 0)
>>   				break;
>> -			else
>> -				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> -					__func__);
>> +
>> +			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> +				__func__);
>>   		}
>>   
>>   		start_offset += cur_data_count;
>> @@ -637,9 +635,9 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
>>   }
>>   
>>   int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
>> -				unsigned int reg_addr,
>> -				unsigned int count,
>> -				unsigned char data[])
>> +				   unsigned int reg_addr,
>> +				   unsigned int count,
>> +				   unsigned char data[])
>>   {
>>   	u32 reg;
>>   	unsigned int start_offset;
>> @@ -683,9 +681,9 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
>>   			retval = exynos_dp_start_aux_transaction(dp);
>>   			if (retval == 0)
>>   				break;
>> -			else
>> -				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> -					__func__);
>> +
>> +			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> +				__func__);
>>   		}
>>   
>>   		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
>> @@ -736,9 +734,9 @@ int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
>>   }
>>   
>>   int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
>> -				unsigned int device_addr,
>> -				unsigned int reg_addr,
>> -				unsigned int *data)
>> +				 unsigned int device_addr,
>> +				 unsigned int reg_addr,
>> +				 unsigned int *data)
>>   {
>>   	u32 reg;
>>   	int i;
>> @@ -767,9 +765,8 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
>>   		retval = exynos_dp_start_aux_transaction(dp);
>>   		if (retval == 0)
>>   			break;
>> -		else
>> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> -				__func__);
>> +
>> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
>>   	}
>>   
>>   	/* Read data */
>> @@ -780,10 +777,10 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
>>   }
>>   
>>   int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
>> -				unsigned int device_addr,
>> -				unsigned int reg_addr,
>> -				unsigned int count,
>> -				unsigned char edid[])
>> +				  unsigned int device_addr,
>> +				  unsigned int reg_addr,
>> +				  unsigned int count,
>> +				  unsigned char edid[])
>>   {
>>   	u32 reg;
>>   	unsigned int i, j;
>> @@ -807,8 +804,8 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
>>   			 * request without sending address
>>   			 */
>>   			if (!defer)
>> -				retval = exynos_dp_select_i2c_device(dp,
>> -						device_addr, reg_addr + i);
>> +				retval = exynos_dp_select_i2c_device(
>> +						dp, device_addr, reg_addr + i);
> ditto

Done

Thanks,
- Yakir

>
> Best regards,
> Krzysztof
>
>>   			else
>>   				defer = 0;
>>   
>> @@ -819,24 +816,23 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
>>   				 * If Bit 3 is 0, I2C transaction.
>>   				 */
>>   				reg = AUX_LENGTH(16) |
>> -					AUX_TX_COMM_I2C_TRANSACTION |
>> -					AUX_TX_COMM_READ;
>> +				      AUX_TX_COMM_I2C_TRANSACTION |
>> +				      AUX_TX_COMM_READ;
>>   				writel(reg, dp->reg_base +
>> -					EXYNOS_DP_AUX_CH_CTL_1);
>> +				       EXYNOS_DP_AUX_CH_CTL_1);
>>   
>>   				/* Start AUX transaction */
>>   				retval = exynos_dp_start_aux_transaction(dp);
>>   				if (retval == 0)
>>   					break;
>> -				else
>> -					dev_dbg(dp->dev,
>> -						"%s: Aux Transaction fail!\n",
>> -						__func__);
>> +
>> +				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
>> +					__func__);
>>   			}
>>   			/* Check if Rx sends defer */
>>   			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
>>   			if (reg == AUX_RX_COMM_AUX_DEFER ||
>> -				reg == AUX_RX_COMM_I2C_DEFER) {
>> +			    reg == AUX_RX_COMM_I2C_DEFER) {
>>   				dev_err(dp->dev, "Defer: %d\n\n", reg);
>>   				defer = 1;
>>   			}
>> @@ -901,7 +897,7 @@ void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
>>   }
>>   
>>   void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
>> -				 enum pattern_set pattern)
>> +				    enum pattern_set pattern)
>>   {
>>   	u32 reg;
>>   
>> @@ -974,7 +970,7 @@ void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
>>   }
>>   
>>   void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
>> -					u32 training_lane)
>> +				       u32 training_lane)
>>   {
>>   	u32 reg;
>>   
>> @@ -983,7 +979,7 @@ void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
>>   }
>>   
>>   void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
>> -					u32 training_lane)
>> +				       u32 training_lane)
>>   {
>>   	u32 reg;
>>   
>> @@ -992,7 +988,7 @@ void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
>>   }
>>   
>>   void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
>> -					u32 training_lane)
>> +				       u32 training_lane)
>>   {
>>   	u32 reg;
>>   
>> @@ -1001,7 +997,7 @@ void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
>>   }
>>   
>>   void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
>> -					u32 training_lane)
>> +				       u32 training_lane)
>>   {
>>   	u32 reg;
>>   
>> @@ -1125,9 +1121,9 @@ int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
>>   }
>>   
>>   void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
>> -		enum clock_recovery_m_value_type type,
>> -		u32 m_value,
>> -		u32 n_value)
>> +			       enum clock_recovery_m_value_type type,
>> +			       u32 m_value,
>> +			       u32 n_value)
>>   {
>>   	u32 reg;
>>   
>> @@ -1221,7 +1217,7 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
>>   	u32 reg;
>>   
>>   	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
>> -	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
>> +	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
>>   	reg |= MASTER_VID_FUNC_EN_N;
>>   	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
>>   
>>
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 01/16] drm: exynos/dp: fix code style
  2015-09-03  5:04       ` Yakir Yang
@ 2015-09-03  5:08         ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-03  5:08 UTC (permalink / raw)
  To: Yakir Yang, Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

On 03.09.2015 14:04, Yakir Yang wrote:
> Hi Krzysztof,
> 
> 在 09/03/2015 08:21 AM, Krzysztof Kozlowski 写道:
>> On 01.09.2015 14:46, Yakir Yang wrote:
>>> After run "checkpatch.pl -f --subjective" command, I see there
>>> are lots of alignment problem in exynos_dp driver, so let just
>>> fix them.
>> Hi,
>>
>> Warnings from checkpatch are not a reason for a commit. Reason for a
>> commit could be for example an unreadable code, violation of
>> coding-style leading to decrease in code maintainability or just
>> improving the code readability so it will be easier to review and
>> maintain it.
>>
>> You do not make commits because some tool tells you that. We do not
>> listen to machines :) ... If that would be the case, the commit could be
>> made automatically, without human interaction. Such automated commit
>> could be even easily tested by the machine by comparing object files.
>>
>> Especially that you enabled "subjective" rule. This is not a valid
>> motivation for a commit.
>>
>> Please rephrase this to sensible reason and convince that change is
>> worth the effort.
> 
> Oh, nice, thanks for your remind. I would rephrase the commit.
> 
>>> - Take Romain suggest, rebase on linux-next branch
>> That comment seems unrelated to the commit. Please remove it.
> 
> Done,
> 
>>
>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>> ---
>>> Changes in v4: None
>>> Changes in v3: None
>>> Changes in v2:
>>> - Take Joe Preches advise, improved commit message more readable, and
>>>    avoid using some uncommon style like bellow:
>>>    -  retval = exynos_dp_read_bytes_from_i2c(...
>>>                 ...)
>>>    +  retval =
>>>    +  exynos_dp_read_bytes_from_i2c(......);
>>>
>>>   drivers/gpu/drm/exynos/exynos_dp_core.c | 226
>>> ++++++++++++++++----------------
>>>   drivers/gpu/drm/exynos/exynos_dp_core.h |  54 ++++----
>>>   drivers/gpu/drm/exynos/exynos_dp_reg.c  | 106 +++++++--------
>>>   3 files changed, 188 insertions(+), 198 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>> b/drivers/gpu/drm/exynos/exynos_dp_core.c
>>> index d66ade0..266f7f7 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
>>> @@ -115,8 +115,8 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>>>         /* Read Extension Flag, Number of 128-byte EDID extension
>>> blocks */
>>>       retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>>> -                EDID_EXTENSION_FLAG,
>>> -                &extend_block);
>>> +                          EDID_EXTENSION_FLAG,
>>> +                          &extend_block);
>>>       if (retval)
>>>           return retval;
>>>   @@ -124,10 +124,11 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>>>           dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>>>             /* Read EDID data */
>>> -        retval = exynos_dp_read_bytes_from_i2c(dp,
>>> I2C_EDID_DEVICE_ADDR,
>>> -                        EDID_HEADER_PATTERN,
>>> -                        EDID_BLOCK_LENGTH,
>>> -                        &edid[EDID_HEADER_PATTERN]);
>>> +        retval = exynos_dp_read_bytes_from_i2c(
>>> +                    dp, I2C_EDID_DEVICE_ADDR,
>>> +                    EDID_HEADER_PATTERN,
>>> +                    EDID_BLOCK_LENGTH,
>>> +                    &edid[EDID_HEADER_PATTERN]);
>>>           if (retval != 0) {
>>>               dev_err(dp->dev, "EDID Read failed!\n");
>>>               return -EIO;
>>> @@ -139,11 +140,11 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>>>           }
>>>             /* Read additional EDID data */
>>> -        retval = exynos_dp_read_bytes_from_i2c(dp,
>>> -                I2C_EDID_DEVICE_ADDR,
>>> -                EDID_BLOCK_LENGTH,
>>> -                EDID_BLOCK_LENGTH,
>>> -                &edid[EDID_BLOCK_LENGTH]);
>>> +        retval = exynos_dp_read_bytes_from_i2c(
>>> +                    dp, I2C_EDID_DEVICE_ADDR,
>>> +                    EDID_BLOCK_LENGTH,
>>> +                    EDID_BLOCK_LENGTH,
>>> +                    &edid[EDID_BLOCK_LENGTH]);
>>>           if (retval != 0) {
>>>               dev_err(dp->dev, "EDID Read failed!\n");
>>>               return -EIO;
>>> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>>>           }
>>>             exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
>>> -                    &test_vector);
>>> +                          &test_vector);
>>>           if (test_vector & DP_TEST_LINK_EDID_READ) {
>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>> -                DP_TEST_EDID_CHECKSUM,
>>> +            exynos_dp_write_byte_to_dpcd(
>>> +                dp, DP_TEST_EDID_CHECKSUM,
>>>                   edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>> -                DP_TEST_RESPONSE,
>>> +            exynos_dp_write_byte_to_dpcd(
>>> +                dp, DP_TEST_RESPONSE,
>>>                   DP_TEST_EDID_CHECKSUM_WRITE);
>> To me, missing argument after opening parenthesis, looks worse. I would
>> prefer:
>>
>>             exynos_dp_write_byte_to_dpcd(dp,
>>
>> Why you moved the 'dp' argument to new line?
> 
> Hmm... Just like style tool indicate, no more warning after
> that change.
> 
> For now, I would like to follow the original style, just improved
> some obvious style problem.  :-)

What was the checkpatch warning that said 'dp' has to move to new line?
I tried this and I don't see it.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 01/16] drm: exynos/dp: fix code style
@ 2015-09-03  5:08         ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-03  5:08 UTC (permalink / raw)
  To: linux-arm-kernel

On 03.09.2015 14:04, Yakir Yang wrote:
> Hi Krzysztof,
> 
> ? 09/03/2015 08:21 AM, Krzysztof Kozlowski ??:
>> On 01.09.2015 14:46, Yakir Yang wrote:
>>> After run "checkpatch.pl -f --subjective" command, I see there
>>> are lots of alignment problem in exynos_dp driver, so let just
>>> fix them.
>> Hi,
>>
>> Warnings from checkpatch are not a reason for a commit. Reason for a
>> commit could be for example an unreadable code, violation of
>> coding-style leading to decrease in code maintainability or just
>> improving the code readability so it will be easier to review and
>> maintain it.
>>
>> You do not make commits because some tool tells you that. We do not
>> listen to machines :) ... If that would be the case, the commit could be
>> made automatically, without human interaction. Such automated commit
>> could be even easily tested by the machine by comparing object files.
>>
>> Especially that you enabled "subjective" rule. This is not a valid
>> motivation for a commit.
>>
>> Please rephrase this to sensible reason and convince that change is
>> worth the effort.
> 
> Oh, nice, thanks for your remind. I would rephrase the commit.
> 
>>> - Take Romain suggest, rebase on linux-next branch
>> That comment seems unrelated to the commit. Please remove it.
> 
> Done,
> 
>>
>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>> ---
>>> Changes in v4: None
>>> Changes in v3: None
>>> Changes in v2:
>>> - Take Joe Preches advise, improved commit message more readable, and
>>>    avoid using some uncommon style like bellow:
>>>    -  retval = exynos_dp_read_bytes_from_i2c(...
>>>                 ...)
>>>    +  retval =
>>>    +  exynos_dp_read_bytes_from_i2c(......);
>>>
>>>   drivers/gpu/drm/exynos/exynos_dp_core.c | 226
>>> ++++++++++++++++----------------
>>>   drivers/gpu/drm/exynos/exynos_dp_core.h |  54 ++++----
>>>   drivers/gpu/drm/exynos/exynos_dp_reg.c  | 106 +++++++--------
>>>   3 files changed, 188 insertions(+), 198 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>> b/drivers/gpu/drm/exynos/exynos_dp_core.c
>>> index d66ade0..266f7f7 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
>>> @@ -115,8 +115,8 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>>>         /* Read Extension Flag, Number of 128-byte EDID extension
>>> blocks */
>>>       retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>>> -                EDID_EXTENSION_FLAG,
>>> -                &extend_block);
>>> +                          EDID_EXTENSION_FLAG,
>>> +                          &extend_block);
>>>       if (retval)
>>>           return retval;
>>>   @@ -124,10 +124,11 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>>>           dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>>>             /* Read EDID data */
>>> -        retval = exynos_dp_read_bytes_from_i2c(dp,
>>> I2C_EDID_DEVICE_ADDR,
>>> -                        EDID_HEADER_PATTERN,
>>> -                        EDID_BLOCK_LENGTH,
>>> -                        &edid[EDID_HEADER_PATTERN]);
>>> +        retval = exynos_dp_read_bytes_from_i2c(
>>> +                    dp, I2C_EDID_DEVICE_ADDR,
>>> +                    EDID_HEADER_PATTERN,
>>> +                    EDID_BLOCK_LENGTH,
>>> +                    &edid[EDID_HEADER_PATTERN]);
>>>           if (retval != 0) {
>>>               dev_err(dp->dev, "EDID Read failed!\n");
>>>               return -EIO;
>>> @@ -139,11 +140,11 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>>>           }
>>>             /* Read additional EDID data */
>>> -        retval = exynos_dp_read_bytes_from_i2c(dp,
>>> -                I2C_EDID_DEVICE_ADDR,
>>> -                EDID_BLOCK_LENGTH,
>>> -                EDID_BLOCK_LENGTH,
>>> -                &edid[EDID_BLOCK_LENGTH]);
>>> +        retval = exynos_dp_read_bytes_from_i2c(
>>> +                    dp, I2C_EDID_DEVICE_ADDR,
>>> +                    EDID_BLOCK_LENGTH,
>>> +                    EDID_BLOCK_LENGTH,
>>> +                    &edid[EDID_BLOCK_LENGTH]);
>>>           if (retval != 0) {
>>>               dev_err(dp->dev, "EDID Read failed!\n");
>>>               return -EIO;
>>> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>>>           }
>>>             exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
>>> -                    &test_vector);
>>> +                          &test_vector);
>>>           if (test_vector & DP_TEST_LINK_EDID_READ) {
>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>> -                DP_TEST_EDID_CHECKSUM,
>>> +            exynos_dp_write_byte_to_dpcd(
>>> +                dp, DP_TEST_EDID_CHECKSUM,
>>>                   edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>> -                DP_TEST_RESPONSE,
>>> +            exynos_dp_write_byte_to_dpcd(
>>> +                dp, DP_TEST_RESPONSE,
>>>                   DP_TEST_EDID_CHECKSUM_WRITE);
>> To me, missing argument after opening parenthesis, looks worse. I would
>> prefer:
>>
>>             exynos_dp_write_byte_to_dpcd(dp,
>>
>> Why you moved the 'dp' argument to new line?
> 
> Hmm... Just like style tool indicate, no more warning after
> that change.
> 
> For now, I would like to follow the original style, just improved
> some obvious style problem.  :-)

What was the checkpatch warning that said 'dp' has to move to new line?
I tried this and I don't see it.

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
  2015-09-03  0:58     ` Krzysztof Kozlowski
@ 2015-09-03  5:30       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  5:30 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Krzysztof,

在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
> On 01.09.2015 14:49, Yakir Yang wrote:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code to analogix_dp-exynos.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
>> - Take Archit suggest, create a separate folder for analogix code in bridge/
>>
>> Changes in v3:
>> - Take Thierry Reding suggest, move exynos's video_timing code
>>    to analogix_dp-exynos platform driver, add get_modes method
>>    to struct analogix_dp_plat_data.
>> - Take Heiko suggest, rename some "samsung*" dts propery to "analogix*".
>>
>> Changes in v2:
>> - Take Jingoo Han suggest, remove new copyright
>> - Fix compiled failed dut to analogix_dp_device misspell
>>
>>   drivers/gpu/drm/bridge/Kconfig                     |    2 +
>>   drivers/gpu/drm/bridge/Makefile                    |    1 +
>>   drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
>>   drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
>>   .../analogix/analogix_dp_core.c}                   |  817 ++++++-------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  283 +++++
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1265 ++++++++++++++++++++
>>   .../analogix/analogix_dp_reg.h}                    |  258 ++--
>>   drivers/gpu/drm/exynos/Kconfig                     |    3 +-
>>   drivers/gpu/drm/exynos/Makefile                    |    2 +-
>>   drivers/gpu/drm/exynos/exynos_dp.c                 |  306 +++++
>>   drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 -----
>>   drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1259 -------------------
>>   include/drm/bridge/analogix_dp.h                   |   24 +
>>   14 files changed, 2357 insertions(+), 2150 deletions(-)
>>   create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
>>   create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
>>   rename drivers/gpu/drm/{exynos/exynos_dp_core.c => bridge/analogix/analogix_dp_core.c} (50%)
>>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>>   rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (64%)
>>   create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
>>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
>>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
>>   create mode 100644 include/drm/bridge/analogix_dp.h
>>
>> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
>> index 2de52a5..7b5b77a 100644
>> --- a/drivers/gpu/drm/bridge/Kconfig
>> +++ b/drivers/gpu/drm/bridge/Kconfig
>> @@ -29,4 +29,6 @@ config DRM_PARADE_PS8622
>>   	---help---
>>   	  Parade eDP-LVDS bridge chip driver.
>>   
>> +source "drivers/gpu/drm/bridge/analogix/Kconfig"
>> +
>>   endmenu
>> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
>> index e2eef1c..5366c6b 100644
>> --- a/drivers/gpu/drm/bridge/Makefile
>> +++ b/drivers/gpu/drm/bridge/Makefile
>> @@ -3,3 +3,4 @@ ccflags-y := -Iinclude/drm
>>   obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o
>>   obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
>>   obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
>> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
>> diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
>> new file mode 100644
>> index 0000000..5ff6551
>> --- /dev/null
>> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
>> @@ -0,0 +1,4 @@
>> +config DRM_ANALOGIX_DP
>> +	tristate
>> +	depends on DRM
>> +	select DRM_KMS_HELPER
>> diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
>> new file mode 100644
>> index 0000000..9107b86
>> --- /dev/null
>> +++ b/drivers/gpu/drm/bridge/analogix/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> similarity index 50%
>> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
>> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index bed0252..7d62f22 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -1,14 +1,14 @@
>>   /*
>> - * Samsung SoC DP (Display Port) interface driver.
>> - *
>> - * Copyright (C) 2012 Samsung Electronics Co., Ltd.
>> - * Author: Jingoo Han <jg1.han@samsung.com>
>> - *
>> - * This program is free software; you can redistribute it and/or modify it
>> - * under the terms of the GNU General Public License as published by the
>> - * Free Software Foundation; either version 2 of the License, or (at your
>> - * option) any later version.
>> - */
>> +* Analogix DP (Display Port) core interface driver.
>> +*
>> +* Copyright (C) 2012 Samsung Electronics Co., Ltd.
>> +* Author: Jingoo Han <jg1.han@samsung.com>
>> +*
>> +* This program is free software; you can redistribute it and/or modify it
>> +* under the terms of the GNU General Public License as published by the
>> +* Free Software Foundation; either version 2 of the License, or (at your
>> +* option) any later version.
>> +*/
>>   
>>   #include <linux/module.h>
>>   #include <linux/platform_device.h>
>> @@ -18,12 +18,9 @@
>>   #include <linux/interrupt.h>
>>   #include <linux/of.h>
>>   #include <linux/of_gpio.h>
>> -#include <linux/of_graph.h>
>>   #include <linux/gpio.h>
>>   #include <linux/component.h>
>>   #include <linux/phy/phy.h>
>> -#include <video/of_display_timing.h>
>> -#include <video/of_videomode.h>
>>   
>>   #include <drm/drmP.h>
>>   #include <drm/drm_crtc.h>
>> @@ -31,52 +28,42 @@
>>   #include <drm/drm_atomic_helper.h>
>>   #include <drm/drm_panel.h>
>>   
>> -#include "exynos_dp_core.h"
>> -#include "exynos_drm_crtc.h"
>> +#include <drm/bridge/analogix_dp.h>
>>   
>> -#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
>> -					connector)
>> +#include "analogix_dp_core.h"
>>   
>> -static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
>> -{
>> -	return to_exynos_crtc(dp->encoder.crtc);
>> -}
>> -
>> -static inline struct exynos_dp_device *encoder_to_dp(
>> -						struct drm_encoder *e)
>> -{
>> -	return container_of(e, struct exynos_dp_device, encoder);
>> -}
>> +#define connector_to_dp(c) \
>> +	container_of(c, struct analogix_dp_device, connector)
>>   
>>   struct bridge_init {
>>   	struct i2c_client *client;
>>   	struct device_node *node;
>>   };
>>   
>> -static void exynos_dp_init_dp(struct exynos_dp_device *dp)
>> +static void analogix_dp_init_dp(struct analogix_dp_device *dp)
>>   {
>> -	exynos_dp_reset(dp);
>> +	analogix_dp_reset(dp);
>>   
>> -	exynos_dp_swreset(dp);
>> +	analogix_dp_swreset(dp);
>>   
>> -	exynos_dp_init_analog_param(dp);
>> -	exynos_dp_init_interrupt(dp);
>> +	analogix_dp_init_analog_param(dp);
>> +	analogix_dp_init_interrupt(dp);
>>   
>>   	/* SW defined function Normal operation */
>> -	exynos_dp_enable_sw_function(dp);
>> +	analogix_dp_enable_sw_function(dp);
>>   
>> -	exynos_dp_config_interrupt(dp);
>> -	exynos_dp_init_analog_func(dp);
>> +	analogix_dp_config_interrupt(dp);
>> +	analogix_dp_init_analog_func(dp);
>>   
>> -	exynos_dp_init_hpd(dp);
>> -	exynos_dp_init_aux(dp);
>> +	analogix_dp_init_hpd(dp);
>> +	analogix_dp_init_aux(dp);
>>   }
>>   
>> -static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
>> +static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
>>   {
>>   	int timeout_loop = 0;
>>   
>> -	while (exynos_dp_get_plug_in_status(dp) != 0) {
>> +	while (analogix_dp_get_plug_in_status(dp) != 0) {
>>   		timeout_loop++;
>>   		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
>>   			dev_err(dp->dev, "failed to get hpd plug status\n");
>> @@ -88,7 +75,7 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
>>   	return 0;
>>   }
>>   
>> -static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
>> +static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
>>   {
>>   	int i;
>>   	unsigned char sum = 0;
>> @@ -99,7 +86,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
>>   	return sum;
>>   }
>>   
>> -static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>> +static int analogix_dp_read_edid(struct analogix_dp_device *dp)
>>   {
>>   	unsigned char edid[EDID_BLOCK_LENGTH * 2];
>>   	unsigned int extend_block = 0;
>> @@ -114,9 +101,9 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   	 */
>>   
>>   	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
>> -	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>> -					      EDID_EXTENSION_FLAG,
>> -					      &extend_block);
>> +	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>> +						EDID_EXTENSION_FLAG,
>> +						&extend_block);
> Hi,
>
> What was the point of patch 1 (checkpatch -f --subjective) if you
> have to re-align the parameters again? It's meaningless.
>
> I could understand that idea if this patch touched only first
> line - name of the function. This would result in small
> and effective diff, like:
>
> -	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> +	retval = SAME_LEGNTH____byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>   					      EDID_EXTENSION_FLAG,
>
> But this is not the case. The reviewer have to look at 6 lines
> of changes instead of two. You fixed the alignment just for two
> patches and then you re-written it. It's meaningless.

Yes, this is the place that crazy me too. After rename "exynos"
to "analogix", there would bring some "over-80-char" problem :(

> Nope. Please drop all changes from patch 1 which:
> (all conditions apply):
> 1. change alignment,
> 2. are immediately changed in next patches (e.g. like here),
>
> and fix the alignment while renaming the function.
>
> This is actually another point for not accepting commits where
> the reason is "checkpatch told me".

Okay, so there would be two patches to fix the alignment, done.

Thanks for your careful remind.

>
>
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -124,7 +111,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>>   
>>   		/* Read EDID data */
>> -		retval = exynos_dp_read_bytes_from_i2c(
>> +		retval = analogix_dp_read_bytes_from_i2c(
>>   					dp, I2C_EDID_DEVICE_ADDR,
>>   					EDID_HEADER_PATTERN,
>>   					EDID_BLOCK_LENGTH,
>> @@ -133,14 +120,14 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
> (...)
>
>> @@ -871,218 +862,204 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
>>   	return IRQ_HANDLED;
>>   }
>>   
>> -static void exynos_dp_hotplug(struct work_struct *work)
>> +static void analogix_dp_hotplug(struct work_struct *work)
>>   {
>> -	struct exynos_dp_device *dp;
>> +	struct analogix_dp_device *dp;
>>   
>> -	dp = container_of(work, struct exynos_dp_device, hotplug_work);
>> +	dp = container_of(work, struct analogix_dp_device, hotplug_work);
>>   
>>   	if (dp->drm_dev)
>>   		drm_helper_hpd_irq_event(dp->drm_dev);
>>   }
>>   
>> -static void exynos_dp_commit(struct drm_encoder *encoder)
>> +static void analogix_dp_commit(struct analogix_dp_device *dp)
>>   {
>> -	struct exynos_dp_device *dp = encoder_to_dp(encoder);
>>   	int ret;
>>   
>>   	/* Keep the panel disabled while we configure video */
>> -	if (dp->panel) {
>> -		if (drm_panel_disable(dp->panel))
>> +	if (dp->plat_data && dp->plat_data->panel) {
>> +		if (drm_panel_disable(dp->plat_data->panel))
>>   			DRM_ERROR("failed to disable the panel\n");
>>   	}
>>   
>> -	ret = exynos_dp_detect_hpd(dp);
>> +	ret = analogix_dp_detect_hpd(dp);
>>   	if (ret) {
>>   		/* Cable has been disconnected, we're done */
>>   		return;
>>   	}
>>   
>> -	ret = exynos_dp_handle_edid(dp);
>> +	ret = analogix_dp_handle_edid(dp);
>>   	if (ret) {
>>   		dev_err(dp->dev, "unable to handle edid\n");
>>   		return;
>>   	}
>>   
>> -	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
>> -				       dp->video_info->link_rate);
>> +	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
>> +					 dp->video_info->link_rate);
>>   	if (ret) {
>>   		dev_err(dp->dev, "unable to do link train\n");
>>   		return;
>>   	}
>>   
>> -	exynos_dp_enable_scramble(dp, 1);
>> -	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
>> -	exynos_dp_enable_enhanced_mode(dp, 1);
>> +	analogix_dp_enable_scramble(dp, 1);
>> +	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
>> +	analogix_dp_enable_enhanced_mode(dp, 1);
>>   
>> -	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
>> -	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
>> +	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
>> +	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
>>   
>> -	exynos_dp_init_video(dp);
>> -	ret = exynos_dp_config_video(dp);
>> +	analogix_dp_init_video(dp);
>> +	ret = analogix_dp_config_video(dp);
>>   	if (ret)
>>   		dev_err(dp->dev, "unable to config video\n");
>>   
>>   	/* Safe to enable the panel now */
>> -	if (dp->panel) {
>> -		if (drm_panel_enable(dp->panel))
>> +	if (dp->plat_data && dp->plat_data->panel) {
>> +		if (drm_panel_enable(dp->plat_data->panel))
>>   			DRM_ERROR("failed to enable the panel\n");
>>   	}
>>   
>>   	/* Enable video */
>> -	exynos_dp_start_video(dp);
>> +	analogix_dp_start_video(dp);
>>   }
>>   
>>   static enum drm_connector_status
>> -exynos_dp_detect(struct drm_connector *connector, bool force)
>> +analogix_dp_detect(struct drm_connector *connector, bool force)
>>   {
>>   	return connector_status_connected;
>>   }
>>   
>> -static void exynos_dp_connector_destroy(struct drm_connector *connector)
>> +static void analogix_dp_connector_destroy(struct drm_connector *connector)
>>   {
>>   	drm_connector_unregister(connector);
>>   	drm_connector_cleanup(connector);
>>   }
>>   
>> -static struct drm_connector_funcs exynos_dp_connector_funcs = {
>> +static struct drm_connector_funcs analogix_dp_connector_funcs = {
>>   	.dpms = drm_atomic_helper_connector_dpms,
>>   	.fill_modes = drm_helper_probe_single_connector_modes,
>> -	.detect = exynos_dp_detect,
>> -	.destroy = exynos_dp_connector_destroy,
>> +	.detect = analogix_dp_detect,
>> +	.destroy = analogix_dp_connector_destroy,
>>   	.reset = drm_atomic_helper_connector_reset,
>>   	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
>>   	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>>   };
>>   
>> -static int exynos_dp_get_modes(struct drm_connector *connector)
>> +static int analogix_dp_get_modes(struct drm_connector *connector)
>>   {
>> -	struct exynos_dp_device *dp = ctx_from_connector(connector);
>> -	struct drm_display_mode *mode;
>> -
>> -	if (dp->panel)
>> -		return drm_panel_get_modes(dp->panel);
>> +	struct analogix_dp_device *dp = connector_to_dp(connector);
>> +	struct analogix_dp_plat_data *plat_data = dp->plat_data;
>> +	int num_modes = 0;
>>   
>> -	mode = drm_mode_create(connector->dev);
>> -	if (!mode) {
>> -		DRM_ERROR("failed to create a new display mode.\n");
>> -		return 0;
>> -	}
>> -
>> -	drm_display_mode_from_videomode(&dp->priv.vm, mode);
>> -	mode->width_mm = dp->priv.width_mm;
>> -	mode->height_mm = dp->priv.height_mm;
>> -	connector->display_info.width_mm = mode->width_mm;
>> -	connector->display_info.height_mm = mode->height_mm;
>> +	if (plat_data && plat_data->panel)
>> +		num_modes += drm_panel_get_modes(plat_data->panel);
>>   
>> -	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
>> -	drm_mode_set_name(mode);
>> -	drm_mode_probed_add(connector, mode);
>> +	if (plat_data && plat_data->get_modes)
>> +		 num_modes += plat_data->get_modes(plat_data, connector);
>>   
>> -	return 1;
>> +	return num_modes;
>>   }
>>   
>>   static struct drm_encoder *
>> -exynos_dp_best_encoder(struct drm_connector *connector)
>> +analogix_dp_best_encoder(struct drm_connector *connector)
>>   {
>> -	struct exynos_dp_device *dp = ctx_from_connector(connector);
>> +	struct analogix_dp_device *dp = connector_to_dp(connector);
>>   
>> -	return &dp->encoder;
>> +	return dp->encoder;
>>   }
>>   
>> -static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
>> -	.get_modes = exynos_dp_get_modes,
>> -	.best_encoder = exynos_dp_best_encoder,
>> +static struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
>> +	.get_modes = analogix_dp_get_modes,
>> +	.best_encoder = analogix_dp_best_encoder,
>>   };
>>   
>> -/* returns the number of bridges attached */
>> -static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
>> -					struct drm_encoder *encoder)
>> -{
>> -	int ret;
>> -
>> -	encoder->bridge->next = dp->ptn_bridge;
>> -	dp->ptn_bridge->encoder = encoder;
>> -	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
>> -	if (ret) {
>> -		DRM_ERROR("Failed to attach bridge to drm\n");
>> -		return ret;
>> -	}
>> -
>> -	return 0;
>> -}
>> -
>> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
>> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>>   {
>> -	struct exynos_dp_device *dp = bridge->driver_private;
>> -	struct drm_encoder *encoder = &dp->encoder;
>> +	struct analogix_dp_device *dp = bridge->driver_private;
>> +	struct drm_encoder *encoder = dp->encoder;
>>   	struct drm_connector *connector = &dp->connector;
>>   	int ret;
>>   
>> -	/* Pre-empt DP connector creation if there's a bridge */
>> -	if (dp->ptn_bridge) {
>> -		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
>> -		if (!ret)
>> -			return 0;
>> +	if (!bridge->encoder) {
>> +		DRM_ERROR("Parent encoder object not found");
>> +		return -ENODEV;
>>   	}
>>   
>> +	encoder->bridge = bridge;
>> +
>>   	connector->polled = DRM_CONNECTOR_POLL_HPD;
>>   
>>   	ret = drm_connector_init(dp->drm_dev, connector,
>> -				 &exynos_dp_connector_funcs,
>> +				 &analogix_dp_connector_funcs,
>>   				 DRM_MODE_CONNECTOR_eDP);
>>   	if (ret) {
>>   		DRM_ERROR("Failed to initialize connector with drm\n");
>>   		return ret;
>>   	}
>>   
>> -	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
>> +	drm_connector_helper_add(connector,
>> +				 &analogix_dp_connector_helper_funcs);
>>   	drm_connector_register(connector);
>>   	drm_mode_connector_attach_encoder(connector, encoder);
>>   
>> -	if (dp->panel)
>> -		ret = drm_panel_attach(dp->panel, &dp->connector);
>> +	if (dp->plat_data && dp->plat_data->panel) {
>> +		ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>> +		if (ret) {
>> +			DRM_ERROR("Failed to attach panel\n");
>> +			return ret;
>> +		}
>> +	}
>> +
>> +	/*
>> +	 * This should be the end of attach function, caused
>> +	 * we should ensure dp bridge could attach first.
>> +	 */
>> +	 if (dp->plat_data && dp->plat_data->attach) {
>> +		 ret = dp->plat_data->attach(dp->plat_data, bridge);
>> +		 if (ret) {
>> +			 DRM_ERROR("Failed at platform attch func\n");
> Two new error paths appeared here and above. Don't you have to
> cleanup something? I don't know, just wondering...

Hmm... I think both panel & platform_attch need ERROR remind when
it failed. But if it still need clean, I though it is tge platform attch 
error,
this is not relate to DRM directly, just analogix driver logic, so code 
would
like.

-	if (dp->panel)
-		ret = drm_panel_attach(dp->panel, &dp->connector);
+	if (dp->plat_data && dp->plat_data->panel) {
+		ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
+		if (ret) {
+			DRM_ERROR("Failed to attach panel\n");
+			return ret;
+		}
+	}

+	/*
+	 * This should be the end of attach function, caused
+	 * we should ensure dp bridge could attach first.
+	 */
+	 if (dp->plat_data && dp->plat_data->attach) {
+		 ret = dp->plat_data->attach(dp->plat_data, bridge);

           return ret;
> (...)
>
>> @@ -1345,22 +1286,9 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>>   	disable_irq(dp->irq);
>>   
>>   	dp->drm_dev = drm_dev;
>> +	dp->encoder = encoder;
>>   
>> -	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
>> -						  EXYNOS_DISPLAY_TYPE_LCD);
>> -	if (pipe < 0)
>> -		return pipe;
>> -
>> -	encoder->possible_crtcs = 1 << pipe;
>> -
>> -	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
>> -
>> -	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
>> -			 DRM_MODE_ENCODER_TMDS);
>> -
>> -	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
>> -
>> -	ret = exynos_dp_create_connector(encoder);
>> +	ret = analogix_dp_create_bridge(drm_dev, dp);
>>   	if (ret) {
>>   		DRM_ERROR("failed to create connector ret = %d\n", ret);
>>   		drm_encoder_cleanup(encoder);
>> @@ -1369,103 +1297,36 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>>   
>>   	return 0;
>>   }
>> +EXPORT_SYMBOL_GPL(analogix_dp_bind);
> Ooo, a new export symbol. I suppose it is necessary for the split
> but the commit message does not mention exporting
> anything nor the reason for doing it. Could you extend the commit
> message describing more tha changes here and rationale for it?

Okay, got it.

> (...)
>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> new file mode 100644
>> index 0000000..b879d8c
>> --- /dev/null
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> @@ -0,0 +1,1265 @@
>> +/*
>> + * Analogix DP (Display port) core register interface driver.
>> + *
>> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
>> + * Author: Jingoo Han <jg1.han@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License as published by the
>> + * Free Software Foundation; either version 2 of the License, or (at your
>> + * option) any later version.
>> + */
>> +
>> +#include <linux/device.h>
>> +#include <linux/io.h>
>> +#include <linux/delay.h>
>> +#include <linux/gpio.h>
>> +
>> +#include "analogix_dp_core.h"
>> +#include "analogix_dp_reg.h"
>> +
>> +#define COMMON_INT_MASK_1	0
>> +#define COMMON_INT_MASK_2	0
>> +#define COMMON_INT_MASK_3	0
>> +#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
>> +#define INT_STA_MASK		INT_HPD
>> +
>> +void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
>> +{
>> +	u32 reg;
>> +
>> +	if (enable) {
>> +		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
>> +		reg |= HDCP_VIDEO_MUTE;
>> +		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
>> +	} else {
>> +		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
>> +		reg &= ~HDCP_VIDEO_MUTE;
>> +		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
>> +	}
>> +}
>> +
>> +void analogix_dp_stop_video(struct analogix_dp_device *dp)
>> +{
>> +	u32 reg;
>> +
>> +	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
>> +	reg &= ~VIDEO_EN;
>> +	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
>> +}
>> +
>> +void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
>> +{
>> +	u32 reg;
>> +
>> +	if (enable)
>> +		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
>> +			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
>> +	else
>> +		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
>> +			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
> Here and in few other places with new code: no alignment?
>
> You spent some time fixing these in patch 1, so I would assume
> that new code already comes after "checkpatch -f --subjective".
> That's actually the only valid reason for using checkpatch - new code.
> However my mail reader could corrupt the output so maybe this is aligned?

This is another mistaken I make, and surprise by that checkpatch
fine with this no-alignment style. Anyway I would just do rename
change in this split patch, and move the style change to another
separate patch (maybe I should adjust the order, correct style
problem after this patch).


> Code seems fine after looking at it but review was rather shallow.
> I don't know the Exynos DP driver.

I really appreciate for your careful review  ;)

- Yakir
> Best regards,
> Krzysztof
>
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-03  5:30       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  5:30 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Krzysztof,

? 09/03/2015 08:58 AM, Krzysztof Kozlowski ??:
> On 01.09.2015 14:49, Yakir Yang wrote:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code to analogix_dp-exynos.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT propery.
>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to "exynos_dp.c"
>> - Take Archit suggest, create a separate folder for analogix code in bridge/
>>
>> Changes in v3:
>> - Take Thierry Reding suggest, move exynos's video_timing code
>>    to analogix_dp-exynos platform driver, add get_modes method
>>    to struct analogix_dp_plat_data.
>> - Take Heiko suggest, rename some "samsung*" dts propery to "analogix*".
>>
>> Changes in v2:
>> - Take Jingoo Han suggest, remove new copyright
>> - Fix compiled failed dut to analogix_dp_device misspell
>>
>>   drivers/gpu/drm/bridge/Kconfig                     |    2 +
>>   drivers/gpu/drm/bridge/Makefile                    |    1 +
>>   drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
>>   drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
>>   .../analogix/analogix_dp_core.c}                   |  817 ++++++-------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  283 +++++
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1265 ++++++++++++++++++++
>>   .../analogix/analogix_dp_reg.h}                    |  258 ++--
>>   drivers/gpu/drm/exynos/Kconfig                     |    3 +-
>>   drivers/gpu/drm/exynos/Makefile                    |    2 +-
>>   drivers/gpu/drm/exynos/exynos_dp.c                 |  306 +++++
>>   drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 -----
>>   drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1259 -------------------
>>   include/drm/bridge/analogix_dp.h                   |   24 +
>>   14 files changed, 2357 insertions(+), 2150 deletions(-)
>>   create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
>>   create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
>>   rename drivers/gpu/drm/{exynos/exynos_dp_core.c => bridge/analogix/analogix_dp_core.c} (50%)
>>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>>   rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (64%)
>>   create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
>>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
>>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
>>   create mode 100644 include/drm/bridge/analogix_dp.h
>>
>> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
>> index 2de52a5..7b5b77a 100644
>> --- a/drivers/gpu/drm/bridge/Kconfig
>> +++ b/drivers/gpu/drm/bridge/Kconfig
>> @@ -29,4 +29,6 @@ config DRM_PARADE_PS8622
>>   	---help---
>>   	  Parade eDP-LVDS bridge chip driver.
>>   
>> +source "drivers/gpu/drm/bridge/analogix/Kconfig"
>> +
>>   endmenu
>> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
>> index e2eef1c..5366c6b 100644
>> --- a/drivers/gpu/drm/bridge/Makefile
>> +++ b/drivers/gpu/drm/bridge/Makefile
>> @@ -3,3 +3,4 @@ ccflags-y := -Iinclude/drm
>>   obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o
>>   obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
>>   obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
>> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
>> diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
>> new file mode 100644
>> index 0000000..5ff6551
>> --- /dev/null
>> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
>> @@ -0,0 +1,4 @@
>> +config DRM_ANALOGIX_DP
>> +	tristate
>> +	depends on DRM
>> +	select DRM_KMS_HELPER
>> diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
>> new file mode 100644
>> index 0000000..9107b86
>> --- /dev/null
>> +++ b/drivers/gpu/drm/bridge/analogix/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> similarity index 50%
>> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
>> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index bed0252..7d62f22 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -1,14 +1,14 @@
>>   /*
>> - * Samsung SoC DP (Display Port) interface driver.
>> - *
>> - * Copyright (C) 2012 Samsung Electronics Co., Ltd.
>> - * Author: Jingoo Han <jg1.han@samsung.com>
>> - *
>> - * This program is free software; you can redistribute it and/or modify it
>> - * under the terms of the GNU General Public License as published by the
>> - * Free Software Foundation; either version 2 of the License, or (at your
>> - * option) any later version.
>> - */
>> +* Analogix DP (Display Port) core interface driver.
>> +*
>> +* Copyright (C) 2012 Samsung Electronics Co., Ltd.
>> +* Author: Jingoo Han <jg1.han@samsung.com>
>> +*
>> +* This program is free software; you can redistribute it and/or modify it
>> +* under the terms of the GNU General Public License as published by the
>> +* Free Software Foundation; either version 2 of the License, or (at your
>> +* option) any later version.
>> +*/
>>   
>>   #include <linux/module.h>
>>   #include <linux/platform_device.h>
>> @@ -18,12 +18,9 @@
>>   #include <linux/interrupt.h>
>>   #include <linux/of.h>
>>   #include <linux/of_gpio.h>
>> -#include <linux/of_graph.h>
>>   #include <linux/gpio.h>
>>   #include <linux/component.h>
>>   #include <linux/phy/phy.h>
>> -#include <video/of_display_timing.h>
>> -#include <video/of_videomode.h>
>>   
>>   #include <drm/drmP.h>
>>   #include <drm/drm_crtc.h>
>> @@ -31,52 +28,42 @@
>>   #include <drm/drm_atomic_helper.h>
>>   #include <drm/drm_panel.h>
>>   
>> -#include "exynos_dp_core.h"
>> -#include "exynos_drm_crtc.h"
>> +#include <drm/bridge/analogix_dp.h>
>>   
>> -#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
>> -					connector)
>> +#include "analogix_dp_core.h"
>>   
>> -static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
>> -{
>> -	return to_exynos_crtc(dp->encoder.crtc);
>> -}
>> -
>> -static inline struct exynos_dp_device *encoder_to_dp(
>> -						struct drm_encoder *e)
>> -{
>> -	return container_of(e, struct exynos_dp_device, encoder);
>> -}
>> +#define connector_to_dp(c) \
>> +	container_of(c, struct analogix_dp_device, connector)
>>   
>>   struct bridge_init {
>>   	struct i2c_client *client;
>>   	struct device_node *node;
>>   };
>>   
>> -static void exynos_dp_init_dp(struct exynos_dp_device *dp)
>> +static void analogix_dp_init_dp(struct analogix_dp_device *dp)
>>   {
>> -	exynos_dp_reset(dp);
>> +	analogix_dp_reset(dp);
>>   
>> -	exynos_dp_swreset(dp);
>> +	analogix_dp_swreset(dp);
>>   
>> -	exynos_dp_init_analog_param(dp);
>> -	exynos_dp_init_interrupt(dp);
>> +	analogix_dp_init_analog_param(dp);
>> +	analogix_dp_init_interrupt(dp);
>>   
>>   	/* SW defined function Normal operation */
>> -	exynos_dp_enable_sw_function(dp);
>> +	analogix_dp_enable_sw_function(dp);
>>   
>> -	exynos_dp_config_interrupt(dp);
>> -	exynos_dp_init_analog_func(dp);
>> +	analogix_dp_config_interrupt(dp);
>> +	analogix_dp_init_analog_func(dp);
>>   
>> -	exynos_dp_init_hpd(dp);
>> -	exynos_dp_init_aux(dp);
>> +	analogix_dp_init_hpd(dp);
>> +	analogix_dp_init_aux(dp);
>>   }
>>   
>> -static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
>> +static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
>>   {
>>   	int timeout_loop = 0;
>>   
>> -	while (exynos_dp_get_plug_in_status(dp) != 0) {
>> +	while (analogix_dp_get_plug_in_status(dp) != 0) {
>>   		timeout_loop++;
>>   		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
>>   			dev_err(dp->dev, "failed to get hpd plug status\n");
>> @@ -88,7 +75,7 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
>>   	return 0;
>>   }
>>   
>> -static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
>> +static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
>>   {
>>   	int i;
>>   	unsigned char sum = 0;
>> @@ -99,7 +86,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
>>   	return sum;
>>   }
>>   
>> -static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>> +static int analogix_dp_read_edid(struct analogix_dp_device *dp)
>>   {
>>   	unsigned char edid[EDID_BLOCK_LENGTH * 2];
>>   	unsigned int extend_block = 0;
>> @@ -114,9 +101,9 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   	 */
>>   
>>   	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
>> -	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>> -					      EDID_EXTENSION_FLAG,
>> -					      &extend_block);
>> +	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>> +						EDID_EXTENSION_FLAG,
>> +						&extend_block);
> Hi,
>
> What was the point of patch 1 (checkpatch -f --subjective) if you
> have to re-align the parameters again? It's meaningless.
>
> I could understand that idea if this patch touched only first
> line - name of the function. This would result in small
> and effective diff, like:
>
> -	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> +	retval = SAME_LEGNTH____byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>   					      EDID_EXTENSION_FLAG,
>
> But this is not the case. The reviewer have to look at 6 lines
> of changes instead of two. You fixed the alignment just for two
> patches and then you re-written it. It's meaningless.

Yes, this is the place that crazy me too. After rename "exynos"
to "analogix", there would bring some "over-80-char" problem :(

> Nope. Please drop all changes from patch 1 which:
> (all conditions apply):
> 1. change alignment,
> 2. are immediately changed in next patches (e.g. like here),
>
> and fix the alignment while renaming the function.
>
> This is actually another point for not accepting commits where
> the reason is "checkpatch told me".

Okay, so there would be two patches to fix the alignment, done.

Thanks for your careful remind.

>
>
>>   	if (retval)
>>   		return retval;
>>   
>> @@ -124,7 +111,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>   		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>>   
>>   		/* Read EDID data */
>> -		retval = exynos_dp_read_bytes_from_i2c(
>> +		retval = analogix_dp_read_bytes_from_i2c(
>>   					dp, I2C_EDID_DEVICE_ADDR,
>>   					EDID_HEADER_PATTERN,
>>   					EDID_BLOCK_LENGTH,
>> @@ -133,14 +120,14 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
> (...)
>
>> @@ -871,218 +862,204 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
>>   	return IRQ_HANDLED;
>>   }
>>   
>> -static void exynos_dp_hotplug(struct work_struct *work)
>> +static void analogix_dp_hotplug(struct work_struct *work)
>>   {
>> -	struct exynos_dp_device *dp;
>> +	struct analogix_dp_device *dp;
>>   
>> -	dp = container_of(work, struct exynos_dp_device, hotplug_work);
>> +	dp = container_of(work, struct analogix_dp_device, hotplug_work);
>>   
>>   	if (dp->drm_dev)
>>   		drm_helper_hpd_irq_event(dp->drm_dev);
>>   }
>>   
>> -static void exynos_dp_commit(struct drm_encoder *encoder)
>> +static void analogix_dp_commit(struct analogix_dp_device *dp)
>>   {
>> -	struct exynos_dp_device *dp = encoder_to_dp(encoder);
>>   	int ret;
>>   
>>   	/* Keep the panel disabled while we configure video */
>> -	if (dp->panel) {
>> -		if (drm_panel_disable(dp->panel))
>> +	if (dp->plat_data && dp->plat_data->panel) {
>> +		if (drm_panel_disable(dp->plat_data->panel))
>>   			DRM_ERROR("failed to disable the panel\n");
>>   	}
>>   
>> -	ret = exynos_dp_detect_hpd(dp);
>> +	ret = analogix_dp_detect_hpd(dp);
>>   	if (ret) {
>>   		/* Cable has been disconnected, we're done */
>>   		return;
>>   	}
>>   
>> -	ret = exynos_dp_handle_edid(dp);
>> +	ret = analogix_dp_handle_edid(dp);
>>   	if (ret) {
>>   		dev_err(dp->dev, "unable to handle edid\n");
>>   		return;
>>   	}
>>   
>> -	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
>> -				       dp->video_info->link_rate);
>> +	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
>> +					 dp->video_info->link_rate);
>>   	if (ret) {
>>   		dev_err(dp->dev, "unable to do link train\n");
>>   		return;
>>   	}
>>   
>> -	exynos_dp_enable_scramble(dp, 1);
>> -	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
>> -	exynos_dp_enable_enhanced_mode(dp, 1);
>> +	analogix_dp_enable_scramble(dp, 1);
>> +	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
>> +	analogix_dp_enable_enhanced_mode(dp, 1);
>>   
>> -	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
>> -	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
>> +	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
>> +	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
>>   
>> -	exynos_dp_init_video(dp);
>> -	ret = exynos_dp_config_video(dp);
>> +	analogix_dp_init_video(dp);
>> +	ret = analogix_dp_config_video(dp);
>>   	if (ret)
>>   		dev_err(dp->dev, "unable to config video\n");
>>   
>>   	/* Safe to enable the panel now */
>> -	if (dp->panel) {
>> -		if (drm_panel_enable(dp->panel))
>> +	if (dp->plat_data && dp->plat_data->panel) {
>> +		if (drm_panel_enable(dp->plat_data->panel))
>>   			DRM_ERROR("failed to enable the panel\n");
>>   	}
>>   
>>   	/* Enable video */
>> -	exynos_dp_start_video(dp);
>> +	analogix_dp_start_video(dp);
>>   }
>>   
>>   static enum drm_connector_status
>> -exynos_dp_detect(struct drm_connector *connector, bool force)
>> +analogix_dp_detect(struct drm_connector *connector, bool force)
>>   {
>>   	return connector_status_connected;
>>   }
>>   
>> -static void exynos_dp_connector_destroy(struct drm_connector *connector)
>> +static void analogix_dp_connector_destroy(struct drm_connector *connector)
>>   {
>>   	drm_connector_unregister(connector);
>>   	drm_connector_cleanup(connector);
>>   }
>>   
>> -static struct drm_connector_funcs exynos_dp_connector_funcs = {
>> +static struct drm_connector_funcs analogix_dp_connector_funcs = {
>>   	.dpms = drm_atomic_helper_connector_dpms,
>>   	.fill_modes = drm_helper_probe_single_connector_modes,
>> -	.detect = exynos_dp_detect,
>> -	.destroy = exynos_dp_connector_destroy,
>> +	.detect = analogix_dp_detect,
>> +	.destroy = analogix_dp_connector_destroy,
>>   	.reset = drm_atomic_helper_connector_reset,
>>   	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
>>   	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>>   };
>>   
>> -static int exynos_dp_get_modes(struct drm_connector *connector)
>> +static int analogix_dp_get_modes(struct drm_connector *connector)
>>   {
>> -	struct exynos_dp_device *dp = ctx_from_connector(connector);
>> -	struct drm_display_mode *mode;
>> -
>> -	if (dp->panel)
>> -		return drm_panel_get_modes(dp->panel);
>> +	struct analogix_dp_device *dp = connector_to_dp(connector);
>> +	struct analogix_dp_plat_data *plat_data = dp->plat_data;
>> +	int num_modes = 0;
>>   
>> -	mode = drm_mode_create(connector->dev);
>> -	if (!mode) {
>> -		DRM_ERROR("failed to create a new display mode.\n");
>> -		return 0;
>> -	}
>> -
>> -	drm_display_mode_from_videomode(&dp->priv.vm, mode);
>> -	mode->width_mm = dp->priv.width_mm;
>> -	mode->height_mm = dp->priv.height_mm;
>> -	connector->display_info.width_mm = mode->width_mm;
>> -	connector->display_info.height_mm = mode->height_mm;
>> +	if (plat_data && plat_data->panel)
>> +		num_modes += drm_panel_get_modes(plat_data->panel);
>>   
>> -	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
>> -	drm_mode_set_name(mode);
>> -	drm_mode_probed_add(connector, mode);
>> +	if (plat_data && plat_data->get_modes)
>> +		 num_modes += plat_data->get_modes(plat_data, connector);
>>   
>> -	return 1;
>> +	return num_modes;
>>   }
>>   
>>   static struct drm_encoder *
>> -exynos_dp_best_encoder(struct drm_connector *connector)
>> +analogix_dp_best_encoder(struct drm_connector *connector)
>>   {
>> -	struct exynos_dp_device *dp = ctx_from_connector(connector);
>> +	struct analogix_dp_device *dp = connector_to_dp(connector);
>>   
>> -	return &dp->encoder;
>> +	return dp->encoder;
>>   }
>>   
>> -static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
>> -	.get_modes = exynos_dp_get_modes,
>> -	.best_encoder = exynos_dp_best_encoder,
>> +static struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
>> +	.get_modes = analogix_dp_get_modes,
>> +	.best_encoder = analogix_dp_best_encoder,
>>   };
>>   
>> -/* returns the number of bridges attached */
>> -static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
>> -					struct drm_encoder *encoder)
>> -{
>> -	int ret;
>> -
>> -	encoder->bridge->next = dp->ptn_bridge;
>> -	dp->ptn_bridge->encoder = encoder;
>> -	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
>> -	if (ret) {
>> -		DRM_ERROR("Failed to attach bridge to drm\n");
>> -		return ret;
>> -	}
>> -
>> -	return 0;
>> -}
>> -
>> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
>> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>>   {
>> -	struct exynos_dp_device *dp = bridge->driver_private;
>> -	struct drm_encoder *encoder = &dp->encoder;
>> +	struct analogix_dp_device *dp = bridge->driver_private;
>> +	struct drm_encoder *encoder = dp->encoder;
>>   	struct drm_connector *connector = &dp->connector;
>>   	int ret;
>>   
>> -	/* Pre-empt DP connector creation if there's a bridge */
>> -	if (dp->ptn_bridge) {
>> -		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
>> -		if (!ret)
>> -			return 0;
>> +	if (!bridge->encoder) {
>> +		DRM_ERROR("Parent encoder object not found");
>> +		return -ENODEV;
>>   	}
>>   
>> +	encoder->bridge = bridge;
>> +
>>   	connector->polled = DRM_CONNECTOR_POLL_HPD;
>>   
>>   	ret = drm_connector_init(dp->drm_dev, connector,
>> -				 &exynos_dp_connector_funcs,
>> +				 &analogix_dp_connector_funcs,
>>   				 DRM_MODE_CONNECTOR_eDP);
>>   	if (ret) {
>>   		DRM_ERROR("Failed to initialize connector with drm\n");
>>   		return ret;
>>   	}
>>   
>> -	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
>> +	drm_connector_helper_add(connector,
>> +				 &analogix_dp_connector_helper_funcs);
>>   	drm_connector_register(connector);
>>   	drm_mode_connector_attach_encoder(connector, encoder);
>>   
>> -	if (dp->panel)
>> -		ret = drm_panel_attach(dp->panel, &dp->connector);
>> +	if (dp->plat_data && dp->plat_data->panel) {
>> +		ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>> +		if (ret) {
>> +			DRM_ERROR("Failed to attach panel\n");
>> +			return ret;
>> +		}
>> +	}
>> +
>> +	/*
>> +	 * This should be the end of attach function, caused
>> +	 * we should ensure dp bridge could attach first.
>> +	 */
>> +	 if (dp->plat_data && dp->plat_data->attach) {
>> +		 ret = dp->plat_data->attach(dp->plat_data, bridge);
>> +		 if (ret) {
>> +			 DRM_ERROR("Failed at platform attch func\n");
> Two new error paths appeared here and above. Don't you have to
> cleanup something? I don't know, just wondering...

Hmm... I think both panel & platform_attch need ERROR remind when
it failed. But if it still need clean, I though it is tge platform attch 
error,
this is not relate to DRM directly, just analogix driver logic, so code 
would
like.

-	if (dp->panel)
-		ret = drm_panel_attach(dp->panel, &dp->connector);
+	if (dp->plat_data && dp->plat_data->panel) {
+		ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
+		if (ret) {
+			DRM_ERROR("Failed to attach panel\n");
+			return ret;
+		}
+	}

+	/*
+	 * This should be the end of attach function, caused
+	 * we should ensure dp bridge could attach first.
+	 */
+	 if (dp->plat_data && dp->plat_data->attach) {
+		 ret = dp->plat_data->attach(dp->plat_data, bridge);

           return ret;
> (...)
>
>> @@ -1345,22 +1286,9 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>>   	disable_irq(dp->irq);
>>   
>>   	dp->drm_dev = drm_dev;
>> +	dp->encoder = encoder;
>>   
>> -	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
>> -						  EXYNOS_DISPLAY_TYPE_LCD);
>> -	if (pipe < 0)
>> -		return pipe;
>> -
>> -	encoder->possible_crtcs = 1 << pipe;
>> -
>> -	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
>> -
>> -	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
>> -			 DRM_MODE_ENCODER_TMDS);
>> -
>> -	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
>> -
>> -	ret = exynos_dp_create_connector(encoder);
>> +	ret = analogix_dp_create_bridge(drm_dev, dp);
>>   	if (ret) {
>>   		DRM_ERROR("failed to create connector ret = %d\n", ret);
>>   		drm_encoder_cleanup(encoder);
>> @@ -1369,103 +1297,36 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>>   
>>   	return 0;
>>   }
>> +EXPORT_SYMBOL_GPL(analogix_dp_bind);
> Ooo, a new export symbol. I suppose it is necessary for the split
> but the commit message does not mention exporting
> anything nor the reason for doing it. Could you extend the commit
> message describing more tha changes here and rationale for it?

Okay, got it.

> (...)
>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> new file mode 100644
>> index 0000000..b879d8c
>> --- /dev/null
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> @@ -0,0 +1,1265 @@
>> +/*
>> + * Analogix DP (Display port) core register interface driver.
>> + *
>> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
>> + * Author: Jingoo Han <jg1.han@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License as published by the
>> + * Free Software Foundation; either version 2 of the License, or (at your
>> + * option) any later version.
>> + */
>> +
>> +#include <linux/device.h>
>> +#include <linux/io.h>
>> +#include <linux/delay.h>
>> +#include <linux/gpio.h>
>> +
>> +#include "analogix_dp_core.h"
>> +#include "analogix_dp_reg.h"
>> +
>> +#define COMMON_INT_MASK_1	0
>> +#define COMMON_INT_MASK_2	0
>> +#define COMMON_INT_MASK_3	0
>> +#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
>> +#define INT_STA_MASK		INT_HPD
>> +
>> +void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
>> +{
>> +	u32 reg;
>> +
>> +	if (enable) {
>> +		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
>> +		reg |= HDCP_VIDEO_MUTE;
>> +		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
>> +	} else {
>> +		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
>> +		reg &= ~HDCP_VIDEO_MUTE;
>> +		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
>> +	}
>> +}
>> +
>> +void analogix_dp_stop_video(struct analogix_dp_device *dp)
>> +{
>> +	u32 reg;
>> +
>> +	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
>> +	reg &= ~VIDEO_EN;
>> +	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
>> +}
>> +
>> +void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
>> +{
>> +	u32 reg;
>> +
>> +	if (enable)
>> +		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
>> +			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
>> +	else
>> +		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
>> +			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
> Here and in few other places with new code: no alignment?
>
> You spent some time fixing these in patch 1, so I would assume
> that new code already comes after "checkpatch -f --subjective".
> That's actually the only valid reason for using checkpatch - new code.
> However my mail reader could corrupt the output so maybe this is aligned?

This is another mistaken I make, and surprise by that checkpatch
fine with this no-alignment style. Anyway I would just do rename
change in this split patch, and move the style change to another
separate patch (maybe I should adjust the order, correct style
problem after this patch).


> Code seems fine after looking at it but review was rather shallow.
> I don't know the Exynos DP driver.

I really appreciate for your careful review  ;)

- Yakir
> Best regards,
> Krzysztof
>
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 01/16] drm: exynos/dp: fix code style
  2015-09-03  5:08         ` Krzysztof Kozlowski
@ 2015-09-03  5:33           ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  5:33 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Krzysztof,

在 09/03/2015 01:08 PM, Krzysztof Kozlowski 写道:
> On 03.09.2015 14:04, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> 在 09/03/2015 08:21 AM, Krzysztof Kozlowski 写道:
>>> On 01.09.2015 14:46, Yakir Yang wrote:
>>>> After run "checkpatch.pl -f --subjective" command, I see there
>>>> are lots of alignment problem in exynos_dp driver, so let just
>>>> fix them.
>>> Hi,
>>>
>>> Warnings from checkpatch are not a reason for a commit. Reason for a
>>> commit could be for example an unreadable code, violation of
>>> coding-style leading to decrease in code maintainability or just
>>> improving the code readability so it will be easier to review and
>>> maintain it.
>>>
>>> You do not make commits because some tool tells you that. We do not
>>> listen to machines :) ... If that would be the case, the commit could be
>>> made automatically, without human interaction. Such automated commit
>>> could be even easily tested by the machine by comparing object files.
>>>
>>> Especially that you enabled "subjective" rule. This is not a valid
>>> motivation for a commit.
>>>
>>> Please rephrase this to sensible reason and convince that change is
>>> worth the effort.
>> Oh, nice, thanks for your remind. I would rephrase the commit.
>>
>>>> - Take Romain suggest, rebase on linux-next branch
>>> That comment seems unrelated to the commit. Please remove it.
>> Done,
>>
>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>> ---
>>>> Changes in v4: None
>>>> Changes in v3: None
>>>> Changes in v2:
>>>> - Take Joe Preches advise, improved commit message more readable, and
>>>>     avoid using some uncommon style like bellow:
>>>>     -  retval = exynos_dp_read_bytes_from_i2c(...
>>>>                  ...)
>>>>     +  retval =
>>>>     +  exynos_dp_read_bytes_from_i2c(......);
>>>>
>>>>    drivers/gpu/drm/exynos/exynos_dp_core.c | 226
>>>> ++++++++++++++++----------------
>>>>    drivers/gpu/drm/exynos/exynos_dp_core.h |  54 ++++----
>>>>    drivers/gpu/drm/exynos/exynos_dp_reg.c  | 106 +++++++--------
>>>>    3 files changed, 188 insertions(+), 198 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>>> b/drivers/gpu/drm/exynos/exynos_dp_core.c
>>>> index d66ade0..266f7f7 100644
>>>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>>> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
>>>> @@ -115,8 +115,8 @@ static int exynos_dp_read_edid(struct
>>>> exynos_dp_device *dp)
>>>>          /* Read Extension Flag, Number of 128-byte EDID extension
>>>> blocks */
>>>>        retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>>>> -                EDID_EXTENSION_FLAG,
>>>> -                &extend_block);
>>>> +                          EDID_EXTENSION_FLAG,
>>>> +                          &extend_block);
>>>>        if (retval)
>>>>            return retval;
>>>>    @@ -124,10 +124,11 @@ static int exynos_dp_read_edid(struct
>>>> exynos_dp_device *dp)
>>>>            dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>>>>              /* Read EDID data */
>>>> -        retval = exynos_dp_read_bytes_from_i2c(dp,
>>>> I2C_EDID_DEVICE_ADDR,
>>>> -                        EDID_HEADER_PATTERN,
>>>> -                        EDID_BLOCK_LENGTH,
>>>> -                        &edid[EDID_HEADER_PATTERN]);
>>>> +        retval = exynos_dp_read_bytes_from_i2c(
>>>> +                    dp, I2C_EDID_DEVICE_ADDR,
>>>> +                    EDID_HEADER_PATTERN,
>>>> +                    EDID_BLOCK_LENGTH,
>>>> +                    &edid[EDID_HEADER_PATTERN]);
>>>>            if (retval != 0) {
>>>>                dev_err(dp->dev, "EDID Read failed!\n");
>>>>                return -EIO;
>>>> @@ -139,11 +140,11 @@ static int exynos_dp_read_edid(struct
>>>> exynos_dp_device *dp)
>>>>            }
>>>>              /* Read additional EDID data */
>>>> -        retval = exynos_dp_read_bytes_from_i2c(dp,
>>>> -                I2C_EDID_DEVICE_ADDR,
>>>> -                EDID_BLOCK_LENGTH,
>>>> -                EDID_BLOCK_LENGTH,
>>>> -                &edid[EDID_BLOCK_LENGTH]);
>>>> +        retval = exynos_dp_read_bytes_from_i2c(
>>>> +                    dp, I2C_EDID_DEVICE_ADDR,
>>>> +                    EDID_BLOCK_LENGTH,
>>>> +                    EDID_BLOCK_LENGTH,
>>>> +                    &edid[EDID_BLOCK_LENGTH]);
>>>>            if (retval != 0) {
>>>>                dev_err(dp->dev, "EDID Read failed!\n");
>>>>                return -EIO;
>>>> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct
>>>> exynos_dp_device *dp)
>>>>            }
>>>>              exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
>>>> -                    &test_vector);
>>>> +                          &test_vector);
>>>>            if (test_vector & DP_TEST_LINK_EDID_READ) {
>>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>>> -                DP_TEST_EDID_CHECKSUM,
>>>> +            exynos_dp_write_byte_to_dpcd(
>>>> +                dp, DP_TEST_EDID_CHECKSUM,
>>>>                    edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
>>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>>> -                DP_TEST_RESPONSE,
>>>> +            exynos_dp_write_byte_to_dpcd(
>>>> +                dp, DP_TEST_RESPONSE,
>>>>                    DP_TEST_EDID_CHECKSUM_WRITE);
>>> To me, missing argument after opening parenthesis, looks worse. I would
>>> prefer:
>>>
>>>              exynos_dp_write_byte_to_dpcd(dp,
>>>
>>> Why you moved the 'dp' argument to new line?
>> Hmm... Just like style tool indicate, no more warning after
>> that change.
>>
>> For now, I would like to follow the original style, just improved
>> some obvious style problem.  :-)
> What was the checkpatch warning that said 'dp' has to move to new line?
> I tried this and I don't see it.

checkpatch haven't remind me that put dp to new line would fix
this warning, this just come from my experiments. And I works,
no more warnings from checkpatch, so I toke this style.

- Yakir

> Best regards,
> Krzysztof
>
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 01/16] drm: exynos/dp: fix code style
@ 2015-09-03  5:33           ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-03  5:33 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Krzysztof,

? 09/03/2015 01:08 PM, Krzysztof Kozlowski ??:
> On 03.09.2015 14:04, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> ? 09/03/2015 08:21 AM, Krzysztof Kozlowski ??:
>>> On 01.09.2015 14:46, Yakir Yang wrote:
>>>> After run "checkpatch.pl -f --subjective" command, I see there
>>>> are lots of alignment problem in exynos_dp driver, so let just
>>>> fix them.
>>> Hi,
>>>
>>> Warnings from checkpatch are not a reason for a commit. Reason for a
>>> commit could be for example an unreadable code, violation of
>>> coding-style leading to decrease in code maintainability or just
>>> improving the code readability so it will be easier to review and
>>> maintain it.
>>>
>>> You do not make commits because some tool tells you that. We do not
>>> listen to machines :) ... If that would be the case, the commit could be
>>> made automatically, without human interaction. Such automated commit
>>> could be even easily tested by the machine by comparing object files.
>>>
>>> Especially that you enabled "subjective" rule. This is not a valid
>>> motivation for a commit.
>>>
>>> Please rephrase this to sensible reason and convince that change is
>>> worth the effort.
>> Oh, nice, thanks for your remind. I would rephrase the commit.
>>
>>>> - Take Romain suggest, rebase on linux-next branch
>>> That comment seems unrelated to the commit. Please remove it.
>> Done,
>>
>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>> ---
>>>> Changes in v4: None
>>>> Changes in v3: None
>>>> Changes in v2:
>>>> - Take Joe Preches advise, improved commit message more readable, and
>>>>     avoid using some uncommon style like bellow:
>>>>     -  retval = exynos_dp_read_bytes_from_i2c(...
>>>>                  ...)
>>>>     +  retval =
>>>>     +  exynos_dp_read_bytes_from_i2c(......);
>>>>
>>>>    drivers/gpu/drm/exynos/exynos_dp_core.c | 226
>>>> ++++++++++++++++----------------
>>>>    drivers/gpu/drm/exynos/exynos_dp_core.h |  54 ++++----
>>>>    drivers/gpu/drm/exynos/exynos_dp_reg.c  | 106 +++++++--------
>>>>    3 files changed, 188 insertions(+), 198 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>>> b/drivers/gpu/drm/exynos/exynos_dp_core.c
>>>> index d66ade0..266f7f7 100644
>>>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>>> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
>>>> @@ -115,8 +115,8 @@ static int exynos_dp_read_edid(struct
>>>> exynos_dp_device *dp)
>>>>          /* Read Extension Flag, Number of 128-byte EDID extension
>>>> blocks */
>>>>        retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>>>> -                EDID_EXTENSION_FLAG,
>>>> -                &extend_block);
>>>> +                          EDID_EXTENSION_FLAG,
>>>> +                          &extend_block);
>>>>        if (retval)
>>>>            return retval;
>>>>    @@ -124,10 +124,11 @@ static int exynos_dp_read_edid(struct
>>>> exynos_dp_device *dp)
>>>>            dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>>>>              /* Read EDID data */
>>>> -        retval = exynos_dp_read_bytes_from_i2c(dp,
>>>> I2C_EDID_DEVICE_ADDR,
>>>> -                        EDID_HEADER_PATTERN,
>>>> -                        EDID_BLOCK_LENGTH,
>>>> -                        &edid[EDID_HEADER_PATTERN]);
>>>> +        retval = exynos_dp_read_bytes_from_i2c(
>>>> +                    dp, I2C_EDID_DEVICE_ADDR,
>>>> +                    EDID_HEADER_PATTERN,
>>>> +                    EDID_BLOCK_LENGTH,
>>>> +                    &edid[EDID_HEADER_PATTERN]);
>>>>            if (retval != 0) {
>>>>                dev_err(dp->dev, "EDID Read failed!\n");
>>>>                return -EIO;
>>>> @@ -139,11 +140,11 @@ static int exynos_dp_read_edid(struct
>>>> exynos_dp_device *dp)
>>>>            }
>>>>              /* Read additional EDID data */
>>>> -        retval = exynos_dp_read_bytes_from_i2c(dp,
>>>> -                I2C_EDID_DEVICE_ADDR,
>>>> -                EDID_BLOCK_LENGTH,
>>>> -                EDID_BLOCK_LENGTH,
>>>> -                &edid[EDID_BLOCK_LENGTH]);
>>>> +        retval = exynos_dp_read_bytes_from_i2c(
>>>> +                    dp, I2C_EDID_DEVICE_ADDR,
>>>> +                    EDID_BLOCK_LENGTH,
>>>> +                    EDID_BLOCK_LENGTH,
>>>> +                    &edid[EDID_BLOCK_LENGTH]);
>>>>            if (retval != 0) {
>>>>                dev_err(dp->dev, "EDID Read failed!\n");
>>>>                return -EIO;
>>>> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct
>>>> exynos_dp_device *dp)
>>>>            }
>>>>              exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
>>>> -                    &test_vector);
>>>> +                          &test_vector);
>>>>            if (test_vector & DP_TEST_LINK_EDID_READ) {
>>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>>> -                DP_TEST_EDID_CHECKSUM,
>>>> +            exynos_dp_write_byte_to_dpcd(
>>>> +                dp, DP_TEST_EDID_CHECKSUM,
>>>>                    edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
>>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>>> -                DP_TEST_RESPONSE,
>>>> +            exynos_dp_write_byte_to_dpcd(
>>>> +                dp, DP_TEST_RESPONSE,
>>>>                    DP_TEST_EDID_CHECKSUM_WRITE);
>>> To me, missing argument after opening parenthesis, looks worse. I would
>>> prefer:
>>>
>>>              exynos_dp_write_byte_to_dpcd(dp,
>>>
>>> Why you moved the 'dp' argument to new line?
>> Hmm... Just like style tool indicate, no more warning after
>> that change.
>>
>> For now, I would like to follow the original style, just improved
>> some obvious style problem.  :-)
> What was the checkpatch warning that said 'dp' has to move to new line?
> I tried this and I don't see it.

checkpatch haven't remind me that put dp to new line would fix
this warning, this just come from my experiments. And I works,
no more warnings from checkpatch, so I toke this style.

- Yakir

> Best regards,
> Krzysztof
>
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 01/16] drm: exynos/dp: fix code style
  2015-09-03  5:33           ` Yakir Yang
  (?)
@ 2015-09-03  5:57             ` Joe Perches
  -1 siblings, 0 replies; 370+ messages in thread
From: Joe Perches @ 2015-09-03  5:57 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, Kukjin Kim, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

On Thu, 2015-09-03 at 13:33 +0800, Yakir Yang wrote:
[]
> >>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
[]
> >>>> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct
> >>>> exynos_dp_device *dp)
> >>>>            }
> >>>>              exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
> >>>> -                    &test_vector);
> >>>> +                          &test_vector);
> >>>>            if (test_vector & DP_TEST_LINK_EDID_READ) {
> >>>> -            exynos_dp_write_byte_to_dpcd(dp,
> >>>> -                DP_TEST_EDID_CHECKSUM,
> >>>> +            exynos_dp_write_byte_to_dpcd(
> >>>> +                dp, DP_TEST_EDID_CHECKSUM,
> >>>>                    edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
> >>>> -            exynos_dp_write_byte_to_dpcd(dp,
> >>>> -                DP_TEST_RESPONSE,
> >>>> +            exynos_dp_write_byte_to_dpcd(
> >>>> +                dp, DP_TEST_RESPONSE,
> >>>>                    DP_TEST_EDID_CHECKSUM_WRITE);
> >>> To me, missing argument after opening parenthesis, looks worse. I would
> >>> prefer:
> >>>
> >>>              exynos_dp_write_byte_to_dpcd(dp,
> >>>
> >>> Why you moved the 'dp' argument to new line?
> >> Hmm... Just like style tool indicate, no more warning after
> >> that change.
> >>
> >> For now, I would like to follow the original style, just improved
> >> some obvious style problem.  :-)
> > What was the checkpatch warning that said 'dp' has to move to new line?
> > I tried this and I don't see it.
> 
> checkpatch haven't remind me that put dp to new line would fix
> this warning, this just come from my experiments. And I works,
> no more warnings from checkpatch, so I toke this style.

Checkpatch isn't a great arbiter of style.
It's just a brainless tool.

Always use your instead of anything brainless.

If it were code I was writing, I'd ignore 80 columns warnings
where appropriate.

These are long function names and long macro defines, so it's
inappropriate to use 80 columns as a guiding style.

I'd write:

		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, &test_vector);
		if (test_vector & DP_TEST_LINK_EDID_READ) {
			exynos_dp_write_byte_to_dpcd(dp, DP_TEST_EDID_CHECKSUM,
						     edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
			exynos_dp_write_byte_to_dpcd(dp, DP_TEST_RESPONSE,
						     DP_TEST_EDID_CHECKSUM_WRITE);
		}



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 01/16] drm: exynos/dp: fix code style
@ 2015-09-03  5:57             ` Joe Perches
  0 siblings, 0 replies; 370+ messages in thread
From: Joe Perches @ 2015-09-03  5:57 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, Kukjin Kim, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree

On Thu, 2015-09-03 at 13:33 +0800, Yakir Yang wrote:
[]
> >>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
[]
> >>>> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct
> >>>> exynos_dp_device *dp)
> >>>>            }
> >>>>              exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
> >>>> -                    &test_vector);
> >>>> +                          &test_vector);
> >>>>            if (test_vector & DP_TEST_LINK_EDID_READ) {
> >>>> -            exynos_dp_write_byte_to_dpcd(dp,
> >>>> -                DP_TEST_EDID_CHECKSUM,
> >>>> +            exynos_dp_write_byte_to_dpcd(
> >>>> +                dp, DP_TEST_EDID_CHECKSUM,
> >>>>                    edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
> >>>> -            exynos_dp_write_byte_to_dpcd(dp,
> >>>> -                DP_TEST_RESPONSE,
> >>>> +            exynos_dp_write_byte_to_dpcd(
> >>>> +                dp, DP_TEST_RESPONSE,
> >>>>                    DP_TEST_EDID_CHECKSUM_WRITE);
> >>> To me, missing argument after opening parenthesis, looks worse. I would
> >>> prefer:
> >>>
> >>>              exynos_dp_write_byte_to_dpcd(dp,
> >>>
> >>> Why you moved the 'dp' argument to new line?
> >> Hmm... Just like style tool indicate, no more warning after
> >> that change.
> >>
> >> For now, I would like to follow the original style, just improved
> >> some obvious style problem.  :-)
> > What was the checkpatch warning that said 'dp' has to move to new line?
> > I tried this and I don't see it.
> 
> checkpatch haven't remind me that put dp to new line would fix
> this warning, this just come from my experiments. And I works,
> no more warnings from checkpatch, so I toke this style.

Checkpatch isn't a great arbiter of style.
It's just a brainless tool.

Always use your instead of anything brainless.

If it were code I was writing, I'd ignore 80 columns warnings
where appropriate.

These are long function names and long macro defines, so it's
inappropriate to use 80 columns as a guiding style.

I'd write:

		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, &test_vector);
		if (test_vector & DP_TEST_LINK_EDID_READ) {
			exynos_dp_write_byte_to_dpcd(dp, DP_TEST_EDID_CHECKSUM,
						     edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
			exynos_dp_write_byte_to_dpcd(dp, DP_TEST_RESPONSE,
						     DP_TEST_EDID_CHECKSUM_WRITE);
		}

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 01/16] drm: exynos/dp: fix code style
@ 2015-09-03  5:57             ` Joe Perches
  0 siblings, 0 replies; 370+ messages in thread
From: Joe Perches @ 2015-09-03  5:57 UTC (permalink / raw)
  To: linux-arm-kernel

On Thu, 2015-09-03 at 13:33 +0800, Yakir Yang wrote:
[]
> >>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
[]
> >>>> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct
> >>>> exynos_dp_device *dp)
> >>>>            }
> >>>>              exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
> >>>> -                    &test_vector);
> >>>> +                          &test_vector);
> >>>>            if (test_vector & DP_TEST_LINK_EDID_READ) {
> >>>> -            exynos_dp_write_byte_to_dpcd(dp,
> >>>> -                DP_TEST_EDID_CHECKSUM,
> >>>> +            exynos_dp_write_byte_to_dpcd(
> >>>> +                dp, DP_TEST_EDID_CHECKSUM,
> >>>>                    edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
> >>>> -            exynos_dp_write_byte_to_dpcd(dp,
> >>>> -                DP_TEST_RESPONSE,
> >>>> +            exynos_dp_write_byte_to_dpcd(
> >>>> +                dp, DP_TEST_RESPONSE,
> >>>>                    DP_TEST_EDID_CHECKSUM_WRITE);
> >>> To me, missing argument after opening parenthesis, looks worse. I would
> >>> prefer:
> >>>
> >>>              exynos_dp_write_byte_to_dpcd(dp,
> >>>
> >>> Why you moved the 'dp' argument to new line?
> >> Hmm... Just like style tool indicate, no more warning after
> >> that change.
> >>
> >> For now, I would like to follow the original style, just improved
> >> some obvious style problem.  :-)
> > What was the checkpatch warning that said 'dp' has to move to new line?
> > I tried this and I don't see it.
> 
> checkpatch haven't remind me that put dp to new line would fix
> this warning, this just come from my experiments. And I works,
> no more warnings from checkpatch, so I toke this style.

Checkpatch isn't a great arbiter of style.
It's just a brainless tool.

Always use your instead of anything brainless.

If it were code I was writing, I'd ignore 80 columns warnings
where appropriate.

These are long function names and long macro defines, so it's
inappropriate to use 80 columns as a guiding style.

I'd write:

		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, &test_vector);
		if (test_vector & DP_TEST_LINK_EDID_READ) {
			exynos_dp_write_byte_to_dpcd(dp, DP_TEST_EDID_CHECKSUM,
						     edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
			exynos_dp_write_byte_to_dpcd(dp, DP_TEST_RESPONSE,
						     DP_TEST_EDID_CHECKSUM_WRITE);
		}

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 05/16] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & colorimetry
  2015-09-01  5:55   ` Yakir Yang
@ 2015-09-03  8:04     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-03  8:04 UTC (permalink / raw)
  To: Yakir Yang, Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

On 01.09.2015 14:55, Yakir Yang wrote:
> Both hsync/vsync polarity and interlace mode can be parsed from
> drm display mode, and dynamic_range and ycbcr_coeff can be judge
> by the video code, same to color space and color depth can be
> parsed from EDID.
> 
> But presumably Exynos still relaies on the DT properties, so take

s/relaies/relies/

> good use of mode_fixup() in to achieve the compatibility hacks.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Krzysztof suggest, provide backword compatibility with samsung.
> - Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.
> 
> Changes in v3:
> - Take Thierry Reding suggest, dynamic parse video timing info from
>   struct drm_display_mode and struct drm_display_info.
> 
> Changes in v2: None
> 
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 141 +++++++++++++--------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>  drivers/gpu/drm/exynos/exynos_dp.c                 |  58 ++++++++-
>  4 files changed, 151 insertions(+), 64 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index 7196097..f0db92e 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -897,8 +897,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
>  		return;
>  	}
>  
> -	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
> -					 dp->video_info->link_rate);
> +	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
> +					 dp->video_info.link_rate);
>  	if (ret) {
>  		dev_err(dp->dev, "unable to do link train\n");
>  		return;
> @@ -1081,6 +1081,82 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
>  	dp->dpms_mode = DRM_MODE_DPMS_OFF;
>  }
>  
> +static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
> +					struct drm_display_mode *orig_mode,
> +					struct drm_display_mode *mode)
> +{
> +	struct analogix_dp_device *dp = bridge->driver_private;
> +	struct drm_display_info *display_info = &dp->connector.display_info;
> +	struct video_info *video_info = &dp->video_info;
> +	struct device_node *dp_node = dp->dev->of_node;
> +	int vic;
> +
> +	/* interlaces & hsync pol & vsync pol */
> +	video_info->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
> +	video_info->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
> +	video_info->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
> +
> +	/* dynamic_range & colorimetry */
> +	vic = drm_match_cea_mode(mode);
> +	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
> +	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
> +		video_info->dynamic_range = CEA;
> +		video_info->ycbcr_coeff = COLOR_YCBCR601;
> +	} else if (vic) {
> +		video_info->dynamic_range = CEA;
> +		video_info->ycbcr_coeff = COLOR_YCBCR709;
> +	} else {
> +		video_info->dynamic_range = VESA;
> +		video_info->ycbcr_coeff = COLOR_YCBCR709;
> +	}
> +
> +	switch (display_info->bpc) {
> +	case 12:
> +		video_info->color_depth = COLOR_12;
> +		break;
> +	case 10:
> +		video_info->color_depth = COLOR_10;
> +		break;
> +	case 8:
> +		video_info->color_depth = COLOR_8;
> +		break;
> +	case 6:
> +		video_info->color_depth = COLOR_6;
> +		break;
> +	default:
> +		video_info->color_depth = COLOR_8;
> +		break;
> +	}
> +
> +	if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB444)
> +		video_info->color_space = COLOR_YCBCR444;
> +	else if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB422)
> +		video_info->color_space = COLOR_YCBCR422;
> +	else if (display_info->color_formats | DRM_COLOR_FORMAT_RGB444)
> +		video_info->color_space = COLOR_RGB;
> +	else
> +		video_info->color_space = COLOR_RGB;
> +
> +	/*
> +	 * NOTE: those property parseing code is used for

s/parseing/parsing/

BTW, you can easily integrate spell-check to vim... It is not that I
search for such misspellings - they are highlighted...

> +	 * providing backward compatibility for samsung platform.
> +	 */
> +	of_property_read_u32(dp_node, "samsung,color-space",
> +			     &video_info->color_space);
> +	of_property_read_u32(dp_node, "samsung,dynamic-range",
> +			     &video_info->dynamic_range);
> +	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> +			     &video_info->ycbcr_coeff);
> +	of_property_read_u32(dp_node, "samsung,color-depth",
> +			     &video_info->color_depth);
> +	of_property_read_u32(dp_node, "hsync-active-high",
> +			     (unsigned int *)&video_info->h_sync_polarity);
> +	of_property_read_u32(dp_node, "vsync-active-high",
> +			     (unsigned int *)&video_info->v_sync_polarity);
> +	of_property_read_u32(dp_node, "interlaced",
> +			     (unsigned int *)&video_info->interlaced);

You made assumption that the sizeof(bool) is always equal to
sizeof(u32)... Then you cast it to pointer to unsigned int but function
wants pointer to u32. Just for reading boolean property. There's easier
way - of_property_read_bool. It returns bool.


> +}
> +
>  static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
>  {
>  	/* do nothing */
> @@ -1091,6 +1167,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
>  	.disable = analogix_dp_bridge_disable,
>  	.pre_enable = analogix_dp_bridge_nop,
>  	.post_disable = analogix_dp_bridge_nop,
> +	.mode_set = analogix_dp_bridge_mode_set,
>  	.attach = analogix_dp_bridge_attach,
>  };
>  
> @@ -1121,62 +1198,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>  	return 0;
>  }
>  
> -static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
> +static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
>  {
> -	struct device_node *dp_node = dev->of_node;
> -	struct video_info *dp_video_config;
> -
> -	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
> -				       GFP_KERNEL);
> -	if (!dp_video_config)
> -		return ERR_PTR(-ENOMEM);
> -
> -	dp_video_config->h_sync_polarity =
> -		of_property_read_bool(dp_node, "hsync-active-high");
> -
> -	dp_video_config->v_sync_polarity =
> -		of_property_read_bool(dp_node, "vsync-active-high");
> -
> -	dp_video_config->interlaced =
> -		of_property_read_bool(dp_node, "interlaced");
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-space",
> -				 &dp_video_config->color_space)) {
> -		dev_err(dev, "failed to get color-space\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
> -				 &dp_video_config->dynamic_range)) {
> -		dev_err(dev, "failed to get dynamic-range\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> -				 &dp_video_config->ycbcr_coeff)) {
> -		dev_err(dev, "failed to get ycbcr-coeff\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-depth",
> -				 &dp_video_config->color_depth)) {
> -		dev_err(dev, "failed to get color-depth\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> +	struct device_node *dp_node = dp->dev->of_node;
> +	struct video_info *video_config = &dp->video_info;
>  
>  	if (of_property_read_u32(dp_node, "samsung,link-rate",
> -				 &dp_video_config->link_rate)) {
> +				 &video_info->link_rate)) {
>  		dev_err(dev, "failed to get link-rate\n");
> -		return ERR_PTR(-EINVAL);
> +		return -EINVAL;
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,lane-count",
> -				 &dp_video_config->lane_count)) {
> +				 &video_info->lane_count)) {
>  		dev_err(dev, "failed to get lane-count\n");
> -		return ERR_PTR(-EINVAL);
> +		return -EINVAL;
>  	}
>  
> -	return dp_video_config;
> +	return 0;
>  }
>  
>  int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
> @@ -1205,9 +1244,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>  	 */
>  	dp->plat_data = plat_data;
>  
> -	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
> -	if (IS_ERR(dp->video_info))
> -		return PTR_ERR(dp->video_info);
> +	ret = analogix_dp_dt_parse_pdata(dp);
> +	if (ret)
> +		return ret;
>  
>  	dp->phy = devm_phy_get(dp->dev, "dp");
>  	if (IS_ERR(dp->phy)) {
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> index ffabbd0..6e3d5bc 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> @@ -154,7 +154,7 @@ struct analogix_dp_device {
>  	unsigned int		irq;
>  	void __iomem		*reg_base;
>  
> -	struct video_info	*video_info;
> +	struct video_info	video_info;
>  	struct link_train	link_train;
>  	struct work_struct	hotplug_work;
>  	struct phy		*phy;
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index b879d8c..6a643be 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
>  	u32 reg;
>  
>  	/* Configure the input color depth, color space, dynamic range */
> -	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
> -		(dp->video_info->color_depth << IN_BPC_SHIFT) |
> -		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
> +	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
> +		(dp->video_info.color_depth << IN_BPC_SHIFT) |
> +		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
>  
>  	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>  	reg &= ~IN_YC_COEFFI_MASK;
> -	if (dp->video_info->ycbcr_coeff)
> +	if (dp->video_info.ycbcr_coeff)
>  		reg |= IN_YC_COEFFI_ITU709;
>  	else
>  		reg |= IN_YC_COEFFI_ITU601;
> @@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~INTERACE_SCAN_CFG;
> -	reg |= (dp->video_info->interlaced << 2);
> +	reg |= (dp->video_info.interlaced << 2);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~VSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->v_sync_polarity << 1);
> +	reg |= (dp->video_info.v_sync_polarity << 1);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~HSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->h_sync_polarity << 0);
> +	reg |= (dp->video_info.h_sync_polarity << 0);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
> index 7e1be72..6060d2c 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
> @@ -28,8 +28,13 @@
>  
>  #include "exynos_drm_crtc.h"
>  
> -#define plat_data_to_dp(pd) \
> -		container_of(pd, struct exynos_dp_device, plat_data)
> +#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
> +
> +struct video_info {
> +	bool h_sync_polarity;
> +	bool v_sync_polarity;
> +	bool interlaced;
> +};
>  
>  struct exynos_dp_device {
>  	struct drm_encoder         encoder;
> @@ -39,12 +44,13 @@ struct exynos_dp_device {
>  
>  	struct exynos_drm_panel_info priv;
>  	struct analogix_dp_plat_data plat_data;
> +	struct video_info            video_info;
>  };
>  
>  int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
>  				bool enable)
>  {
> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
> +	struct exynos_dp_device *dp = to_dp(plat_data);
>  	struct drm_encoder *encoder = &dp->encoder;
>  	struct exynos_drm_crtc *crtc;
>  
> @@ -71,7 +77,7 @@ static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
>  static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
>  			       struct drm_connector *connector)
>  {
> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
> +	struct exynos_dp_device *dp = to_dp(plat_data);
>  	struct drm_display_mode *mode;
>  
>  	if (dp->plat_data.panel)
> @@ -99,7 +105,7 @@ static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
>  static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
>  				   struct drm_bridge *bridge)
>  {
> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
> +	struct exynos_dp_device *dp = to_dp(plat_data);
>  	struct drm_encoder *encoder = &dp->encoder;
>  	int ret;
>  
> @@ -122,6 +128,28 @@ static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
>  				 const struct drm_display_mode *mode,
>  				 struct drm_display_mode *adjusted_mode)
>  {
> +	struct exynos_dp_device *dp = to_dp(encoder);
> +	int flags = adjusted_mode->flags;
> +
> +	flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |
> +		   DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC |
> +		   DRM_MODE_FLAG_INTERLACE);
> +
> +	if (dp->video_info.h_sync_polarity)
> +		flags |= DRM_MODE_FLAG_PHSYNC;
> +	else
> +		flags |= DRM_MODE_FLAG_NHSYNC;
> +
> +	if (dp->video_info.v_sync_polarity)
> +		flags |= DRM_MODE_FLAG_PVSYNC;
> +	else
> +		flags |= DRM_MODE_FLAG_NVSYNC;
> +
> +	if (dp->video_info.interlaced)
> +		flags |= DRM_MODE_FLAG_INTERLACE;
> +
> +	adjusted_mode->flags = flags;
> +
>  	return true;
>  }
>  
> @@ -163,6 +191,22 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
>  	return 0;
>  }
>  
> +static int exynos_dp_dt_parse_video_info(struct exynos_dp_device *dp)
> +{
> +	struct device_node *dp_node = dp->dev->of_node;
> +
> +	dp->video_info.h_sync_polarity =
> +		of_property_read_bool(dp_node, "hsync-active-high");
> +
> +	dp->video_info.v_sync_polarity =
> +		of_property_read_bool(dp_node, "vsync-active-high");
> +
> +	dp->video_info.interlaced =
> +		of_property_read_bool(dp_node, "interlaced");
> +
> +	return 0;

Probably you wanted to follow the convention of other DT-parse functions
but there is no need. This function cannot fail so maybe make it void?
It would simplify a bit the code in exynos_dp_bind().

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 05/16] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & colorimetry
@ 2015-09-03  8:04     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-03  8:04 UTC (permalink / raw)
  To: linux-arm-kernel

On 01.09.2015 14:55, Yakir Yang wrote:
> Both hsync/vsync polarity and interlace mode can be parsed from
> drm display mode, and dynamic_range and ycbcr_coeff can be judge
> by the video code, same to color space and color depth can be
> parsed from EDID.
> 
> But presumably Exynos still relaies on the DT properties, so take

s/relaies/relies/

> good use of mode_fixup() in to achieve the compatibility hacks.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4:
> - Take Krzysztof suggest, provide backword compatibility with samsung.
> - Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.
> 
> Changes in v3:
> - Take Thierry Reding suggest, dynamic parse video timing info from
>   struct drm_display_mode and struct drm_display_info.
> 
> Changes in v2: None
> 
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 141 +++++++++++++--------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>  drivers/gpu/drm/exynos/exynos_dp.c                 |  58 ++++++++-
>  4 files changed, 151 insertions(+), 64 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index 7196097..f0db92e 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -897,8 +897,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
>  		return;
>  	}
>  
> -	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
> -					 dp->video_info->link_rate);
> +	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
> +					 dp->video_info.link_rate);
>  	if (ret) {
>  		dev_err(dp->dev, "unable to do link train\n");
>  		return;
> @@ -1081,6 +1081,82 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
>  	dp->dpms_mode = DRM_MODE_DPMS_OFF;
>  }
>  
> +static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
> +					struct drm_display_mode *orig_mode,
> +					struct drm_display_mode *mode)
> +{
> +	struct analogix_dp_device *dp = bridge->driver_private;
> +	struct drm_display_info *display_info = &dp->connector.display_info;
> +	struct video_info *video_info = &dp->video_info;
> +	struct device_node *dp_node = dp->dev->of_node;
> +	int vic;
> +
> +	/* interlaces & hsync pol & vsync pol */
> +	video_info->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
> +	video_info->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
> +	video_info->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
> +
> +	/* dynamic_range & colorimetry */
> +	vic = drm_match_cea_mode(mode);
> +	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
> +	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
> +		video_info->dynamic_range = CEA;
> +		video_info->ycbcr_coeff = COLOR_YCBCR601;
> +	} else if (vic) {
> +		video_info->dynamic_range = CEA;
> +		video_info->ycbcr_coeff = COLOR_YCBCR709;
> +	} else {
> +		video_info->dynamic_range = VESA;
> +		video_info->ycbcr_coeff = COLOR_YCBCR709;
> +	}
> +
> +	switch (display_info->bpc) {
> +	case 12:
> +		video_info->color_depth = COLOR_12;
> +		break;
> +	case 10:
> +		video_info->color_depth = COLOR_10;
> +		break;
> +	case 8:
> +		video_info->color_depth = COLOR_8;
> +		break;
> +	case 6:
> +		video_info->color_depth = COLOR_6;
> +		break;
> +	default:
> +		video_info->color_depth = COLOR_8;
> +		break;
> +	}
> +
> +	if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB444)
> +		video_info->color_space = COLOR_YCBCR444;
> +	else if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB422)
> +		video_info->color_space = COLOR_YCBCR422;
> +	else if (display_info->color_formats | DRM_COLOR_FORMAT_RGB444)
> +		video_info->color_space = COLOR_RGB;
> +	else
> +		video_info->color_space = COLOR_RGB;
> +
> +	/*
> +	 * NOTE: those property parseing code is used for

s/parseing/parsing/

BTW, you can easily integrate spell-check to vim... It is not that I
search for such misspellings - they are highlighted...

> +	 * providing backward compatibility for samsung platform.
> +	 */
> +	of_property_read_u32(dp_node, "samsung,color-space",
> +			     &video_info->color_space);
> +	of_property_read_u32(dp_node, "samsung,dynamic-range",
> +			     &video_info->dynamic_range);
> +	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> +			     &video_info->ycbcr_coeff);
> +	of_property_read_u32(dp_node, "samsung,color-depth",
> +			     &video_info->color_depth);
> +	of_property_read_u32(dp_node, "hsync-active-high",
> +			     (unsigned int *)&video_info->h_sync_polarity);
> +	of_property_read_u32(dp_node, "vsync-active-high",
> +			     (unsigned int *)&video_info->v_sync_polarity);
> +	of_property_read_u32(dp_node, "interlaced",
> +			     (unsigned int *)&video_info->interlaced);

You made assumption that the sizeof(bool) is always equal to
sizeof(u32)... Then you cast it to pointer to unsigned int but function
wants pointer to u32. Just for reading boolean property. There's easier
way - of_property_read_bool. It returns bool.


> +}
> +
>  static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
>  {
>  	/* do nothing */
> @@ -1091,6 +1167,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
>  	.disable = analogix_dp_bridge_disable,
>  	.pre_enable = analogix_dp_bridge_nop,
>  	.post_disable = analogix_dp_bridge_nop,
> +	.mode_set = analogix_dp_bridge_mode_set,
>  	.attach = analogix_dp_bridge_attach,
>  };
>  
> @@ -1121,62 +1198,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>  	return 0;
>  }
>  
> -static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
> +static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
>  {
> -	struct device_node *dp_node = dev->of_node;
> -	struct video_info *dp_video_config;
> -
> -	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
> -				       GFP_KERNEL);
> -	if (!dp_video_config)
> -		return ERR_PTR(-ENOMEM);
> -
> -	dp_video_config->h_sync_polarity =
> -		of_property_read_bool(dp_node, "hsync-active-high");
> -
> -	dp_video_config->v_sync_polarity =
> -		of_property_read_bool(dp_node, "vsync-active-high");
> -
> -	dp_video_config->interlaced =
> -		of_property_read_bool(dp_node, "interlaced");
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-space",
> -				 &dp_video_config->color_space)) {
> -		dev_err(dev, "failed to get color-space\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
> -				 &dp_video_config->dynamic_range)) {
> -		dev_err(dev, "failed to get dynamic-range\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> -				 &dp_video_config->ycbcr_coeff)) {
> -		dev_err(dev, "failed to get ycbcr-coeff\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-depth",
> -				 &dp_video_config->color_depth)) {
> -		dev_err(dev, "failed to get color-depth\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> +	struct device_node *dp_node = dp->dev->of_node;
> +	struct video_info *video_config = &dp->video_info;
>  
>  	if (of_property_read_u32(dp_node, "samsung,link-rate",
> -				 &dp_video_config->link_rate)) {
> +				 &video_info->link_rate)) {
>  		dev_err(dev, "failed to get link-rate\n");
> -		return ERR_PTR(-EINVAL);
> +		return -EINVAL;
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,lane-count",
> -				 &dp_video_config->lane_count)) {
> +				 &video_info->lane_count)) {
>  		dev_err(dev, "failed to get lane-count\n");
> -		return ERR_PTR(-EINVAL);
> +		return -EINVAL;
>  	}
>  
> -	return dp_video_config;
> +	return 0;
>  }
>  
>  int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
> @@ -1205,9 +1244,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>  	 */
>  	dp->plat_data = plat_data;
>  
> -	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
> -	if (IS_ERR(dp->video_info))
> -		return PTR_ERR(dp->video_info);
> +	ret = analogix_dp_dt_parse_pdata(dp);
> +	if (ret)
> +		return ret;
>  
>  	dp->phy = devm_phy_get(dp->dev, "dp");
>  	if (IS_ERR(dp->phy)) {
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> index ffabbd0..6e3d5bc 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> @@ -154,7 +154,7 @@ struct analogix_dp_device {
>  	unsigned int		irq;
>  	void __iomem		*reg_base;
>  
> -	struct video_info	*video_info;
> +	struct video_info	video_info;
>  	struct link_train	link_train;
>  	struct work_struct	hotplug_work;
>  	struct phy		*phy;
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index b879d8c..6a643be 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
>  	u32 reg;
>  
>  	/* Configure the input color depth, color space, dynamic range */
> -	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
> -		(dp->video_info->color_depth << IN_BPC_SHIFT) |
> -		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
> +	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
> +		(dp->video_info.color_depth << IN_BPC_SHIFT) |
> +		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
>  
>  	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>  	reg &= ~IN_YC_COEFFI_MASK;
> -	if (dp->video_info->ycbcr_coeff)
> +	if (dp->video_info.ycbcr_coeff)
>  		reg |= IN_YC_COEFFI_ITU709;
>  	else
>  		reg |= IN_YC_COEFFI_ITU601;
> @@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~INTERACE_SCAN_CFG;
> -	reg |= (dp->video_info->interlaced << 2);
> +	reg |= (dp->video_info.interlaced << 2);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~VSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->v_sync_polarity << 1);
> +	reg |= (dp->video_info.v_sync_polarity << 1);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~HSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->h_sync_polarity << 0);
> +	reg |= (dp->video_info.h_sync_polarity << 0);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
> index 7e1be72..6060d2c 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
> @@ -28,8 +28,13 @@
>  
>  #include "exynos_drm_crtc.h"
>  
> -#define plat_data_to_dp(pd) \
> -		container_of(pd, struct exynos_dp_device, plat_data)
> +#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
> +
> +struct video_info {
> +	bool h_sync_polarity;
> +	bool v_sync_polarity;
> +	bool interlaced;
> +};
>  
>  struct exynos_dp_device {
>  	struct drm_encoder         encoder;
> @@ -39,12 +44,13 @@ struct exynos_dp_device {
>  
>  	struct exynos_drm_panel_info priv;
>  	struct analogix_dp_plat_data plat_data;
> +	struct video_info            video_info;
>  };
>  
>  int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
>  				bool enable)
>  {
> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
> +	struct exynos_dp_device *dp = to_dp(plat_data);
>  	struct drm_encoder *encoder = &dp->encoder;
>  	struct exynos_drm_crtc *crtc;
>  
> @@ -71,7 +77,7 @@ static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
>  static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
>  			       struct drm_connector *connector)
>  {
> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
> +	struct exynos_dp_device *dp = to_dp(plat_data);
>  	struct drm_display_mode *mode;
>  
>  	if (dp->plat_data.panel)
> @@ -99,7 +105,7 @@ static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
>  static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
>  				   struct drm_bridge *bridge)
>  {
> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
> +	struct exynos_dp_device *dp = to_dp(plat_data);
>  	struct drm_encoder *encoder = &dp->encoder;
>  	int ret;
>  
> @@ -122,6 +128,28 @@ static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
>  				 const struct drm_display_mode *mode,
>  				 struct drm_display_mode *adjusted_mode)
>  {
> +	struct exynos_dp_device *dp = to_dp(encoder);
> +	int flags = adjusted_mode->flags;
> +
> +	flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |
> +		   DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC |
> +		   DRM_MODE_FLAG_INTERLACE);
> +
> +	if (dp->video_info.h_sync_polarity)
> +		flags |= DRM_MODE_FLAG_PHSYNC;
> +	else
> +		flags |= DRM_MODE_FLAG_NHSYNC;
> +
> +	if (dp->video_info.v_sync_polarity)
> +		flags |= DRM_MODE_FLAG_PVSYNC;
> +	else
> +		flags |= DRM_MODE_FLAG_NVSYNC;
> +
> +	if (dp->video_info.interlaced)
> +		flags |= DRM_MODE_FLAG_INTERLACE;
> +
> +	adjusted_mode->flags = flags;
> +
>  	return true;
>  }
>  
> @@ -163,6 +191,22 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
>  	return 0;
>  }
>  
> +static int exynos_dp_dt_parse_video_info(struct exynos_dp_device *dp)
> +{
> +	struct device_node *dp_node = dp->dev->of_node;
> +
> +	dp->video_info.h_sync_polarity =
> +		of_property_read_bool(dp_node, "hsync-active-high");
> +
> +	dp->video_info.v_sync_polarity =
> +		of_property_read_bool(dp_node, "vsync-active-high");
> +
> +	dp->video_info.interlaced =
> +		of_property_read_bool(dp_node, "interlaced");
> +
> +	return 0;

Probably you wanted to follow the convention of other DT-parse functions
but there is no need. This function cannot fail so maybe make it void?
It would simplify a bit the code in exynos_dp_bind().

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
  2015-09-02 10:02           ` Yakir Yang
@ 2015-09-03  8:38             ` Thierry Reding
  -1 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-03  8:38 UTC (permalink / raw)
  To: Yakir Yang, Mark Yao
  Cc: Heiko Stuebner, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Russell King, djkurtz, dianders, seanpaul,
	ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel, s.infradead.org, Mark Yao

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On Wed, Sep 02, 2015 at 06:02:25PM +0800, Yakir Yang wrote:
> 在 2015/9/2 16:34, Thierry Reding 写道:
[...]
> >At the very least your code must compile when applied against a recent
> >upstream tree. I would also expect you to make sure the code works at
> >runtime, though, contrary to build testing, not everybody will be able
> >to verify that you've actually done so. It is ultimately your platform
> >maintainer's (i.e. Heiko's) responsibility to ensure that because they
> >will get to deal with user complaints if people can't run an upstream
> >kernel on the devices.
> 
> Oh, first time to know this rule. So I should work on Heiko's github
> kernel branch at the first time to start send upstream.

It's usually not necessary to rebase on a specific platform tree. Most
platform trees should feed into linux-next anyway, so linux-next would
be the appropriate base in almost all cases.

Note, though, that that's only true if you expect somebody else to merge
your code. The reason is that whoever will end up applying your patches
will likely apply to a tree that feeds into linux-next, and that way you
both end up having roughly the same base.

On the other hand if you are a maintainer yourself you should be keeping
a branch based on the latest -rc1. That's especially important if your
tree feeds into linux-next, because basing on linux-next will break very
horribly that way.

So for this particular case I would expect either Mark or Inki to apply
these patches when they're ready. Their trees should be based on the
latest -rc1. At least the Exynos DRM tree feeds into linux-next, so you
should be fine if you use linux-next as a base.

Mark, have you ever considered having your tree added to linux-next?

I'm beginning to think that we need to make that a requirement for all
DRM drivers so that we can resolve integration issues early on rather
than Dave having to deal with them when he pulls code in.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
@ 2015-09-03  8:38             ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-03  8:38 UTC (permalink / raw)
  To: Yakir Yang, Mark Yao
  Cc: Heiko Stuebner, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Russell King, djkurtz, dianders, seanpaul,
	ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 1978 bytes --]

On Wed, Sep 02, 2015 at 06:02:25PM +0800, Yakir Yang wrote:
> 在 2015/9/2 16:34, Thierry Reding 写道:
[...]
> >At the very least your code must compile when applied against a recent
> >upstream tree. I would also expect you to make sure the code works at
> >runtime, though, contrary to build testing, not everybody will be able
> >to verify that you've actually done so. It is ultimately your platform
> >maintainer's (i.e. Heiko's) responsibility to ensure that because they
> >will get to deal with user complaints if people can't run an upstream
> >kernel on the devices.
> 
> Oh, first time to know this rule. So I should work on Heiko's github
> kernel branch at the first time to start send upstream.

It's usually not necessary to rebase on a specific platform tree. Most
platform trees should feed into linux-next anyway, so linux-next would
be the appropriate base in almost all cases.

Note, though, that that's only true if you expect somebody else to merge
your code. The reason is that whoever will end up applying your patches
will likely apply to a tree that feeds into linux-next, and that way you
both end up having roughly the same base.

On the other hand if you are a maintainer yourself you should be keeping
a branch based on the latest -rc1. That's especially important if your
tree feeds into linux-next, because basing on linux-next will break very
horribly that way.

So for this particular case I would expect either Mark or Inki to apply
these patches when they're ready. Their trees should be based on the
latest -rc1. At least the Exynos DRM tree feeds into linux-next, so you
should be fine if you use linux-next as a base.

Mark, have you ever considered having your tree added to linux-next?

I'm beginning to think that we need to make that a requirement for all
DRM drivers so that we can resolve integration issues early on rather
than Dave having to deal with them when he pulls code in.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2015-09-02 20:17     ` Rob Herring
  (?)
@ 2015-09-03  8:47       ` Thierry Reding
  -1 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-03  8:47 UTC (permalink / raw)
  To: Rob Herring
  Cc: Yakir Yang, Heiko Stuebner, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

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On Wed, Sep 02, 2015 at 03:17:57PM -0500, Rob Herring wrote:
[...]
> Are there any eDP panels which don't have EDID and need panel details in DT?

Most panels need information other than EDID. They typically have some
requirements regarding the power up sequence that aren't to be found
anywhere in EDID or detectable by some other mechanism. A decision was
therefore made a long time ago to require panels to be listed in DT with
a specific compatible string. That way all of these details can be
stashed away in drivers that know how to deal with these kinds of
details.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-03  8:47       ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-03  8:47 UTC (permalink / raw)
  To: Rob Herring
  Cc: Yakir Yang, Heiko Stuebner, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel

[-- Attachment #1: Type: text/plain, Size: 582 bytes --]

On Wed, Sep 02, 2015 at 03:17:57PM -0500, Rob Herring wrote:
[...]
> Are there any eDP panels which don't have EDID and need panel details in DT?

Most panels need information other than EDID. They typically have some
requirements regarding the power up sequence that aren't to be found
anywhere in EDID or detectable by some other mechanism. A decision was
therefore made a long time ago to require panels to be listed in DT with
a specific compatible string. That way all of these details can be
stashed away in drivers that know how to deal with these kinds of
details.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-03  8:47       ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-03  8:47 UTC (permalink / raw)
  To: linux-arm-kernel

On Wed, Sep 02, 2015 at 03:17:57PM -0500, Rob Herring wrote:
[...]
> Are there any eDP panels which don't have EDID and need panel details in DT?

Most panels need information other than EDID. They typically have some
requirements regarding the power up sequence that aren't to be found
anywhere in EDID or detectable by some other mechanism. A decision was
therefore made a long time ago to require panels to be listed in DT with
a specific compatible string. That way all of these details can be
stashed away in drivers that know how to deal with these kinds of
details.

Thierry
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2015-09-03  4:27       ` Yakir Yang
  (?)
@ 2015-09-03  9:04         ` Thierry Reding
  -1 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-03  9:04 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Rob Herring, Heiko Stuebner, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

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On Thu, Sep 03, 2015 at 12:27:47PM +0800, Yakir Yang wrote:
> Hi Rob,
> 
> 在 09/03/2015 04:17 AM, Rob Herring 写道:
> >On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> >>Some edp screen do not have hpd signal, so we can't just return
> >>failed when hpd plug in detect failed.
> >This is a property of the panel (or connector perhaps), so this
> >property should be located there. At least, it is a common issue and
> >not specific to this chip. We could have an HDMI connector and failed
> >to hook up HPD for example. A connector node is also where hpd-gpios
> >should be located instead (and are already defined by
> >../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
> >binding, too.
> 
> Yep, I agree with your front point, it is a property of panel, not specific
> to eDP controller, so this code should handle in connector logic.

From your description it sounds more like this is in fact a property of
the panel. Or maybe I should say "quirk". If the panel doesn't generate
the HPD signal, then that should be a property of the panel, not the
connector. The eDP specification mandates that connectors have a HPD
signal, though it allows the "HPD conductor in the connector cable" to
be omitted if not used by the source. I'd consider the cable to belong
to the panel rather than the connector, so absence of HPD, either
because the cable doesn't have the conductor or because the panel does
not generate the signal, should be a quirk of the panel.

That said you could have a panel that supports HPD connected via a cable
that doesn't transmit it, so this would be a per-board variant and hence
should be a device tree property rather than hard-coded in some panel
driver.

Conversely, if the panel isn't capable of generating an HPD signal, then
I don't think it would be appropriate to make it a DT property. It would
be better to hard-code it in the driver, lest someone forget to set the
property in DT and get stuck with a device that isn't operational.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-03  9:04         ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-03  9:04 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Rob Herring, Heiko Stuebner, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel

[-- Attachment #1: Type: text/plain, Size: 2064 bytes --]

On Thu, Sep 03, 2015 at 12:27:47PM +0800, Yakir Yang wrote:
> Hi Rob,
> 
> 在 09/03/2015 04:17 AM, Rob Herring 写道:
> >On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> >>Some edp screen do not have hpd signal, so we can't just return
> >>failed when hpd plug in detect failed.
> >This is a property of the panel (or connector perhaps), so this
> >property should be located there. At least, it is a common issue and
> >not specific to this chip. We could have an HDMI connector and failed
> >to hook up HPD for example. A connector node is also where hpd-gpios
> >should be located instead (and are already defined by
> >../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
> >binding, too.
> 
> Yep, I agree with your front point, it is a property of panel, not specific
> to eDP controller, so this code should handle in connector logic.

From your description it sounds more like this is in fact a property of
the panel. Or maybe I should say "quirk". If the panel doesn't generate
the HPD signal, then that should be a property of the panel, not the
connector. The eDP specification mandates that connectors have a HPD
signal, though it allows the "HPD conductor in the connector cable" to
be omitted if not used by the source. I'd consider the cable to belong
to the panel rather than the connector, so absence of HPD, either
because the cable doesn't have the conductor or because the panel does
not generate the signal, should be a quirk of the panel.

That said you could have a panel that supports HPD connected via a cable
that doesn't transmit it, so this would be a per-board variant and hence
should be a device tree property rather than hard-coded in some panel
driver.

Conversely, if the panel isn't capable of generating an HPD signal, then
I don't think it would be appropriate to make it a DT property. It would
be better to hard-code it in the driver, lest someone forget to set the
property in DT and get stuck with a device that isn't operational.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-03  9:04         ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-03  9:04 UTC (permalink / raw)
  To: linux-arm-kernel

On Thu, Sep 03, 2015 at 12:27:47PM +0800, Yakir Yang wrote:
> Hi Rob,
> 
> ? 09/03/2015 04:17 AM, Rob Herring ??:
> >On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> >>Some edp screen do not have hpd signal, so we can't just return
> >>failed when hpd plug in detect failed.
> >This is a property of the panel (or connector perhaps), so this
> >property should be located there. At least, it is a common issue and
> >not specific to this chip. We could have an HDMI connector and failed
> >to hook up HPD for example. A connector node is also where hpd-gpios
> >should be located instead (and are already defined by
> >../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
> >binding, too.
> 
> Yep, I agree with your front point, it is a property of panel, not specific
> to eDP controller, so this code should handle in connector logic.

>From your description it sounds more like this is in fact a property of
the panel. Or maybe I should say "quirk". If the panel doesn't generate
the HPD signal, then that should be a property of the panel, not the
connector. The eDP specification mandates that connectors have a HPD
signal, though it allows the "HPD conductor in the connector cable" to
be omitted if not used by the source. I'd consider the cable to belong
to the panel rather than the connector, so absence of HPD, either
because the cable doesn't have the conductor or because the panel does
not generate the signal, should be a quirk of the panel.

That said you could have a panel that supports HPD connected via a cable
that doesn't transmit it, so this would be a per-board variant and hence
should be a device tree property rather than hard-coded in some panel
driver.

Conversely, if the panel isn't capable of generating an HPD signal, then
I don't think it would be appropriate to make it a DT property. It would
be better to hard-code it in the driver, lest someone forget to set the
property in DT and get stuck with a device that isn't operational.

Thierry
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
  2015-09-03  3:25       ` Yakir Yang
  (?)
@ 2015-09-03 13:52         ` Heiko Stuebner
  -1 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-03 13:52 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Rob Herring, Thierry Reding, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Am Donnerstag, 3. September 2015, 11:25:00 schrieb Yakir Yang:
> 在 09/02/2015 09:27 PM, Rob Herring 写道:
> > On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> >> +- clocks: from common clock binding: handle to dp clock.
> >> +       of memory mapped region.
> >> +- clock-names: from common clock binding:
> >> +       Required elements: "sclk_dp" "sclk_dp_24m"
> >> +
> >> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> > 
> > I have no idea what GRF means.
> 
> GRF is an module of our IC chip, the full name is General Register Files.
> I would rather to pick some words from our TRM.
> 
> The general register file will be used to do static set by software, which
> is composed of many registers for system control.

The general register files are present on all Rockchip SoCs I've seen so far 
and really are just an aggregation of registers for settings and status 
indications, ranging from memory stuff, dma-controller settings, usb-phy and 
settings for a lot of other phys, etc.

The most prevalent description in dt-bindings is currently:

- rockchip,grf: phandle to the syscon managing the "general register files"


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-03 13:52         ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-03 13:52 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Rob Herring, Thierry Reding, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel

Am Donnerstag, 3. September 2015, 11:25:00 schrieb Yakir Yang:
> 在 09/02/2015 09:27 PM, Rob Herring 写道:
> > On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> >> +- clocks: from common clock binding: handle to dp clock.
> >> +       of memory mapped region.
> >> +- clock-names: from common clock binding:
> >> +       Required elements: "sclk_dp" "sclk_dp_24m"
> >> +
> >> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> > 
> > I have no idea what GRF means.
> 
> GRF is an module of our IC chip, the full name is General Register Files.
> I would rather to pick some words from our TRM.
> 
> The general register file will be used to do static set by software, which
> is composed of many registers for system control.

The general register files are present on all Rockchip SoCs I've seen so far 
and really are just an aggregation of registers for settings and status 
indications, ranging from memory stuff, dma-controller settings, usb-phy and 
settings for a lot of other phys, etc.

The most prevalent description in dt-bindings is currently:

- rockchip,grf: phandle to the syscon managing the "general register files"


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-03 13:52         ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-03 13:52 UTC (permalink / raw)
  To: linux-arm-kernel

Am Donnerstag, 3. September 2015, 11:25:00 schrieb Yakir Yang:
> ? 09/02/2015 09:27 PM, Rob Herring ??:
> > On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> >> +- clocks: from common clock binding: handle to dp clock.
> >> +       of memory mapped region.
> >> +- clock-names: from common clock binding:
> >> +       Required elements: "sclk_dp" "sclk_dp_24m"
> >> +
> >> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> > 
> > I have no idea what GRF means.
> 
> GRF is an module of our IC chip, the full name is General Register Files.
> I would rather to pick some words from our TRM.
> 
> The general register file will be used to do static set by software, which
> is composed of many registers for system control.

The general register files are present on all Rockchip SoCs I've seen so far 
and really are just an aggregation of registers for settings and status 
indications, ranging from memory stuff, dma-controller settings, usb-phy and 
settings for a lot of other phys, etc.

The most prevalent description in dt-bindings is currently:

- rockchip,grf: phandle to the syscon managing the "general register files"


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2015-09-03  8:47       ` Thierry Reding
  (?)
@ 2015-09-03 21:55         ` Rob Herring
  -1 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-03 21:55 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Yakir Yang, Heiko Stuebner, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

On Thu, Sep 3, 2015 at 3:47 AM, Thierry Reding <treding@nvidia.com> wrote:
> On Wed, Sep 02, 2015 at 03:17:57PM -0500, Rob Herring wrote:
> [...]
>> Are there any eDP panels which don't have EDID and need panel details in DT?
>
> Most panels need information other than EDID. They typically have some
> requirements regarding the power up sequence that aren't to be found
> anywhere in EDID or detectable by some other mechanism. A decision was
> therefore made a long time ago to require panels to be listed in DT with
> a specific compatible string. That way all of these details can be
> stashed away in drivers that know how to deal with these kinds of
> details.

I guess I was being hopeful that eDP was improving that situation.

Rob

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-03 21:55         ` Rob Herring
  0 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-03 21:55 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Yakir Yang, Heiko Stuebner, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel

On Thu, Sep 3, 2015 at 3:47 AM, Thierry Reding <treding@nvidia.com> wrote:
> On Wed, Sep 02, 2015 at 03:17:57PM -0500, Rob Herring wrote:
> [...]
>> Are there any eDP panels which don't have EDID and need panel details in DT?
>
> Most panels need information other than EDID. They typically have some
> requirements regarding the power up sequence that aren't to be found
> anywhere in EDID or detectable by some other mechanism. A decision was
> therefore made a long time ago to require panels to be listed in DT with
> a specific compatible string. That way all of these details can be
> stashed away in drivers that know how to deal with these kinds of
> details.

I guess I was being hopeful that eDP was improving that situation.

Rob

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-03 21:55         ` Rob Herring
  0 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-03 21:55 UTC (permalink / raw)
  To: linux-arm-kernel

On Thu, Sep 3, 2015 at 3:47 AM, Thierry Reding <treding@nvidia.com> wrote:
> On Wed, Sep 02, 2015 at 03:17:57PM -0500, Rob Herring wrote:
> [...]
>> Are there any eDP panels which don't have EDID and need panel details in DT?
>
> Most panels need information other than EDID. They typically have some
> requirements regarding the power up sequence that aren't to be found
> anywhere in EDID or detectable by some other mechanism. A decision was
> therefore made a long time ago to require panels to be listed in DT with
> a specific compatible string. That way all of these details can be
> stashed away in drivers that know how to deal with these kinds of
> details.

I guess I was being hopeful that eDP was improving that situation.

Rob

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support
  2015-09-01  6:07   ` Yakir Yang
@ 2015-09-04  0:36     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-04  0:36 UTC (permalink / raw)
  To: Yakir Yang, Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

On 01.09.2015 15:07, Yakir Yang wrote:

Empty commit message. Please explain here why you want to add platform
device type support.

Actually the title is confusing. You are not adding support for platform
device types but rather adding a field containing type of device.


> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Add GNU license v2 declared and samsung copyright
> 
>  drivers/gpu/drm/exynos/exynos_dp.c              |  1 +
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c |  1 +
>  include/drm/bridge/analogix_dp.h                | 16 ++++++++++++++++
>  3 files changed, 18 insertions(+)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
> index 6060d2c..40ef727 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
> @@ -224,6 +224,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>  	dp->dev = dev;
>  	dp->drm_dev = drm_dev;
>  
> +	dp->plat_data.dev_type = EXYNOS_DP;
>  	dp->plat_data.power_on = exynos_dp_poweron;
>  	dp->plat_data.power_off = exynos_dp_poweroff;
>  	dp->plat_data.get_modes = exynos_dp_get_modes;
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> index efea045..4934271 100644
> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -293,6 +293,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
>  		return ret;
>  	}
>  
> +	dp->plat_data.dev_type = RK3288_DP;
>  	dp->plat_data.attach = NULL;
>  	dp->plat_data.get_modes = NULL;
>  	dp->plat_data.power_on = rockchip_dp_poweron;
> diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
> index 8b4ffad..7209a64 100644
> --- a/include/drm/bridge/analogix_dp.h
> +++ b/include/drm/bridge/analogix_dp.h
> @@ -1,9 +1,25 @@
> +/*
> + * Analogix Core DP (Display Port) interface driver.
> + *
> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */

Two questions:
1. Why this change is here? I would rather expect it at patch 3/16 when
you created this file... That is the usual time for adding copyrights.

2. Does this file contains previous Samsung work?

Best regards,
Krzysztof

>  #ifndef _ANALOGIX_DP_H_
>  #define _ANALOGIX_DP_H_
>  
>  #include <drm/drm_crtc.h>
>  
> +enum analogix_dp_devtype {
> +	EXYNOS_DP,
> +	RK3288_DP,
> +};
> +
>  struct analogix_dp_plat_data {
> +	enum analogix_dp_devtype dev_type;
>  	struct drm_panel *panel;
>  
>  	int (*power_on)(struct analogix_dp_plat_data *);
> 


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support
@ 2015-09-04  0:36     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-04  0:36 UTC (permalink / raw)
  To: linux-arm-kernel

On 01.09.2015 15:07, Yakir Yang wrote:

Empty commit message. Please explain here why you want to add platform
device type support.

Actually the title is confusing. You are not adding support for platform
device types but rather adding a field containing type of device.


> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Add GNU license v2 declared and samsung copyright
> 
>  drivers/gpu/drm/exynos/exynos_dp.c              |  1 +
>  drivers/gpu/drm/rockchip/analogix_dp-rockchip.c |  1 +
>  include/drm/bridge/analogix_dp.h                | 16 ++++++++++++++++
>  3 files changed, 18 insertions(+)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
> index 6060d2c..40ef727 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
> @@ -224,6 +224,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>  	dp->dev = dev;
>  	dp->drm_dev = drm_dev;
>  
> +	dp->plat_data.dev_type = EXYNOS_DP;
>  	dp->plat_data.power_on = exynos_dp_poweron;
>  	dp->plat_data.power_off = exynos_dp_poweroff;
>  	dp->plat_data.get_modes = exynos_dp_get_modes;
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> index efea045..4934271 100644
> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -293,6 +293,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
>  		return ret;
>  	}
>  
> +	dp->plat_data.dev_type = RK3288_DP;
>  	dp->plat_data.attach = NULL;
>  	dp->plat_data.get_modes = NULL;
>  	dp->plat_data.power_on = rockchip_dp_poweron;
> diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
> index 8b4ffad..7209a64 100644
> --- a/include/drm/bridge/analogix_dp.h
> +++ b/include/drm/bridge/analogix_dp.h
> @@ -1,9 +1,25 @@
> +/*
> + * Analogix Core DP (Display Port) interface driver.
> + *
> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */

Two questions:
1. Why this change is here? I would rather expect it at patch 3/16 when
you created this file... That is the usual time for adding copyrights.

2. Does this file contains previous Samsung work?

Best regards,
Krzysztof

>  #ifndef _ANALOGIX_DP_H_
>  #define _ANALOGIX_DP_H_
>  
>  #include <drm/drm_crtc.h>
>  
> +enum analogix_dp_devtype {
> +	EXYNOS_DP,
> +	RK3288_DP,
> +};
> +
>  struct analogix_dp_plat_data {
> +	enum analogix_dp_devtype dev_type;
>  	struct drm_panel *panel;
>  
>  	int (*power_on)(struct analogix_dp_plat_data *);
> 

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
  2015-09-03  5:30       ` Yakir Yang
@ 2015-09-04  0:41         ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-04  0:41 UTC (permalink / raw)
  To: Yakir Yang, Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

On 03.09.2015 14:30, Yakir Yang wrote:
> Hi Krzysztof,
> 
> 在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
>> On 01.09.2015 14:49, Yakir Yang wrote:
>>> Split the dp core driver from exynos directory to bridge
>>> directory, and rename the core driver to analogix_dp_*,
>>> leave the platform code to analogix_dp-exynos.
>>>
>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>> ---
>>> Changes in v4:
>>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT
>>> propery.
>>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to
>>> "exynos_dp.c"
>>> - Take Archit suggest, create a separate folder for analogix code in
>>> bridge/
>>>
>>> Changes in v3:
>>> - Take Thierry Reding suggest, move exynos's video_timing code
>>>    to analogix_dp-exynos platform driver, add get_modes method
>>>    to struct analogix_dp_plat_data.
>>> - Take Heiko suggest, rename some "samsung*" dts propery to "analogix*".
>>>
>>> Changes in v2:
>>> - Take Jingoo Han suggest, remove new copyright
>>> - Fix compiled failed dut to analogix_dp_device misspell
>>>
>>>   drivers/gpu/drm/bridge/Kconfig                     |    2 +
>>>   drivers/gpu/drm/bridge/Makefile                    |    1 +
>>>   drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
>>>   drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
>>>   .../analogix/analogix_dp_core.c}                   |  817
>>> ++++++-------
>>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  283 +++++
>>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1265
>>> ++++++++++++++++++++
>>>   .../analogix/analogix_dp_reg.h}                    |  258 ++--
>>>   drivers/gpu/drm/exynos/Kconfig                     |    3 +-
>>>   drivers/gpu/drm/exynos/Makefile                    |    2 +-
>>>   drivers/gpu/drm/exynos/exynos_dp.c                 |  306 +++++
>>>   drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 -----
>>>   drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1259
>>> -------------------
>>>   include/drm/bridge/analogix_dp.h                   |   24 +
>>>   14 files changed, 2357 insertions(+), 2150 deletions(-)
>>>   create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
>>>   create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
>>>   rename drivers/gpu/drm/{exynos/exynos_dp_core.c =>
>>> bridge/analogix/analogix_dp_core.c} (50%)
>>>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>>>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>>>   rename drivers/gpu/drm/{exynos/exynos_dp_reg.h =>
>>> bridge/analogix/analogix_dp_reg.h} (64%)
>>>   create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
>>>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
>>>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
>>>   create mode 100644 include/drm/bridge/analogix_dp.h
>>>
>>> diff --git a/drivers/gpu/drm/bridge/Kconfig
>>> b/drivers/gpu/drm/bridge/Kconfig
>>> index 2de52a5..7b5b77a 100644
>>> --- a/drivers/gpu/drm/bridge/Kconfig
>>> +++ b/drivers/gpu/drm/bridge/Kconfig
>>> @@ -29,4 +29,6 @@ config DRM_PARADE_PS8622
>>>       ---help---
>>>         Parade eDP-LVDS bridge chip driver.
>>>   +source "drivers/gpu/drm/bridge/analogix/Kconfig"
>>> +
>>>   endmenu
>>> diff --git a/drivers/gpu/drm/bridge/Makefile
>>> b/drivers/gpu/drm/bridge/Makefile
>>> index e2eef1c..5366c6b 100644
>>> --- a/drivers/gpu/drm/bridge/Makefile
>>> +++ b/drivers/gpu/drm/bridge/Makefile
>>> @@ -3,3 +3,4 @@ ccflags-y := -Iinclude/drm
>>>   obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o
>>>   obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
>>>   obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
>>> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
>>> diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig
>>> b/drivers/gpu/drm/bridge/analogix/Kconfig
>>> new file mode 100644
>>> index 0000000..5ff6551
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
>>> @@ -0,0 +1,4 @@
>>> +config DRM_ANALOGIX_DP
>>> +    tristate
>>> +    depends on DRM
>>> +    select DRM_KMS_HELPER
>>> diff --git a/drivers/gpu/drm/bridge/analogix/Makefile
>>> b/drivers/gpu/drm/bridge/analogix/Makefile
>>> new file mode 100644
>>> index 0000000..9107b86
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/bridge/analogix/Makefile
>>> @@ -0,0 +1 @@
>>> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>>> similarity index 50%
>>> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
>>> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>>> index bed0252..7d62f22 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>>> @@ -1,14 +1,14 @@
>>>   /*
>>> - * Samsung SoC DP (Display Port) interface driver.
>>> - *
>>> - * Copyright (C) 2012 Samsung Electronics Co., Ltd.
>>> - * Author: Jingoo Han <jg1.han@samsung.com>
>>> - *
>>> - * This program is free software; you can redistribute it and/or
>>> modify it
>>> - * under the terms of the GNU General Public License as published by
>>> the
>>> - * Free Software Foundation; either version 2 of the License, or (at
>>> your
>>> - * option) any later version.
>>> - */
>>> +* Analogix DP (Display Port) core interface driver.
>>> +*
>>> +* Copyright (C) 2012 Samsung Electronics Co., Ltd.
>>> +* Author: Jingoo Han <jg1.han@samsung.com>
>>> +*
>>> +* This program is free software; you can redistribute it and/or
>>> modify it
>>> +* under the terms of the GNU General Public License as published by the
>>> +* Free Software Foundation; either version 2 of the License, or (at
>>> your
>>> +* option) any later version.
>>> +*/
>>>     #include <linux/module.h>
>>>   #include <linux/platform_device.h>
>>> @@ -18,12 +18,9 @@
>>>   #include <linux/interrupt.h>
>>>   #include <linux/of.h>
>>>   #include <linux/of_gpio.h>
>>> -#include <linux/of_graph.h>
>>>   #include <linux/gpio.h>
>>>   #include <linux/component.h>
>>>   #include <linux/phy/phy.h>
>>> -#include <video/of_display_timing.h>
>>> -#include <video/of_videomode.h>
>>>     #include <drm/drmP.h>
>>>   #include <drm/drm_crtc.h>
>>> @@ -31,52 +28,42 @@
>>>   #include <drm/drm_atomic_helper.h>
>>>   #include <drm/drm_panel.h>
>>>   -#include "exynos_dp_core.h"
>>> -#include "exynos_drm_crtc.h"
>>> +#include <drm/bridge/analogix_dp.h>
>>>   -#define ctx_from_connector(c)    container_of(c, struct
>>> exynos_dp_device, \
>>> -                    connector)
>>> +#include "analogix_dp_core.h"
>>>   -static inline struct exynos_drm_crtc *dp_to_crtc(struct
>>> exynos_dp_device *dp)
>>> -{
>>> -    return to_exynos_crtc(dp->encoder.crtc);
>>> -}
>>> -
>>> -static inline struct exynos_dp_device *encoder_to_dp(
>>> -                        struct drm_encoder *e)
>>> -{
>>> -    return container_of(e, struct exynos_dp_device, encoder);
>>> -}
>>> +#define connector_to_dp(c) \
>>> +    container_of(c, struct analogix_dp_device, connector)
>>>     struct bridge_init {
>>>       struct i2c_client *client;
>>>       struct device_node *node;
>>>   };
>>>   -static void exynos_dp_init_dp(struct exynos_dp_device *dp)
>>> +static void analogix_dp_init_dp(struct analogix_dp_device *dp)
>>>   {
>>> -    exynos_dp_reset(dp);
>>> +    analogix_dp_reset(dp);
>>>   -    exynos_dp_swreset(dp);
>>> +    analogix_dp_swreset(dp);
>>>   -    exynos_dp_init_analog_param(dp);
>>> -    exynos_dp_init_interrupt(dp);
>>> +    analogix_dp_init_analog_param(dp);
>>> +    analogix_dp_init_interrupt(dp);
>>>         /* SW defined function Normal operation */
>>> -    exynos_dp_enable_sw_function(dp);
>>> +    analogix_dp_enable_sw_function(dp);
>>>   -    exynos_dp_config_interrupt(dp);
>>> -    exynos_dp_init_analog_func(dp);
>>> +    analogix_dp_config_interrupt(dp);
>>> +    analogix_dp_init_analog_func(dp);
>>>   -    exynos_dp_init_hpd(dp);
>>> -    exynos_dp_init_aux(dp);
>>> +    analogix_dp_init_hpd(dp);
>>> +    analogix_dp_init_aux(dp);
>>>   }
>>>   -static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
>>> +static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
>>>   {
>>>       int timeout_loop = 0;
>>>   -    while (exynos_dp_get_plug_in_status(dp) != 0) {
>>> +    while (analogix_dp_get_plug_in_status(dp) != 0) {
>>>           timeout_loop++;
>>>           if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
>>>               dev_err(dp->dev, "failed to get hpd plug status\n");
>>> @@ -88,7 +75,7 @@ static int exynos_dp_detect_hpd(struct
>>> exynos_dp_device *dp)
>>>       return 0;
>>>   }
>>>   -static unsigned char exynos_dp_calc_edid_check_sum(unsigned char
>>> *edid_data)
>>> +static unsigned char analogix_dp_calc_edid_check_sum(unsigned char
>>> *edid_data)
>>>   {
>>>       int i;
>>>       unsigned char sum = 0;
>>> @@ -99,7 +86,7 @@ static unsigned char
>>> exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
>>>       return sum;
>>>   }
>>>   -static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>> +static int analogix_dp_read_edid(struct analogix_dp_device *dp)
>>>   {
>>>       unsigned char edid[EDID_BLOCK_LENGTH * 2];
>>>       unsigned int extend_block = 0;
>>> @@ -114,9 +101,9 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>>>        */
>>>         /* Read Extension Flag, Number of 128-byte EDID extension
>>> blocks */
>>> -    retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>>> -                          EDID_EXTENSION_FLAG,
>>> -                          &extend_block);
>>> +    retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>>> +                        EDID_EXTENSION_FLAG,
>>> +                        &extend_block);
>> Hi,
>>
>> What was the point of patch 1 (checkpatch -f --subjective) if you
>> have to re-align the parameters again? It's meaningless.
>>
>> I could understand that idea if this patch touched only first
>> line - name of the function. This would result in small
>> and effective diff, like:
>>
>> -    retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>> +    retval = SAME_LEGNTH____byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>>                             EDID_EXTENSION_FLAG,
>>
>> But this is not the case. The reviewer have to look at 6 lines
>> of changes instead of two. You fixed the alignment just for two
>> patches and then you re-written it. It's meaningless.
> 
> Yes, this is the place that crazy me too. After rename "exynos"
> to "analogix", there would bring some "over-80-char" problem :(

If you can't avoid it then it's okay. When you rename the function this
could happen and then you just re-align the block.

> 
>> Nope. Please drop all changes from patch 1 which:
>> (all conditions apply):
>> 1. change alignment,
>> 2. are immediately changed in next patches (e.g. like here),
>>
>> and fix the alignment while renaming the function.
>>
>> This is actually another point for not accepting commits where
>> the reason is "checkpatch told me".
> 
> Okay, so there would be two patches to fix the alignment, done.
> 
> Thanks for your careful remind.

Two patches but fixing alignment in different places. Do not fix the
alignment in 1/16 and then re-align the same line at 3/16.


> 
>>
>>
>>>       if (retval)
>>>           return retval;
>>>   @@ -124,7 +111,7 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>>>           dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>>>             /* Read EDID data */
>>> -        retval = exynos_dp_read_bytes_from_i2c(
>>> +        retval = analogix_dp_read_bytes_from_i2c(
>>>                       dp, I2C_EDID_DEVICE_ADDR,
>>>                       EDID_HEADER_PATTERN,
>>>                       EDID_BLOCK_LENGTH,
>>> @@ -133,14 +120,14 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>> (...)
>>
>>> @@ -871,218 +862,204 @@ static irqreturn_t exynos_dp_irq_handler(int
>>> irq, void *arg)
>>>       return IRQ_HANDLED;
>>>   }
>>>   -static void exynos_dp_hotplug(struct work_struct *work)
>>> +static void analogix_dp_hotplug(struct work_struct *work)
>>>   {
>>> -    struct exynos_dp_device *dp;
>>> +    struct analogix_dp_device *dp;
>>>   -    dp = container_of(work, struct exynos_dp_device, hotplug_work);
>>> +    dp = container_of(work, struct analogix_dp_device, hotplug_work);
>>>         if (dp->drm_dev)
>>>           drm_helper_hpd_irq_event(dp->drm_dev);
>>>   }
>>>   -static void exynos_dp_commit(struct drm_encoder *encoder)
>>> +static void analogix_dp_commit(struct analogix_dp_device *dp)
>>>   {
>>> -    struct exynos_dp_device *dp = encoder_to_dp(encoder);
>>>       int ret;
>>>         /* Keep the panel disabled while we configure video */
>>> -    if (dp->panel) {
>>> -        if (drm_panel_disable(dp->panel))
>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>> +        if (drm_panel_disable(dp->plat_data->panel))
>>>               DRM_ERROR("failed to disable the panel\n");
>>>       }
>>>   -    ret = exynos_dp_detect_hpd(dp);
>>> +    ret = analogix_dp_detect_hpd(dp);
>>>       if (ret) {
>>>           /* Cable has been disconnected, we're done */
>>>           return;
>>>       }
>>>   -    ret = exynos_dp_handle_edid(dp);
>>> +    ret = analogix_dp_handle_edid(dp);
>>>       if (ret) {
>>>           dev_err(dp->dev, "unable to handle edid\n");
>>>           return;
>>>       }
>>>   -    ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
>>> -                       dp->video_info->link_rate);
>>> +    ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
>>> +                     dp->video_info->link_rate);
>>>       if (ret) {
>>>           dev_err(dp->dev, "unable to do link train\n");
>>>           return;
>>>       }
>>>   -    exynos_dp_enable_scramble(dp, 1);
>>> -    exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
>>> -    exynos_dp_enable_enhanced_mode(dp, 1);
>>> +    analogix_dp_enable_scramble(dp, 1);
>>> +    analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
>>> +    analogix_dp_enable_enhanced_mode(dp, 1);
>>>   -    exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
>>> -    exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
>>> +    analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
>>> +    analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
>>>   -    exynos_dp_init_video(dp);
>>> -    ret = exynos_dp_config_video(dp);
>>> +    analogix_dp_init_video(dp);
>>> +    ret = analogix_dp_config_video(dp);
>>>       if (ret)
>>>           dev_err(dp->dev, "unable to config video\n");
>>>         /* Safe to enable the panel now */
>>> -    if (dp->panel) {
>>> -        if (drm_panel_enable(dp->panel))
>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>> +        if (drm_panel_enable(dp->plat_data->panel))
>>>               DRM_ERROR("failed to enable the panel\n");
>>>       }
>>>         /* Enable video */
>>> -    exynos_dp_start_video(dp);
>>> +    analogix_dp_start_video(dp);
>>>   }
>>>     static enum drm_connector_status
>>> -exynos_dp_detect(struct drm_connector *connector, bool force)
>>> +analogix_dp_detect(struct drm_connector *connector, bool force)
>>>   {
>>>       return connector_status_connected;
>>>   }
>>>   -static void exynos_dp_connector_destroy(struct drm_connector
>>> *connector)
>>> +static void analogix_dp_connector_destroy(struct drm_connector
>>> *connector)
>>>   {
>>>       drm_connector_unregister(connector);
>>>       drm_connector_cleanup(connector);
>>>   }
>>>   -static struct drm_connector_funcs exynos_dp_connector_funcs = {
>>> +static struct drm_connector_funcs analogix_dp_connector_funcs = {
>>>       .dpms = drm_atomic_helper_connector_dpms,
>>>       .fill_modes = drm_helper_probe_single_connector_modes,
>>> -    .detect = exynos_dp_detect,
>>> -    .destroy = exynos_dp_connector_destroy,
>>> +    .detect = analogix_dp_detect,
>>> +    .destroy = analogix_dp_connector_destroy,
>>>       .reset = drm_atomic_helper_connector_reset,
>>>       .atomic_duplicate_state =
>>> drm_atomic_helper_connector_duplicate_state,
>>>       .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>>>   };
>>>   -static int exynos_dp_get_modes(struct drm_connector *connector)
>>> +static int analogix_dp_get_modes(struct drm_connector *connector)
>>>   {
>>> -    struct exynos_dp_device *dp = ctx_from_connector(connector);
>>> -    struct drm_display_mode *mode;
>>> -
>>> -    if (dp->panel)
>>> -        return drm_panel_get_modes(dp->panel);
>>> +    struct analogix_dp_device *dp = connector_to_dp(connector);
>>> +    struct analogix_dp_plat_data *plat_data = dp->plat_data;
>>> +    int num_modes = 0;
>>>   -    mode = drm_mode_create(connector->dev);
>>> -    if (!mode) {
>>> -        DRM_ERROR("failed to create a new display mode.\n");
>>> -        return 0;
>>> -    }
>>> -
>>> -    drm_display_mode_from_videomode(&dp->priv.vm, mode);
>>> -    mode->width_mm = dp->priv.width_mm;
>>> -    mode->height_mm = dp->priv.height_mm;
>>> -    connector->display_info.width_mm = mode->width_mm;
>>> -    connector->display_info.height_mm = mode->height_mm;
>>> +    if (plat_data && plat_data->panel)
>>> +        num_modes += drm_panel_get_modes(plat_data->panel);
>>>   -    mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
>>> -    drm_mode_set_name(mode);
>>> -    drm_mode_probed_add(connector, mode);
>>> +    if (plat_data && plat_data->get_modes)
>>> +         num_modes += plat_data->get_modes(plat_data, connector);
>>>   -    return 1;
>>> +    return num_modes;
>>>   }
>>>     static struct drm_encoder *
>>> -exynos_dp_best_encoder(struct drm_connector *connector)
>>> +analogix_dp_best_encoder(struct drm_connector *connector)
>>>   {
>>> -    struct exynos_dp_device *dp = ctx_from_connector(connector);
>>> +    struct analogix_dp_device *dp = connector_to_dp(connector);
>>>   -    return &dp->encoder;
>>> +    return dp->encoder;
>>>   }
>>>   -static struct drm_connector_helper_funcs
>>> exynos_dp_connector_helper_funcs = {
>>> -    .get_modes = exynos_dp_get_modes,
>>> -    .best_encoder = exynos_dp_best_encoder,
>>> +static struct drm_connector_helper_funcs
>>> analogix_dp_connector_helper_funcs = {
>>> +    .get_modes = analogix_dp_get_modes,
>>> +    .best_encoder = analogix_dp_best_encoder,
>>>   };
>>>   -/* returns the number of bridges attached */
>>> -static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
>>> -                    struct drm_encoder *encoder)
>>> -{
>>> -    int ret;
>>> -
>>> -    encoder->bridge->next = dp->ptn_bridge;
>>> -    dp->ptn_bridge->encoder = encoder;
>>> -    ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
>>> -    if (ret) {
>>> -        DRM_ERROR("Failed to attach bridge to drm\n");
>>> -        return ret;
>>> -    }
>>> -
>>> -    return 0;
>>> -}
>>> -
>>> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
>>> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>>>   {
>>> -    struct exynos_dp_device *dp = bridge->driver_private;
>>> -    struct drm_encoder *encoder = &dp->encoder;
>>> +    struct analogix_dp_device *dp = bridge->driver_private;
>>> +    struct drm_encoder *encoder = dp->encoder;
>>>       struct drm_connector *connector = &dp->connector;
>>>       int ret;
>>>   -    /* Pre-empt DP connector creation if there's a bridge */
>>> -    if (dp->ptn_bridge) {
>>> -        ret = exynos_drm_attach_lcd_bridge(dp, encoder);
>>> -        if (!ret)
>>> -            return 0;
>>> +    if (!bridge->encoder) {
>>> +        DRM_ERROR("Parent encoder object not found");
>>> +        return -ENODEV;
>>>       }
>>>   +    encoder->bridge = bridge;
>>> +
>>>       connector->polled = DRM_CONNECTOR_POLL_HPD;
>>>         ret = drm_connector_init(dp->drm_dev, connector,
>>> -                 &exynos_dp_connector_funcs,
>>> +                 &analogix_dp_connector_funcs,
>>>                    DRM_MODE_CONNECTOR_eDP);
>>>       if (ret) {
>>>           DRM_ERROR("Failed to initialize connector with drm\n");
>>>           return ret;
>>>       }
>>>   -    drm_connector_helper_add(connector,
>>> &exynos_dp_connector_helper_funcs);
>>> +    drm_connector_helper_add(connector,
>>> +                 &analogix_dp_connector_helper_funcs);
>>>       drm_connector_register(connector);
>>>       drm_mode_connector_attach_encoder(connector, encoder);
>>>   -    if (dp->panel)
>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>> +        if (ret) {
>>> +            DRM_ERROR("Failed to attach panel\n");
>>> +            return ret;
>>> +        }
>>> +    }
>>> +
>>> +    /*
>>> +     * This should be the end of attach function, caused
>>> +     * we should ensure dp bridge could attach first.
>>> +     */
>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>> +         if (ret) {
>>> +             DRM_ERROR("Failed at platform attch func\n");
>> Two new error paths appeared here and above. Don't you have to
>> cleanup something? I don't know, just wondering...
> 
> Hmm... I think both panel & platform_attch need ERROR remind when
> it failed. But if it still need clean, I though it is tge platform attch
> error,
> this is not relate to DRM directly, just analogix driver logic, so code
> would
> like.
> 
> -    if (dp->panel)
> -        ret = drm_panel_attach(dp->panel, &dp->connector);
> +    if (dp->plat_data && dp->plat_data->panel) {
> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
> +        if (ret) {
> +            DRM_ERROR("Failed to attach panel\n");
> +            return ret;
> +        }
> +    }
> 
> +    /*
> +     * This should be the end of attach function, caused
> +     * we should ensure dp bridge could attach first.
> +     */
> +     if (dp->plat_data && dp->plat_data->attach) {
> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
> 
>           return ret;

I am lost... the code looks the same. What did you change?

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-04  0:41         ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-04  0:41 UTC (permalink / raw)
  To: linux-arm-kernel

On 03.09.2015 14:30, Yakir Yang wrote:
> Hi Krzysztof,
> 
> ? 09/03/2015 08:58 AM, Krzysztof Kozlowski ??:
>> On 01.09.2015 14:49, Yakir Yang wrote:
>>> Split the dp core driver from exynos directory to bridge
>>> directory, and rename the core driver to analogix_dp_*,
>>> leave the platform code to analogix_dp-exynos.
>>>
>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>> ---
>>> Changes in v4:
>>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT
>>> propery.
>>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to
>>> "exynos_dp.c"
>>> - Take Archit suggest, create a separate folder for analogix code in
>>> bridge/
>>>
>>> Changes in v3:
>>> - Take Thierry Reding suggest, move exynos's video_timing code
>>>    to analogix_dp-exynos platform driver, add get_modes method
>>>    to struct analogix_dp_plat_data.
>>> - Take Heiko suggest, rename some "samsung*" dts propery to "analogix*".
>>>
>>> Changes in v2:
>>> - Take Jingoo Han suggest, remove new copyright
>>> - Fix compiled failed dut to analogix_dp_device misspell
>>>
>>>   drivers/gpu/drm/bridge/Kconfig                     |    2 +
>>>   drivers/gpu/drm/bridge/Makefile                    |    1 +
>>>   drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
>>>   drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
>>>   .../analogix/analogix_dp_core.c}                   |  817
>>> ++++++-------
>>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  283 +++++
>>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1265
>>> ++++++++++++++++++++
>>>   .../analogix/analogix_dp_reg.h}                    |  258 ++--
>>>   drivers/gpu/drm/exynos/Kconfig                     |    3 +-
>>>   drivers/gpu/drm/exynos/Makefile                    |    2 +-
>>>   drivers/gpu/drm/exynos/exynos_dp.c                 |  306 +++++
>>>   drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 -----
>>>   drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1259
>>> -------------------
>>>   include/drm/bridge/analogix_dp.h                   |   24 +
>>>   14 files changed, 2357 insertions(+), 2150 deletions(-)
>>>   create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
>>>   create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
>>>   rename drivers/gpu/drm/{exynos/exynos_dp_core.c =>
>>> bridge/analogix/analogix_dp_core.c} (50%)
>>>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>>>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>>>   rename drivers/gpu/drm/{exynos/exynos_dp_reg.h =>
>>> bridge/analogix/analogix_dp_reg.h} (64%)
>>>   create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
>>>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
>>>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
>>>   create mode 100644 include/drm/bridge/analogix_dp.h
>>>
>>> diff --git a/drivers/gpu/drm/bridge/Kconfig
>>> b/drivers/gpu/drm/bridge/Kconfig
>>> index 2de52a5..7b5b77a 100644
>>> --- a/drivers/gpu/drm/bridge/Kconfig
>>> +++ b/drivers/gpu/drm/bridge/Kconfig
>>> @@ -29,4 +29,6 @@ config DRM_PARADE_PS8622
>>>       ---help---
>>>         Parade eDP-LVDS bridge chip driver.
>>>   +source "drivers/gpu/drm/bridge/analogix/Kconfig"
>>> +
>>>   endmenu
>>> diff --git a/drivers/gpu/drm/bridge/Makefile
>>> b/drivers/gpu/drm/bridge/Makefile
>>> index e2eef1c..5366c6b 100644
>>> --- a/drivers/gpu/drm/bridge/Makefile
>>> +++ b/drivers/gpu/drm/bridge/Makefile
>>> @@ -3,3 +3,4 @@ ccflags-y := -Iinclude/drm
>>>   obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o
>>>   obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
>>>   obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
>>> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
>>> diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig
>>> b/drivers/gpu/drm/bridge/analogix/Kconfig
>>> new file mode 100644
>>> index 0000000..5ff6551
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
>>> @@ -0,0 +1,4 @@
>>> +config DRM_ANALOGIX_DP
>>> +    tristate
>>> +    depends on DRM
>>> +    select DRM_KMS_HELPER
>>> diff --git a/drivers/gpu/drm/bridge/analogix/Makefile
>>> b/drivers/gpu/drm/bridge/analogix/Makefile
>>> new file mode 100644
>>> index 0000000..9107b86
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/bridge/analogix/Makefile
>>> @@ -0,0 +1 @@
>>> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>>> similarity index 50%
>>> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
>>> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>>> index bed0252..7d62f22 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>>> @@ -1,14 +1,14 @@
>>>   /*
>>> - * Samsung SoC DP (Display Port) interface driver.
>>> - *
>>> - * Copyright (C) 2012 Samsung Electronics Co., Ltd.
>>> - * Author: Jingoo Han <jg1.han@samsung.com>
>>> - *
>>> - * This program is free software; you can redistribute it and/or
>>> modify it
>>> - * under the terms of the GNU General Public License as published by
>>> the
>>> - * Free Software Foundation; either version 2 of the License, or (at
>>> your
>>> - * option) any later version.
>>> - */
>>> +* Analogix DP (Display Port) core interface driver.
>>> +*
>>> +* Copyright (C) 2012 Samsung Electronics Co., Ltd.
>>> +* Author: Jingoo Han <jg1.han@samsung.com>
>>> +*
>>> +* This program is free software; you can redistribute it and/or
>>> modify it
>>> +* under the terms of the GNU General Public License as published by the
>>> +* Free Software Foundation; either version 2 of the License, or (at
>>> your
>>> +* option) any later version.
>>> +*/
>>>     #include <linux/module.h>
>>>   #include <linux/platform_device.h>
>>> @@ -18,12 +18,9 @@
>>>   #include <linux/interrupt.h>
>>>   #include <linux/of.h>
>>>   #include <linux/of_gpio.h>
>>> -#include <linux/of_graph.h>
>>>   #include <linux/gpio.h>
>>>   #include <linux/component.h>
>>>   #include <linux/phy/phy.h>
>>> -#include <video/of_display_timing.h>
>>> -#include <video/of_videomode.h>
>>>     #include <drm/drmP.h>
>>>   #include <drm/drm_crtc.h>
>>> @@ -31,52 +28,42 @@
>>>   #include <drm/drm_atomic_helper.h>
>>>   #include <drm/drm_panel.h>
>>>   -#include "exynos_dp_core.h"
>>> -#include "exynos_drm_crtc.h"
>>> +#include <drm/bridge/analogix_dp.h>
>>>   -#define ctx_from_connector(c)    container_of(c, struct
>>> exynos_dp_device, \
>>> -                    connector)
>>> +#include "analogix_dp_core.h"
>>>   -static inline struct exynos_drm_crtc *dp_to_crtc(struct
>>> exynos_dp_device *dp)
>>> -{
>>> -    return to_exynos_crtc(dp->encoder.crtc);
>>> -}
>>> -
>>> -static inline struct exynos_dp_device *encoder_to_dp(
>>> -                        struct drm_encoder *e)
>>> -{
>>> -    return container_of(e, struct exynos_dp_device, encoder);
>>> -}
>>> +#define connector_to_dp(c) \
>>> +    container_of(c, struct analogix_dp_device, connector)
>>>     struct bridge_init {
>>>       struct i2c_client *client;
>>>       struct device_node *node;
>>>   };
>>>   -static void exynos_dp_init_dp(struct exynos_dp_device *dp)
>>> +static void analogix_dp_init_dp(struct analogix_dp_device *dp)
>>>   {
>>> -    exynos_dp_reset(dp);
>>> +    analogix_dp_reset(dp);
>>>   -    exynos_dp_swreset(dp);
>>> +    analogix_dp_swreset(dp);
>>>   -    exynos_dp_init_analog_param(dp);
>>> -    exynos_dp_init_interrupt(dp);
>>> +    analogix_dp_init_analog_param(dp);
>>> +    analogix_dp_init_interrupt(dp);
>>>         /* SW defined function Normal operation */
>>> -    exynos_dp_enable_sw_function(dp);
>>> +    analogix_dp_enable_sw_function(dp);
>>>   -    exynos_dp_config_interrupt(dp);
>>> -    exynos_dp_init_analog_func(dp);
>>> +    analogix_dp_config_interrupt(dp);
>>> +    analogix_dp_init_analog_func(dp);
>>>   -    exynos_dp_init_hpd(dp);
>>> -    exynos_dp_init_aux(dp);
>>> +    analogix_dp_init_hpd(dp);
>>> +    analogix_dp_init_aux(dp);
>>>   }
>>>   -static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
>>> +static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
>>>   {
>>>       int timeout_loop = 0;
>>>   -    while (exynos_dp_get_plug_in_status(dp) != 0) {
>>> +    while (analogix_dp_get_plug_in_status(dp) != 0) {
>>>           timeout_loop++;
>>>           if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
>>>               dev_err(dp->dev, "failed to get hpd plug status\n");
>>> @@ -88,7 +75,7 @@ static int exynos_dp_detect_hpd(struct
>>> exynos_dp_device *dp)
>>>       return 0;
>>>   }
>>>   -static unsigned char exynos_dp_calc_edid_check_sum(unsigned char
>>> *edid_data)
>>> +static unsigned char analogix_dp_calc_edid_check_sum(unsigned char
>>> *edid_data)
>>>   {
>>>       int i;
>>>       unsigned char sum = 0;
>>> @@ -99,7 +86,7 @@ static unsigned char
>>> exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
>>>       return sum;
>>>   }
>>>   -static int exynos_dp_read_edid(struct exynos_dp_device *dp)
>>> +static int analogix_dp_read_edid(struct analogix_dp_device *dp)
>>>   {
>>>       unsigned char edid[EDID_BLOCK_LENGTH * 2];
>>>       unsigned int extend_block = 0;
>>> @@ -114,9 +101,9 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>>>        */
>>>         /* Read Extension Flag, Number of 128-byte EDID extension
>>> blocks */
>>> -    retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>>> -                          EDID_EXTENSION_FLAG,
>>> -                          &extend_block);
>>> +    retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>>> +                        EDID_EXTENSION_FLAG,
>>> +                        &extend_block);
>> Hi,
>>
>> What was the point of patch 1 (checkpatch -f --subjective) if you
>> have to re-align the parameters again? It's meaningless.
>>
>> I could understand that idea if this patch touched only first
>> line - name of the function. This would result in small
>> and effective diff, like:
>>
>> -    retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>> +    retval = SAME_LEGNTH____byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
>>                             EDID_EXTENSION_FLAG,
>>
>> But this is not the case. The reviewer have to look at 6 lines
>> of changes instead of two. You fixed the alignment just for two
>> patches and then you re-written it. It's meaningless.
> 
> Yes, this is the place that crazy me too. After rename "exynos"
> to "analogix", there would bring some "over-80-char" problem :(

If you can't avoid it then it's okay. When you rename the function this
could happen and then you just re-align the block.

> 
>> Nope. Please drop all changes from patch 1 which:
>> (all conditions apply):
>> 1. change alignment,
>> 2. are immediately changed in next patches (e.g. like here),
>>
>> and fix the alignment while renaming the function.
>>
>> This is actually another point for not accepting commits where
>> the reason is "checkpatch told me".
> 
> Okay, so there would be two patches to fix the alignment, done.
> 
> Thanks for your careful remind.

Two patches but fixing alignment in different places. Do not fix the
alignment in 1/16 and then re-align the same line at 3/16.


> 
>>
>>
>>>       if (retval)
>>>           return retval;
>>>   @@ -124,7 +111,7 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>>>           dev_dbg(dp->dev, "EDID data includes a single extension!\n");
>>>             /* Read EDID data */
>>> -        retval = exynos_dp_read_bytes_from_i2c(
>>> +        retval = analogix_dp_read_bytes_from_i2c(
>>>                       dp, I2C_EDID_DEVICE_ADDR,
>>>                       EDID_HEADER_PATTERN,
>>>                       EDID_BLOCK_LENGTH,
>>> @@ -133,14 +120,14 @@ static int exynos_dp_read_edid(struct
>>> exynos_dp_device *dp)
>> (...)
>>
>>> @@ -871,218 +862,204 @@ static irqreturn_t exynos_dp_irq_handler(int
>>> irq, void *arg)
>>>       return IRQ_HANDLED;
>>>   }
>>>   -static void exynos_dp_hotplug(struct work_struct *work)
>>> +static void analogix_dp_hotplug(struct work_struct *work)
>>>   {
>>> -    struct exynos_dp_device *dp;
>>> +    struct analogix_dp_device *dp;
>>>   -    dp = container_of(work, struct exynos_dp_device, hotplug_work);
>>> +    dp = container_of(work, struct analogix_dp_device, hotplug_work);
>>>         if (dp->drm_dev)
>>>           drm_helper_hpd_irq_event(dp->drm_dev);
>>>   }
>>>   -static void exynos_dp_commit(struct drm_encoder *encoder)
>>> +static void analogix_dp_commit(struct analogix_dp_device *dp)
>>>   {
>>> -    struct exynos_dp_device *dp = encoder_to_dp(encoder);
>>>       int ret;
>>>         /* Keep the panel disabled while we configure video */
>>> -    if (dp->panel) {
>>> -        if (drm_panel_disable(dp->panel))
>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>> +        if (drm_panel_disable(dp->plat_data->panel))
>>>               DRM_ERROR("failed to disable the panel\n");
>>>       }
>>>   -    ret = exynos_dp_detect_hpd(dp);
>>> +    ret = analogix_dp_detect_hpd(dp);
>>>       if (ret) {
>>>           /* Cable has been disconnected, we're done */
>>>           return;
>>>       }
>>>   -    ret = exynos_dp_handle_edid(dp);
>>> +    ret = analogix_dp_handle_edid(dp);
>>>       if (ret) {
>>>           dev_err(dp->dev, "unable to handle edid\n");
>>>           return;
>>>       }
>>>   -    ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
>>> -                       dp->video_info->link_rate);
>>> +    ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
>>> +                     dp->video_info->link_rate);
>>>       if (ret) {
>>>           dev_err(dp->dev, "unable to do link train\n");
>>>           return;
>>>       }
>>>   -    exynos_dp_enable_scramble(dp, 1);
>>> -    exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
>>> -    exynos_dp_enable_enhanced_mode(dp, 1);
>>> +    analogix_dp_enable_scramble(dp, 1);
>>> +    analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
>>> +    analogix_dp_enable_enhanced_mode(dp, 1);
>>>   -    exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
>>> -    exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
>>> +    analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
>>> +    analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
>>>   -    exynos_dp_init_video(dp);
>>> -    ret = exynos_dp_config_video(dp);
>>> +    analogix_dp_init_video(dp);
>>> +    ret = analogix_dp_config_video(dp);
>>>       if (ret)
>>>           dev_err(dp->dev, "unable to config video\n");
>>>         /* Safe to enable the panel now */
>>> -    if (dp->panel) {
>>> -        if (drm_panel_enable(dp->panel))
>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>> +        if (drm_panel_enable(dp->plat_data->panel))
>>>               DRM_ERROR("failed to enable the panel\n");
>>>       }
>>>         /* Enable video */
>>> -    exynos_dp_start_video(dp);
>>> +    analogix_dp_start_video(dp);
>>>   }
>>>     static enum drm_connector_status
>>> -exynos_dp_detect(struct drm_connector *connector, bool force)
>>> +analogix_dp_detect(struct drm_connector *connector, bool force)
>>>   {
>>>       return connector_status_connected;
>>>   }
>>>   -static void exynos_dp_connector_destroy(struct drm_connector
>>> *connector)
>>> +static void analogix_dp_connector_destroy(struct drm_connector
>>> *connector)
>>>   {
>>>       drm_connector_unregister(connector);
>>>       drm_connector_cleanup(connector);
>>>   }
>>>   -static struct drm_connector_funcs exynos_dp_connector_funcs = {
>>> +static struct drm_connector_funcs analogix_dp_connector_funcs = {
>>>       .dpms = drm_atomic_helper_connector_dpms,
>>>       .fill_modes = drm_helper_probe_single_connector_modes,
>>> -    .detect = exynos_dp_detect,
>>> -    .destroy = exynos_dp_connector_destroy,
>>> +    .detect = analogix_dp_detect,
>>> +    .destroy = analogix_dp_connector_destroy,
>>>       .reset = drm_atomic_helper_connector_reset,
>>>       .atomic_duplicate_state =
>>> drm_atomic_helper_connector_duplicate_state,
>>>       .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>>>   };
>>>   -static int exynos_dp_get_modes(struct drm_connector *connector)
>>> +static int analogix_dp_get_modes(struct drm_connector *connector)
>>>   {
>>> -    struct exynos_dp_device *dp = ctx_from_connector(connector);
>>> -    struct drm_display_mode *mode;
>>> -
>>> -    if (dp->panel)
>>> -        return drm_panel_get_modes(dp->panel);
>>> +    struct analogix_dp_device *dp = connector_to_dp(connector);
>>> +    struct analogix_dp_plat_data *plat_data = dp->plat_data;
>>> +    int num_modes = 0;
>>>   -    mode = drm_mode_create(connector->dev);
>>> -    if (!mode) {
>>> -        DRM_ERROR("failed to create a new display mode.\n");
>>> -        return 0;
>>> -    }
>>> -
>>> -    drm_display_mode_from_videomode(&dp->priv.vm, mode);
>>> -    mode->width_mm = dp->priv.width_mm;
>>> -    mode->height_mm = dp->priv.height_mm;
>>> -    connector->display_info.width_mm = mode->width_mm;
>>> -    connector->display_info.height_mm = mode->height_mm;
>>> +    if (plat_data && plat_data->panel)
>>> +        num_modes += drm_panel_get_modes(plat_data->panel);
>>>   -    mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
>>> -    drm_mode_set_name(mode);
>>> -    drm_mode_probed_add(connector, mode);
>>> +    if (plat_data && plat_data->get_modes)
>>> +         num_modes += plat_data->get_modes(plat_data, connector);
>>>   -    return 1;
>>> +    return num_modes;
>>>   }
>>>     static struct drm_encoder *
>>> -exynos_dp_best_encoder(struct drm_connector *connector)
>>> +analogix_dp_best_encoder(struct drm_connector *connector)
>>>   {
>>> -    struct exynos_dp_device *dp = ctx_from_connector(connector);
>>> +    struct analogix_dp_device *dp = connector_to_dp(connector);
>>>   -    return &dp->encoder;
>>> +    return dp->encoder;
>>>   }
>>>   -static struct drm_connector_helper_funcs
>>> exynos_dp_connector_helper_funcs = {
>>> -    .get_modes = exynos_dp_get_modes,
>>> -    .best_encoder = exynos_dp_best_encoder,
>>> +static struct drm_connector_helper_funcs
>>> analogix_dp_connector_helper_funcs = {
>>> +    .get_modes = analogix_dp_get_modes,
>>> +    .best_encoder = analogix_dp_best_encoder,
>>>   };
>>>   -/* returns the number of bridges attached */
>>> -static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
>>> -                    struct drm_encoder *encoder)
>>> -{
>>> -    int ret;
>>> -
>>> -    encoder->bridge->next = dp->ptn_bridge;
>>> -    dp->ptn_bridge->encoder = encoder;
>>> -    ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
>>> -    if (ret) {
>>> -        DRM_ERROR("Failed to attach bridge to drm\n");
>>> -        return ret;
>>> -    }
>>> -
>>> -    return 0;
>>> -}
>>> -
>>> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
>>> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>>>   {
>>> -    struct exynos_dp_device *dp = bridge->driver_private;
>>> -    struct drm_encoder *encoder = &dp->encoder;
>>> +    struct analogix_dp_device *dp = bridge->driver_private;
>>> +    struct drm_encoder *encoder = dp->encoder;
>>>       struct drm_connector *connector = &dp->connector;
>>>       int ret;
>>>   -    /* Pre-empt DP connector creation if there's a bridge */
>>> -    if (dp->ptn_bridge) {
>>> -        ret = exynos_drm_attach_lcd_bridge(dp, encoder);
>>> -        if (!ret)
>>> -            return 0;
>>> +    if (!bridge->encoder) {
>>> +        DRM_ERROR("Parent encoder object not found");
>>> +        return -ENODEV;
>>>       }
>>>   +    encoder->bridge = bridge;
>>> +
>>>       connector->polled = DRM_CONNECTOR_POLL_HPD;
>>>         ret = drm_connector_init(dp->drm_dev, connector,
>>> -                 &exynos_dp_connector_funcs,
>>> +                 &analogix_dp_connector_funcs,
>>>                    DRM_MODE_CONNECTOR_eDP);
>>>       if (ret) {
>>>           DRM_ERROR("Failed to initialize connector with drm\n");
>>>           return ret;
>>>       }
>>>   -    drm_connector_helper_add(connector,
>>> &exynos_dp_connector_helper_funcs);
>>> +    drm_connector_helper_add(connector,
>>> +                 &analogix_dp_connector_helper_funcs);
>>>       drm_connector_register(connector);
>>>       drm_mode_connector_attach_encoder(connector, encoder);
>>>   -    if (dp->panel)
>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>> +        if (ret) {
>>> +            DRM_ERROR("Failed to attach panel\n");
>>> +            return ret;
>>> +        }
>>> +    }
>>> +
>>> +    /*
>>> +     * This should be the end of attach function, caused
>>> +     * we should ensure dp bridge could attach first.
>>> +     */
>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>> +         if (ret) {
>>> +             DRM_ERROR("Failed at platform attch func\n");
>> Two new error paths appeared here and above. Don't you have to
>> cleanup something? I don't know, just wondering...
> 
> Hmm... I think both panel & platform_attch need ERROR remind when
> it failed. But if it still need clean, I though it is tge platform attch
> error,
> this is not relate to DRM directly, just analogix driver logic, so code
> would
> like.
> 
> -    if (dp->panel)
> -        ret = drm_panel_attach(dp->panel, &dp->connector);
> +    if (dp->plat_data && dp->plat_data->panel) {
> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
> +        if (ret) {
> +            DRM_ERROR("Failed to attach panel\n");
> +            return ret;
> +        }
> +    }
> 
> +    /*
> +     * This should be the end of attach function, caused
> +     * we should ensure dp bridge could attach first.
> +     */
> +     if (dp->plat_data && dp->plat_data->attach) {
> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
> 
>           return ret;

I am lost... the code looks the same. What did you change?

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2015-09-03 21:55         ` Rob Herring
  (?)
@ 2015-09-04 10:01           ` Thierry Reding
  -1 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-04 10:01 UTC (permalink / raw)
  To: Rob Herring
  Cc: Yakir Yang, Heiko Stuebner, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

[-- Attachment #1: Type: text/plain, Size: 1963 bytes --]

On Thu, Sep 03, 2015 at 04:55:59PM -0500, Rob Herring wrote:
> On Thu, Sep 3, 2015 at 3:47 AM, Thierry Reding <treding@nvidia.com> wrote:
> > On Wed, Sep 02, 2015 at 03:17:57PM -0500, Rob Herring wrote:
> > [...]
> >> Are there any eDP panels which don't have EDID and need panel details in DT?
> >
> > Most panels need information other than EDID. They typically have some
> > requirements regarding the power up sequence that aren't to be found
> > anywhere in EDID or detectable by some other mechanism. A decision was
> > therefore made a long time ago to require panels to be listed in DT with
> > a specific compatible string. That way all of these details can be
> > stashed away in drivers that know how to deal with these kinds of
> > details.
> 
> I guess I was being hopeful that eDP was improving that situation.

Unfortunately not. eDP helps with a number of things (DPCD and link
training take care of a lot of the issues), but it doesn't provide a
solution for everything.

To my knowledge in most cases the power up sequence isn't strictly
necessary to get the panel to operate. But there have been instances
where this is absolutely required if you want to avoid visual artifacts
as you set a mode. A lot of panels that I've come across require
receiving a couple of frames before they guarantee that something will
actually be displayed on the screen. So if your code is too quickly
enabling backlight, and your backlight doesn't happen to have just the
right amount of ramp-up time you might end up seeing garbage on the
screen for a couple of frames.

It would be great if somebody came up with, say, an EDID extension to
describe these requirements, but I'm not sure if even that would give
us panels that could be driven with a generic driver. Often the power
supplies or reset/enable signals are very different across panels. So
describing it all generically would become messy rather quickly.

Thierry

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-04 10:01           ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-04 10:01 UTC (permalink / raw)
  To: Rob Herring
  Cc: Yakir Yang, Heiko Stuebner, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King,
	djkurtz-F7+t8E8rja9Wk0Htik3J/w, dianders-F7+t8E8rja9Wk0Htik3J/w,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, Ajay kumar, Andrzej Hajda,
	Kyungmin Park, David Airlie, Gustavo Padovan, Andy Yan,
	Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt-sgV2jX0FEOL9JmXXK+q4OQ,
	dri-devel

[-- Attachment #1: Type: text/plain, Size: 1992 bytes --]

On Thu, Sep 03, 2015 at 04:55:59PM -0500, Rob Herring wrote:
> On Thu, Sep 3, 2015 at 3:47 AM, Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> > On Wed, Sep 02, 2015 at 03:17:57PM -0500, Rob Herring wrote:
> > [...]
> >> Are there any eDP panels which don't have EDID and need panel details in DT?
> >
> > Most panels need information other than EDID. They typically have some
> > requirements regarding the power up sequence that aren't to be found
> > anywhere in EDID or detectable by some other mechanism. A decision was
> > therefore made a long time ago to require panels to be listed in DT with
> > a specific compatible string. That way all of these details can be
> > stashed away in drivers that know how to deal with these kinds of
> > details.
> 
> I guess I was being hopeful that eDP was improving that situation.

Unfortunately not. eDP helps with a number of things (DPCD and link
training take care of a lot of the issues), but it doesn't provide a
solution for everything.

To my knowledge in most cases the power up sequence isn't strictly
necessary to get the panel to operate. But there have been instances
where this is absolutely required if you want to avoid visual artifacts
as you set a mode. A lot of panels that I've come across require
receiving a couple of frames before they guarantee that something will
actually be displayed on the screen. So if your code is too quickly
enabling backlight, and your backlight doesn't happen to have just the
right amount of ramp-up time you might end up seeing garbage on the
screen for a couple of frames.

It would be great if somebody came up with, say, an EDID extension to
describe these requirements, but I'm not sure if even that would give
us panels that could be driven with a generic driver. Often the power
supplies or reset/enable signals are very different across panels. So
describing it all generically would become messy rather quickly.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-04 10:01           ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-04 10:01 UTC (permalink / raw)
  To: linux-arm-kernel

On Thu, Sep 03, 2015 at 04:55:59PM -0500, Rob Herring wrote:
> On Thu, Sep 3, 2015 at 3:47 AM, Thierry Reding <treding@nvidia.com> wrote:
> > On Wed, Sep 02, 2015 at 03:17:57PM -0500, Rob Herring wrote:
> > [...]
> >> Are there any eDP panels which don't have EDID and need panel details in DT?
> >
> > Most panels need information other than EDID. They typically have some
> > requirements regarding the power up sequence that aren't to be found
> > anywhere in EDID or detectable by some other mechanism. A decision was
> > therefore made a long time ago to require panels to be listed in DT with
> > a specific compatible string. That way all of these details can be
> > stashed away in drivers that know how to deal with these kinds of
> > details.
> 
> I guess I was being hopeful that eDP was improving that situation.

Unfortunately not. eDP helps with a number of things (DPCD and link
training take care of a lot of the issues), but it doesn't provide a
solution for everything.

To my knowledge in most cases the power up sequence isn't strictly
necessary to get the panel to operate. But there have been instances
where this is absolutely required if you want to avoid visual artifacts
as you set a mode. A lot of panels that I've come across require
receiving a couple of frames before they guarantee that something will
actually be displayed on the screen. So if your code is too quickly
enabling backlight, and your backlight doesn't happen to have just the
right amount of ramp-up time you might end up seeing garbage on the
screen for a couple of frames.

It would be great if somebody came up with, say, an EDID extension to
describe these requirements, but I'm not sure if even that would give
us panels that could be driven with a generic driver. Often the power
supplies or reset/enable signals are very different across panels. So
describing it all generically would become messy rather quickly.

Thierry
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2015-09-03  9:04         ` Thierry Reding
  (?)
@ 2015-09-04 10:20           ` Russell King - ARM Linux
  -1 siblings, 0 replies; 370+ messages in thread
From: Russell King - ARM Linux @ 2015-09-04 10:20 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Yakir Yang, Rob Herring, Heiko Stuebner, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

On Thu, Sep 03, 2015 at 11:04:40AM +0200, Thierry Reding wrote:
> Conversely, if the panel isn't capable of generating an HPD signal, then
> I don't think it would be appropriate to make it a DT property. It would
> be better to hard-code it in the driver, lest someone forget to set the
> property in DT and get stuck with a device that isn't operational.

There is another way to deal with this: DRM supports the idea of connector
forcing - where you can force the connector to think that it's connected
or disconnected.

One of the problems is that not many ARM DRM drivers implement it - maybe
it should be a requirement for code to be accepted? :)

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-04 10:20           ` Russell King - ARM Linux
  0 siblings, 0 replies; 370+ messages in thread
From: Russell King - ARM Linux @ 2015-09-04 10:20 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Yakir Yang, Rob Herring, Heiko Stuebner, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel

On Thu, Sep 03, 2015 at 11:04:40AM +0200, Thierry Reding wrote:
> Conversely, if the panel isn't capable of generating an HPD signal, then
> I don't think it would be appropriate to make it a DT property. It would
> be better to hard-code it in the driver, lest someone forget to set the
> property in DT and get stuck with a device that isn't operational.

There is another way to deal with this: DRM supports the idea of connector
forcing - where you can force the connector to think that it's connected
or disconnected.

One of the problems is that not many ARM DRM drivers implement it - maybe
it should be a requirement for code to be accepted? :)

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-04 10:20           ` Russell King - ARM Linux
  0 siblings, 0 replies; 370+ messages in thread
From: Russell King - ARM Linux @ 2015-09-04 10:20 UTC (permalink / raw)
  To: linux-arm-kernel

On Thu, Sep 03, 2015 at 11:04:40AM +0200, Thierry Reding wrote:
> Conversely, if the panel isn't capable of generating an HPD signal, then
> I don't think it would be appropriate to make it a DT property. It would
> be better to hard-code it in the driver, lest someone forget to set the
> property in DT and get stuck with a device that isn't operational.

There is another way to deal with this: DRM supports the idea of connector
forcing - where you can force the connector to think that it's connected
or disconnected.

One of the problems is that not many ARM DRM drivers implement it - maybe
it should be a requirement for code to be accepted? :)

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
  2015-09-01 20:46     ` Heiko Stuebner
  (?)
@ 2015-09-04 21:06       ` Rob Herring
  -1 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-04 21:06 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Yakir Yang, Thierry Reding, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King,
	Ajay kumar, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel, Doug Anderson, Sean Paul, Daniel Kurtz

On Tue, Sep 1, 2015 at 3:46 PM, Heiko Stuebner <heiko@sntech.de> wrote:
> Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code to analogix_dp-exynos.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>
> [...]
>
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
>> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
>> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index bed0252..7d62f22 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>
> [...]
>
>>       connector->polled = DRM_CONNECTOR_POLL_HPD;
>>
>>       ret = drm_connector_init(dp->drm_dev, connector,
>> -                              &exynos_dp_connector_funcs,
>> +                              &analogix_dp_connector_funcs,
>>                                DRM_MODE_CONNECTOR_eDP);
>>       if (ret) {
>>               DRM_ERROR("Failed to initialize connector with drm\n");
>>               return ret;
>>       }
>>
>> -     drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
>> +     drm_connector_helper_add(connector,
>> +                              &analogix_dp_connector_helper_funcs);
>>       drm_connector_register(connector);
>
> this should only run on exynos, as we're doing all our connector registration
> in the core driver after all components are bound, so I guess something like
> the following is needed:
>
>        if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
>                drm_connector_register(connector);

Yuck!

Surely there is a better way. From what I've seen of DRM, I have no
doubt this is needed, but really a better solution is needed. Surely
there can be a more generic way for the driver to determine if it
should handle the connector or not. This seems like a common problem
including one I have seen. What I'm working on has onchip DSI encoder
-> ADV7533 -> HDMI. The DSI encoder can also have a direct attached
panel. So I have to check for a bridge in the encoder driver and only
register the connector for the panel if a bridge is not attached.

Rob

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-04 21:06       ` Rob Herring
  0 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-04 21:06 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Yakir Yang, Thierry Reding, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King,
	Ajay kumar, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel, devicetree

On Tue, Sep 1, 2015 at 3:46 PM, Heiko Stuebner <heiko@sntech.de> wrote:
> Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code to analogix_dp-exynos.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>
> [...]
>
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
>> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
>> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index bed0252..7d62f22 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>
> [...]
>
>>       connector->polled = DRM_CONNECTOR_POLL_HPD;
>>
>>       ret = drm_connector_init(dp->drm_dev, connector,
>> -                              &exynos_dp_connector_funcs,
>> +                              &analogix_dp_connector_funcs,
>>                                DRM_MODE_CONNECTOR_eDP);
>>       if (ret) {
>>               DRM_ERROR("Failed to initialize connector with drm\n");
>>               return ret;
>>       }
>>
>> -     drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
>> +     drm_connector_helper_add(connector,
>> +                              &analogix_dp_connector_helper_funcs);
>>       drm_connector_register(connector);
>
> this should only run on exynos, as we're doing all our connector registration
> in the core driver after all components are bound, so I guess something like
> the following is needed:
>
>        if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
>                drm_connector_register(connector);

Yuck!

Surely there is a better way. From what I've seen of DRM, I have no
doubt this is needed, but really a better solution is needed. Surely
there can be a more generic way for the driver to determine if it
should handle the connector or not. This seems like a common problem
including one I have seen. What I'm working on has onchip DSI encoder
-> ADV7533 -> HDMI. The DSI encoder can also have a direct attached
panel. So I have to check for a bridge in the encoder driver and only
register the connector for the panel if a bridge is not attached.

Rob

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-04 21:06       ` Rob Herring
  0 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-04 21:06 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, Sep 1, 2015 at 3:46 PM, Heiko Stuebner <heiko@sntech.de> wrote:
> Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code to analogix_dp-exynos.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>
> [...]
>
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
>> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
>> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index bed0252..7d62f22 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>
> [...]
>
>>       connector->polled = DRM_CONNECTOR_POLL_HPD;
>>
>>       ret = drm_connector_init(dp->drm_dev, connector,
>> -                              &exynos_dp_connector_funcs,
>> +                              &analogix_dp_connector_funcs,
>>                                DRM_MODE_CONNECTOR_eDP);
>>       if (ret) {
>>               DRM_ERROR("Failed to initialize connector with drm\n");
>>               return ret;
>>       }
>>
>> -     drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
>> +     drm_connector_helper_add(connector,
>> +                              &analogix_dp_connector_helper_funcs);
>>       drm_connector_register(connector);
>
> this should only run on exynos, as we're doing all our connector registration
> in the core driver after all components are bound, so I guess something like
> the following is needed:
>
>        if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
>                drm_connector_register(connector);

Yuck!

Surely there is a better way. From what I've seen of DRM, I have no
doubt this is needed, but really a better solution is needed. Surely
there can be a more generic way for the driver to determine if it
should handle the connector or not. This seems like a common problem
including one I have seen. What I'm working on has onchip DSI encoder
-> ADV7533 -> HDMI. The DSI encoder can also have a direct attached
panel. So I have to check for a bridge in the encoder driver and only
register the connector for the panel if a bridge is not attached.

Rob

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
  2015-09-04 21:06       ` Rob Herring
  (?)
@ 2015-09-04 21:29         ` Heiko Stuebner
  -1 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-04 21:29 UTC (permalink / raw)
  To: Rob Herring
  Cc: Yakir Yang, Thierry Reding, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King,
	Ajay kumar, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel, Doug Anderson, Sean Paul, Daniel Kurtz

Am Freitag, 4. September 2015, 16:06:02 schrieb Rob Herring:
> On Tue, Sep 1, 2015 at 3:46 PM, Heiko Stuebner <heiko@sntech.de> wrote:
> > Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
> >> Split the dp core driver from exynos directory to bridge
> >> directory, and rename the core driver to analogix_dp_*,
> >> leave the platform code to analogix_dp-exynos.
> >> 
> >> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> > 
> > [...]
> > 
> >> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> >> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
> >> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
> >> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> >> index bed0252..7d62f22 100644
> >> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> >> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> > 
> > [...]
> > 
> >>       connector->polled = DRM_CONNECTOR_POLL_HPD;
> >>       
> >>       ret = drm_connector_init(dp->drm_dev, connector,
> >> 
> >> -                              &exynos_dp_connector_funcs,
> >> +                              &analogix_dp_connector_funcs,
> >> 
> >>                                DRM_MODE_CONNECTOR_eDP);
> >>       
> >>       if (ret) {
> >>       
> >>               DRM_ERROR("Failed to initialize connector with drm\n");
> >>               return ret;
> >>       
> >>       }
> >> 
> >> -     drm_connector_helper_add(connector,
> >> &exynos_dp_connector_helper_funcs); +    
> >> drm_connector_helper_add(connector,
> >> +                              &analogix_dp_connector_helper_funcs);
> >> 
> >>       drm_connector_register(connector);
> > 
> > this should only run on exynos, as we're doing all our connector
> > registration in the core driver after all components are bound, so I
> > guess something like> 
> > the following is needed:
> >        if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
> >        
> >                drm_connector_register(connector);
> 
> Yuck!
> 
> Surely there is a better way. From what I've seen of DRM, I have no
> doubt this is needed, but really a better solution is needed. Surely
> there can be a more generic way for the driver to determine if it
> should handle the connector or not. This seems like a common problem
> including one I have seen. What I'm working on has onchip DSI encoder
> -> ADV7533 -> HDMI. The DSI encoder can also have a direct attached
> panel. So I have to check for a bridge in the encoder driver and only
> register the connector for the panel if a bridge is not attached.

I'm also only a part-time drm meddler, so things may be inaccurate.

This conditional is not meant to prevent the registration of the dp connector, 
only delay it for non-exynos drms. The connector registration does publish it 
to userspace, so like i.MX we're doing that for all connectors at the same 
time after all components are bound - to also make x11 happy. Exynos on the 
other hand seems to register its connectors individually and I'm not sure if 
they would be willing to change that.

see d3007dabeff4 ("drm/rockchip: register all connectors after bind") or 
simply rockchip_drm_drv.c line 178.

and e355e7dd607b ("imx-drm: delay publishing sysfs connector entries")


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-04 21:29         ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-04 21:29 UTC (permalink / raw)
  To: Rob Herring
  Cc: Yakir Yang, Thierry Reding, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King,
	Ajay kumar, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel, devicetree

Am Freitag, 4. September 2015, 16:06:02 schrieb Rob Herring:
> On Tue, Sep 1, 2015 at 3:46 PM, Heiko Stuebner <heiko@sntech.de> wrote:
> > Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
> >> Split the dp core driver from exynos directory to bridge
> >> directory, and rename the core driver to analogix_dp_*,
> >> leave the platform code to analogix_dp-exynos.
> >> 
> >> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> > 
> > [...]
> > 
> >> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> >> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
> >> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
> >> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> >> index bed0252..7d62f22 100644
> >> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> >> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> > 
> > [...]
> > 
> >>       connector->polled = DRM_CONNECTOR_POLL_HPD;
> >>       
> >>       ret = drm_connector_init(dp->drm_dev, connector,
> >> 
> >> -                              &exynos_dp_connector_funcs,
> >> +                              &analogix_dp_connector_funcs,
> >> 
> >>                                DRM_MODE_CONNECTOR_eDP);
> >>       
> >>       if (ret) {
> >>       
> >>               DRM_ERROR("Failed to initialize connector with drm\n");
> >>               return ret;
> >>       
> >>       }
> >> 
> >> -     drm_connector_helper_add(connector,
> >> &exynos_dp_connector_helper_funcs); +    
> >> drm_connector_helper_add(connector,
> >> +                              &analogix_dp_connector_helper_funcs);
> >> 
> >>       drm_connector_register(connector);
> > 
> > this should only run on exynos, as we're doing all our connector
> > registration in the core driver after all components are bound, so I
> > guess something like> 
> > the following is needed:
> >        if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
> >        
> >                drm_connector_register(connector);
> 
> Yuck!
> 
> Surely there is a better way. From what I've seen of DRM, I have no
> doubt this is needed, but really a better solution is needed. Surely
> there can be a more generic way for the driver to determine if it
> should handle the connector or not. This seems like a common problem
> including one I have seen. What I'm working on has onchip DSI encoder
> -> ADV7533 -> HDMI. The DSI encoder can also have a direct attached
> panel. So I have to check for a bridge in the encoder driver and only
> register the connector for the panel if a bridge is not attached.

I'm also only a part-time drm meddler, so things may be inaccurate.

This conditional is not meant to prevent the registration of the dp connector, 
only delay it for non-exynos drms. The connector registration does publish it 
to userspace, so like i.MX we're doing that for all connectors at the same 
time after all components are bound - to also make x11 happy. Exynos on the 
other hand seems to register its connectors individually and I'm not sure if 
they would be willing to change that.

see d3007dabeff4 ("drm/rockchip: register all connectors after bind") or 
simply rockchip_drm_drv.c line 178.

and e355e7dd607b ("imx-drm: delay publishing sysfs connector entries")


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-04 21:29         ` Heiko Stuebner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stuebner @ 2015-09-04 21:29 UTC (permalink / raw)
  To: linux-arm-kernel

Am Freitag, 4. September 2015, 16:06:02 schrieb Rob Herring:
> On Tue, Sep 1, 2015 at 3:46 PM, Heiko Stuebner <heiko@sntech.de> wrote:
> > Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
> >> Split the dp core driver from exynos directory to bridge
> >> directory, and rename the core driver to analogix_dp_*,
> >> leave the platform code to analogix_dp-exynos.
> >> 
> >> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> > 
> > [...]
> > 
> >> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> >> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
> >> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
> >> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> >> index bed0252..7d62f22 100644
> >> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> >> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> > 
> > [...]
> > 
> >>       connector->polled = DRM_CONNECTOR_POLL_HPD;
> >>       
> >>       ret = drm_connector_init(dp->drm_dev, connector,
> >> 
> >> -                              &exynos_dp_connector_funcs,
> >> +                              &analogix_dp_connector_funcs,
> >> 
> >>                                DRM_MODE_CONNECTOR_eDP);
> >>       
> >>       if (ret) {
> >>       
> >>               DRM_ERROR("Failed to initialize connector with drm\n");
> >>               return ret;
> >>       
> >>       }
> >> 
> >> -     drm_connector_helper_add(connector,
> >> &exynos_dp_connector_helper_funcs); +    
> >> drm_connector_helper_add(connector,
> >> +                              &analogix_dp_connector_helper_funcs);
> >> 
> >>       drm_connector_register(connector);
> > 
> > this should only run on exynos, as we're doing all our connector
> > registration in the core driver after all components are bound, so I
> > guess something like> 
> > the following is needed:
> >        if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
> >        
> >                drm_connector_register(connector);
> 
> Yuck!
> 
> Surely there is a better way. From what I've seen of DRM, I have no
> doubt this is needed, but really a better solution is needed. Surely
> there can be a more generic way for the driver to determine if it
> should handle the connector or not. This seems like a common problem
> including one I have seen. What I'm working on has onchip DSI encoder
> -> ADV7533 -> HDMI. The DSI encoder can also have a direct attached
> panel. So I have to check for a bridge in the encoder driver and only
> register the connector for the panel if a bridge is not attached.

I'm also only a part-time drm meddler, so things may be inaccurate.

This conditional is not meant to prevent the registration of the dp connector, 
only delay it for non-exynos drms. The connector registration does publish it 
to userspace, so like i.MX we're doing that for all connectors at the same 
time after all components are bound - to also make x11 happy. Exynos on the 
other hand seems to register its connectors individually and I'm not sure if 
they would be willing to change that.

see d3007dabeff4 ("drm/rockchip: register all connectors after bind") or 
simply rockchip_drm_drv.c line 178.

and e355e7dd607b ("imx-drm: delay publishing sysfs connector entries")


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2015-09-03  4:27       ` Yakir Yang
  (?)
@ 2015-09-04 21:46         ` Rob Herring
  -1 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-04 21:46 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	Russell King, djkurtz, dianders, seanpaul, Ajay kumar,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang <ykk@rock-chips.com> wrote:
> Hi Rob,
>
> 在 09/03/2015 04:17 AM, Rob Herring 写道:
>>
>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>>>
>>> Some edp screen do not have hpd signal, so we can't just return
>>> failed when hpd plug in detect failed.
>>
>> This is a property of the panel (or connector perhaps), so this
>> property should be located there. At least, it is a common issue and
>> not specific to this chip. We could have an HDMI connector and failed
>> to hook up HPD for example. A connector node is also where hpd-gpios
>> should be located instead (and are already defined by
>> ../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
>> binding, too.
>
>
> Yep, I agree with your front point, it is a property of panel, not specific
> to eDP controller, so this code should handle in connector logic.
>
> But another question, if we just leave this property to connector,
> then we would need to parse this property in analogix_dp-rockchip.c,
> and then make an hook in analogix_dp_core.c driver. This is not nice,
> and if there are some coming platform which alse want to use analogix_dp
> code and meet this "no-hpd" situation,  then they would need duplicate
> to parse this property and fill the hook in analogix_dp_core.c driver.
> So it's little bit conflict  :-)

Ideally, you would be able to just retrieve this quirk from the
connector or panel. Getting this property from your node vs. the port
you are attached to should not be much harder. Either the connector
struct can have this info or there can be a DT function that can walk
the graph and get it. Just don't open code the graph traversal in your
driver.

> Beside I can not understand your example very well. Do you mean
> that there are some HDMI monitor which also do not have HPD
> signal (just like some eDP panel do not have hpd too), and then
> the "hpd-gpios" ? Hmm... I don't know how the "hpd-gpios" want
> to help in this case, would you mind show some sample code  :-D

I don't know that there is h/w, but it is always possible HPD is not
hooked up or hooked up incorrectly some how.

If there is no HPD support, then hpd-gpios is not going to help you.

I think there are 3 cases to handle:
- HPD handled by bridge chip - The bridge driver knows it has this
capability. No DT properties are needed and no HPD properties on the
connector node imply the bridge chip should handle HPD functions.
- HPD handled by GPIO line (or some other block) - Indicated by
hpd-gpios present
- No or broken HPD - Indicated by "hpd-force" property.

>
>> Are there any eDP panels which don't have EDID and need panel details in
>> DT?
>
>
> Oh, I think you want to collect some info that belong to panel
> property but no indicate in panel EDID message, so those can
> be collect in eDP connector binding, is it right ?

Yes, and as Thierry pointed out we may need to know the exact panel even.

Rob

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-04 21:46         ` Rob Herring
  0 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-04 21:46 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	Russell King, djkurtz, dianders, seanpaul, Ajay kumar,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel

On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang <ykk@rock-chips.com> wrote:
> Hi Rob,
>
> 在 09/03/2015 04:17 AM, Rob Herring 写道:
>>
>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>>>
>>> Some edp screen do not have hpd signal, so we can't just return
>>> failed when hpd plug in detect failed.
>>
>> This is a property of the panel (or connector perhaps), so this
>> property should be located there. At least, it is a common issue and
>> not specific to this chip. We could have an HDMI connector and failed
>> to hook up HPD for example. A connector node is also where hpd-gpios
>> should be located instead (and are already defined by
>> ../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
>> binding, too.
>
>
> Yep, I agree with your front point, it is a property of panel, not specific
> to eDP controller, so this code should handle in connector logic.
>
> But another question, if we just leave this property to connector,
> then we would need to parse this property in analogix_dp-rockchip.c,
> and then make an hook in analogix_dp_core.c driver. This is not nice,
> and if there are some coming platform which alse want to use analogix_dp
> code and meet this "no-hpd" situation,  then they would need duplicate
> to parse this property and fill the hook in analogix_dp_core.c driver.
> So it's little bit conflict  :-)

Ideally, you would be able to just retrieve this quirk from the
connector or panel. Getting this property from your node vs. the port
you are attached to should not be much harder. Either the connector
struct can have this info or there can be a DT function that can walk
the graph and get it. Just don't open code the graph traversal in your
driver.

> Beside I can not understand your example very well. Do you mean
> that there are some HDMI monitor which also do not have HPD
> signal (just like some eDP panel do not have hpd too), and then
> the "hpd-gpios" ? Hmm... I don't know how the "hpd-gpios" want
> to help in this case, would you mind show some sample code  :-D

I don't know that there is h/w, but it is always possible HPD is not
hooked up or hooked up incorrectly some how.

If there is no HPD support, then hpd-gpios is not going to help you.

I think there are 3 cases to handle:
- HPD handled by bridge chip - The bridge driver knows it has this
capability. No DT properties are needed and no HPD properties on the
connector node imply the bridge chip should handle HPD functions.
- HPD handled by GPIO line (or some other block) - Indicated by
hpd-gpios present
- No or broken HPD - Indicated by "hpd-force" property.

>
>> Are there any eDP panels which don't have EDID and need panel details in
>> DT?
>
>
> Oh, I think you want to collect some info that belong to panel
> property but no indicate in panel EDID message, so those can
> be collect in eDP connector binding, is it right ?

Yes, and as Thierry pointed out we may need to know the exact panel even.

Rob

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-04 21:46         ` Rob Herring
  0 siblings, 0 replies; 370+ messages in thread
From: Rob Herring @ 2015-09-04 21:46 UTC (permalink / raw)
  To: linux-arm-kernel

On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang <ykk@rock-chips.com> wrote:
> Hi Rob,
>
> ? 09/03/2015 04:17 AM, Rob Herring ??:
>>
>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>>>
>>> Some edp screen do not have hpd signal, so we can't just return
>>> failed when hpd plug in detect failed.
>>
>> This is a property of the panel (or connector perhaps), so this
>> property should be located there. At least, it is a common issue and
>> not specific to this chip. We could have an HDMI connector and failed
>> to hook up HPD for example. A connector node is also where hpd-gpios
>> should be located instead (and are already defined by
>> ../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
>> binding, too.
>
>
> Yep, I agree with your front point, it is a property of panel, not specific
> to eDP controller, so this code should handle in connector logic.
>
> But another question, if we just leave this property to connector,
> then we would need to parse this property in analogix_dp-rockchip.c,
> and then make an hook in analogix_dp_core.c driver. This is not nice,
> and if there are some coming platform which alse want to use analogix_dp
> code and meet this "no-hpd" situation,  then they would need duplicate
> to parse this property and fill the hook in analogix_dp_core.c driver.
> So it's little bit conflict  :-)

Ideally, you would be able to just retrieve this quirk from the
connector or panel. Getting this property from your node vs. the port
you are attached to should not be much harder. Either the connector
struct can have this info or there can be a DT function that can walk
the graph and get it. Just don't open code the graph traversal in your
driver.

> Beside I can not understand your example very well. Do you mean
> that there are some HDMI monitor which also do not have HPD
> signal (just like some eDP panel do not have hpd too), and then
> the "hpd-gpios" ? Hmm... I don't know how the "hpd-gpios" want
> to help in this case, would you mind show some sample code  :-D

I don't know that there is h/w, but it is always possible HPD is not
hooked up or hooked up incorrectly some how.

If there is no HPD support, then hpd-gpios is not going to help you.

I think there are 3 cases to handle:
- HPD handled by bridge chip - The bridge driver knows it has this
capability. No DT properties are needed and no HPD properties on the
connector node imply the bridge chip should handle HPD functions.
- HPD handled by GPIO line (or some other block) - Indicated by
hpd-gpios present
- No or broken HPD - Indicated by "hpd-force" property.

>
>> Are there any eDP panels which don't have EDID and need panel details in
>> DT?
>
>
> Oh, I think you want to collect some info that belong to panel
> property but no indicate in panel EDID message, so those can
> be collect in eDP connector binding, is it right ?

Yes, and as Thierry pointed out we may need to know the exact panel even.

Rob

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 01/16] drm: exynos/dp: fix code style
@ 2015-09-06  1:33               ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  1:33 UTC (permalink / raw)
  To: Joe Perches
  Cc: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, Kukjin Kim, Mark Yao, Russell King, djkurtz, dianders,
	seanpaul, ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Hi Joe,

在 09/03/2015 01:57 PM, Joe Perches 写道:
> On Thu, 2015-09-03 at 13:33 +0800, Yakir Yang wrote:
> []
>>>>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> []
>>>>>> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct
>>>>>> exynos_dp_device *dp)
>>>>>>             }
>>>>>>               exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
>>>>>> -                    &test_vector);
>>>>>> +                          &test_vector);
>>>>>>             if (test_vector & DP_TEST_LINK_EDID_READ) {
>>>>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>>>>> -                DP_TEST_EDID_CHECKSUM,
>>>>>> +            exynos_dp_write_byte_to_dpcd(
>>>>>> +                dp, DP_TEST_EDID_CHECKSUM,
>>>>>>                     edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
>>>>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>>>>> -                DP_TEST_RESPONSE,
>>>>>> +            exynos_dp_write_byte_to_dpcd(
>>>>>> +                dp, DP_TEST_RESPONSE,
>>>>>>                     DP_TEST_EDID_CHECKSUM_WRITE);
>>>>> To me, missing argument after opening parenthesis, looks worse. I would
>>>>> prefer:
>>>>>
>>>>>               exynos_dp_write_byte_to_dpcd(dp,
>>>>>
>>>>> Why you moved the 'dp' argument to new line?
>>>> Hmm... Just like style tool indicate, no more warning after
>>>> that change.
>>>>
>>>> For now, I would like to follow the original style, just improved
>>>> some obvious style problem.  :-)
>>> What was the checkpatch warning that said 'dp' has to move to new line?
>>> I tried this and I don't see it.
>> checkpatch haven't remind me that put dp to new line would fix
>> this warning, this just come from my experiments. And I works,
>> no more warnings from checkpatch, so I toke this style.
> Checkpatch isn't a great arbiter of style.
> It's just a brainless tool.
>
> Always use your instead of anything brainless.
>
> If it were code I was writing, I'd ignore 80 columns warnings
> where appropriate.
>
> These are long function names and long macro defines, so it's
> inappropriate to use 80 columns as a guiding style.
>
> I'd write:
>
> 		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, &test_vector);
> 		if (test_vector & DP_TEST_LINK_EDID_READ) {
> 			exynos_dp_write_byte_to_dpcd(dp, DP_TEST_EDID_CHECKSUM,
> 						     edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
> 			exynos_dp_write_byte_to_dpcd(dp, DP_TEST_RESPONSE,
> 						     DP_TEST_EDID_CHECKSUM_WRITE);
> 		}
>

So... just ignore the 80 columns warnings. Actually I prefer to
keep the original style in this case.

Thanks,
- Yakir
]
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 01/16] drm: exynos/dp: fix code style
@ 2015-09-06  1:33               ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  1:33 UTC (permalink / raw)
  To: Joe Perches
  Cc: Krzysztof Kozlowski, Heiko Stuebner, David Airlie,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Andrzej Hajda,
	Gustavo Padovan, architt-sgV2jX0FEOL9JmXXK+q4OQ,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Russell King, Thierry Reding,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Inki Dae, Rob Herring, dianders-F7+t8E8rja9Wk0Htik3J/w,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Yao,
	Jingoo Han, linux-kernel-u79uwXL29TaqPxH82wqD4g

Hi Joe,

在 09/03/2015 01:57 PM, Joe Perches 写道:
> On Thu, 2015-09-03 at 13:33 +0800, Yakir Yang wrote:
> []
>>>>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> []
>>>>>> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct
>>>>>> exynos_dp_device *dp)
>>>>>>             }
>>>>>>               exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
>>>>>> -                    &test_vector);
>>>>>> +                          &test_vector);
>>>>>>             if (test_vector & DP_TEST_LINK_EDID_READ) {
>>>>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>>>>> -                DP_TEST_EDID_CHECKSUM,
>>>>>> +            exynos_dp_write_byte_to_dpcd(
>>>>>> +                dp, DP_TEST_EDID_CHECKSUM,
>>>>>>                     edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
>>>>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>>>>> -                DP_TEST_RESPONSE,
>>>>>> +            exynos_dp_write_byte_to_dpcd(
>>>>>> +                dp, DP_TEST_RESPONSE,
>>>>>>                     DP_TEST_EDID_CHECKSUM_WRITE);
>>>>> To me, missing argument after opening parenthesis, looks worse. I would
>>>>> prefer:
>>>>>
>>>>>               exynos_dp_write_byte_to_dpcd(dp,
>>>>>
>>>>> Why you moved the 'dp' argument to new line?
>>>> Hmm... Just like style tool indicate, no more warning after
>>>> that change.
>>>>
>>>> For now, I would like to follow the original style, just improved
>>>> some obvious style problem.  :-)
>>> What was the checkpatch warning that said 'dp' has to move to new line?
>>> I tried this and I don't see it.
>> checkpatch haven't remind me that put dp to new line would fix
>> this warning, this just come from my experiments. And I works,
>> no more warnings from checkpatch, so I toke this style.
> Checkpatch isn't a great arbiter of style.
> It's just a brainless tool.
>
> Always use your instead of anything brainless.
>
> If it were code I was writing, I'd ignore 80 columns warnings
> where appropriate.
>
> These are long function names and long macro defines, so it's
> inappropriate to use 80 columns as a guiding style.
>
> I'd write:
>
> 		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, &test_vector);
> 		if (test_vector & DP_TEST_LINK_EDID_READ) {
> 			exynos_dp_write_byte_to_dpcd(dp, DP_TEST_EDID_CHECKSUM,
> 						     edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
> 			exynos_dp_write_byte_to_dpcd(dp, DP_TEST_RESPONSE,
> 						     DP_TEST_EDID_CHECKSUM_WRITE);
> 		}
>

So... just ignore the 80 columns warnings. Actually I prefer to
keep the original style in this case.

Thanks,
- Yakir
]
>
>
>



_______________________________________________
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Linux-rockchip@lists.infradead.org
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 01/16] drm: exynos/dp: fix code style
@ 2015-09-06  1:33               ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  1:33 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Joe,

? 09/03/2015 01:57 PM, Joe Perches ??:
> On Thu, 2015-09-03 at 13:33 +0800, Yakir Yang wrote:
> []
>>>>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> []
>>>>>> @@ -155,24 +156,22 @@ static int exynos_dp_read_edid(struct
>>>>>> exynos_dp_device *dp)
>>>>>>             }
>>>>>>               exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
>>>>>> -                    &test_vector);
>>>>>> +                          &test_vector);
>>>>>>             if (test_vector & DP_TEST_LINK_EDID_READ) {
>>>>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>>>>> -                DP_TEST_EDID_CHECKSUM,
>>>>>> +            exynos_dp_write_byte_to_dpcd(
>>>>>> +                dp, DP_TEST_EDID_CHECKSUM,
>>>>>>                     edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
>>>>>> -            exynos_dp_write_byte_to_dpcd(dp,
>>>>>> -                DP_TEST_RESPONSE,
>>>>>> +            exynos_dp_write_byte_to_dpcd(
>>>>>> +                dp, DP_TEST_RESPONSE,
>>>>>>                     DP_TEST_EDID_CHECKSUM_WRITE);
>>>>> To me, missing argument after opening parenthesis, looks worse. I would
>>>>> prefer:
>>>>>
>>>>>               exynos_dp_write_byte_to_dpcd(dp,
>>>>>
>>>>> Why you moved the 'dp' argument to new line?
>>>> Hmm... Just like style tool indicate, no more warning after
>>>> that change.
>>>>
>>>> For now, I would like to follow the original style, just improved
>>>> some obvious style problem.  :-)
>>> What was the checkpatch warning that said 'dp' has to move to new line?
>>> I tried this and I don't see it.
>> checkpatch haven't remind me that put dp to new line would fix
>> this warning, this just come from my experiments. And I works,
>> no more warnings from checkpatch, so I toke this style.
> Checkpatch isn't a great arbiter of style.
> It's just a brainless tool.
>
> Always use your instead of anything brainless.
>
> If it were code I was writing, I'd ignore 80 columns warnings
> where appropriate.
>
> These are long function names and long macro defines, so it's
> inappropriate to use 80 columns as a guiding style.
>
> I'd write:
>
> 		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, &test_vector);
> 		if (test_vector & DP_TEST_LINK_EDID_READ) {
> 			exynos_dp_write_byte_to_dpcd(dp, DP_TEST_EDID_CHECKSUM,
> 						     edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
> 			exynos_dp_write_byte_to_dpcd(dp, DP_TEST_RESPONSE,
> 						     DP_TEST_EDID_CHECKSUM_WRITE);
> 		}
>

So... just ignore the 80 columns warnings. Actually I prefer to
keep the original style in this case.

Thanks,
- Yakir
]
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 05/16] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & colorimetry
@ 2015-09-06  2:00       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  2:00 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Krzysztof,

在 09/03/2015 04:04 PM, Krzysztof Kozlowski 写道:
> On 01.09.2015 14:55, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code, same to color space and color depth can be
>> parsed from EDID.
>>
>> But presumably Exynos still relaies on the DT properties, so take
> s/relaies/relies/
>
>> good use of mode_fixup() in to achieve the compatibility hacks.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Krzysztof suggest, provide backword compatibility with samsung.
>> - Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.
>>
>> Changes in v3:
>> - Take Thierry Reding suggest, dynamic parse video timing info from
>>    struct drm_display_mode and struct drm_display_info.
>>
>> Changes in v2: None
>>
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 141 +++++++++++++--------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>>   drivers/gpu/drm/exynos/exynos_dp.c                 |  58 ++++++++-
>>   4 files changed, 151 insertions(+), 64 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index 7196097..f0db92e 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -897,8 +897,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
>>   		return;
>>   	}
>>   
>> -	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
>> -					 dp->video_info->link_rate);
>> +	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
>> +					 dp->video_info.link_rate);
>>   	if (ret) {
>>   		dev_err(dp->dev, "unable to do link train\n");
>>   		return;
>> @@ -1081,6 +1081,82 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
>>   	dp->dpms_mode = DRM_MODE_DPMS_OFF;
>>   }
>>   
>> +static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
>> +					struct drm_display_mode *orig_mode,
>> +					struct drm_display_mode *mode)
>> +{
>> +	struct analogix_dp_device *dp = bridge->driver_private;
>> +	struct drm_display_info *display_info = &dp->connector.display_info;
>> +	struct video_info *video_info = &dp->video_info;
>> +	struct device_node *dp_node = dp->dev->of_node;
>> +	int vic;
>> +
>> +	/* interlaces & hsync pol & vsync pol */
>> +	video_info->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
>> +	video_info->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
>> +	video_info->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>> +
>> +	/* dynamic_range & colorimetry */
>> +	vic = drm_match_cea_mode(mode);
>> +	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
>> +	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
>> +		video_info->dynamic_range = CEA;
>> +		video_info->ycbcr_coeff = COLOR_YCBCR601;
>> +	} else if (vic) {
>> +		video_info->dynamic_range = CEA;
>> +		video_info->ycbcr_coeff = COLOR_YCBCR709;
>> +	} else {
>> +		video_info->dynamic_range = VESA;
>> +		video_info->ycbcr_coeff = COLOR_YCBCR709;
>> +	}
>> +
>> +	switch (display_info->bpc) {
>> +	case 12:
>> +		video_info->color_depth = COLOR_12;
>> +		break;
>> +	case 10:
>> +		video_info->color_depth = COLOR_10;
>> +		break;
>> +	case 8:
>> +		video_info->color_depth = COLOR_8;
>> +		break;
>> +	case 6:
>> +		video_info->color_depth = COLOR_6;
>> +		break;
>> +	default:
>> +		video_info->color_depth = COLOR_8;
>> +		break;
>> +	}
>> +
>> +	if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB444)
>> +		video_info->color_space = COLOR_YCBCR444;
>> +	else if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB422)
>> +		video_info->color_space = COLOR_YCBCR422;
>> +	else if (display_info->color_formats | DRM_COLOR_FORMAT_RGB444)
>> +		video_info->color_space = COLOR_RGB;
>> +	else
>> +		video_info->color_space = COLOR_RGB;
>> +
>> +	/*
>> +	 * NOTE: those property parseing code is used for
> s/parseing/parsing/
>
> BTW, you can easily integrate spell-check to vim... It is not that I
> search for such misspellings - they are highlighted...

Wow, thanks for your remind, I have set the spell-check now.  :)

>
>> +	 * providing backward compatibility for samsung platform.
>> +	 */
>> +	of_property_read_u32(dp_node, "samsung,color-space",
>> +			     &video_info->color_space);
>> +	of_property_read_u32(dp_node, "samsung,dynamic-range",
>> +			     &video_info->dynamic_range);
>> +	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
>> +			     &video_info->ycbcr_coeff);
>> +	of_property_read_u32(dp_node, "samsung,color-depth",
>> +			     &video_info->color_depth);
>> +	of_property_read_u32(dp_node, "hsync-active-high",
>> +			     (unsigned int *)&video_info->h_sync_polarity);
>> +	of_property_read_u32(dp_node, "vsync-active-high",
>> +			     (unsigned int *)&video_info->v_sync_polarity);
>> +	of_property_read_u32(dp_node, "interlaced",
>> +			     (unsigned int *)&video_info->interlaced);
> You made assumption that the sizeof(bool) is always equal to
> sizeof(u32)... Then you cast it to pointer to unsigned int but function
> wants pointer to u32. Just for reading boolean property. There's easier
> way - of_property_read_bool. It returns bool.

Thanks, done.

>
>> +}
>> +
>>   static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
>>   {
>>   	/* do nothing */
>> @@ -1091,6 +1167,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
>>   	.disable = analogix_dp_bridge_disable,
>>   	.pre_enable = analogix_dp_bridge_nop,
>>   	.post_disable = analogix_dp_bridge_nop,
>> +	.mode_set = analogix_dp_bridge_mode_set,
>>   	.attach = analogix_dp_bridge_attach,
>>   };
>>   
>> @@ -1121,62 +1198,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>>   	return 0;
>>   }
>>   
>> -static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
>> +static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
>>   {
>> -	struct device_node *dp_node = dev->of_node;
>> -	struct video_info *dp_video_config;
>> -
>> -	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
>> -				       GFP_KERNEL);
>> -	if (!dp_video_config)
>> -		return ERR_PTR(-ENOMEM);
>> -
>> -	dp_video_config->h_sync_polarity =
>> -		of_property_read_bool(dp_node, "hsync-active-high");
>> -
>> -	dp_video_config->v_sync_polarity =
>> -		of_property_read_bool(dp_node, "vsync-active-high");
>> -
>> -	dp_video_config->interlaced =
>> -		of_property_read_bool(dp_node, "interlaced");
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,color-space",
>> -				 &dp_video_config->color_space)) {
>> -		dev_err(dev, "failed to get color-space\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
>> -				 &dp_video_config->dynamic_range)) {
>> -		dev_err(dev, "failed to get dynamic-range\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
>> -				 &dp_video_config->ycbcr_coeff)) {
>> -		dev_err(dev, "failed to get ycbcr-coeff\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,color-depth",
>> -				 &dp_video_config->color_depth)) {
>> -		dev_err(dev, "failed to get color-depth\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> +	struct device_node *dp_node = dp->dev->of_node;
>> +	struct video_info *video_config = &dp->video_info;
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,link-rate",
>> -				 &dp_video_config->link_rate)) {
>> +				 &video_info->link_rate)) {
>>   		dev_err(dev, "failed to get link-rate\n");
>> -		return ERR_PTR(-EINVAL);
>> +		return -EINVAL;
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,lane-count",
>> -				 &dp_video_config->lane_count)) {
>> +				 &video_info->lane_count)) {
>>   		dev_err(dev, "failed to get lane-count\n");
>> -		return ERR_PTR(-EINVAL);
>> +		return -EINVAL;
>>   	}
>>   
>> -	return dp_video_config;
>> +	return 0;
>>   }
>>   
>>   int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>> @@ -1205,9 +1244,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>>   	 */
>>   	dp->plat_data = plat_data;
>>   
>> -	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
>> -	if (IS_ERR(dp->video_info))
>> -		return PTR_ERR(dp->video_info);
>> +	ret = analogix_dp_dt_parse_pdata(dp);
>> +	if (ret)
>> +		return ret;
>>   
>>   	dp->phy = devm_phy_get(dp->dev, "dp");
>>   	if (IS_ERR(dp->phy)) {
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> index ffabbd0..6e3d5bc 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> @@ -154,7 +154,7 @@ struct analogix_dp_device {
>>   	unsigned int		irq;
>>   	void __iomem		*reg_base;
>>   
>> -	struct video_info	*video_info;
>> +	struct video_info	video_info;
>>   	struct link_train	link_train;
>>   	struct work_struct	hotplug_work;
>>   	struct phy		*phy;
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> index b879d8c..6a643be 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> @@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
>>   	u32 reg;
>>   
>>   	/* Configure the input color depth, color space, dynamic range */
>> -	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
>> -		(dp->video_info->color_depth << IN_BPC_SHIFT) |
>> -		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
>> +	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
>> +		(dp->video_info.color_depth << IN_BPC_SHIFT) |
>> +		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
>>   
>>   	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>>   	reg &= ~IN_YC_COEFFI_MASK;
>> -	if (dp->video_info->ycbcr_coeff)
>> +	if (dp->video_info.ycbcr_coeff)
>>   		reg |= IN_YC_COEFFI_ITU709;
>>   	else
>>   		reg |= IN_YC_COEFFI_ITU601;
>> @@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
>>   
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   	reg &= ~INTERACE_SCAN_CFG;
>> -	reg |= (dp->video_info->interlaced << 2);
>> +	reg |= (dp->video_info.interlaced << 2);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   	reg &= ~VSYNC_POLARITY_CFG;
>> -	reg |= (dp->video_info->v_sync_polarity << 1);
>> +	reg |= (dp->video_info.v_sync_polarity << 1);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   	reg &= ~HSYNC_POLARITY_CFG;
>> -	reg |= (dp->video_info->h_sync_polarity << 0);
>> +	reg |= (dp->video_info.h_sync_polarity << 0);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   
>>   	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
>> index 7e1be72..6060d2c 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp.c
>> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
>> @@ -28,8 +28,13 @@
>>   
>>   #include "exynos_drm_crtc.h"
>>   
>> -#define plat_data_to_dp(pd) \
>> -		container_of(pd, struct exynos_dp_device, plat_data)
>> +#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
>> +
>> +struct video_info {
>> +	bool h_sync_polarity;
>> +	bool v_sync_polarity;
>> +	bool interlaced;
>> +};
>>   
>>   struct exynos_dp_device {
>>   	struct drm_encoder         encoder;
>> @@ -39,12 +44,13 @@ struct exynos_dp_device {
>>   
>>   	struct exynos_drm_panel_info priv;
>>   	struct analogix_dp_plat_data plat_data;
>> +	struct video_info            video_info;
>>   };
>>   
>>   int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
>>   				bool enable)
>>   {
>> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
>> +	struct exynos_dp_device *dp = to_dp(plat_data);
>>   	struct drm_encoder *encoder = &dp->encoder;
>>   	struct exynos_drm_crtc *crtc;
>>   
>> @@ -71,7 +77,7 @@ static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
>>   static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
>>   			       struct drm_connector *connector)
>>   {
>> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
>> +	struct exynos_dp_device *dp = to_dp(plat_data);
>>   	struct drm_display_mode *mode;
>>   
>>   	if (dp->plat_data.panel)
>> @@ -99,7 +105,7 @@ static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
>>   static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
>>   				   struct drm_bridge *bridge)
>>   {
>> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
>> +	struct exynos_dp_device *dp = to_dp(plat_data);
>>   	struct drm_encoder *encoder = &dp->encoder;
>>   	int ret;
>>   
>> @@ -122,6 +128,28 @@ static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
>>   				 const struct drm_display_mode *mode,
>>   				 struct drm_display_mode *adjusted_mode)
>>   {
>> +	struct exynos_dp_device *dp = to_dp(encoder);
>> +	int flags = adjusted_mode->flags;
>> +
>> +	flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |
>> +		   DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC |
>> +		   DRM_MODE_FLAG_INTERLACE);
>> +
>> +	if (dp->video_info.h_sync_polarity)
>> +		flags |= DRM_MODE_FLAG_PHSYNC;
>> +	else
>> +		flags |= DRM_MODE_FLAG_NHSYNC;
>> +
>> +	if (dp->video_info.v_sync_polarity)
>> +		flags |= DRM_MODE_FLAG_PVSYNC;
>> +	else
>> +		flags |= DRM_MODE_FLAG_NVSYNC;
>> +
>> +	if (dp->video_info.interlaced)
>> +		flags |= DRM_MODE_FLAG_INTERLACE;
>> +
>> +	adjusted_mode->flags = flags;
>> +
>>   	return true;
>>   }
>>   
>> @@ -163,6 +191,22 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
>>   	return 0;
>>   }
>>   
>> +static int exynos_dp_dt_parse_video_info(struct exynos_dp_device *dp)
>> +{
>> +	struct device_node *dp_node = dp->dev->of_node;
>> +
>> +	dp->video_info.h_sync_polarity =
>> +		of_property_read_bool(dp_node, "hsync-active-high");
>> +
>> +	dp->video_info.v_sync_polarity =
>> +		of_property_read_bool(dp_node, "vsync-active-high");
>> +
>> +	dp->video_info.interlaced =
>> +		of_property_read_bool(dp_node, "interlaced");
>> +
>> +	return 0;
> Probably you wanted to follow the convention of other DT-parse functions
> but there is no need. This function cannot fail so maybe make it void?
> It would simplify a bit the code in exynos_dp_bind().

Actually, I found an mistaken here. I have parsed those two property for 
twice,
one is here, the other is analogix_dp_core.c mode_set() function.
         /*
          * NOTE: those property parseing code is used for
          * providing backward compatibility for samsung platform.
          */
         [....]
         of_property_read_u32(dp_node, "hsync-active-high",
                              (unsigned int *)&video_info->h_sync_polarity);
         of_property_read_u32(dp_node, "vsync-active-high",
                              (unsigned int *)&video_info->v_sync_polarity);
         of_property_read_u32(dp_node, "interlaced",
                              (unsigned int *)&video_info->interlaced);


And I think it would be easy to code when I achieve the backward 
compatibility
in analogix core driver. So I prefer this way :-)

Anyway, thanks,
- Yakir

> Best regards,
> Krzysztof
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 05/16] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & colorimetry
@ 2015-09-06  2:00       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  2:00 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, joe-6d6DIl74uiNBDgjK7y7TUQ, Kukjin Kim, Mark Yao
  Cc: David Airlie, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	Andrzej Hajda, Gustavo Padovan, architt-sgV2jX0FEOL9JmXXK+q4OQ,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Russell King,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Rob Herring, dianders-F7+t8E8rja9Wk0Htik3J/w,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kyungmin Park, Kumar Gala,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan

Hi Krzysztof,

在 09/03/2015 04:04 PM, Krzysztof Kozlowski 写道:
> On 01.09.2015 14:55, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code, same to color space and color depth can be
>> parsed from EDID.
>>
>> But presumably Exynos still relaies on the DT properties, so take
> s/relaies/relies/
>
>> good use of mode_fixup() in to achieve the compatibility hacks.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Krzysztof suggest, provide backword compatibility with samsung.
>> - Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.
>>
>> Changes in v3:
>> - Take Thierry Reding suggest, dynamic parse video timing info from
>>    struct drm_display_mode and struct drm_display_info.
>>
>> Changes in v2: None
>>
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 141 +++++++++++++--------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>>   drivers/gpu/drm/exynos/exynos_dp.c                 |  58 ++++++++-
>>   4 files changed, 151 insertions(+), 64 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index 7196097..f0db92e 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -897,8 +897,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
>>   		return;
>>   	}
>>   
>> -	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
>> -					 dp->video_info->link_rate);
>> +	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
>> +					 dp->video_info.link_rate);
>>   	if (ret) {
>>   		dev_err(dp->dev, "unable to do link train\n");
>>   		return;
>> @@ -1081,6 +1081,82 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
>>   	dp->dpms_mode = DRM_MODE_DPMS_OFF;
>>   }
>>   
>> +static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
>> +					struct drm_display_mode *orig_mode,
>> +					struct drm_display_mode *mode)
>> +{
>> +	struct analogix_dp_device *dp = bridge->driver_private;
>> +	struct drm_display_info *display_info = &dp->connector.display_info;
>> +	struct video_info *video_info = &dp->video_info;
>> +	struct device_node *dp_node = dp->dev->of_node;
>> +	int vic;
>> +
>> +	/* interlaces & hsync pol & vsync pol */
>> +	video_info->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
>> +	video_info->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
>> +	video_info->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>> +
>> +	/* dynamic_range & colorimetry */
>> +	vic = drm_match_cea_mode(mode);
>> +	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
>> +	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
>> +		video_info->dynamic_range = CEA;
>> +		video_info->ycbcr_coeff = COLOR_YCBCR601;
>> +	} else if (vic) {
>> +		video_info->dynamic_range = CEA;
>> +		video_info->ycbcr_coeff = COLOR_YCBCR709;
>> +	} else {
>> +		video_info->dynamic_range = VESA;
>> +		video_info->ycbcr_coeff = COLOR_YCBCR709;
>> +	}
>> +
>> +	switch (display_info->bpc) {
>> +	case 12:
>> +		video_info->color_depth = COLOR_12;
>> +		break;
>> +	case 10:
>> +		video_info->color_depth = COLOR_10;
>> +		break;
>> +	case 8:
>> +		video_info->color_depth = COLOR_8;
>> +		break;
>> +	case 6:
>> +		video_info->color_depth = COLOR_6;
>> +		break;
>> +	default:
>> +		video_info->color_depth = COLOR_8;
>> +		break;
>> +	}
>> +
>> +	if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB444)
>> +		video_info->color_space = COLOR_YCBCR444;
>> +	else if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB422)
>> +		video_info->color_space = COLOR_YCBCR422;
>> +	else if (display_info->color_formats | DRM_COLOR_FORMAT_RGB444)
>> +		video_info->color_space = COLOR_RGB;
>> +	else
>> +		video_info->color_space = COLOR_RGB;
>> +
>> +	/*
>> +	 * NOTE: those property parseing code is used for
> s/parseing/parsing/
>
> BTW, you can easily integrate spell-check to vim... It is not that I
> search for such misspellings - they are highlighted...

Wow, thanks for your remind, I have set the spell-check now.  :)

>
>> +	 * providing backward compatibility for samsung platform.
>> +	 */
>> +	of_property_read_u32(dp_node, "samsung,color-space",
>> +			     &video_info->color_space);
>> +	of_property_read_u32(dp_node, "samsung,dynamic-range",
>> +			     &video_info->dynamic_range);
>> +	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
>> +			     &video_info->ycbcr_coeff);
>> +	of_property_read_u32(dp_node, "samsung,color-depth",
>> +			     &video_info->color_depth);
>> +	of_property_read_u32(dp_node, "hsync-active-high",
>> +			     (unsigned int *)&video_info->h_sync_polarity);
>> +	of_property_read_u32(dp_node, "vsync-active-high",
>> +			     (unsigned int *)&video_info->v_sync_polarity);
>> +	of_property_read_u32(dp_node, "interlaced",
>> +			     (unsigned int *)&video_info->interlaced);
> You made assumption that the sizeof(bool) is always equal to
> sizeof(u32)... Then you cast it to pointer to unsigned int but function
> wants pointer to u32. Just for reading boolean property. There's easier
> way - of_property_read_bool. It returns bool.

Thanks, done.

>
>> +}
>> +
>>   static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
>>   {
>>   	/* do nothing */
>> @@ -1091,6 +1167,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
>>   	.disable = analogix_dp_bridge_disable,
>>   	.pre_enable = analogix_dp_bridge_nop,
>>   	.post_disable = analogix_dp_bridge_nop,
>> +	.mode_set = analogix_dp_bridge_mode_set,
>>   	.attach = analogix_dp_bridge_attach,
>>   };
>>   
>> @@ -1121,62 +1198,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>>   	return 0;
>>   }
>>   
>> -static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
>> +static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
>>   {
>> -	struct device_node *dp_node = dev->of_node;
>> -	struct video_info *dp_video_config;
>> -
>> -	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
>> -				       GFP_KERNEL);
>> -	if (!dp_video_config)
>> -		return ERR_PTR(-ENOMEM);
>> -
>> -	dp_video_config->h_sync_polarity =
>> -		of_property_read_bool(dp_node, "hsync-active-high");
>> -
>> -	dp_video_config->v_sync_polarity =
>> -		of_property_read_bool(dp_node, "vsync-active-high");
>> -
>> -	dp_video_config->interlaced =
>> -		of_property_read_bool(dp_node, "interlaced");
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,color-space",
>> -				 &dp_video_config->color_space)) {
>> -		dev_err(dev, "failed to get color-space\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
>> -				 &dp_video_config->dynamic_range)) {
>> -		dev_err(dev, "failed to get dynamic-range\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
>> -				 &dp_video_config->ycbcr_coeff)) {
>> -		dev_err(dev, "failed to get ycbcr-coeff\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,color-depth",
>> -				 &dp_video_config->color_depth)) {
>> -		dev_err(dev, "failed to get color-depth\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> +	struct device_node *dp_node = dp->dev->of_node;
>> +	struct video_info *video_config = &dp->video_info;
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,link-rate",
>> -				 &dp_video_config->link_rate)) {
>> +				 &video_info->link_rate)) {
>>   		dev_err(dev, "failed to get link-rate\n");
>> -		return ERR_PTR(-EINVAL);
>> +		return -EINVAL;
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,lane-count",
>> -				 &dp_video_config->lane_count)) {
>> +				 &video_info->lane_count)) {
>>   		dev_err(dev, "failed to get lane-count\n");
>> -		return ERR_PTR(-EINVAL);
>> +		return -EINVAL;
>>   	}
>>   
>> -	return dp_video_config;
>> +	return 0;
>>   }
>>   
>>   int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>> @@ -1205,9 +1244,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>>   	 */
>>   	dp->plat_data = plat_data;
>>   
>> -	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
>> -	if (IS_ERR(dp->video_info))
>> -		return PTR_ERR(dp->video_info);
>> +	ret = analogix_dp_dt_parse_pdata(dp);
>> +	if (ret)
>> +		return ret;
>>   
>>   	dp->phy = devm_phy_get(dp->dev, "dp");
>>   	if (IS_ERR(dp->phy)) {
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> index ffabbd0..6e3d5bc 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> @@ -154,7 +154,7 @@ struct analogix_dp_device {
>>   	unsigned int		irq;
>>   	void __iomem		*reg_base;
>>   
>> -	struct video_info	*video_info;
>> +	struct video_info	video_info;
>>   	struct link_train	link_train;
>>   	struct work_struct	hotplug_work;
>>   	struct phy		*phy;
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> index b879d8c..6a643be 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> @@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
>>   	u32 reg;
>>   
>>   	/* Configure the input color depth, color space, dynamic range */
>> -	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
>> -		(dp->video_info->color_depth << IN_BPC_SHIFT) |
>> -		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
>> +	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
>> +		(dp->video_info.color_depth << IN_BPC_SHIFT) |
>> +		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
>>   
>>   	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>>   	reg &= ~IN_YC_COEFFI_MASK;
>> -	if (dp->video_info->ycbcr_coeff)
>> +	if (dp->video_info.ycbcr_coeff)
>>   		reg |= IN_YC_COEFFI_ITU709;
>>   	else
>>   		reg |= IN_YC_COEFFI_ITU601;
>> @@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
>>   
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   	reg &= ~INTERACE_SCAN_CFG;
>> -	reg |= (dp->video_info->interlaced << 2);
>> +	reg |= (dp->video_info.interlaced << 2);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   	reg &= ~VSYNC_POLARITY_CFG;
>> -	reg |= (dp->video_info->v_sync_polarity << 1);
>> +	reg |= (dp->video_info.v_sync_polarity << 1);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   	reg &= ~HSYNC_POLARITY_CFG;
>> -	reg |= (dp->video_info->h_sync_polarity << 0);
>> +	reg |= (dp->video_info.h_sync_polarity << 0);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   
>>   	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
>> index 7e1be72..6060d2c 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp.c
>> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
>> @@ -28,8 +28,13 @@
>>   
>>   #include "exynos_drm_crtc.h"
>>   
>> -#define plat_data_to_dp(pd) \
>> -		container_of(pd, struct exynos_dp_device, plat_data)
>> +#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
>> +
>> +struct video_info {
>> +	bool h_sync_polarity;
>> +	bool v_sync_polarity;
>> +	bool interlaced;
>> +};
>>   
>>   struct exynos_dp_device {
>>   	struct drm_encoder         encoder;
>> @@ -39,12 +44,13 @@ struct exynos_dp_device {
>>   
>>   	struct exynos_drm_panel_info priv;
>>   	struct analogix_dp_plat_data plat_data;
>> +	struct video_info            video_info;
>>   };
>>   
>>   int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
>>   				bool enable)
>>   {
>> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
>> +	struct exynos_dp_device *dp = to_dp(plat_data);
>>   	struct drm_encoder *encoder = &dp->encoder;
>>   	struct exynos_drm_crtc *crtc;
>>   
>> @@ -71,7 +77,7 @@ static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
>>   static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
>>   			       struct drm_connector *connector)
>>   {
>> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
>> +	struct exynos_dp_device *dp = to_dp(plat_data);
>>   	struct drm_display_mode *mode;
>>   
>>   	if (dp->plat_data.panel)
>> @@ -99,7 +105,7 @@ static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
>>   static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
>>   				   struct drm_bridge *bridge)
>>   {
>> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
>> +	struct exynos_dp_device *dp = to_dp(plat_data);
>>   	struct drm_encoder *encoder = &dp->encoder;
>>   	int ret;
>>   
>> @@ -122,6 +128,28 @@ static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
>>   				 const struct drm_display_mode *mode,
>>   				 struct drm_display_mode *adjusted_mode)
>>   {
>> +	struct exynos_dp_device *dp = to_dp(encoder);
>> +	int flags = adjusted_mode->flags;
>> +
>> +	flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |
>> +		   DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC |
>> +		   DRM_MODE_FLAG_INTERLACE);
>> +
>> +	if (dp->video_info.h_sync_polarity)
>> +		flags |= DRM_MODE_FLAG_PHSYNC;
>> +	else
>> +		flags |= DRM_MODE_FLAG_NHSYNC;
>> +
>> +	if (dp->video_info.v_sync_polarity)
>> +		flags |= DRM_MODE_FLAG_PVSYNC;
>> +	else
>> +		flags |= DRM_MODE_FLAG_NVSYNC;
>> +
>> +	if (dp->video_info.interlaced)
>> +		flags |= DRM_MODE_FLAG_INTERLACE;
>> +
>> +	adjusted_mode->flags = flags;
>> +
>>   	return true;
>>   }
>>   
>> @@ -163,6 +191,22 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
>>   	return 0;
>>   }
>>   
>> +static int exynos_dp_dt_parse_video_info(struct exynos_dp_device *dp)
>> +{
>> +	struct device_node *dp_node = dp->dev->of_node;
>> +
>> +	dp->video_info.h_sync_polarity =
>> +		of_property_read_bool(dp_node, "hsync-active-high");
>> +
>> +	dp->video_info.v_sync_polarity =
>> +		of_property_read_bool(dp_node, "vsync-active-high");
>> +
>> +	dp->video_info.interlaced =
>> +		of_property_read_bool(dp_node, "interlaced");
>> +
>> +	return 0;
> Probably you wanted to follow the convention of other DT-parse functions
> but there is no need. This function cannot fail so maybe make it void?
> It would simplify a bit the code in exynos_dp_bind().

Actually, I found an mistaken here. I have parsed those two property for 
twice,
one is here, the other is analogix_dp_core.c mode_set() function.
         /*
          * NOTE: those property parseing code is used for
          * providing backward compatibility for samsung platform.
          */
         [....]
         of_property_read_u32(dp_node, "hsync-active-high",
                              (unsigned int *)&video_info->h_sync_polarity);
         of_property_read_u32(dp_node, "vsync-active-high",
                              (unsigned int *)&video_info->v_sync_polarity);
         of_property_read_u32(dp_node, "interlaced",
                              (unsigned int *)&video_info->interlaced);


And I think it would be easy to code when I achieve the backward 
compatibility
in analogix core driver. So I prefer this way :-)

Anyway, thanks,
- Yakir

> Best regards,
> Krzysztof
>
>
>



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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 05/16] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & colorimetry
@ 2015-09-06  2:00       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  2:00 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Krzysztof,

? 09/03/2015 04:04 PM, Krzysztof Kozlowski ??:
> On 01.09.2015 14:55, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code, same to color space and color depth can be
>> parsed from EDID.
>>
>> But presumably Exynos still relaies on the DT properties, so take
> s/relaies/relies/
>
>> good use of mode_fixup() in to achieve the compatibility hacks.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4:
>> - Take Krzysztof suggest, provide backword compatibility with samsung.
>> - Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.
>>
>> Changes in v3:
>> - Take Thierry Reding suggest, dynamic parse video timing info from
>>    struct drm_display_mode and struct drm_display_info.
>>
>> Changes in v2: None
>>
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 141 +++++++++++++--------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>>   drivers/gpu/drm/exynos/exynos_dp.c                 |  58 ++++++++-
>>   4 files changed, 151 insertions(+), 64 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index 7196097..f0db92e 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -897,8 +897,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
>>   		return;
>>   	}
>>   
>> -	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
>> -					 dp->video_info->link_rate);
>> +	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
>> +					 dp->video_info.link_rate);
>>   	if (ret) {
>>   		dev_err(dp->dev, "unable to do link train\n");
>>   		return;
>> @@ -1081,6 +1081,82 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
>>   	dp->dpms_mode = DRM_MODE_DPMS_OFF;
>>   }
>>   
>> +static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
>> +					struct drm_display_mode *orig_mode,
>> +					struct drm_display_mode *mode)
>> +{
>> +	struct analogix_dp_device *dp = bridge->driver_private;
>> +	struct drm_display_info *display_info = &dp->connector.display_info;
>> +	struct video_info *video_info = &dp->video_info;
>> +	struct device_node *dp_node = dp->dev->of_node;
>> +	int vic;
>> +
>> +	/* interlaces & hsync pol & vsync pol */
>> +	video_info->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
>> +	video_info->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
>> +	video_info->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>> +
>> +	/* dynamic_range & colorimetry */
>> +	vic = drm_match_cea_mode(mode);
>> +	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
>> +	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
>> +		video_info->dynamic_range = CEA;
>> +		video_info->ycbcr_coeff = COLOR_YCBCR601;
>> +	} else if (vic) {
>> +		video_info->dynamic_range = CEA;
>> +		video_info->ycbcr_coeff = COLOR_YCBCR709;
>> +	} else {
>> +		video_info->dynamic_range = VESA;
>> +		video_info->ycbcr_coeff = COLOR_YCBCR709;
>> +	}
>> +
>> +	switch (display_info->bpc) {
>> +	case 12:
>> +		video_info->color_depth = COLOR_12;
>> +		break;
>> +	case 10:
>> +		video_info->color_depth = COLOR_10;
>> +		break;
>> +	case 8:
>> +		video_info->color_depth = COLOR_8;
>> +		break;
>> +	case 6:
>> +		video_info->color_depth = COLOR_6;
>> +		break;
>> +	default:
>> +		video_info->color_depth = COLOR_8;
>> +		break;
>> +	}
>> +
>> +	if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB444)
>> +		video_info->color_space = COLOR_YCBCR444;
>> +	else if (display_info->color_formats | DRM_COLOR_FORMAT_YCRCB422)
>> +		video_info->color_space = COLOR_YCBCR422;
>> +	else if (display_info->color_formats | DRM_COLOR_FORMAT_RGB444)
>> +		video_info->color_space = COLOR_RGB;
>> +	else
>> +		video_info->color_space = COLOR_RGB;
>> +
>> +	/*
>> +	 * NOTE: those property parseing code is used for
> s/parseing/parsing/
>
> BTW, you can easily integrate spell-check to vim... It is not that I
> search for such misspellings - they are highlighted...

Wow, thanks for your remind, I have set the spell-check now.  :)

>
>> +	 * providing backward compatibility for samsung platform.
>> +	 */
>> +	of_property_read_u32(dp_node, "samsung,color-space",
>> +			     &video_info->color_space);
>> +	of_property_read_u32(dp_node, "samsung,dynamic-range",
>> +			     &video_info->dynamic_range);
>> +	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
>> +			     &video_info->ycbcr_coeff);
>> +	of_property_read_u32(dp_node, "samsung,color-depth",
>> +			     &video_info->color_depth);
>> +	of_property_read_u32(dp_node, "hsync-active-high",
>> +			     (unsigned int *)&video_info->h_sync_polarity);
>> +	of_property_read_u32(dp_node, "vsync-active-high",
>> +			     (unsigned int *)&video_info->v_sync_polarity);
>> +	of_property_read_u32(dp_node, "interlaced",
>> +			     (unsigned int *)&video_info->interlaced);
> You made assumption that the sizeof(bool) is always equal to
> sizeof(u32)... Then you cast it to pointer to unsigned int but function
> wants pointer to u32. Just for reading boolean property. There's easier
> way - of_property_read_bool. It returns bool.

Thanks, done.

>
>> +}
>> +
>>   static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
>>   {
>>   	/* do nothing */
>> @@ -1091,6 +1167,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
>>   	.disable = analogix_dp_bridge_disable,
>>   	.pre_enable = analogix_dp_bridge_nop,
>>   	.post_disable = analogix_dp_bridge_nop,
>> +	.mode_set = analogix_dp_bridge_mode_set,
>>   	.attach = analogix_dp_bridge_attach,
>>   };
>>   
>> @@ -1121,62 +1198,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>>   	return 0;
>>   }
>>   
>> -static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
>> +static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
>>   {
>> -	struct device_node *dp_node = dev->of_node;
>> -	struct video_info *dp_video_config;
>> -
>> -	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
>> -				       GFP_KERNEL);
>> -	if (!dp_video_config)
>> -		return ERR_PTR(-ENOMEM);
>> -
>> -	dp_video_config->h_sync_polarity =
>> -		of_property_read_bool(dp_node, "hsync-active-high");
>> -
>> -	dp_video_config->v_sync_polarity =
>> -		of_property_read_bool(dp_node, "vsync-active-high");
>> -
>> -	dp_video_config->interlaced =
>> -		of_property_read_bool(dp_node, "interlaced");
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,color-space",
>> -				 &dp_video_config->color_space)) {
>> -		dev_err(dev, "failed to get color-space\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
>> -				 &dp_video_config->dynamic_range)) {
>> -		dev_err(dev, "failed to get dynamic-range\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
>> -				 &dp_video_config->ycbcr_coeff)) {
>> -		dev_err(dev, "failed to get ycbcr-coeff\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,color-depth",
>> -				 &dp_video_config->color_depth)) {
>> -		dev_err(dev, "failed to get color-depth\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> +	struct device_node *dp_node = dp->dev->of_node;
>> +	struct video_info *video_config = &dp->video_info;
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,link-rate",
>> -				 &dp_video_config->link_rate)) {
>> +				 &video_info->link_rate)) {
>>   		dev_err(dev, "failed to get link-rate\n");
>> -		return ERR_PTR(-EINVAL);
>> +		return -EINVAL;
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,lane-count",
>> -				 &dp_video_config->lane_count)) {
>> +				 &video_info->lane_count)) {
>>   		dev_err(dev, "failed to get lane-count\n");
>> -		return ERR_PTR(-EINVAL);
>> +		return -EINVAL;
>>   	}
>>   
>> -	return dp_video_config;
>> +	return 0;
>>   }
>>   
>>   int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>> @@ -1205,9 +1244,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>>   	 */
>>   	dp->plat_data = plat_data;
>>   
>> -	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
>> -	if (IS_ERR(dp->video_info))
>> -		return PTR_ERR(dp->video_info);
>> +	ret = analogix_dp_dt_parse_pdata(dp);
>> +	if (ret)
>> +		return ret;
>>   
>>   	dp->phy = devm_phy_get(dp->dev, "dp");
>>   	if (IS_ERR(dp->phy)) {
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> index ffabbd0..6e3d5bc 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> @@ -154,7 +154,7 @@ struct analogix_dp_device {
>>   	unsigned int		irq;
>>   	void __iomem		*reg_base;
>>   
>> -	struct video_info	*video_info;
>> +	struct video_info	video_info;
>>   	struct link_train	link_train;
>>   	struct work_struct	hotplug_work;
>>   	struct phy		*phy;
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> index b879d8c..6a643be 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> @@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
>>   	u32 reg;
>>   
>>   	/* Configure the input color depth, color space, dynamic range */
>> -	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
>> -		(dp->video_info->color_depth << IN_BPC_SHIFT) |
>> -		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
>> +	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
>> +		(dp->video_info.color_depth << IN_BPC_SHIFT) |
>> +		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
>>   
>>   	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>>   	reg &= ~IN_YC_COEFFI_MASK;
>> -	if (dp->video_info->ycbcr_coeff)
>> +	if (dp->video_info.ycbcr_coeff)
>>   		reg |= IN_YC_COEFFI_ITU709;
>>   	else
>>   		reg |= IN_YC_COEFFI_ITU601;
>> @@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
>>   
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   	reg &= ~INTERACE_SCAN_CFG;
>> -	reg |= (dp->video_info->interlaced << 2);
>> +	reg |= (dp->video_info.interlaced << 2);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   	reg &= ~VSYNC_POLARITY_CFG;
>> -	reg |= (dp->video_info->v_sync_polarity << 1);
>> +	reg |= (dp->video_info.v_sync_polarity << 1);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   	reg &= ~HSYNC_POLARITY_CFG;
>> -	reg |= (dp->video_info->h_sync_polarity << 0);
>> +	reg |= (dp->video_info.h_sync_polarity << 0);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   
>>   	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
>> index 7e1be72..6060d2c 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp.c
>> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
>> @@ -28,8 +28,13 @@
>>   
>>   #include "exynos_drm_crtc.h"
>>   
>> -#define plat_data_to_dp(pd) \
>> -		container_of(pd, struct exynos_dp_device, plat_data)
>> +#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
>> +
>> +struct video_info {
>> +	bool h_sync_polarity;
>> +	bool v_sync_polarity;
>> +	bool interlaced;
>> +};
>>   
>>   struct exynos_dp_device {
>>   	struct drm_encoder         encoder;
>> @@ -39,12 +44,13 @@ struct exynos_dp_device {
>>   
>>   	struct exynos_drm_panel_info priv;
>>   	struct analogix_dp_plat_data plat_data;
>> +	struct video_info            video_info;
>>   };
>>   
>>   int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
>>   				bool enable)
>>   {
>> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
>> +	struct exynos_dp_device *dp = to_dp(plat_data);
>>   	struct drm_encoder *encoder = &dp->encoder;
>>   	struct exynos_drm_crtc *crtc;
>>   
>> @@ -71,7 +77,7 @@ static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
>>   static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
>>   			       struct drm_connector *connector)
>>   {
>> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
>> +	struct exynos_dp_device *dp = to_dp(plat_data);
>>   	struct drm_display_mode *mode;
>>   
>>   	if (dp->plat_data.panel)
>> @@ -99,7 +105,7 @@ static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data,
>>   static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
>>   				   struct drm_bridge *bridge)
>>   {
>> -	struct exynos_dp_device *dp = plat_data_to_dp(plat_data);
>> +	struct exynos_dp_device *dp = to_dp(plat_data);
>>   	struct drm_encoder *encoder = &dp->encoder;
>>   	int ret;
>>   
>> @@ -122,6 +128,28 @@ static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
>>   				 const struct drm_display_mode *mode,
>>   				 struct drm_display_mode *adjusted_mode)
>>   {
>> +	struct exynos_dp_device *dp = to_dp(encoder);
>> +	int flags = adjusted_mode->flags;
>> +
>> +	flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC |
>> +		   DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC |
>> +		   DRM_MODE_FLAG_INTERLACE);
>> +
>> +	if (dp->video_info.h_sync_polarity)
>> +		flags |= DRM_MODE_FLAG_PHSYNC;
>> +	else
>> +		flags |= DRM_MODE_FLAG_NHSYNC;
>> +
>> +	if (dp->video_info.v_sync_polarity)
>> +		flags |= DRM_MODE_FLAG_PVSYNC;
>> +	else
>> +		flags |= DRM_MODE_FLAG_NVSYNC;
>> +
>> +	if (dp->video_info.interlaced)
>> +		flags |= DRM_MODE_FLAG_INTERLACE;
>> +
>> +	adjusted_mode->flags = flags;
>> +
>>   	return true;
>>   }
>>   
>> @@ -163,6 +191,22 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
>>   	return 0;
>>   }
>>   
>> +static int exynos_dp_dt_parse_video_info(struct exynos_dp_device *dp)
>> +{
>> +	struct device_node *dp_node = dp->dev->of_node;
>> +
>> +	dp->video_info.h_sync_polarity =
>> +		of_property_read_bool(dp_node, "hsync-active-high");
>> +
>> +	dp->video_info.v_sync_polarity =
>> +		of_property_read_bool(dp_node, "vsync-active-high");
>> +
>> +	dp->video_info.interlaced =
>> +		of_property_read_bool(dp_node, "interlaced");
>> +
>> +	return 0;
> Probably you wanted to follow the convention of other DT-parse functions
> but there is no need. This function cannot fail so maybe make it void?
> It would simplify a bit the code in exynos_dp_bind().

Actually, I found an mistaken here. I have parsed those two property for 
twice,
one is here, the other is analogix_dp_core.c mode_set() function.
         /*
          * NOTE: those property parseing code is used for
          * providing backward compatibility for samsung platform.
          */
         [....]
         of_property_read_u32(dp_node, "hsync-active-high",
                              (unsigned int *)&video_info->h_sync_polarity);
         of_property_read_u32(dp_node, "vsync-active-high",
                              (unsigned int *)&video_info->v_sync_polarity);
         of_property_read_u32(dp_node, "interlaced",
                              (unsigned int *)&video_info->interlaced);


And I think it would be easy to code when I achieve the backward 
compatibility
in analogix core driver. So I prefer this way :-)

Anyway, thanks,
- Yakir

> Best regards,
> Krzysztof
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
  2015-09-03  8:38             ` Thierry Reding
@ 2015-09-06  2:06               ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  2:06 UTC (permalink / raw)
  To: Thierry Reding, Mark Yao
  Cc: Heiko Stuebner, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Russell King, djkurtz, dianders, seanpaul,
	ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel, s.infradead.org, Mark Yao

Hi Thierry,

在 09/03/2015 04:38 PM, Thierry Reding 写道:
> On Wed, Sep 02, 2015 at 06:02:25PM +0800, Yakir Yang wrote:
>> 在 2015/9/2 16:34, Thierry Reding 写道:
> [...]
>>> At the very least your code must compile when applied against a recent
>>> upstream tree. I would also expect you to make sure the code works at
>>> runtime, though, contrary to build testing, not everybody will be able
>>> to verify that you've actually done so. It is ultimately your platform
>>> maintainer's (i.e. Heiko's) responsibility to ensure that because they
>>> will get to deal with user complaints if people can't run an upstream
>>> kernel on the devices.
>> Oh, first time to know this rule. So I should work on Heiko's github
>> kernel branch at the first time to start send upstream.
> It's usually not necessary to rebase on a specific platform tree. Most
> platform trees should feed into linux-next anyway, so linux-next would
> be the appropriate base in almost all cases.
>
> Note, though, that that's only true if you expect somebody else to merge
> your code. The reason is that whoever will end up applying your patches
> will likely apply to a tree that feeds into linux-next, and that way you
> both end up having roughly the same base.
>
> On the other hand if you are a maintainer yourself you should be keeping
> a branch based on the latest -rc1. That's especially important if your
> tree feeds into linux-next, because basing on linux-next will break very
> horribly that way.
>
> So for this particular case I would expect either Mark or Inki to apply
> these patches when they're ready. Their trees should be based on the
> latest -rc1. At least the Exynos DRM tree feeds into linux-next, so you
> should be fine if you use linux-next as a base.

Glad to know this, thanks,
- Yakir

>
> Mark, have you ever considered having your tree added to linux-next?
>
> I'm beginning to think that we need to make that a requirement for all
> DRM drivers so that we can resolve integration issues early on rather
> than Dave having to deal with them when he pulls code in.
>
> Thierry



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting
@ 2015-09-06  2:06               ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  2:06 UTC (permalink / raw)
  To: Thierry Reding, Mark Yao
  Cc: Heiko Stuebner, Jingoo Han, Inki Dae, joe, Kukjin Kim,
	Krzysztof Kozlowski, Russell King, djkurtz, dianders, seanpaul,
	ajaynumb, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I, architt, robherring2,
	dri-devel, devicetree, linux-kernel, linux-samsung-soc

Hi Thierry,

在 09/03/2015 04:38 PM, Thierry Reding 写道:
> On Wed, Sep 02, 2015 at 06:02:25PM +0800, Yakir Yang wrote:
>> 在 2015/9/2 16:34, Thierry Reding 写道:
> [...]
>>> At the very least your code must compile when applied against a recent
>>> upstream tree. I would also expect you to make sure the code works at
>>> runtime, though, contrary to build testing, not everybody will be able
>>> to verify that you've actually done so. It is ultimately your platform
>>> maintainer's (i.e. Heiko's) responsibility to ensure that because they
>>> will get to deal with user complaints if people can't run an upstream
>>> kernel on the devices.
>> Oh, first time to know this rule. So I should work on Heiko's github
>> kernel branch at the first time to start send upstream.
> It's usually not necessary to rebase on a specific platform tree. Most
> platform trees should feed into linux-next anyway, so linux-next would
> be the appropriate base in almost all cases.
>
> Note, though, that that's only true if you expect somebody else to merge
> your code. The reason is that whoever will end up applying your patches
> will likely apply to a tree that feeds into linux-next, and that way you
> both end up having roughly the same base.
>
> On the other hand if you are a maintainer yourself you should be keeping
> a branch based on the latest -rc1. That's especially important if your
> tree feeds into linux-next, because basing on linux-next will break very
> horribly that way.
>
> So for this particular case I would expect either Mark or Inki to apply
> these patches when they're ready. Their trees should be based on the
> latest -rc1. At least the Exynos DRM tree feeds into linux-next, so you
> should be fine if you use linux-next as a base.

Glad to know this, thanks,
- Yakir

>
> Mark, have you ever considered having your tree added to linux-next?
>
> I'm beginning to think that we need to make that a requirement for all
> DRM drivers so that we can resolve integration issues early on rather
> than Dave having to deal with them when he pulls code in.
>
> Thierry

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2015-09-03  9:04         ` Thierry Reding
@ 2015-09-06  3:59           ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  3:59 UTC (permalink / raw)
  To: Thierry Reding, Russell King
  Cc: Krzysztof Kozlowski, dri-devel, Andrzej Hajda, Gustavo Padovan,
	linux-samsung-soc, seanpaul, djkurtz, Kishon Vijay Abraham I,
	linux-rockchip, Kukjin Kim, Rob Herring, devicetree, Pawel Moll,
	Ian Campbell, Joe Perches, Rob Herring, dianders,
	linux-arm-kernel, Jingoo Han, linux-kernel, Kyungmin Park


[-- Attachment #1.1: Type: text/plain, Size: 3023 bytes --]

Hi Thierry,

在 09/03/2015 05:04 PM, Thierry Reding 写道:
> On Thu, Sep 03, 2015 at 12:27:47PM +0800, Yakir Yang wrote:
>> Hi Rob,
>>
>> 在 09/03/2015 04:17 AM, Rob Herring 写道:
>>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>>>> Some edp screen do not have hpd signal, so we can't just return
>>>> failed when hpd plug in detect failed.
>>> This is a property of the panel (or connector perhaps), so this
>>> property should be located there. At least, it is a common issue and
>>> not specific to this chip. We could have an HDMI connector and failed
>>> to hook up HPD for example. A connector node is also where hpd-gpios
>>> should be located instead (and are already defined by
>>> ../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
>>> binding, too.
>> Yep, I agree with your front point, it is a property of panel, not specific
>> to eDP controller, so this code should handle in connector logic.
>  From your description it sounds more like this is in fact a property of
> the panel. Or maybe I should say "quirk". If the panel doesn't generate
> the HPD signal, then that should be a property of the panel, not the
> connector. The eDP specification mandates that connectors have a HPD
> signal, though it allows the "HPD conductor in the connector cable" to
> be omitted if not used by the source. I'd consider the cable to belong
> to the panel rather than the connector, so absence of HPD, either
> because the cable doesn't have the conductor or because the panel does
> not generate the signal, should be a quirk of the panel.
>
> That said you could have a panel that supports HPD connected via a cable
> that doesn't transmit it, so this would be a per-board variant and hence
> should be a device tree property rather than hard-coded in some panel
> driver.
>
> Conversely, if the panel isn't capable of generating an HPD signal, then
> I don't think it would be appropriate to make it a DT property. It would
> be better to hard-code it in the driver, lest someone forget to set the
> property in DT and get stuck with a device that isn't operational.

Oh, you're right, if it's a cable quirk, then DT property would be okay, 
if it
is a problem of panel, then maybe hard-code in driver would be better.

After look up for the document of panel "innolux,n116bge", I haven't see
any description of hot plug signal, and even not found in PIN ASSIGNMENT.
So I believe it's a panel problem, that's to say it should handle in 
panel driver.

Hmm... But I don't know how to cover the whole hpd situation in panel 
detect,
it looks complicate  *_*

And Russell have remind that DRM .force is another way to handle this one,
but I haven't understand it very well. I see we need make connector->force =
DRM_FORCE_ON, then we can enable eDP in connector->funcs->force(). But
I don't how to handle connector->force automatically without DT property,
could some guys help here    :-D

Thanks,
- Yakir

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_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-06  3:59           ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  3:59 UTC (permalink / raw)
  To: Thierry Reding, Russell King
  Cc: Krzysztof Kozlowski, dri-devel, Andrzej Hajda, Gustavo Padovan,
	linux-samsung-soc, seanpaul, djkurtz, Kishon Vijay Abraham I,
	linux-rockchip, Kukjin Kim, Rob Herring, devicetree, Pawel Moll,
	Ian Campbell, Joe Perches, Rob Herring, dianders,
	linux-arm-kernel, Jingoo Han, linux-kernel, Kyungmin Park


[-- Attachment #1.1: Type: text/plain, Size: 3023 bytes --]

Hi Thierry,

在 09/03/2015 05:04 PM, Thierry Reding 写道:
> On Thu, Sep 03, 2015 at 12:27:47PM +0800, Yakir Yang wrote:
>> Hi Rob,
>>
>> 在 09/03/2015 04:17 AM, Rob Herring 写道:
>>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>>>> Some edp screen do not have hpd signal, so we can't just return
>>>> failed when hpd plug in detect failed.
>>> This is a property of the panel (or connector perhaps), so this
>>> property should be located there. At least, it is a common issue and
>>> not specific to this chip. We could have an HDMI connector and failed
>>> to hook up HPD for example. A connector node is also where hpd-gpios
>>> should be located instead (and are already defined by
>>> ../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
>>> binding, too.
>> Yep, I agree with your front point, it is a property of panel, not specific
>> to eDP controller, so this code should handle in connector logic.
>  From your description it sounds more like this is in fact a property of
> the panel. Or maybe I should say "quirk". If the panel doesn't generate
> the HPD signal, then that should be a property of the panel, not the
> connector. The eDP specification mandates that connectors have a HPD
> signal, though it allows the "HPD conductor in the connector cable" to
> be omitted if not used by the source. I'd consider the cable to belong
> to the panel rather than the connector, so absence of HPD, either
> because the cable doesn't have the conductor or because the panel does
> not generate the signal, should be a quirk of the panel.
>
> That said you could have a panel that supports HPD connected via a cable
> that doesn't transmit it, so this would be a per-board variant and hence
> should be a device tree property rather than hard-coded in some panel
> driver.
>
> Conversely, if the panel isn't capable of generating an HPD signal, then
> I don't think it would be appropriate to make it a DT property. It would
> be better to hard-code it in the driver, lest someone forget to set the
> property in DT and get stuck with a device that isn't operational.

Oh, you're right, if it's a cable quirk, then DT property would be okay, 
if it
is a problem of panel, then maybe hard-code in driver would be better.

After look up for the document of panel "innolux,n116bge", I haven't see
any description of hot plug signal, and even not found in PIN ASSIGNMENT.
So I believe it's a panel problem, that's to say it should handle in 
panel driver.

Hmm... But I don't know how to cover the whole hpd situation in panel 
detect,
it looks complicate  *_*

And Russell have remind that DRM .force is another way to handle this one,
but I haven't understand it very well. I see we need make connector->force =
DRM_FORCE_ON, then we can enable eDP in connector->funcs->force(). But
I don't how to handle connector->force automatically without DT property,
could some guys help here    :-D

Thanks,
- Yakir

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_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support
  2015-09-04  0:36     ` Krzysztof Kozlowski
@ 2015-09-06  4:07       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  4:07 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Krzysztof,

在 09/04/2015 08:36 AM, Krzysztof Kozlowski 写道:
> On 01.09.2015 15:07, Yakir Yang wrote:
>
> Empty commit message. Please explain here why you want to add platform
> device type support.
>
> Actually the title is confusing. You are not adding support for platform
> device types but rather adding a field containing type of device.
>
>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2:
>> - Add GNU license v2 declared and samsung copyright
>>
>>   drivers/gpu/drm/exynos/exynos_dp.c              |  1 +
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c |  1 +
>>   include/drm/bridge/analogix_dp.h                | 16 ++++++++++++++++
>>   3 files changed, 18 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
>> index 6060d2c..40ef727 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp.c
>> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
>> @@ -224,6 +224,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>>   	dp->dev = dev;
>>   	dp->drm_dev = drm_dev;
>>   
>> +	dp->plat_data.dev_type = EXYNOS_DP;
>>   	dp->plat_data.power_on = exynos_dp_poweron;
>>   	dp->plat_data.power_off = exynos_dp_poweroff;
>>   	dp->plat_data.get_modes = exynos_dp_get_modes;
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> index efea045..4934271 100644
>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -293,6 +293,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
>>   		return ret;
>>   	}
>>   
>> +	dp->plat_data.dev_type = RK3288_DP;
>>   	dp->plat_data.attach = NULL;
>>   	dp->plat_data.get_modes = NULL;
>>   	dp->plat_data.power_on = rockchip_dp_poweron;
>> diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
>> index 8b4ffad..7209a64 100644
>> --- a/include/drm/bridge/analogix_dp.h
>> +++ b/include/drm/bridge/analogix_dp.h
>> @@ -1,9 +1,25 @@
>> +/*
>> + * Analogix Core DP (Display Port) interface driver.
>> + *
>> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License as published by the
>> + * Free Software Foundation; either version 2 of the License, or (at your
>> + * option) any later version.
>> + */
> Two questions:
> 1. Why this change is here? I would rather expect it at patch 3/16 when
> you created this file... That is the usual time for adding copyrights.

Yep, I should move this to 03/16.

> 2. Does this file contains previous Samsung work?

Hmm... I think this haven't contains the previous Samsung works,
but I have the cover the head message from analogix_dp_core driver
(include the copyright, but without ant author).

Thanks
- Yakir

> Best regards,
> Krzysztof
>
>>   #ifndef _ANALOGIX_DP_H_
>>   #define _ANALOGIX_DP_H_
>>   
>>   #include <drm/drm_crtc.h>
>>   
>> +enum analogix_dp_devtype {
>> +	EXYNOS_DP,
>> +	RK3288_DP,
>> +};
>> +
>>   struct analogix_dp_plat_data {
>> +	enum analogix_dp_devtype dev_type;
>>   	struct drm_panel *panel;
>>   
>>   	int (*power_on)(struct analogix_dp_plat_data *);
>>
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support
@ 2015-09-06  4:07       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  4:07 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Krzysztof,

? 09/04/2015 08:36 AM, Krzysztof Kozlowski ??:
> On 01.09.2015 15:07, Yakir Yang wrote:
>
> Empty commit message. Please explain here why you want to add platform
> device type support.
>
> Actually the title is confusing. You are not adding support for platform
> device types but rather adding a field containing type of device.
>
>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2:
>> - Add GNU license v2 declared and samsung copyright
>>
>>   drivers/gpu/drm/exynos/exynos_dp.c              |  1 +
>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c |  1 +
>>   include/drm/bridge/analogix_dp.h                | 16 ++++++++++++++++
>>   3 files changed, 18 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
>> index 6060d2c..40ef727 100644
>> --- a/drivers/gpu/drm/exynos/exynos_dp.c
>> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
>> @@ -224,6 +224,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>>   	dp->dev = dev;
>>   	dp->drm_dev = drm_dev;
>>   
>> +	dp->plat_data.dev_type = EXYNOS_DP;
>>   	dp->plat_data.power_on = exynos_dp_poweron;
>>   	dp->plat_data.power_off = exynos_dp_poweroff;
>>   	dp->plat_data.get_modes = exynos_dp_get_modes;
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> index efea045..4934271 100644
>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -293,6 +293,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
>>   		return ret;
>>   	}
>>   
>> +	dp->plat_data.dev_type = RK3288_DP;
>>   	dp->plat_data.attach = NULL;
>>   	dp->plat_data.get_modes = NULL;
>>   	dp->plat_data.power_on = rockchip_dp_poweron;
>> diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
>> index 8b4ffad..7209a64 100644
>> --- a/include/drm/bridge/analogix_dp.h
>> +++ b/include/drm/bridge/analogix_dp.h
>> @@ -1,9 +1,25 @@
>> +/*
>> + * Analogix Core DP (Display Port) interface driver.
>> + *
>> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License as published by the
>> + * Free Software Foundation; either version 2 of the License, or (at your
>> + * option) any later version.
>> + */
> Two questions:
> 1. Why this change is here? I would rather expect it at patch 3/16 when
> you created this file... That is the usual time for adding copyrights.

Yep, I should move this to 03/16.

> 2. Does this file contains previous Samsung work?

Hmm... I think this haven't contains the previous Samsung works,
but I have the cover the head message from analogix_dp_core driver
(include the copyright, but without ant author).

Thanks
- Yakir

> Best regards,
> Krzysztof
>
>>   #ifndef _ANALOGIX_DP_H_
>>   #define _ANALOGIX_DP_H_
>>   
>>   #include <drm/drm_crtc.h>
>>   
>> +enum analogix_dp_devtype {
>> +	EXYNOS_DP,
>> +	RK3288_DP,
>> +};
>> +
>>   struct analogix_dp_plat_data {
>> +	enum analogix_dp_devtype dev_type;
>>   	struct drm_panel *panel;
>>   
>>   	int (*power_on)(struct analogix_dp_plat_data *);
>>
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
  2015-09-03 13:52         ` Heiko Stuebner
@ 2015-09-06  4:09           ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  4:09 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Rob Herring, Thierry Reding, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel

Hi Heiko,

在 09/03/2015 09:52 PM, Heiko Stuebner 写道:
> Am Donnerstag, 3. September 2015, 11:25:00 schrieb Yakir Yang:
>> 在 09/02/2015 09:27 PM, Rob Herring 写道:
>>> On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>>>> +- clocks: from common clock binding: handle to dp clock.
>>>> +       of memory mapped region.
>>>> +- clock-names: from common clock binding:
>>>> +       Required elements: "sclk_dp" "sclk_dp_24m"
>>>> +
>>>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>>> I have no idea what GRF means.
>> GRF is an module of our IC chip, the full name is General Register Files.
>> I would rather to pick some words from our TRM.
>>
>> The general register file will be used to do static set by software, which
>> is composed of many registers for system control.
> The general register files are present on all Rockchip SoCs I've seen so far
> and really are just an aggregation of registers for settings and status
> indications, ranging from memory stuff, dma-controller settings, usb-phy and
> settings for a lot of other phys, etc.
>
> The most prevalent description in dt-bindings is currently:
>
> - rockchip,grf: phandle to the syscon managing the "general register files"

Wow, thanks for your explain, and your "rockchip,grf" DT property
description is better, I would like to copy it :)

Thanks,
- Yakir
>
> Heiko
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY
@ 2015-09-06  4:09           ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  4:09 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Heiko,

? 09/03/2015 09:52 PM, Heiko Stuebner ??:
> Am Donnerstag, 3. September 2015, 11:25:00 schrieb Yakir Yang:
>> ? 09/02/2015 09:27 PM, Rob Herring ??:
>>> On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>>>> +- clocks: from common clock binding: handle to dp clock.
>>>> +       of memory mapped region.
>>>> +- clock-names: from common clock binding:
>>>> +       Required elements: "sclk_dp" "sclk_dp_24m"
>>>> +
>>>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>>> I have no idea what GRF means.
>> GRF is an module of our IC chip, the full name is General Register Files.
>> I would rather to pick some words from our TRM.
>>
>> The general register file will be used to do static set by software, which
>> is composed of many registers for system control.
> The general register files are present on all Rockchip SoCs I've seen so far
> and really are just an aggregation of registers for settings and status
> indications, ranging from memory stuff, dma-controller settings, usb-phy and
> settings for a lot of other phys, etc.
>
> The most prevalent description in dt-bindings is currently:
>
> - rockchip,grf: phandle to the syscon managing the "general register files"

Wow, thanks for your explain, and your "rockchip,grf" DT property
description is better, I would like to copy it :)

Thanks,
- Yakir
>
> Heiko
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
  2015-09-04  0:41         ` Krzysztof Kozlowski
@ 2015-09-06  7:49           ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  7:49 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Krzysztof,

在 09/04/2015 08:41 AM, Krzysztof Kozlowski 写道:
> On 03.09.2015 14:30, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> 在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
>>> On 01.09.2015 14:49, Yakir Yang wrote:
>>>> Split the dp core driver from exynos directory to bridge
>>>> directory, and rename the core driver to analogix_dp_*,
>>>> leave the platform code to analogix_dp-exynos.
>>>>
>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>> ---
>>>> Changes in v4:
>>>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT
>>>> propery.
>>>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to
>>>> "exynos_dp.c"
>>>> - Take Archit suggest, create a separate folder for analogix code in
>>>> bridge/
>>>>
>>>> Changes in v3:
>>>> - Take Thierry Reding suggest, move exynos's video_timing code
>>>>     to analogix_dp-exynos platform driver, add get_modes method
>>>>     to struct analogix_dp_plat_data.
>>>> - Take Heiko suggest, rename some "samsung*" dts propery to "analogix*".
>>>>
>>>> Changes in v2:
>>>> - Take Jingoo Han suggest, remove new copyright
>>>> - Fix compiled failed dut to analogix_dp_device misspell

[.....]

>>>> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
>>>> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>>>>    {
>>>> -    struct exynos_dp_device *dp = bridge->driver_private;
>>>> -    struct drm_encoder *encoder = &dp->encoder;
>>>> +    struct analogix_dp_device *dp = bridge->driver_private;
>>>> +    struct drm_encoder *encoder = dp->encoder;
>>>>        struct drm_connector *connector = &dp->connector;
>>>>        int ret;
>>>>    -    /* Pre-empt DP connector creation if there's a bridge */
>>>> -    if (dp->ptn_bridge) {
>>>> -        ret = exynos_drm_attach_lcd_bridge(dp, encoder);
>>>> -        if (!ret)
>>>> -            return 0;
>>>> +    if (!bridge->encoder) {
>>>> +        DRM_ERROR("Parent encoder object not found");
>>>> +        return -ENODEV;
>>>>        }
>>>>    +    encoder->bridge = bridge;
>>>> +
>>>>        connector->polled = DRM_CONNECTOR_POLL_HPD;
>>>>          ret = drm_connector_init(dp->drm_dev, connector,
>>>> -                 &exynos_dp_connector_funcs,
>>>> +                 &analogix_dp_connector_funcs,
>>>>                     DRM_MODE_CONNECTOR_eDP);
>>>>        if (ret) {
>>>>            DRM_ERROR("Failed to initialize connector with drm\n");
>>>>            return ret;
>>>>        }
>>>>    -    drm_connector_helper_add(connector,
>>>> &exynos_dp_connector_helper_funcs);
>>>> +    drm_connector_helper_add(connector,
>>>> +                 &analogix_dp_connector_helper_funcs);
>>>>        drm_connector_register(connector);
>>>>        drm_mode_connector_attach_encoder(connector, encoder);
>>>>    -    if (dp->panel)
>>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>>> +        if (ret) {
>>>> +            DRM_ERROR("Failed to attach panel\n");
>>>> +            return ret;
>>>> +        }
>>>> +    }
>>>> +
>>>> +    /*
>>>> +     * This should be the end of attach function, caused
>>>> +     * we should ensure dp bridge could attach first.
>>>> +     */
>>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>>> +         if (ret) {
>>>> +             DRM_ERROR("Failed at platform attch func\n");
>>> Two new error paths appeared here and above. Don't you have to
>>> cleanup something? I don't know, just wondering...
>> Hmm... I think both panel & platform_attch need ERROR remind when
>> it failed. But if it still need clean, I though it should clean the platform attch
>> error,
>> this is not relate to DRM directly, just analogix driver logic, so code would like,
>>
>> -    if (dp->panel)
>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>> +    if (dp->plat_data && dp->plat_data->panel) {
>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>> +        if (ret) {
>> +            DRM_ERROR("Failed to attach panel\n");
>> +            return ret;
>> +        }
>> +    }
>>
>> +    /*
>> +     * This should be the end of attach function, caused
>> +     * we should ensure dp bridge could attach first.
>> +     */
>> +     if (dp->plat_data && dp->plat_data->attach) {
>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>
>>            return ret;
> I am lost... the code looks the same. What did you change?

I just remove the DRM_ERROR after dp->plat_data->attach(),
maybe I should paste the change that rebase on this patch,
here are they,

     /*
      * This should be the end of attach function, caused
      * we should ensure dp bridge could attach first.
      */
-     if (dp->plat_data && dp->plat_data->attach) {
+     if (dp->plat_data && dp->plat_data->attach)
            ret = dp->plat_data->attach(dp->plat_data, bridge);
-          if (ret) {
-              DRM_ERROR("Failed at platform attch func\n");
-              return ret;
-          }
-      }

-    return 0;
+   return ret;


If this haven't meet your comment, I maybe start to think that
your comment  "Two new error paths appeared here and above"
indicated that those two function is the same.
     "dp->plat_data->attach(dp->plat_data, bridge); "
     "drm_panel_attach(dp->plat_data->panel, &dp->connector); "

Thanks,
- Yakir
> Best regards,
> Krzysztof
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-06  7:49           ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  7:49 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Krzysztof,

? 09/04/2015 08:41 AM, Krzysztof Kozlowski ??:
> On 03.09.2015 14:30, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> ? 09/03/2015 08:58 AM, Krzysztof Kozlowski ??:
>>> On 01.09.2015 14:49, Yakir Yang wrote:
>>>> Split the dp core driver from exynos directory to bridge
>>>> directory, and rename the core driver to analogix_dp_*,
>>>> leave the platform code to analogix_dp-exynos.
>>>>
>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>> ---
>>>> Changes in v4:
>>>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT
>>>> propery.
>>>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to
>>>> "exynos_dp.c"
>>>> - Take Archit suggest, create a separate folder for analogix code in
>>>> bridge/
>>>>
>>>> Changes in v3:
>>>> - Take Thierry Reding suggest, move exynos's video_timing code
>>>>     to analogix_dp-exynos platform driver, add get_modes method
>>>>     to struct analogix_dp_plat_data.
>>>> - Take Heiko suggest, rename some "samsung*" dts propery to "analogix*".
>>>>
>>>> Changes in v2:
>>>> - Take Jingoo Han suggest, remove new copyright
>>>> - Fix compiled failed dut to analogix_dp_device misspell

[.....]

>>>> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
>>>> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>>>>    {
>>>> -    struct exynos_dp_device *dp = bridge->driver_private;
>>>> -    struct drm_encoder *encoder = &dp->encoder;
>>>> +    struct analogix_dp_device *dp = bridge->driver_private;
>>>> +    struct drm_encoder *encoder = dp->encoder;
>>>>        struct drm_connector *connector = &dp->connector;
>>>>        int ret;
>>>>    -    /* Pre-empt DP connector creation if there's a bridge */
>>>> -    if (dp->ptn_bridge) {
>>>> -        ret = exynos_drm_attach_lcd_bridge(dp, encoder);
>>>> -        if (!ret)
>>>> -            return 0;
>>>> +    if (!bridge->encoder) {
>>>> +        DRM_ERROR("Parent encoder object not found");
>>>> +        return -ENODEV;
>>>>        }
>>>>    +    encoder->bridge = bridge;
>>>> +
>>>>        connector->polled = DRM_CONNECTOR_POLL_HPD;
>>>>          ret = drm_connector_init(dp->drm_dev, connector,
>>>> -                 &exynos_dp_connector_funcs,
>>>> +                 &analogix_dp_connector_funcs,
>>>>                     DRM_MODE_CONNECTOR_eDP);
>>>>        if (ret) {
>>>>            DRM_ERROR("Failed to initialize connector with drm\n");
>>>>            return ret;
>>>>        }
>>>>    -    drm_connector_helper_add(connector,
>>>> &exynos_dp_connector_helper_funcs);
>>>> +    drm_connector_helper_add(connector,
>>>> +                 &analogix_dp_connector_helper_funcs);
>>>>        drm_connector_register(connector);
>>>>        drm_mode_connector_attach_encoder(connector, encoder);
>>>>    -    if (dp->panel)
>>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>>> +        if (ret) {
>>>> +            DRM_ERROR("Failed to attach panel\n");
>>>> +            return ret;
>>>> +        }
>>>> +    }
>>>> +
>>>> +    /*
>>>> +     * This should be the end of attach function, caused
>>>> +     * we should ensure dp bridge could attach first.
>>>> +     */
>>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>>> +         if (ret) {
>>>> +             DRM_ERROR("Failed at platform attch func\n");
>>> Two new error paths appeared here and above. Don't you have to
>>> cleanup something? I don't know, just wondering...
>> Hmm... I think both panel & platform_attch need ERROR remind when
>> it failed. But if it still need clean, I though it should clean the platform attch
>> error,
>> this is not relate to DRM directly, just analogix driver logic, so code would like,
>>
>> -    if (dp->panel)
>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>> +    if (dp->plat_data && dp->plat_data->panel) {
>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>> +        if (ret) {
>> +            DRM_ERROR("Failed to attach panel\n");
>> +            return ret;
>> +        }
>> +    }
>>
>> +    /*
>> +     * This should be the end of attach function, caused
>> +     * we should ensure dp bridge could attach first.
>> +     */
>> +     if (dp->plat_data && dp->plat_data->attach) {
>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>
>>            return ret;
> I am lost... the code looks the same. What did you change?

I just remove the DRM_ERROR after dp->plat_data->attach(),
maybe I should paste the change that rebase on this patch,
here are they,

     /*
      * This should be the end of attach function, caused
      * we should ensure dp bridge could attach first.
      */
-     if (dp->plat_data && dp->plat_data->attach) {
+     if (dp->plat_data && dp->plat_data->attach)
            ret = dp->plat_data->attach(dp->plat_data, bridge);
-          if (ret) {
-              DRM_ERROR("Failed at platform attch func\n");
-              return ret;
-          }
-      }

-    return 0;
+   return ret;


If this haven't meet your comment, I maybe start to think that
your comment  "Two new error paths appeared here and above"
indicated that those two function is the same.
     "dp->plat_data->attach(dp->plat_data, bridge); "
     "drm_panel_attach(dp->plat_data->panel, &dp->connector); "

Thanks,
- Yakir
> Best regards,
> Krzysztof
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-06  8:20           ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  8:20 UTC (permalink / raw)
  To: Rob Herring
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	Russell King, djkurtz, dianders, seanpaul, Ajay kumar,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Rob,

在 09/05/2015 05:46 AM, Rob Herring 写道:
> On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang <ykk@rock-chips.com> wrote:
>> Hi Rob,
>>
>> 在 09/03/2015 04:17 AM, Rob Herring 写道:
>>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>>>> Some edp screen do not have hpd signal, so we can't just return
>>>> failed when hpd plug in detect failed.
>>> This is a property of the panel (or connector perhaps), so this
>>> property should be located there. At least, it is a common issue and
>>> not specific to this chip. We could have an HDMI connector and failed
>>> to hook up HPD for example. A connector node is also where hpd-gpios
>>> should be located instead (and are already defined by
>>> ../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
>>> binding, too.
>>
>> Yep, I agree with your front point, it is a property of panel, not specific
>> to eDP controller, so this code should handle in connector logic.
>>
>> But another question, if we just leave this property to connector,
>> then we would need to parse this property in analogix_dp-rockchip.c,
>> and then make an hook in analogix_dp_core.c driver. This is not nice,
>> and if there are some coming platform which alse want to use analogix_dp
>> code and meet this "no-hpd" situation,  then they would need duplicate
>> to parse this property and fill the hook in analogix_dp_core.c driver.
>> So it's little bit conflict  :-)
> Ideally, you would be able to just retrieve this quirk from the
> connector or panel. Getting this property from your node vs. the port
> you are attached to should not be much harder. Either the connector
> struct can have this info or there can be a DT function that can walk
> the graph and get it. Just don't open code the graph traversal in your
> driver.
>
>> Beside I can not understand your example very well. Do you mean
>> that there are some HDMI monitor which also do not have HPD
>> signal (just like some eDP panel do not have hpd too), and then
>> the "hpd-gpios" ? Hmm... I don't know how the "hpd-gpios" want
>> to help in this case, would you mind show some sample code  :-D
> I don't know that there is h/w, but it is always possible HPD is not
> hooked up or hooked up incorrectly some how.
>
> If there is no HPD support, then hpd-gpios is not going to help you.
>
> I think there are 3 cases to handle:
> - HPD handled by bridge chip - The bridge driver knows it has this
> capability. No DT properties are needed and no HPD properties on the
> connector node imply the bridge chip should handle HPD functions.
> - HPD handled by GPIO line (or some other block) - Indicated by
> hpd-gpios present
> - No or broken HPD - Indicated by "hpd-force" property.

Oh, I think the first/second case isn't suitable in this case, my panel
"cnm,n116bgeea2" haven't included HPD signal.

>
>>> Are there any eDP panels which don't have EDID and need panel details in
>>> DT?
>>
>> Oh, I think you want to collect some info that belong to panel
>> property but no indicate in panel EDID message, so those can
>> be collect in eDP connector binding, is it right ?
> Yes, and as Thierry pointed out we may need to know the exact panel even.

Yeah, just like I reply to Thierry, this is a panel quirk. And he 
suggest we should
handle this in panel driver, but I have no idea how to handle this in 
common panel
driver.   :)

- Yakir

> Rob
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-06  8:20           ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  8:20 UTC (permalink / raw)
  To: Rob Herring
  Cc: Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	Russell King, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	dianders-F7+t8E8rja9Wk0Htik3J/w, seanpaul-F7+t8E8rja9Wk0Htik3J/w,
	Ajay kumar, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Rob Herring,
	Pawel Moll, Kishon Vijay Abraham I,
	architt-sgV2jX0FEOL9JmXXK+q4OQ, dri-devel

Hi Rob,

在 09/05/2015 05:46 AM, Rob Herring 写道:
> On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
>> Hi Rob,
>>
>> 在 09/03/2015 04:17 AM, Rob Herring 写道:
>>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
>>>> Some edp screen do not have hpd signal, so we can't just return
>>>> failed when hpd plug in detect failed.
>>> This is a property of the panel (or connector perhaps), so this
>>> property should be located there. At least, it is a common issue and
>>> not specific to this chip. We could have an HDMI connector and failed
>>> to hook up HPD for example. A connector node is also where hpd-gpios
>>> should be located instead (and are already defined by
>>> ../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
>>> binding, too.
>>
>> Yep, I agree with your front point, it is a property of panel, not specific
>> to eDP controller, so this code should handle in connector logic.
>>
>> But another question, if we just leave this property to connector,
>> then we would need to parse this property in analogix_dp-rockchip.c,
>> and then make an hook in analogix_dp_core.c driver. This is not nice,
>> and if there are some coming platform which alse want to use analogix_dp
>> code and meet this "no-hpd" situation,  then they would need duplicate
>> to parse this property and fill the hook in analogix_dp_core.c driver.
>> So it's little bit conflict  :-)
> Ideally, you would be able to just retrieve this quirk from the
> connector or panel. Getting this property from your node vs. the port
> you are attached to should not be much harder. Either the connector
> struct can have this info or there can be a DT function that can walk
> the graph and get it. Just don't open code the graph traversal in your
> driver.
>
>> Beside I can not understand your example very well. Do you mean
>> that there are some HDMI monitor which also do not have HPD
>> signal (just like some eDP panel do not have hpd too), and then
>> the "hpd-gpios" ? Hmm... I don't know how the "hpd-gpios" want
>> to help in this case, would you mind show some sample code  :-D
> I don't know that there is h/w, but it is always possible HPD is not
> hooked up or hooked up incorrectly some how.
>
> If there is no HPD support, then hpd-gpios is not going to help you.
>
> I think there are 3 cases to handle:
> - HPD handled by bridge chip - The bridge driver knows it has this
> capability. No DT properties are needed and no HPD properties on the
> connector node imply the bridge chip should handle HPD functions.
> - HPD handled by GPIO line (or some other block) - Indicated by
> hpd-gpios present
> - No or broken HPD - Indicated by "hpd-force" property.

Oh, I think the first/second case isn't suitable in this case, my panel
"cnm,n116bgeea2" haven't included HPD signal.

>
>>> Are there any eDP panels which don't have EDID and need panel details in
>>> DT?
>>
>> Oh, I think you want to collect some info that belong to panel
>> property but no indicate in panel EDID message, so those can
>> be collect in eDP connector binding, is it right ?
> Yes, and as Thierry pointed out we may need to know the exact panel even.

Yeah, just like I reply to Thierry, this is a panel quirk. And he 
suggest we should
handle this in panel driver, but I have no idea how to handle this in 
common panel
driver.   :)

- Yakir

> Rob
>
>
>


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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-06  8:20           ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-06  8:20 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Rob,

? 09/05/2015 05:46 AM, Rob Herring ??:
> On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang <ykk@rock-chips.com> wrote:
>> Hi Rob,
>>
>> ? 09/03/2015 04:17 AM, Rob Herring ??:
>>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>>>> Some edp screen do not have hpd signal, so we can't just return
>>>> failed when hpd plug in detect failed.
>>> This is a property of the panel (or connector perhaps), so this
>>> property should be located there. At least, it is a common issue and
>>> not specific to this chip. We could have an HDMI connector and failed
>>> to hook up HPD for example. A connector node is also where hpd-gpios
>>> should be located instead (and are already defined by
>>> ../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
>>> binding, too.
>>
>> Yep, I agree with your front point, it is a property of panel, not specific
>> to eDP controller, so this code should handle in connector logic.
>>
>> But another question, if we just leave this property to connector,
>> then we would need to parse this property in analogix_dp-rockchip.c,
>> and then make an hook in analogix_dp_core.c driver. This is not nice,
>> and if there are some coming platform which alse want to use analogix_dp
>> code and meet this "no-hpd" situation,  then they would need duplicate
>> to parse this property and fill the hook in analogix_dp_core.c driver.
>> So it's little bit conflict  :-)
> Ideally, you would be able to just retrieve this quirk from the
> connector or panel. Getting this property from your node vs. the port
> you are attached to should not be much harder. Either the connector
> struct can have this info or there can be a DT function that can walk
> the graph and get it. Just don't open code the graph traversal in your
> driver.
>
>> Beside I can not understand your example very well. Do you mean
>> that there are some HDMI monitor which also do not have HPD
>> signal (just like some eDP panel do not have hpd too), and then
>> the "hpd-gpios" ? Hmm... I don't know how the "hpd-gpios" want
>> to help in this case, would you mind show some sample code  :-D
> I don't know that there is h/w, but it is always possible HPD is not
> hooked up or hooked up incorrectly some how.
>
> If there is no HPD support, then hpd-gpios is not going to help you.
>
> I think there are 3 cases to handle:
> - HPD handled by bridge chip - The bridge driver knows it has this
> capability. No DT properties are needed and no HPD properties on the
> connector node imply the bridge chip should handle HPD functions.
> - HPD handled by GPIO line (or some other block) - Indicated by
> hpd-gpios present
> - No or broken HPD - Indicated by "hpd-force" property.

Oh, I think the first/second case isn't suitable in this case, my panel
"cnm,n116bgeea2" haven't included HPD signal.

>
>>> Are there any eDP panels which don't have EDID and need panel details in
>>> DT?
>>
>> Oh, I think you want to collect some info that belong to panel
>> property but no indicate in panel EDID message, so those can
>> be collect in eDP connector binding, is it right ?
> Yes, and as Thierry pointed out we may need to know the exact panel even.

Yeah, just like I reply to Thierry, this is a panel quirk. And he 
suggest we should
handle this in panel driver, but I have no idea how to handle this in 
common panel
driver.   :)

- Yakir

> Rob
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support
  2015-09-06  4:07       ` Yakir Yang
@ 2015-09-06 23:55         ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-06 23:55 UTC (permalink / raw)
  To: Yakir Yang, Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

On 06.09.2015 13:07, Yakir Yang wrote:
> Hi Krzysztof,
> 
> 在 09/04/2015 08:36 AM, Krzysztof Kozlowski 写道:
>> On 01.09.2015 15:07, Yakir Yang wrote:
>>
>> Empty commit message. Please explain here why you want to add platform
>> device type support.
>>
>> Actually the title is confusing. You are not adding support for platform
>> device types but rather adding a field containing type of device.
>>
>>
>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>> ---
>>> Changes in v4: None
>>> Changes in v3: None
>>> Changes in v2:
>>> - Add GNU license v2 declared and samsung copyright
>>>
>>>   drivers/gpu/drm/exynos/exynos_dp.c              |  1 +
>>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c |  1 +
>>>   include/drm/bridge/analogix_dp.h                | 16 ++++++++++++++++
>>>   3 files changed, 18 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c
>>> b/drivers/gpu/drm/exynos/exynos_dp.c
>>> index 6060d2c..40ef727 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_dp.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
>>> @@ -224,6 +224,7 @@ static int exynos_dp_bind(struct device *dev,
>>> struct device *master, void *data)
>>>       dp->dev = dev;
>>>       dp->drm_dev = drm_dev;
>>>   +    dp->plat_data.dev_type = EXYNOS_DP;
>>>       dp->plat_data.power_on = exynos_dp_poweron;
>>>       dp->plat_data.power_off = exynos_dp_poweroff;
>>>       dp->plat_data.get_modes = exynos_dp_get_modes;
>>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>> index efea045..4934271 100644
>>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>> @@ -293,6 +293,7 @@ static int rockchip_dp_bind(struct device *dev,
>>> struct device *master,
>>>           return ret;
>>>       }
>>>   +    dp->plat_data.dev_type = RK3288_DP;
>>>       dp->plat_data.attach = NULL;
>>>       dp->plat_data.get_modes = NULL;
>>>       dp->plat_data.power_on = rockchip_dp_poweron;
>>> diff --git a/include/drm/bridge/analogix_dp.h
>>> b/include/drm/bridge/analogix_dp.h
>>> index 8b4ffad..7209a64 100644
>>> --- a/include/drm/bridge/analogix_dp.h
>>> +++ b/include/drm/bridge/analogix_dp.h
>>> @@ -1,9 +1,25 @@
>>> +/*
>>> + * Analogix Core DP (Display Port) interface driver.
>>> + *
>>> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> modify it
>>> + * under the terms of the GNU General Public License as published by
>>> the
>>> + * Free Software Foundation; either version 2 of the License, or (at
>>> your
>>> + * option) any later version.
>>> + */
>> Two questions:
>> 1. Why this change is here? I would rather expect it at patch 3/16 when
>> you created this file... That is the usual time for adding copyrights.
> 
> Yep, I should move this to 03/16.
> 
>> 2. Does this file contains previous Samsung work?
> 
> Hmm... I think this haven't contains the previous Samsung works,
> but I have the cover the head message from analogix_dp_core driver
> (include the copyright, but without ant author).

If it does not contain Samsung's work then don't mention its copyrights.

Best regards,
Krzysztof

> 
> Thanks
> - Yakir
> 
>> Best regards,
>> Krzysztof
>>
>>>   #ifndef _ANALOGIX_DP_H_
>>>   #define _ANALOGIX_DP_H_
>>>     #include <drm/drm_crtc.h>
>>>   +enum analogix_dp_devtype {
>>> +    EXYNOS_DP,
>>> +    RK3288_DP,
>>> +};
>>> +
>>>   struct analogix_dp_plat_data {
>>> +    enum analogix_dp_devtype dev_type;
>>>       struct drm_panel *panel;
>>>         int (*power_on)(struct analogix_dp_plat_data *);
>>>
>>
>>
>>
> 
> 
> 


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support
@ 2015-09-06 23:55         ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-06 23:55 UTC (permalink / raw)
  To: linux-arm-kernel

On 06.09.2015 13:07, Yakir Yang wrote:
> Hi Krzysztof,
> 
> ? 09/04/2015 08:36 AM, Krzysztof Kozlowski ??:
>> On 01.09.2015 15:07, Yakir Yang wrote:
>>
>> Empty commit message. Please explain here why you want to add platform
>> device type support.
>>
>> Actually the title is confusing. You are not adding support for platform
>> device types but rather adding a field containing type of device.
>>
>>
>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>> ---
>>> Changes in v4: None
>>> Changes in v3: None
>>> Changes in v2:
>>> - Add GNU license v2 declared and samsung copyright
>>>
>>>   drivers/gpu/drm/exynos/exynos_dp.c              |  1 +
>>>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c |  1 +
>>>   include/drm/bridge/analogix_dp.h                | 16 ++++++++++++++++
>>>   3 files changed, 18 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c
>>> b/drivers/gpu/drm/exynos/exynos_dp.c
>>> index 6060d2c..40ef727 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_dp.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
>>> @@ -224,6 +224,7 @@ static int exynos_dp_bind(struct device *dev,
>>> struct device *master, void *data)
>>>       dp->dev = dev;
>>>       dp->drm_dev = drm_dev;
>>>   +    dp->plat_data.dev_type = EXYNOS_DP;
>>>       dp->plat_data.power_on = exynos_dp_poweron;
>>>       dp->plat_data.power_off = exynos_dp_poweroff;
>>>       dp->plat_data.get_modes = exynos_dp_get_modes;
>>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>> index efea045..4934271 100644
>>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>> @@ -293,6 +293,7 @@ static int rockchip_dp_bind(struct device *dev,
>>> struct device *master,
>>>           return ret;
>>>       }
>>>   +    dp->plat_data.dev_type = RK3288_DP;
>>>       dp->plat_data.attach = NULL;
>>>       dp->plat_data.get_modes = NULL;
>>>       dp->plat_data.power_on = rockchip_dp_poweron;
>>> diff --git a/include/drm/bridge/analogix_dp.h
>>> b/include/drm/bridge/analogix_dp.h
>>> index 8b4ffad..7209a64 100644
>>> --- a/include/drm/bridge/analogix_dp.h
>>> +++ b/include/drm/bridge/analogix_dp.h
>>> @@ -1,9 +1,25 @@
>>> +/*
>>> + * Analogix Core DP (Display Port) interface driver.
>>> + *
>>> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> modify it
>>> + * under the terms of the GNU General Public License as published by
>>> the
>>> + * Free Software Foundation; either version 2 of the License, or (at
>>> your
>>> + * option) any later version.
>>> + */
>> Two questions:
>> 1. Why this change is here? I would rather expect it at patch 3/16 when
>> you created this file... That is the usual time for adding copyrights.
> 
> Yep, I should move this to 03/16.
> 
>> 2. Does this file contains previous Samsung work?
> 
> Hmm... I think this haven't contains the previous Samsung works,
> but I have the cover the head message from analogix_dp_core driver
> (include the copyright, but without ant author).

If it does not contain Samsung's work then don't mention its copyrights.

Best regards,
Krzysztof

> 
> Thanks
> - Yakir
> 
>> Best regards,
>> Krzysztof
>>
>>>   #ifndef _ANALOGIX_DP_H_
>>>   #define _ANALOGIX_DP_H_
>>>     #include <drm/drm_crtc.h>
>>>   +enum analogix_dp_devtype {
>>> +    EXYNOS_DP,
>>> +    RK3288_DP,
>>> +};
>>> +
>>>   struct analogix_dp_plat_data {
>>> +    enum analogix_dp_devtype dev_type;
>>>       struct drm_panel *panel;
>>>         int (*power_on)(struct analogix_dp_plat_data *);
>>>
>>
>>
>>
> 
> 
> 

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-07  0:22             ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-07  0:22 UTC (permalink / raw)
  To: Yakir Yang, Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

On 06.09.2015 16:49, Yakir Yang wrote:
> Hi Krzysztof,
> 
> 在 09/04/2015 08:41 AM, Krzysztof Kozlowski 写道:
>> On 03.09.2015 14:30, Yakir Yang wrote:
>>> Hi Krzysztof,
>>>
>>> 在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
>>>> On 01.09.2015 14:49, Yakir Yang wrote:
>>>>> Split the dp core driver from exynos directory to bridge
>>>>> directory, and rename the core driver to analogix_dp_*,
>>>>> leave the platform code to analogix_dp-exynos.
>>>>>
>>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>>> ---
>>>>> Changes in v4:
>>>>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT
>>>>> propery.
>>>>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to
>>>>> "exynos_dp.c"
>>>>> - Take Archit suggest, create a separate folder for analogix code in
>>>>> bridge/
>>>>>
>>>>> Changes in v3:
>>>>> - Take Thierry Reding suggest, move exynos's video_timing code
>>>>>     to analogix_dp-exynos platform driver, add get_modes method
>>>>>     to struct analogix_dp_plat_data.
>>>>> - Take Heiko suggest, rename some "samsung*" dts propery to
>>>>> "analogix*".
>>>>>
>>>>> Changes in v2:
>>>>> - Take Jingoo Han suggest, remove new copyright
>>>>> - Fix compiled failed dut to analogix_dp_device misspell
> 
> [.....]
> 
>>>>> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
>>>>> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>>>>>    {
>>>>> -    struct exynos_dp_device *dp = bridge->driver_private;
>>>>> -    struct drm_encoder *encoder = &dp->encoder;
>>>>> +    struct analogix_dp_device *dp = bridge->driver_private;
>>>>> +    struct drm_encoder *encoder = dp->encoder;
>>>>>        struct drm_connector *connector = &dp->connector;
>>>>>        int ret;
>>>>>    -    /* Pre-empt DP connector creation if there's a bridge */
>>>>> -    if (dp->ptn_bridge) {
>>>>> -        ret = exynos_drm_attach_lcd_bridge(dp, encoder);
>>>>> -        if (!ret)
>>>>> -            return 0;
>>>>> +    if (!bridge->encoder) {
>>>>> +        DRM_ERROR("Parent encoder object not found");
>>>>> +        return -ENODEV;
>>>>>        }
>>>>>    +    encoder->bridge = bridge;
>>>>> +
>>>>>        connector->polled = DRM_CONNECTOR_POLL_HPD;
>>>>>          ret = drm_connector_init(dp->drm_dev, connector,
>>>>> -                 &exynos_dp_connector_funcs,
>>>>> +                 &analogix_dp_connector_funcs,
>>>>>                     DRM_MODE_CONNECTOR_eDP);
>>>>>        if (ret) {
>>>>>            DRM_ERROR("Failed to initialize connector with drm\n");
>>>>>            return ret;
>>>>>        }
>>>>>    -    drm_connector_helper_add(connector,
>>>>> &exynos_dp_connector_helper_funcs);
>>>>> +    drm_connector_helper_add(connector,
>>>>> +                 &analogix_dp_connector_helper_funcs);
>>>>>        drm_connector_register(connector);
>>>>>        drm_mode_connector_attach_encoder(connector, encoder);
>>>>>    -    if (dp->panel)
>>>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>>>> +        if (ret) {
>>>>> +            DRM_ERROR("Failed to attach panel\n");
>>>>> +            return ret;
>>>>> +        }
>>>>> +    }
>>>>> +
>>>>> +    /*
>>>>> +     * This should be the end of attach function, caused
>>>>> +     * we should ensure dp bridge could attach first.
>>>>> +     */
>>>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>>>> +         if (ret) {
>>>>> +             DRM_ERROR("Failed at platform attch func\n");
>>>> Two new error paths appeared here and above. Don't you have to
>>>> cleanup something? I don't know, just wondering...
>>> Hmm... I think both panel & platform_attch need ERROR remind when
>>> it failed. But if it still need clean, I though it should clean the
>>> platform attch
>>> error,
>>> this is not relate to DRM directly, just analogix driver logic, so
>>> code would like,
>>>
>>> -    if (dp->panel)
>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>> +        if (ret) {
>>> +            DRM_ERROR("Failed to attach panel\n");
>>> +            return ret;
>>> +        }
>>> +    }
>>>
>>> +    /*
>>> +     * This should be the end of attach function, caused
>>> +     * we should ensure dp bridge could attach first.
>>> +     */
>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>>
>>>            return ret;
>> I am lost... the code looks the same. What did you change?
> 
> I just remove the DRM_ERROR after dp->plat_data->attach(),
> maybe I should paste the change that rebase on this patch,
> here are they,
> 
>     /*
>      * This should be the end of attach function, caused
>      * we should ensure dp bridge could attach first.
>      */
> -     if (dp->plat_data && dp->plat_data->attach) {
> +     if (dp->plat_data && dp->plat_data->attach)
>            ret = dp->plat_data->attach(dp->plat_data, bridge);
> -          if (ret) {
> -              DRM_ERROR("Failed at platform attch func\n");
> -              return ret;
> -          }
> -      }
> 
> -    return 0;
> +   return ret;
> 
> 
> If this haven't meet your comment, I maybe start to think that
> your comment  "Two new error paths appeared here and above"
> indicated that those two function is the same.
>     "dp->plat_data->attach(dp->plat_data, bridge); "
>     "drm_panel_attach(dp->plat_data->panel, &dp->connector); "

I wasn't talking about error message but rather about possible need of
clean up in error path. Previously there was only drm_panel_attach().
Now you have two of them (drm_panel_attach() and
dp->plat_data->attach()). If the second fails don't you have to clean up
before exit? I don't know, just asking.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-07  0:22             ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-07  0:22 UTC (permalink / raw)
  To: Yakir Yang, Heiko Stuebner, Thierry Reding, Jingoo Han, Inki Dae,
	joe-6d6DIl74uiNBDgjK7y7TUQ, Kukjin Kim, Mark Yao
  Cc: David Airlie, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	Andrzej Hajda, Gustavo Padovan, architt-sgV2jX0FEOL9JmXXK+q4OQ,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Russell King,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Rob Herring, dianders-F7+t8E8rja9Wk0Htik3J/w,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kyungmin Park, Kumar Gala,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan

On 06.09.2015 16:49, Yakir Yang wrote:
> Hi Krzysztof,
> 
> 在 09/04/2015 08:41 AM, Krzysztof Kozlowski 写道:
>> On 03.09.2015 14:30, Yakir Yang wrote:
>>> Hi Krzysztof,
>>>
>>> 在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
>>>> On 01.09.2015 14:49, Yakir Yang wrote:
>>>>> Split the dp core driver from exynos directory to bridge
>>>>> directory, and rename the core driver to analogix_dp_*,
>>>>> leave the platform code to analogix_dp-exynos.
>>>>>
>>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>>> ---
>>>>> Changes in v4:
>>>>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT
>>>>> propery.
>>>>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to
>>>>> "exynos_dp.c"
>>>>> - Take Archit suggest, create a separate folder for analogix code in
>>>>> bridge/
>>>>>
>>>>> Changes in v3:
>>>>> - Take Thierry Reding suggest, move exynos's video_timing code
>>>>>     to analogix_dp-exynos platform driver, add get_modes method
>>>>>     to struct analogix_dp_plat_data.
>>>>> - Take Heiko suggest, rename some "samsung*" dts propery to
>>>>> "analogix*".
>>>>>
>>>>> Changes in v2:
>>>>> - Take Jingoo Han suggest, remove new copyright
>>>>> - Fix compiled failed dut to analogix_dp_device misspell
> 
> [.....]
> 
>>>>> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
>>>>> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>>>>>    {
>>>>> -    struct exynos_dp_device *dp = bridge->driver_private;
>>>>> -    struct drm_encoder *encoder = &dp->encoder;
>>>>> +    struct analogix_dp_device *dp = bridge->driver_private;
>>>>> +    struct drm_encoder *encoder = dp->encoder;
>>>>>        struct drm_connector *connector = &dp->connector;
>>>>>        int ret;
>>>>>    -    /* Pre-empt DP connector creation if there's a bridge */
>>>>> -    if (dp->ptn_bridge) {
>>>>> -        ret = exynos_drm_attach_lcd_bridge(dp, encoder);
>>>>> -        if (!ret)
>>>>> -            return 0;
>>>>> +    if (!bridge->encoder) {
>>>>> +        DRM_ERROR("Parent encoder object not found");
>>>>> +        return -ENODEV;
>>>>>        }
>>>>>    +    encoder->bridge = bridge;
>>>>> +
>>>>>        connector->polled = DRM_CONNECTOR_POLL_HPD;
>>>>>          ret = drm_connector_init(dp->drm_dev, connector,
>>>>> -                 &exynos_dp_connector_funcs,
>>>>> +                 &analogix_dp_connector_funcs,
>>>>>                     DRM_MODE_CONNECTOR_eDP);
>>>>>        if (ret) {
>>>>>            DRM_ERROR("Failed to initialize connector with drm\n");
>>>>>            return ret;
>>>>>        }
>>>>>    -    drm_connector_helper_add(connector,
>>>>> &exynos_dp_connector_helper_funcs);
>>>>> +    drm_connector_helper_add(connector,
>>>>> +                 &analogix_dp_connector_helper_funcs);
>>>>>        drm_connector_register(connector);
>>>>>        drm_mode_connector_attach_encoder(connector, encoder);
>>>>>    -    if (dp->panel)
>>>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>>>> +        if (ret) {
>>>>> +            DRM_ERROR("Failed to attach panel\n");
>>>>> +            return ret;
>>>>> +        }
>>>>> +    }
>>>>> +
>>>>> +    /*
>>>>> +     * This should be the end of attach function, caused
>>>>> +     * we should ensure dp bridge could attach first.
>>>>> +     */
>>>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>>>> +         if (ret) {
>>>>> +             DRM_ERROR("Failed at platform attch func\n");
>>>> Two new error paths appeared here and above. Don't you have to
>>>> cleanup something? I don't know, just wondering...
>>> Hmm... I think both panel & platform_attch need ERROR remind when
>>> it failed. But if it still need clean, I though it should clean the
>>> platform attch
>>> error,
>>> this is not relate to DRM directly, just analogix driver logic, so
>>> code would like,
>>>
>>> -    if (dp->panel)
>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>> +        if (ret) {
>>> +            DRM_ERROR("Failed to attach panel\n");
>>> +            return ret;
>>> +        }
>>> +    }
>>>
>>> +    /*
>>> +     * This should be the end of attach function, caused
>>> +     * we should ensure dp bridge could attach first.
>>> +     */
>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>>
>>>            return ret;
>> I am lost... the code looks the same. What did you change?
> 
> I just remove the DRM_ERROR after dp->plat_data->attach(),
> maybe I should paste the change that rebase on this patch,
> here are they,
> 
>     /*
>      * This should be the end of attach function, caused
>      * we should ensure dp bridge could attach first.
>      */
> -     if (dp->plat_data && dp->plat_data->attach) {
> +     if (dp->plat_data && dp->plat_data->attach)
>            ret = dp->plat_data->attach(dp->plat_data, bridge);
> -          if (ret) {
> -              DRM_ERROR("Failed at platform attch func\n");
> -              return ret;
> -          }
> -      }
> 
> -    return 0;
> +   return ret;
> 
> 
> If this haven't meet your comment, I maybe start to think that
> your comment  "Two new error paths appeared here and above"
> indicated that those two function is the same.
>     "dp->plat_data->attach(dp->plat_data, bridge); "
>     "drm_panel_attach(dp->plat_data->panel, &dp->connector); "

I wasn't talking about error message but rather about possible need of
clean up in error path. Previously there was only drm_panel_attach().
Now you have two of them (drm_panel_attach() and
dp->plat_data->attach()). If the second fails don't you have to clean up
before exit? I don't know, just asking.

Best regards,
Krzysztof


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-07  0:22             ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-07  0:22 UTC (permalink / raw)
  To: linux-arm-kernel

On 06.09.2015 16:49, Yakir Yang wrote:
> Hi Krzysztof,
> 
> ? 09/04/2015 08:41 AM, Krzysztof Kozlowski ??:
>> On 03.09.2015 14:30, Yakir Yang wrote:
>>> Hi Krzysztof,
>>>
>>> ? 09/03/2015 08:58 AM, Krzysztof Kozlowski ??:
>>>> On 01.09.2015 14:49, Yakir Yang wrote:
>>>>> Split the dp core driver from exynos directory to bridge
>>>>> directory, and rename the core driver to analogix_dp_*,
>>>>> leave the platform code to analogix_dp-exynos.
>>>>>
>>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>>> ---
>>>>> Changes in v4:
>>>>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT
>>>>> propery.
>>>>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to
>>>>> "exynos_dp.c"
>>>>> - Take Archit suggest, create a separate folder for analogix code in
>>>>> bridge/
>>>>>
>>>>> Changes in v3:
>>>>> - Take Thierry Reding suggest, move exynos's video_timing code
>>>>>     to analogix_dp-exynos platform driver, add get_modes method
>>>>>     to struct analogix_dp_plat_data.
>>>>> - Take Heiko suggest, rename some "samsung*" dts propery to
>>>>> "analogix*".
>>>>>
>>>>> Changes in v2:
>>>>> - Take Jingoo Han suggest, remove new copyright
>>>>> - Fix compiled failed dut to analogix_dp_device misspell
> 
> [.....]
> 
>>>>> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
>>>>> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>>>>>    {
>>>>> -    struct exynos_dp_device *dp = bridge->driver_private;
>>>>> -    struct drm_encoder *encoder = &dp->encoder;
>>>>> +    struct analogix_dp_device *dp = bridge->driver_private;
>>>>> +    struct drm_encoder *encoder = dp->encoder;
>>>>>        struct drm_connector *connector = &dp->connector;
>>>>>        int ret;
>>>>>    -    /* Pre-empt DP connector creation if there's a bridge */
>>>>> -    if (dp->ptn_bridge) {
>>>>> -        ret = exynos_drm_attach_lcd_bridge(dp, encoder);
>>>>> -        if (!ret)
>>>>> -            return 0;
>>>>> +    if (!bridge->encoder) {
>>>>> +        DRM_ERROR("Parent encoder object not found");
>>>>> +        return -ENODEV;
>>>>>        }
>>>>>    +    encoder->bridge = bridge;
>>>>> +
>>>>>        connector->polled = DRM_CONNECTOR_POLL_HPD;
>>>>>          ret = drm_connector_init(dp->drm_dev, connector,
>>>>> -                 &exynos_dp_connector_funcs,
>>>>> +                 &analogix_dp_connector_funcs,
>>>>>                     DRM_MODE_CONNECTOR_eDP);
>>>>>        if (ret) {
>>>>>            DRM_ERROR("Failed to initialize connector with drm\n");
>>>>>            return ret;
>>>>>        }
>>>>>    -    drm_connector_helper_add(connector,
>>>>> &exynos_dp_connector_helper_funcs);
>>>>> +    drm_connector_helper_add(connector,
>>>>> +                 &analogix_dp_connector_helper_funcs);
>>>>>        drm_connector_register(connector);
>>>>>        drm_mode_connector_attach_encoder(connector, encoder);
>>>>>    -    if (dp->panel)
>>>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>>>> +        if (ret) {
>>>>> +            DRM_ERROR("Failed to attach panel\n");
>>>>> +            return ret;
>>>>> +        }
>>>>> +    }
>>>>> +
>>>>> +    /*
>>>>> +     * This should be the end of attach function, caused
>>>>> +     * we should ensure dp bridge could attach first.
>>>>> +     */
>>>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>>>> +         if (ret) {
>>>>> +             DRM_ERROR("Failed at platform attch func\n");
>>>> Two new error paths appeared here and above. Don't you have to
>>>> cleanup something? I don't know, just wondering...
>>> Hmm... I think both panel & platform_attch need ERROR remind when
>>> it failed. But if it still need clean, I though it should clean the
>>> platform attch
>>> error,
>>> this is not relate to DRM directly, just analogix driver logic, so
>>> code would like,
>>>
>>> -    if (dp->panel)
>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>> +        if (ret) {
>>> +            DRM_ERROR("Failed to attach panel\n");
>>> +            return ret;
>>> +        }
>>> +    }
>>>
>>> +    /*
>>> +     * This should be the end of attach function, caused
>>> +     * we should ensure dp bridge could attach first.
>>> +     */
>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>>
>>>            return ret;
>> I am lost... the code looks the same. What did you change?
> 
> I just remove the DRM_ERROR after dp->plat_data->attach(),
> maybe I should paste the change that rebase on this patch,
> here are they,
> 
>     /*
>      * This should be the end of attach function, caused
>      * we should ensure dp bridge could attach first.
>      */
> -     if (dp->plat_data && dp->plat_data->attach) {
> +     if (dp->plat_data && dp->plat_data->attach)
>            ret = dp->plat_data->attach(dp->plat_data, bridge);
> -          if (ret) {
> -              DRM_ERROR("Failed at platform attch func\n");
> -              return ret;
> -          }
> -      }
> 
> -    return 0;
> +   return ret;
> 
> 
> If this haven't meet your comment, I maybe start to think that
> your comment  "Two new error paths appeared here and above"
> indicated that those two function is the same.
>     "dp->plat_data->attach(dp->plat_data, bridge); "
>     "drm_panel_attach(dp->plat_data->panel, &dp->connector); "

I wasn't talking about error message but rather about possible need of
clean up in error path. Previously there was only drm_panel_attach().
Now you have two of them (drm_panel_attach() and
dp->plat_data->attach()). If the second fails don't you have to clean up
before exit? I don't know, just asking.

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support
  2015-09-06 23:55         ` Krzysztof Kozlowski
  (?)
@ 2015-09-07  1:47         ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-07  1:47 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Krzysztof,

在 09/07/2015 07:55 AM, Krzysztof Kozlowski 写道:
> On 06.09.2015 13:07, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> 在 09/04/2015 08:36 AM, Krzysztof Kozlowski 写道:
>>> On 01.09.2015 15:07, Yakir Yang wrote:
>>>
>>> Empty commit message. Please explain here why you want to add platform
>>> device type support.
>>>
>>> Actually the title is confusing. You are not adding support for platform
>>> device types but rather adding a field containing type of device.
>>>
>>>
>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>> ---
>>>> Changes in v4: None
>>>> Changes in v3: None
>>>> Changes in v2:
>>>> - Add GNU license v2 declared and samsung copyright
>>>>
>>>>    drivers/gpu/drm/exynos/exynos_dp.c              |  1 +
>>>>    drivers/gpu/drm/rockchip/analogix_dp-rockchip.c |  1 +
>>>>    include/drm/bridge/analogix_dp.h                | 16 ++++++++++++++++
>>>>    3 files changed, 18 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c
>>>> b/drivers/gpu/drm/exynos/exynos_dp.c
>>>> index 6060d2c..40ef727 100644
>>>> --- a/drivers/gpu/drm/exynos/exynos_dp.c
>>>> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
>>>> @@ -224,6 +224,7 @@ static int exynos_dp_bind(struct device *dev,
>>>> struct device *master, void *data)
>>>>        dp->dev = dev;
>>>>        dp->drm_dev = drm_dev;
>>>>    +    dp->plat_data.dev_type = EXYNOS_DP;
>>>>        dp->plat_data.power_on = exynos_dp_poweron;
>>>>        dp->plat_data.power_off = exynos_dp_poweroff;
>>>>        dp->plat_data.get_modes = exynos_dp_get_modes;
>>>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>>> b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>>> index efea045..4934271 100644
>>>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>>>> @@ -293,6 +293,7 @@ static int rockchip_dp_bind(struct device *dev,
>>>> struct device *master,
>>>>            return ret;
>>>>        }
>>>>    +    dp->plat_data.dev_type = RK3288_DP;
>>>>        dp->plat_data.attach = NULL;
>>>>        dp->plat_data.get_modes = NULL;
>>>>        dp->plat_data.power_on = rockchip_dp_poweron;
>>>> diff --git a/include/drm/bridge/analogix_dp.h
>>>> b/include/drm/bridge/analogix_dp.h
>>>> index 8b4ffad..7209a64 100644
>>>> --- a/include/drm/bridge/analogix_dp.h
>>>> +++ b/include/drm/bridge/analogix_dp.h
>>>> @@ -1,9 +1,25 @@
>>>> +/*
>>>> + * Analogix Core DP (Display Port) interface driver.
>>>> + *
>>>> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or
>>>> modify it
>>>> + * under the terms of the GNU General Public License as published by
>>>> the
>>>> + * Free Software Foundation; either version 2 of the License, or (at
>>>> your
>>>> + * option) any later version.
>>>> + */
>>> Two questions:
>>> 1. Why this change is here? I would rather expect it at patch 3/16 when
>>> you created this file... That is the usual time for adding copyrights.
>> Yep, I should move this to 03/16.
>>
>>> 2. Does this file contains previous Samsung work?
>> Hmm... I think this haven't contains the previous Samsung works,
>> but I have the cover the head message from analogix_dp_core driver
>> (include the copyright, but without ant author).
> If it does not contain Samsung's work then don't mention its copyrights.

Okay,

- Yakir

>
> Best regards,
> Krzysztof
>
>> Thanks
>> - Yakir
>>
>>> Best regards,
>>> Krzysztof
>>>
>>>>    #ifndef _ANALOGIX_DP_H_
>>>>    #define _ANALOGIX_DP_H_
>>>>      #include <drm/drm_crtc.h>
>>>>    +enum analogix_dp_devtype {
>>>> +    EXYNOS_DP,
>>>> +    RK3288_DP,
>>>> +};
>>>> +
>>>>    struct analogix_dp_plat_data {
>>>> +    enum analogix_dp_devtype dev_type;
>>>>        struct drm_panel *panel;
>>>>          int (*power_on)(struct analogix_dp_plat_data *);
>>>>
>>>
>>>
>>
>>
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-07  2:27               ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-07  2:27 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, joe, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz, dianders, seanpaul, ajaynumb,
	Andrzej Hajda, Kyungmin Park, David Airlie, Gustavo Padovan,
	Andy Yan, Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt, robherring2, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Krzysztof,

在 09/07/2015 08:22 AM, Krzysztof Kozlowski 写道:
> On 06.09.2015 16:49, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> 在 09/04/2015 08:41 AM, Krzysztof Kozlowski 写道:
>>> On 03.09.2015 14:30, Yakir Yang wrote:
>>>> Hi Krzysztof,
>>>>
>>>> 在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
>>>>> On 01.09.2015 14:49, Yakir Yang wrote:
>>>>>> Split the dp core driver from exynos directory to bridge
>>>>>> directory, and rename the core driver to analogix_dp_*,
>>>>>> leave the platform code to analogix_dp-exynos.
>>>>>>
>>>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>>>> ---
>>>>>> Changes in v4:
>>>>>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT
>>>>>> propery.
>>>>>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to
>>>>>> "exynos_dp.c"
>>>>>> - Take Archit suggest, create a separate folder for analogix code in
>>>>>> bridge/
>>>>>>
>>>>>> Changes in v3:
>>>>>> - Take Thierry Reding suggest, move exynos's video_timing code
>>>>>>      to analogix_dp-exynos platform driver, add get_modes method
>>>>>>      to struct analogix_dp_plat_data.
>>>>>> - Take Heiko suggest, rename some "samsung*" dts propery to
>>>>>> "analogix*".
>>>>>>
>>>>>> Changes in v2:
>>>>>> - Take Jingoo Han suggest, remove new copyright
>>>>>> - Fix compiled failed dut to analogix_dp_device misspell
>> [.....]
>>
>>>>>> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
>>>>>> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>>>>>>     {
>>>>>> -    struct exynos_dp_device *dp = bridge->driver_private;
>>>>>> -    struct drm_encoder *encoder = &dp->encoder;
>>>>>> +    struct analogix_dp_device *dp = bridge->driver_private;
>>>>>> +    struct drm_encoder *encoder = dp->encoder;
>>>>>>         struct drm_connector *connector = &dp->connector;
>>>>>>         int ret;
>>>>>>     -    /* Pre-empt DP connector creation if there's a bridge */
>>>>>> -    if (dp->ptn_bridge) {
>>>>>> -        ret = exynos_drm_attach_lcd_bridge(dp, encoder);
>>>>>> -        if (!ret)
>>>>>> -            return 0;
>>>>>> +    if (!bridge->encoder) {
>>>>>> +        DRM_ERROR("Parent encoder object not found");
>>>>>> +        return -ENODEV;
>>>>>>         }
>>>>>>     +    encoder->bridge = bridge;
>>>>>> +
>>>>>>         connector->polled = DRM_CONNECTOR_POLL_HPD;
>>>>>>           ret = drm_connector_init(dp->drm_dev, connector,
>>>>>> -                 &exynos_dp_connector_funcs,
>>>>>> +                 &analogix_dp_connector_funcs,
>>>>>>                      DRM_MODE_CONNECTOR_eDP);
>>>>>>         if (ret) {
>>>>>>             DRM_ERROR("Failed to initialize connector with drm\n");
>>>>>>             return ret;
>>>>>>         }
>>>>>>     -    drm_connector_helper_add(connector,
>>>>>> &exynos_dp_connector_helper_funcs);
>>>>>> +    drm_connector_helper_add(connector,
>>>>>> +                 &analogix_dp_connector_helper_funcs);
>>>>>>         drm_connector_register(connector);
>>>>>>         drm_mode_connector_attach_encoder(connector, encoder);
>>>>>>     -    if (dp->panel)
>>>>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>>>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>>>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>>>>> +        if (ret) {
>>>>>> +            DRM_ERROR("Failed to attach panel\n");
>>>>>> +            return ret;
>>>>>> +        }
>>>>>> +    }
>>>>>> +
>>>>>> +    /*
>>>>>> +     * This should be the end of attach function, caused
>>>>>> +     * we should ensure dp bridge could attach first.
>>>>>> +     */
>>>>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>>>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>>>>> +         if (ret) {
>>>>>> +             DRM_ERROR("Failed at platform attch func\n");
>>>>> Two new error paths appeared here and above. Don't you have to
>>>>> cleanup something? I don't know, just wondering...
>>>> Hmm... I think both panel & platform_attch need ERROR remind when
>>>> it failed. But if it still need clean, I though it should clean the
>>>> platform attch
>>>> error,
>>>> this is not relate to DRM directly, just analogix driver logic, so
>>>> code would like,
>>>>
>>>> -    if (dp->panel)
>>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>>> +        if (ret) {
>>>> +            DRM_ERROR("Failed to attach panel\n");
>>>> +            return ret;
>>>> +        }
>>>> +    }
>>>>
>>>> +    /*
>>>> +     * This should be the end of attach function, caused
>>>> +     * we should ensure dp bridge could attach first.
>>>> +     */
>>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>>>
>>>>             return ret;
>>> I am lost... the code looks the same. What did you change?
>> I just remove the DRM_ERROR after dp->plat_data->attach(),
>> maybe I should paste the change that rebase on this patch,
>> here are they,
>>
>>      /*
>>       * This should be the end of attach function, caused
>>       * we should ensure dp bridge could attach first.
>>       */
>> -     if (dp->plat_data && dp->plat_data->attach) {
>> +     if (dp->plat_data && dp->plat_data->attach)
>>             ret = dp->plat_data->attach(dp->plat_data, bridge);
>> -          if (ret) {
>> -              DRM_ERROR("Failed at platform attch func\n");
>> -              return ret;
>> -          }
>> -      }
>>
>> -    return 0;
>> +   return ret;
>>
>>
>> If this haven't meet your comment, I maybe start to think that
>> your comment  "Two new error paths appeared here and above"
>> indicated that those two function is the same.
>>      "dp->plat_data->attach(dp->plat_data, bridge); "
>>      "drm_panel_attach(dp->plat_data->panel, &dp->connector); "
> I wasn't talking about error message but rather about possible need of
> clean up in error path. Previously there was only drm_panel_attach().
> Now you have two of them (drm_panel_attach() and
> dp->plat_data->attach()). If the second fails don't you have to clean up
> before exit? I don't know, just asking.

Oh... Sorry about missing your words. Yes, 
drm_panel_detach(dp->plat_data->panel)
was missed in this error path.

Thanks,
- Yakir

>
> Best regards,
> Krzysztof
>
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-07  2:27               ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-07  2:27 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Heiko Stuebner, Thierry Reding, Jingoo Han,
	Inki Dae, joe-6d6DIl74uiNBDgjK7y7TUQ, Kukjin Kim, Mark Yao
  Cc: Russell King, djkurtz-F7+t8E8rja9Wk0Htik3J/w,
	dianders-F7+t8E8rja9Wk0Htik3J/w, seanpaul-F7+t8E8rja9Wk0Htik3J/w,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt-sgV2jX0FEOL9JmXXK+q4OQ,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Hi Krzysztof,

在 09/07/2015 08:22 AM, Krzysztof Kozlowski 写道:
> On 06.09.2015 16:49, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> 在 09/04/2015 08:41 AM, Krzysztof Kozlowski 写道:
>>> On 03.09.2015 14:30, Yakir Yang wrote:
>>>> Hi Krzysztof,
>>>>
>>>> 在 09/03/2015 08:58 AM, Krzysztof Kozlowski 写道:
>>>>> On 01.09.2015 14:49, Yakir Yang wrote:
>>>>>> Split the dp core driver from exynos directory to bridge
>>>>>> directory, and rename the core driver to analogix_dp_*,
>>>>>> leave the platform code to analogix_dp-exynos.
>>>>>>
>>>>>> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>>>>>> ---
>>>>>> Changes in v4:
>>>>>> - Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT
>>>>>> propery.
>>>>>> - Take Jingoo suggest, rename "analogix_dp-exynos.c" file name to
>>>>>> "exynos_dp.c"
>>>>>> - Take Archit suggest, create a separate folder for analogix code in
>>>>>> bridge/
>>>>>>
>>>>>> Changes in v3:
>>>>>> - Take Thierry Reding suggest, move exynos's video_timing code
>>>>>>      to analogix_dp-exynos platform driver, add get_modes method
>>>>>>      to struct analogix_dp_plat_data.
>>>>>> - Take Heiko suggest, rename some "samsung*" dts propery to
>>>>>> "analogix*".
>>>>>>
>>>>>> Changes in v2:
>>>>>> - Take Jingoo Han suggest, remove new copyright
>>>>>> - Fix compiled failed dut to analogix_dp_device misspell
>> [.....]
>>
>>>>>> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
>>>>>> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
>>>>>>     {
>>>>>> -    struct exynos_dp_device *dp = bridge->driver_private;
>>>>>> -    struct drm_encoder *encoder = &dp->encoder;
>>>>>> +    struct analogix_dp_device *dp = bridge->driver_private;
>>>>>> +    struct drm_encoder *encoder = dp->encoder;
>>>>>>         struct drm_connector *connector = &dp->connector;
>>>>>>         int ret;
>>>>>>     -    /* Pre-empt DP connector creation if there's a bridge */
>>>>>> -    if (dp->ptn_bridge) {
>>>>>> -        ret = exynos_drm_attach_lcd_bridge(dp, encoder);
>>>>>> -        if (!ret)
>>>>>> -            return 0;
>>>>>> +    if (!bridge->encoder) {
>>>>>> +        DRM_ERROR("Parent encoder object not found");
>>>>>> +        return -ENODEV;
>>>>>>         }
>>>>>>     +    encoder->bridge = bridge;
>>>>>> +
>>>>>>         connector->polled = DRM_CONNECTOR_POLL_HPD;
>>>>>>           ret = drm_connector_init(dp->drm_dev, connector,
>>>>>> -                 &exynos_dp_connector_funcs,
>>>>>> +                 &analogix_dp_connector_funcs,
>>>>>>                      DRM_MODE_CONNECTOR_eDP);
>>>>>>         if (ret) {
>>>>>>             DRM_ERROR("Failed to initialize connector with drm\n");
>>>>>>             return ret;
>>>>>>         }
>>>>>>     -    drm_connector_helper_add(connector,
>>>>>> &exynos_dp_connector_helper_funcs);
>>>>>> +    drm_connector_helper_add(connector,
>>>>>> +                 &analogix_dp_connector_helper_funcs);
>>>>>>         drm_connector_register(connector);
>>>>>>         drm_mode_connector_attach_encoder(connector, encoder);
>>>>>>     -    if (dp->panel)
>>>>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>>>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>>>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>>>>> +        if (ret) {
>>>>>> +            DRM_ERROR("Failed to attach panel\n");
>>>>>> +            return ret;
>>>>>> +        }
>>>>>> +    }
>>>>>> +
>>>>>> +    /*
>>>>>> +     * This should be the end of attach function, caused
>>>>>> +     * we should ensure dp bridge could attach first.
>>>>>> +     */
>>>>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>>>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>>>>> +         if (ret) {
>>>>>> +             DRM_ERROR("Failed at platform attch func\n");
>>>>> Two new error paths appeared here and above. Don't you have to
>>>>> cleanup something? I don't know, just wondering...
>>>> Hmm... I think both panel & platform_attch need ERROR remind when
>>>> it failed. But if it still need clean, I though it should clean the
>>>> platform attch
>>>> error,
>>>> this is not relate to DRM directly, just analogix driver logic, so
>>>> code would like,
>>>>
>>>> -    if (dp->panel)
>>>> -        ret = drm_panel_attach(dp->panel, &dp->connector);
>>>> +    if (dp->plat_data && dp->plat_data->panel) {
>>>> +        ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
>>>> +        if (ret) {
>>>> +            DRM_ERROR("Failed to attach panel\n");
>>>> +            return ret;
>>>> +        }
>>>> +    }
>>>>
>>>> +    /*
>>>> +     * This should be the end of attach function, caused
>>>> +     * we should ensure dp bridge could attach first.
>>>> +     */
>>>> +     if (dp->plat_data && dp->plat_data->attach) {
>>>> +         ret = dp->plat_data->attach(dp->plat_data, bridge);
>>>>
>>>>             return ret;
>>> I am lost... the code looks the same. What did you change?
>> I just remove the DRM_ERROR after dp->plat_data->attach(),
>> maybe I should paste the change that rebase on this patch,
>> here are they,
>>
>>      /*
>>       * This should be the end of attach function, caused
>>       * we should ensure dp bridge could attach first.
>>       */
>> -     if (dp->plat_data && dp->plat_data->attach) {
>> +     if (dp->plat_data && dp->plat_data->attach)
>>             ret = dp->plat_data->attach(dp->plat_data, bridge);
>> -          if (ret) {
>> -              DRM_ERROR("Failed at platform attch func\n");
>> -              return ret;
>> -          }
>> -      }
>>
>> -    return 0;
>> +   return ret;
>>
>>
>> If this haven't meet your comment, I maybe start to think that
>> your comment  "Two new error paths appeared here and above"
>> indicated that those two function is the same.
>>      "dp->plat_data->attach(dp->plat_data, bridge); "
>>      "drm_panel_attach(dp->plat_data->panel, &dp->connector); "
> I wasn't talking about error message but rather about possible need of
> clean up in error path. Previously there was only drm_panel_attach().
> Now you have two of them (drm_panel_attach() and
> dp->plat_data->attach()). If the second fails don't you have to clean up
> before exit? I don't know, just asking.

Oh... Sorry about missing your words. Yes, 
drm_panel_detach(dp->plat_data->panel)
was missed in this error path.

Thanks,
- Yakir

>
> Best regards,
> Krzysztof
>
>
>
>


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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
  2015-09-04 21:29         ` Heiko Stuebner
  (?)
@ 2015-09-07  8:11           ` Thierry Reding
  -1 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-07  8:11 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Rob Herring, Yakir Yang, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King,
	Ajay kumar, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel, Doug Anderson, Sean Paul, Daniel Kurtz

[-- Attachment #1: Type: text/plain, Size: 4160 bytes --]

On Fri, Sep 04, 2015 at 11:29:30PM +0200, Heiko Stuebner wrote:
> Am Freitag, 4. September 2015, 16:06:02 schrieb Rob Herring:
> > On Tue, Sep 1, 2015 at 3:46 PM, Heiko Stuebner <heiko@sntech.de> wrote:
> > > Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
> > >> Split the dp core driver from exynos directory to bridge
> > >> directory, and rename the core driver to analogix_dp_*,
> > >> leave the platform code to analogix_dp-exynos.
> > >> 
> > >> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> > > 
> > > [...]
> > > 
> > >> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> > >> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
> > >> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
> > >> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> > >> index bed0252..7d62f22 100644
> > >> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> > >> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> > > 
> > > [...]
> > > 
> > >>       connector->polled = DRM_CONNECTOR_POLL_HPD;
> > >>       
> > >>       ret = drm_connector_init(dp->drm_dev, connector,
> > >> 
> > >> -                              &exynos_dp_connector_funcs,
> > >> +                              &analogix_dp_connector_funcs,
> > >> 
> > >>                                DRM_MODE_CONNECTOR_eDP);
> > >>       
> > >>       if (ret) {
> > >>       
> > >>               DRM_ERROR("Failed to initialize connector with drm\n");
> > >>               return ret;
> > >>       
> > >>       }
> > >> 
> > >> -     drm_connector_helper_add(connector,
> > >> &exynos_dp_connector_helper_funcs); +    
> > >> drm_connector_helper_add(connector,
> > >> +                              &analogix_dp_connector_helper_funcs);
> > >> 
> > >>       drm_connector_register(connector);
> > > 
> > > this should only run on exynos, as we're doing all our connector
> > > registration in the core driver after all components are bound, so I
> > > guess something like> 
> > > the following is needed:
> > >        if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
> > >        
> > >                drm_connector_register(connector);
> > 
> > Yuck!
> > 
> > Surely there is a better way. From what I've seen of DRM, I have no
> > doubt this is needed, but really a better solution is needed. Surely
> > there can be a more generic way for the driver to determine if it
> > should handle the connector or not. This seems like a common problem
> > including one I have seen. What I'm working on has onchip DSI encoder
> > -> ADV7533 -> HDMI. The DSI encoder can also have a direct attached
> > panel. So I have to check for a bridge in the encoder driver and only
> > register the connector for the panel if a bridge is not attached.
> 
> I'm also only a part-time drm meddler, so things may be inaccurate.
> 
> This conditional is not meant to prevent the registration of the dp connector, 
> only delay it for non-exynos drms. The connector registration does publish it 
> to userspace, so like i.MX we're doing that for all connectors at the same 
> time after all components are bound - to also make x11 happy. Exynos on the 
> other hand seems to register its connectors individually and I'm not sure if 
> they would be willing to change that.
> 
> see d3007dabeff4 ("drm/rockchip: register all connectors after bind") or 
> simply rockchip_drm_drv.c line 178.
> 
> and e355e7dd607b ("imx-drm: delay publishing sysfs connector entries")

There really shouldn't be a reason for both drivers to behave
differently in this case. Gustavo has done a lot of work on cleaning up
the Exynos driver lately, so perhaps you should sync up with him to see
if this is something that he can integrate with his changes.

If you can't reach an agreement and Exynos must keep the exact behaviour
as it has now, then perhaps a better option would be to have the
Analogix core driver not register the connector but rather leave that up
to users of the helpers. Then you don't have to clutter the core driver
with this type of platform-specific data.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-07  8:11           ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-07  8:11 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Rob Herring, Yakir Yang, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King,
	Ajay kumar, Andrzej Hajda, Kyungmin Park, David Airlie,
	Gustavo Padovan, Andy Yan, Kumar Gala, Ian Campbell, Pawel Moll,
	Kishon Vijay Abraham I, architt, dri-devel, devicetree,
	linux-kernel

[-- Attachment #1: Type: text/plain, Size: 4160 bytes --]

On Fri, Sep 04, 2015 at 11:29:30PM +0200, Heiko Stuebner wrote:
> Am Freitag, 4. September 2015, 16:06:02 schrieb Rob Herring:
> > On Tue, Sep 1, 2015 at 3:46 PM, Heiko Stuebner <heiko@sntech.de> wrote:
> > > Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
> > >> Split the dp core driver from exynos directory to bridge
> > >> directory, and rename the core driver to analogix_dp_*,
> > >> leave the platform code to analogix_dp-exynos.
> > >> 
> > >> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> > > 
> > > [...]
> > > 
> > >> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> > >> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
> > >> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
> > >> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> > >> index bed0252..7d62f22 100644
> > >> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> > >> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> > > 
> > > [...]
> > > 
> > >>       connector->polled = DRM_CONNECTOR_POLL_HPD;
> > >>       
> > >>       ret = drm_connector_init(dp->drm_dev, connector,
> > >> 
> > >> -                              &exynos_dp_connector_funcs,
> > >> +                              &analogix_dp_connector_funcs,
> > >> 
> > >>                                DRM_MODE_CONNECTOR_eDP);
> > >>       
> > >>       if (ret) {
> > >>       
> > >>               DRM_ERROR("Failed to initialize connector with drm\n");
> > >>               return ret;
> > >>       
> > >>       }
> > >> 
> > >> -     drm_connector_helper_add(connector,
> > >> &exynos_dp_connector_helper_funcs); +    
> > >> drm_connector_helper_add(connector,
> > >> +                              &analogix_dp_connector_helper_funcs);
> > >> 
> > >>       drm_connector_register(connector);
> > > 
> > > this should only run on exynos, as we're doing all our connector
> > > registration in the core driver after all components are bound, so I
> > > guess something like> 
> > > the following is needed:
> > >        if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
> > >        
> > >                drm_connector_register(connector);
> > 
> > Yuck!
> > 
> > Surely there is a better way. From what I've seen of DRM, I have no
> > doubt this is needed, but really a better solution is needed. Surely
> > there can be a more generic way for the driver to determine if it
> > should handle the connector or not. This seems like a common problem
> > including one I have seen. What I'm working on has onchip DSI encoder
> > -> ADV7533 -> HDMI. The DSI encoder can also have a direct attached
> > panel. So I have to check for a bridge in the encoder driver and only
> > register the connector for the panel if a bridge is not attached.
> 
> I'm also only a part-time drm meddler, so things may be inaccurate.
> 
> This conditional is not meant to prevent the registration of the dp connector, 
> only delay it for non-exynos drms. The connector registration does publish it 
> to userspace, so like i.MX we're doing that for all connectors at the same 
> time after all components are bound - to also make x11 happy. Exynos on the 
> other hand seems to register its connectors individually and I'm not sure if 
> they would be willing to change that.
> 
> see d3007dabeff4 ("drm/rockchip: register all connectors after bind") or 
> simply rockchip_drm_drv.c line 178.
> 
> and e355e7dd607b ("imx-drm: delay publishing sysfs connector entries")

There really shouldn't be a reason for both drivers to behave
differently in this case. Gustavo has done a lot of work on cleaning up
the Exynos driver lately, so perhaps you should sync up with him to see
if this is something that he can integrate with his changes.

If you can't reach an agreement and Exynos must keep the exact behaviour
as it has now, then perhaps a better option would be to have the
Analogix core driver not register the connector but rather leave that up
to users of the helpers. Then you don't have to clutter the core driver
with this type of platform-specific data.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir
@ 2015-09-07  8:11           ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-07  8:11 UTC (permalink / raw)
  To: linux-arm-kernel

On Fri, Sep 04, 2015 at 11:29:30PM +0200, Heiko Stuebner wrote:
> Am Freitag, 4. September 2015, 16:06:02 schrieb Rob Herring:
> > On Tue, Sep 1, 2015 at 3:46 PM, Heiko Stuebner <heiko@sntech.de> wrote:
> > > Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
> > >> Split the dp core driver from exynos directory to bridge
> > >> directory, and rename the core driver to analogix_dp_*,
> > >> leave the platform code to analogix_dp-exynos.
> > >> 
> > >> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> > > 
> > > [...]
> > > 
> > >> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> > >> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c similarity index 50%
> > >> rename from drivers/gpu/drm/exynos/exynos_dp_core.c
> > >> rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> > >> index bed0252..7d62f22 100644
> > >> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> > >> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> > > 
> > > [...]
> > > 
> > >>       connector->polled = DRM_CONNECTOR_POLL_HPD;
> > >>       
> > >>       ret = drm_connector_init(dp->drm_dev, connector,
> > >> 
> > >> -                              &exynos_dp_connector_funcs,
> > >> +                              &analogix_dp_connector_funcs,
> > >> 
> > >>                                DRM_MODE_CONNECTOR_eDP);
> > >>       
> > >>       if (ret) {
> > >>       
> > >>               DRM_ERROR("Failed to initialize connector with drm\n");
> > >>               return ret;
> > >>       
> > >>       }
> > >> 
> > >> -     drm_connector_helper_add(connector,
> > >> &exynos_dp_connector_helper_funcs); +    
> > >> drm_connector_helper_add(connector,
> > >> +                              &analogix_dp_connector_helper_funcs);
> > >> 
> > >>       drm_connector_register(connector);
> > > 
> > > this should only run on exynos, as we're doing all our connector
> > > registration in the core driver after all components are bound, so I
> > > guess something like> 
> > > the following is needed:
> > >        if (dp->plat_data && dp->plat_data->dev_type == EXYNOS_DP)
> > >        
> > >                drm_connector_register(connector);
> > 
> > Yuck!
> > 
> > Surely there is a better way. From what I've seen of DRM, I have no
> > doubt this is needed, but really a better solution is needed. Surely
> > there can be a more generic way for the driver to determine if it
> > should handle the connector or not. This seems like a common problem
> > including one I have seen. What I'm working on has onchip DSI encoder
> > -> ADV7533 -> HDMI. The DSI encoder can also have a direct attached
> > panel. So I have to check for a bridge in the encoder driver and only
> > register the connector for the panel if a bridge is not attached.
> 
> I'm also only a part-time drm meddler, so things may be inaccurate.
> 
> This conditional is not meant to prevent the registration of the dp connector, 
> only delay it for non-exynos drms. The connector registration does publish it 
> to userspace, so like i.MX we're doing that for all connectors at the same 
> time after all components are bound - to also make x11 happy. Exynos on the 
> other hand seems to register its connectors individually and I'm not sure if 
> they would be willing to change that.
> 
> see d3007dabeff4 ("drm/rockchip: register all connectors after bind") or 
> simply rockchip_drm_drv.c line 178.
> 
> and e355e7dd607b ("imx-drm: delay publishing sysfs connector entries")

There really shouldn't be a reason for both drivers to behave
differently in this case. Gustavo has done a lot of work on cleaning up
the Exynos driver lately, so perhaps you should sync up with him to see
if this is something that he can integrate with his changes.

If you can't reach an agreement and Exynos must keep the exact behaviour
as it has now, then perhaps a better option would be to have the
Analogix core driver not register the connector but rather leave that up
to users of the helpers. Then you don't have to clutter the core driver
with this type of platform-specific data.

Thierry
-------------- next part --------------
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-07  8:20             ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-07  8:20 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Russell King, Rob Herring, Heiko Stuebner, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

[-- Attachment #1: Type: text/plain, Size: 3096 bytes --]

On Sun, Sep 06, 2015 at 11:59:08AM +0800, Yakir Yang wrote:
> Hi Thierry,
> 
> 在 09/03/2015 05:04 PM, Thierry Reding 写道:
> >On Thu, Sep 03, 2015 at 12:27:47PM +0800, Yakir Yang wrote:
> >>Hi Rob,
> >>
> >>在 09/03/2015 04:17 AM, Rob Herring 写道:
> >>>On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> >>>>Some edp screen do not have hpd signal, so we can't just return
> >>>>failed when hpd plug in detect failed.
> >>>This is a property of the panel (or connector perhaps), so this
> >>>property should be located there. At least, it is a common issue and
> >>>not specific to this chip. We could have an HDMI connector and failed
> >>>to hook up HPD for example. A connector node is also where hpd-gpios
> >>>should be located instead (and are already defined by
> >>>../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
> >>>binding, too.
> >>Yep, I agree with your front point, it is a property of panel, not specific
> >>to eDP controller, so this code should handle in connector logic.
> > From your description it sounds more like this is in fact a property of
> >the panel. Or maybe I should say "quirk". If the panel doesn't generate
> >the HPD signal, then that should be a property of the panel, not the
> >connector. The eDP specification mandates that connectors have a HPD
> >signal, though it allows the "HPD conductor in the connector cable" to
> >be omitted if not used by the source. I'd consider the cable to belong
> >to the panel rather than the connector, so absence of HPD, either
> >because the cable doesn't have the conductor or because the panel does
> >not generate the signal, should be a quirk of the panel.
> >
> >That said you could have a panel that supports HPD connected via a cable
> >that doesn't transmit it, so this would be a per-board variant and hence
> >should be a device tree property rather than hard-coded in some panel
> >driver.
> >
> >Conversely, if the panel isn't capable of generating an HPD signal, then
> >I don't think it would be appropriate to make it a DT property. It would
> >be better to hard-code it in the driver, lest someone forget to set the
> >property in DT and get stuck with a device that isn't operational.
> 
> Oh, you're right, if it's a cable quirk, then DT property would be okay, if
> it
> is a problem of panel, then maybe hard-code in driver would be better.
> 
> After look up for the document of panel "innolux,n116bge", I haven't see
> any description of hot plug signal, and even not found in PIN ASSIGNMENT.
> So I believe it's a panel problem, that's to say it should handle in panel
> driver.

The datasheet that I have for that panel lists HPD as pin 17. Also I
used to have a setup with that panel and I distinctly remember hotplug
working just fine. Perhaps this is an issue with a specific variant of
the panel? Or perhaps this is indeed a problem with the cable that's
connecting the panel to the board. It could be one of those cases where
they left out the HPD conductor to save money.

Thierry

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-07  8:20             ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-07  8:20 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Russell King, Rob Herring, Heiko Stuebner, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao,
	djkurtz-F7+t8E8rja9Wk0Htik3J/w, dianders-F7+t8E8rja9Wk0Htik3J/w,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, Ajay kumar, Andrzej Hajda,
	Kyungmin Park, David Airlie, Gustavo Padovan, Andy Yan,
	Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt-sgV2jX0FEOL9JmXXK+q4OQ,
	dri-devel

[-- Attachment #1: Type: text/plain, Size: 3121 bytes --]

On Sun, Sep 06, 2015 at 11:59:08AM +0800, Yakir Yang wrote:
> Hi Thierry,
> 
> 在 09/03/2015 05:04 PM, Thierry Reding 写道:
> >On Thu, Sep 03, 2015 at 12:27:47PM +0800, Yakir Yang wrote:
> >>Hi Rob,
> >>
> >>在 09/03/2015 04:17 AM, Rob Herring 写道:
> >>>On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
> >>>>Some edp screen do not have hpd signal, so we can't just return
> >>>>failed when hpd plug in detect failed.
> >>>This is a property of the panel (or connector perhaps), so this
> >>>property should be located there. At least, it is a common issue and
> >>>not specific to this chip. We could have an HDMI connector and failed
> >>>to hook up HPD for example. A connector node is also where hpd-gpios
> >>>should be located instead (and are already defined by
> >>>../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
> >>>binding, too.
> >>Yep, I agree with your front point, it is a property of panel, not specific
> >>to eDP controller, so this code should handle in connector logic.
> > From your description it sounds more like this is in fact a property of
> >the panel. Or maybe I should say "quirk". If the panel doesn't generate
> >the HPD signal, then that should be a property of the panel, not the
> >connector. The eDP specification mandates that connectors have a HPD
> >signal, though it allows the "HPD conductor in the connector cable" to
> >be omitted if not used by the source. I'd consider the cable to belong
> >to the panel rather than the connector, so absence of HPD, either
> >because the cable doesn't have the conductor or because the panel does
> >not generate the signal, should be a quirk of the panel.
> >
> >That said you could have a panel that supports HPD connected via a cable
> >that doesn't transmit it, so this would be a per-board variant and hence
> >should be a device tree property rather than hard-coded in some panel
> >driver.
> >
> >Conversely, if the panel isn't capable of generating an HPD signal, then
> >I don't think it would be appropriate to make it a DT property. It would
> >be better to hard-code it in the driver, lest someone forget to set the
> >property in DT and get stuck with a device that isn't operational.
> 
> Oh, you're right, if it's a cable quirk, then DT property would be okay, if
> it
> is a problem of panel, then maybe hard-code in driver would be better.
> 
> After look up for the document of panel "innolux,n116bge", I haven't see
> any description of hot plug signal, and even not found in PIN ASSIGNMENT.
> So I believe it's a panel problem, that's to say it should handle in panel
> driver.

The datasheet that I have for that panel lists HPD as pin 17. Also I
used to have a setup with that panel and I distinctly remember hotplug
working just fine. Perhaps this is an issue with a specific variant of
the panel? Or perhaps this is indeed a problem with the cable that's
connecting the panel to the board. It could be one of those cases where
they left out the HPD conductor to save money.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-07  8:20             ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-07  8:20 UTC (permalink / raw)
  To: linux-arm-kernel

On Sun, Sep 06, 2015 at 11:59:08AM +0800, Yakir Yang wrote:
> Hi Thierry,
> 
> ? 09/03/2015 05:04 PM, Thierry Reding ??:
> >On Thu, Sep 03, 2015 at 12:27:47PM +0800, Yakir Yang wrote:
> >>Hi Rob,
> >>
> >>? 09/03/2015 04:17 AM, Rob Herring ??:
> >>>On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> >>>>Some edp screen do not have hpd signal, so we can't just return
> >>>>failed when hpd plug in detect failed.
> >>>This is a property of the panel (or connector perhaps), so this
> >>>property should be located there. At least, it is a common issue and
> >>>not specific to this chip. We could have an HDMI connector and failed
> >>>to hook up HPD for example. A connector node is also where hpd-gpios
> >>>should be located instead (and are already defined by
> >>>../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
> >>>binding, too.
> >>Yep, I agree with your front point, it is a property of panel, not specific
> >>to eDP controller, so this code should handle in connector logic.
> > From your description it sounds more like this is in fact a property of
> >the panel. Or maybe I should say "quirk". If the panel doesn't generate
> >the HPD signal, then that should be a property of the panel, not the
> >connector. The eDP specification mandates that connectors have a HPD
> >signal, though it allows the "HPD conductor in the connector cable" to
> >be omitted if not used by the source. I'd consider the cable to belong
> >to the panel rather than the connector, so absence of HPD, either
> >because the cable doesn't have the conductor or because the panel does
> >not generate the signal, should be a quirk of the panel.
> >
> >That said you could have a panel that supports HPD connected via a cable
> >that doesn't transmit it, so this would be a per-board variant and hence
> >should be a device tree property rather than hard-coded in some panel
> >driver.
> >
> >Conversely, if the panel isn't capable of generating an HPD signal, then
> >I don't think it would be appropriate to make it a DT property. It would
> >be better to hard-code it in the driver, lest someone forget to set the
> >property in DT and get stuck with a device that isn't operational.
> 
> Oh, you're right, if it's a cable quirk, then DT property would be okay, if
> it
> is a problem of panel, then maybe hard-code in driver would be better.
> 
> After look up for the document of panel "innolux,n116bge", I haven't see
> any description of hot plug signal, and even not found in PIN ASSIGNMENT.
> So I believe it's a panel problem, that's to say it should handle in panel
> driver.

The datasheet that I have for that panel lists HPD as pin 17. Also I
used to have a setup with that panel and I distinctly remember hotplug
working just fine. Perhaps this is an issue with a specific variant of
the panel? Or perhaps this is indeed a problem with the cable that's
connecting the panel to the board. It could be one of those cases where
they left out the HPD conductor to save money.

Thierry
-------------- next part --------------
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-07  8:39             ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-07  8:39 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Rob Herring, Heiko Stuebner, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

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On Sun, Sep 06, 2015 at 04:20:39PM +0800, Yakir Yang wrote:
> Hi Rob,
> 
> 在 09/05/2015 05:46 AM, Rob Herring 写道:
> >On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang <ykk@rock-chips.com> wrote:
> >>Hi Rob,
> >>
> >>在 09/03/2015 04:17 AM, Rob Herring 写道:
> >>>On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> >>>>Some edp screen do not have hpd signal, so we can't just return
> >>>>failed when hpd plug in detect failed.
> >>>This is a property of the panel (or connector perhaps), so this
> >>>property should be located there. At least, it is a common issue and
> >>>not specific to this chip. We could have an HDMI connector and failed
> >>>to hook up HPD for example. A connector node is also where hpd-gpios
> >>>should be located instead (and are already defined by
> >>>../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
> >>>binding, too.
> >>
> >>Yep, I agree with your front point, it is a property of panel, not specific
> >>to eDP controller, so this code should handle in connector logic.
> >>
> >>But another question, if we just leave this property to connector,
> >>then we would need to parse this property in analogix_dp-rockchip.c,
> >>and then make an hook in analogix_dp_core.c driver. This is not nice,
> >>and if there are some coming platform which alse want to use analogix_dp
> >>code and meet this "no-hpd" situation,  then they would need duplicate
> >>to parse this property and fill the hook in analogix_dp_core.c driver.
> >>So it's little bit conflict  :-)
> >Ideally, you would be able to just retrieve this quirk from the
> >connector or panel. Getting this property from your node vs. the port
> >you are attached to should not be much harder. Either the connector
> >struct can have this info or there can be a DT function that can walk
> >the graph and get it. Just don't open code the graph traversal in your
> >driver.
> >
> >>Beside I can not understand your example very well. Do you mean
> >>that there are some HDMI monitor which also do not have HPD
> >>signal (just like some eDP panel do not have hpd too), and then
> >>the "hpd-gpios" ? Hmm... I don't know how the "hpd-gpios" want
> >>to help in this case, would you mind show some sample code  :-D
> >I don't know that there is h/w, but it is always possible HPD is not
> >hooked up or hooked up incorrectly some how.
> >
> >If there is no HPD support, then hpd-gpios is not going to help you.
> >
> >I think there are 3 cases to handle:
> >- HPD handled by bridge chip - The bridge driver knows it has this
> >capability. No DT properties are needed and no HPD properties on the
> >connector node imply the bridge chip should handle HPD functions.
> >- HPD handled by GPIO line (or some other block) - Indicated by
> >hpd-gpios present
> >- No or broken HPD - Indicated by "hpd-force" property.
> 
> Oh, I think the first/second case isn't suitable in this case, my panel
> "cnm,n116bgeea2" haven't included HPD signal.

Note that if your panel doesn't signal HPD you're supposed to poll the
sink to make sure you catch loss of link integrity. I've always found it
odd that people would want to save a couple of bucks on the HPD signal
conductor when that means that you will consume more power because you
need to periodically poll the link for integrity.

> >>>Are there any eDP panels which don't have EDID and need panel details in
> >>>DT?
> >>
> >>Oh, I think you want to collect some info that belong to panel
> >>property but no indicate in panel EDID message, so those can
> >>be collect in eDP connector binding, is it right ?
> >Yes, and as Thierry pointed out we may need to know the exact panel even.
> 
> Yeah, just like I reply to Thierry, this is a panel quirk. And he suggest we
> should
> handle this in panel driver, but I have no idea how to handle this in common
> panel
> driver.   :)

Like I said in another subthread, this panel does have an HPD line in a
variant that I've used in the past. So if your variant doesn't have the
HPD line, we're dealing with quirks within the same family of panels.
That would make this some sort of quirk, and I'm not sure if there is a
standard way for defining quirks in DT. Rob, do you know of any
precedent for this?

I suppose we could always add a variant-specific compatible string that
would allow this quirk to be encoded in the driver, though I'm not sure
if the model string in datasheets has enough detail to tell them apart.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-07  8:39             ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-07  8:39 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Rob Herring, Heiko Stuebner, Jingoo Han, Inki Dae, Joe Perches,
	Kukjin Kim, Krzysztof Kozlowski, Mark Yao, Russell King,
	djkurtz-F7+t8E8rja9Wk0Htik3J/w, dianders-F7+t8E8rja9Wk0Htik3J/w,
	seanpaul-F7+t8E8rja9Wk0Htik3J/w, Ajay kumar, Andrzej Hajda,
	Kyungmin Park, David Airlie, Gustavo Padovan, Andy Yan,
	Kumar Gala, Ian Campbell, Rob Herring, Pawel Moll,
	Kishon Vijay Abraham I, architt-sgV2jX0FEOL9JmXXK+q4OQ,
	dri-devel

[-- Attachment #1: Type: text/plain, Size: 4594 bytes --]

On Sun, Sep 06, 2015 at 04:20:39PM +0800, Yakir Yang wrote:
> Hi Rob,
> 
> 在 09/05/2015 05:46 AM, Rob Herring 写道:
> >On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
> >>Hi Rob,
> >>
> >>在 09/03/2015 04:17 AM, Rob Herring 写道:
> >>>On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
> >>>>Some edp screen do not have hpd signal, so we can't just return
> >>>>failed when hpd plug in detect failed.
> >>>This is a property of the panel (or connector perhaps), so this
> >>>property should be located there. At least, it is a common issue and
> >>>not specific to this chip. We could have an HDMI connector and failed
> >>>to hook up HPD for example. A connector node is also where hpd-gpios
> >>>should be located instead (and are already defined by
> >>>../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
> >>>binding, too.
> >>
> >>Yep, I agree with your front point, it is a property of panel, not specific
> >>to eDP controller, so this code should handle in connector logic.
> >>
> >>But another question, if we just leave this property to connector,
> >>then we would need to parse this property in analogix_dp-rockchip.c,
> >>and then make an hook in analogix_dp_core.c driver. This is not nice,
> >>and if there are some coming platform which alse want to use analogix_dp
> >>code and meet this "no-hpd" situation,  then they would need duplicate
> >>to parse this property and fill the hook in analogix_dp_core.c driver.
> >>So it's little bit conflict  :-)
> >Ideally, you would be able to just retrieve this quirk from the
> >connector or panel. Getting this property from your node vs. the port
> >you are attached to should not be much harder. Either the connector
> >struct can have this info or there can be a DT function that can walk
> >the graph and get it. Just don't open code the graph traversal in your
> >driver.
> >
> >>Beside I can not understand your example very well. Do you mean
> >>that there are some HDMI monitor which also do not have HPD
> >>signal (just like some eDP panel do not have hpd too), and then
> >>the "hpd-gpios" ? Hmm... I don't know how the "hpd-gpios" want
> >>to help in this case, would you mind show some sample code  :-D
> >I don't know that there is h/w, but it is always possible HPD is not
> >hooked up or hooked up incorrectly some how.
> >
> >If there is no HPD support, then hpd-gpios is not going to help you.
> >
> >I think there are 3 cases to handle:
> >- HPD handled by bridge chip - The bridge driver knows it has this
> >capability. No DT properties are needed and no HPD properties on the
> >connector node imply the bridge chip should handle HPD functions.
> >- HPD handled by GPIO line (or some other block) - Indicated by
> >hpd-gpios present
> >- No or broken HPD - Indicated by "hpd-force" property.
> 
> Oh, I think the first/second case isn't suitable in this case, my panel
> "cnm,n116bgeea2" haven't included HPD signal.

Note that if your panel doesn't signal HPD you're supposed to poll the
sink to make sure you catch loss of link integrity. I've always found it
odd that people would want to save a couple of bucks on the HPD signal
conductor when that means that you will consume more power because you
need to periodically poll the link for integrity.

> >>>Are there any eDP panels which don't have EDID and need panel details in
> >>>DT?
> >>
> >>Oh, I think you want to collect some info that belong to panel
> >>property but no indicate in panel EDID message, so those can
> >>be collect in eDP connector binding, is it right ?
> >Yes, and as Thierry pointed out we may need to know the exact panel even.
> 
> Yeah, just like I reply to Thierry, this is a panel quirk. And he suggest we
> should
> handle this in panel driver, but I have no idea how to handle this in common
> panel
> driver.   :)

Like I said in another subthread, this panel does have an HPD line in a
variant that I've used in the past. So if your variant doesn't have the
HPD line, we're dealing with quirks within the same family of panels.
That would make this some sort of quirk, and I'm not sure if there is a
standard way for defining quirks in DT. Rob, do you know of any
precedent for this?

I suppose we could always add a variant-specific compatible string that
would allow this quirk to be encoded in the driver, though I'm not sure
if the model string in datasheets has enough detail to tell them apart.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-07  8:39             ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-07  8:39 UTC (permalink / raw)
  To: linux-arm-kernel

On Sun, Sep 06, 2015 at 04:20:39PM +0800, Yakir Yang wrote:
> Hi Rob,
> 
> ? 09/05/2015 05:46 AM, Rob Herring ??:
> >On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang <ykk@rock-chips.com> wrote:
> >>Hi Rob,
> >>
> >>? 09/03/2015 04:17 AM, Rob Herring ??:
> >>>On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> >>>>Some edp screen do not have hpd signal, so we can't just return
> >>>>failed when hpd plug in detect failed.
> >>>This is a property of the panel (or connector perhaps), so this
> >>>property should be located there. At least, it is a common issue and
> >>>not specific to this chip. We could have an HDMI connector and failed
> >>>to hook up HPD for example. A connector node is also where hpd-gpios
> >>>should be located instead (and are already defined by
> >>>../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
> >>>binding, too.
> >>
> >>Yep, I agree with your front point, it is a property of panel, not specific
> >>to eDP controller, so this code should handle in connector logic.
> >>
> >>But another question, if we just leave this property to connector,
> >>then we would need to parse this property in analogix_dp-rockchip.c,
> >>and then make an hook in analogix_dp_core.c driver. This is not nice,
> >>and if there are some coming platform which alse want to use analogix_dp
> >>code and meet this "no-hpd" situation,  then they would need duplicate
> >>to parse this property and fill the hook in analogix_dp_core.c driver.
> >>So it's little bit conflict  :-)
> >Ideally, you would be able to just retrieve this quirk from the
> >connector or panel. Getting this property from your node vs. the port
> >you are attached to should not be much harder. Either the connector
> >struct can have this info or there can be a DT function that can walk
> >the graph and get it. Just don't open code the graph traversal in your
> >driver.
> >
> >>Beside I can not understand your example very well. Do you mean
> >>that there are some HDMI monitor which also do not have HPD
> >>signal (just like some eDP panel do not have hpd too), and then
> >>the "hpd-gpios" ? Hmm... I don't know how the "hpd-gpios" want
> >>to help in this case, would you mind show some sample code  :-D
> >I don't know that there is h/w, but it is always possible HPD is not
> >hooked up or hooked up incorrectly some how.
> >
> >If there is no HPD support, then hpd-gpios is not going to help you.
> >
> >I think there are 3 cases to handle:
> >- HPD handled by bridge chip - The bridge driver knows it has this
> >capability. No DT properties are needed and no HPD properties on the
> >connector node imply the bridge chip should handle HPD functions.
> >- HPD handled by GPIO line (or some other block) - Indicated by
> >hpd-gpios present
> >- No or broken HPD - Indicated by "hpd-force" property.
> 
> Oh, I think the first/second case isn't suitable in this case, my panel
> "cnm,n116bgeea2" haven't included HPD signal.

Note that if your panel doesn't signal HPD you're supposed to poll the
sink to make sure you catch loss of link integrity. I've always found it
odd that people would want to save a couple of bucks on the HPD signal
conductor when that means that you will consume more power because you
need to periodically poll the link for integrity.

> >>>Are there any eDP panels which don't have EDID and need panel details in
> >>>DT?
> >>
> >>Oh, I think you want to collect some info that belong to panel
> >>property but no indicate in panel EDID message, so those can
> >>be collect in eDP connector binding, is it right ?
> >Yes, and as Thierry pointed out we may need to know the exact panel even.
> 
> Yeah, just like I reply to Thierry, this is a panel quirk. And he suggest we
> should
> handle this in panel driver, but I have no idea how to handle this in common
> panel
> driver.   :)

Like I said in another subthread, this panel does have an HPD line in a
variant that I've used in the past. So if your variant doesn't have the
HPD line, we're dealing with quirks within the same family of panels.
That would make this some sort of quirk, and I'm not sure if there is a
standard way for defining quirks in DT. Rob, do you know of any
precedent for this?

I suppose we could always add a variant-specific compatible string that
would allow this quirk to be encoded in the driver, though I'm not sure
if the model string in datasheets has enough detail to tell them apart.

Thierry
-------------- next part --------------
A non-text attachment was scrubbed...
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2015-09-04 10:20           ` Russell King - ARM Linux
  (?)
@ 2015-09-07  9:01             ` Thierry Reding
  -1 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-07  9:01 UTC (permalink / raw)
  To: Russell King - ARM Linux
  Cc: Yakir Yang, Rob Herring, Heiko Stuebner, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

[-- Attachment #1: Type: text/plain, Size: 2338 bytes --]

On Fri, Sep 04, 2015 at 11:20:03AM +0100, Russell King - ARM Linux wrote:
> On Thu, Sep 03, 2015 at 11:04:40AM +0200, Thierry Reding wrote:
> > Conversely, if the panel isn't capable of generating an HPD signal, then
> > I don't think it would be appropriate to make it a DT property. It would
> > be better to hard-code it in the driver, lest someone forget to set the
> > property in DT and get stuck with a device that isn't operational.
> 
> There is another way to deal with this: DRM supports the idea of connector
> forcing - where you can force the connector to think that it's connected
> or disconnected.

Yes, this could work well for RGB/LVDS or DSI connectors perhaps. For
eDP there is added complexity because the HPD interrupt function is also
used to signal loss of link integrity. That is, after receiving an HPD
interrupt you are supposed to retrain the link (or at least check the
link status to see if the interrupt cause is loss of integrity). While
the eDP specification makes HPD optional, it also says that if HPD isn't
available, then the source must use polling to monitor link integrity
instead.

DRM does provide a mechanism for that as well. You can set the
connector's ->polled field to DRM_CONNECTOR_POLL_CONNECT |
DRM_CONNECTOR_POLL_DISCONNECT and have the core actively poll for the
connector status (i.e. call ->detect() every 100 ms).

I think use of polling would be more appropriate in case of eDP.

> One of the problems is that not many ARM DRM drivers implement it - maybe
> it should be a requirement for code to be accepted? :)

I suspect that many drivers may roll their own. In fact I'm guilty of
that myself. On Tegra we have a default implementation for outputs which
will default to the state of an HPD GPIO where available and fall back
to "always connected" for outputs that have a panel connected. Outputs
that have a separate mechanism to signal hotplug detection (such as DP)
simply use a custom ->detect() implementation.

The overhead of rolling one's own is almost zero and connector forcing
has the disadvantage of being available via sysfs and debugfs, so the
default set by drivers could be overwritten by users at runtime with no
easy way back.

Given the above I'm not sure enforcing connector forcing would be
beneficial.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-07  9:01             ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-07  9:01 UTC (permalink / raw)
  To: Russell King - ARM Linux
  Cc: Yakir Yang, Rob Herring, Heiko Stuebner, Jingoo Han, Inki Dae,
	Joe Perches, Kukjin Kim, Krzysztof Kozlowski, Mark Yao, djkurtz,
	dianders, seanpaul, Ajay kumar, Andrzej Hajda, Kyungmin Park,
	David Airlie, Gustavo Padovan, Andy Yan, Kumar Gala,
	Ian Campbell, Rob Herring, Pawel Moll, Kishon Vijay Abraham I,
	architt, dri-devel

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On Fri, Sep 04, 2015 at 11:20:03AM +0100, Russell King - ARM Linux wrote:
> On Thu, Sep 03, 2015 at 11:04:40AM +0200, Thierry Reding wrote:
> > Conversely, if the panel isn't capable of generating an HPD signal, then
> > I don't think it would be appropriate to make it a DT property. It would
> > be better to hard-code it in the driver, lest someone forget to set the
> > property in DT and get stuck with a device that isn't operational.
> 
> There is another way to deal with this: DRM supports the idea of connector
> forcing - where you can force the connector to think that it's connected
> or disconnected.

Yes, this could work well for RGB/LVDS or DSI connectors perhaps. For
eDP there is added complexity because the HPD interrupt function is also
used to signal loss of link integrity. That is, after receiving an HPD
interrupt you are supposed to retrain the link (or at least check the
link status to see if the interrupt cause is loss of integrity). While
the eDP specification makes HPD optional, it also says that if HPD isn't
available, then the source must use polling to monitor link integrity
instead.

DRM does provide a mechanism for that as well. You can set the
connector's ->polled field to DRM_CONNECTOR_POLL_CONNECT |
DRM_CONNECTOR_POLL_DISCONNECT and have the core actively poll for the
connector status (i.e. call ->detect() every 100 ms).

I think use of polling would be more appropriate in case of eDP.

> One of the problems is that not many ARM DRM drivers implement it - maybe
> it should be a requirement for code to be accepted? :)

I suspect that many drivers may roll their own. In fact I'm guilty of
that myself. On Tegra we have a default implementation for outputs which
will default to the state of an HPD GPIO where available and fall back
to "always connected" for outputs that have a panel connected. Outputs
that have a separate mechanism to signal hotplug detection (such as DP)
simply use a custom ->detect() implementation.

The overhead of rolling one's own is almost zero and connector forcing
has the disadvantage of being available via sysfs and debugfs, so the
default set by drivers could be overwritten by users at runtime with no
easy way back.

Given the above I'm not sure enforcing connector forcing would be
beneficial.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-07  9:01             ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-07  9:01 UTC (permalink / raw)
  To: linux-arm-kernel

On Fri, Sep 04, 2015 at 11:20:03AM +0100, Russell King - ARM Linux wrote:
> On Thu, Sep 03, 2015 at 11:04:40AM +0200, Thierry Reding wrote:
> > Conversely, if the panel isn't capable of generating an HPD signal, then
> > I don't think it would be appropriate to make it a DT property. It would
> > be better to hard-code it in the driver, lest someone forget to set the
> > property in DT and get stuck with a device that isn't operational.
> 
> There is another way to deal with this: DRM supports the idea of connector
> forcing - where you can force the connector to think that it's connected
> or disconnected.

Yes, this could work well for RGB/LVDS or DSI connectors perhaps. For
eDP there is added complexity because the HPD interrupt function is also
used to signal loss of link integrity. That is, after receiving an HPD
interrupt you are supposed to retrain the link (or at least check the
link status to see if the interrupt cause is loss of integrity). While
the eDP specification makes HPD optional, it also says that if HPD isn't
available, then the source must use polling to monitor link integrity
instead.

DRM does provide a mechanism for that as well. You can set the
connector's ->polled field to DRM_CONNECTOR_POLL_CONNECT |
DRM_CONNECTOR_POLL_DISCONNECT and have the core actively poll for the
connector status (i.e. call ->detect() every 100 ms).

I think use of polling would be more appropriate in case of eDP.

> One of the problems is that not many ARM DRM drivers implement it - maybe
> it should be a requirement for code to be accepted? :)

I suspect that many drivers may roll their own. In fact I'm guilty of
that myself. On Tegra we have a default implementation for outputs which
will default to the state of an HPD GPIO where available and fall back
to "always connected" for outputs that have a panel connected. Outputs
that have a separate mechanism to signal hotplug detection (such as DP)
simply use a custom ->detect() implementation.

The overhead of rolling one's own is almost zero and connector forcing
has the disadvantage of being available via sysfs and debugfs, so the
default set by drivers could be overwritten by users at runtime with no
easy way back.

Given the above I'm not sure enforcing connector forcing would be
beneficial.

Thierry
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver
  2015-09-02  2:15     ` Yakir Yang
  (?)
@ 2015-09-21  8:45     ` Yakir Yang
  2015-09-21  9:15         ` Thierry Reding
  -1 siblings, 1 reply; 370+ messages in thread
From: Yakir Yang @ 2015-09-21  8:45 UTC (permalink / raw)
  To: Heiko Stuebner
  Cc: Krzysztof Kozlowski, s.infradead.org, dri-devel, Andrzej Hajda,
	Gustavo Padovan, linux-samsung-soc, seanpaul, djkurtz,
	Kishon Vijay Abraham I, linux-rockchip, Kukjin Kim, robherring2,
	Russell King, Thierry Reding, linux-arm-kernel, devicetree,
	Pawel Moll, Ian Campbell, ajaynumb, Rob Herring, dianders,
	Jingoo Han, linux-kernel, Kyungmin Park, Kumar Gala, joe,
	Andy Yan


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Hi Heiko,

On 09/02/2015 10:15 AM, Yakir Yang wrote:
> Hi Heiko,
>
> 在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
>> Hi Yakir,
>>
>> Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>>>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP 
>>> controller
>>> share the same IP, so a lot of parts can be re-used. I split the common
>>> code into bridge directory, then rk3288 and exynos only need to keep
>>> some platform code. Cause I can't find the exact IP name of exynos dp
>>> controller, so I decide to name dp core driver with "analogix" which I
>>> find in rk3288 eDP TRM ;)
>>>
>>> Beyond that, there are three light registers setting differents bewteen
>>> exynos and rk3288.
>>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>>     dp controller.
>>> 2. The address of DP_PHY_PD(dp phy power manager register) are 
>>> different
>>>     between rk3288 and exynos.
>>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp 
>>> debug
>>>     register).
>>>
>>> I have verified this series on two kinds of rockchip platform board, 
>>> one
>>> is rk3288 sdk board which connect with a 2K display port monitor, 
>>> the other
>>> is google jerry chromebook which connect with a eDP screen 
>>> "cnm,n116bgeea2",
>>> both of them works rightlly.
>> it looks like during the rebase something did go wrong and I found 
>> some issues
>> I mentioned in the replies to individual patches.
>>
>> I did prepare a branch based on mainline [0] with both the old and 
>> the new edp
>> driver - rk3288_veyron_defconfig build both drivers into the image.
>>
>> While the old driver still works, I wasn't able to make the new one 
>> work yet
>> ... the drm core does find the connector, but not that anything is 
>> connected
>> to it. I'll try to dig deeper tomorrow, but maybe you'll see anything
>> interesting before then.
>
> Many thanks for your comment and debug, I would rebase on your
> "edp-with-veyron" branch and fix the broken, make sure v6 would
> work rightly at least in your side and my side.

Just like we talk off line, I guess there are two tricky questions which 
make analogix_dp just crash/failed on rockchip platform:

-  One is how to reach a agreement with the common way to register 
connector. There would be a conflict with Exynos & IMX & Rockchip.
      On analogix_dp thread, Exynos want to register connector when that 
connector is ready.
      On dw_hdmi thread, IMX want to register connector when all 
component is already.
      So Exynos & IMX & Rockchip should reach a common way to register 
connector to fix this issue.

-  The other is atomic API.
       The rockchip drm haven't implemented the atomic API, but the 
original exynos_dp have used the atomic API on connector helper 
function. That's why analogix_dp just keep crash on your side.

I have prepared the v5 version, although those would work directly on 
rockchip side, but I could upload some HACK patches to gerrit  to make 
this works,  hope we can keep the discussion going forward.

Thanks,
- Yakir

>
> - Yakir
>
>>
>> Heiko
>>
>> [0] https://github.com/mmind/linux-rockchip/tree/tmp/edp-with-veyron
>>
>>
>>
>>
>
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


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_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2015-09-07  8:20             ` Thierry Reding
  (?)
  (?)
@ 2015-09-21  9:10             ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-21  9:10 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Krzysztof Kozlowski, dri-devel, Andrzej Hajda, Gustavo Padovan,
	linux-samsung-soc, seanpaul, djkurtz, Kishon Vijay Abraham I,
	linux-rockchip, Kukjin Kim, Rob Herring, Russell King,
	devicetree, Pawel Moll, Ian Campbell, Ajay kumar, Rob Herring,
	dianders, linux-arm-kernel, Jingoo Han,
	linux-kernel@vger.kernel.org


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Hi Thierry & Rob,

Sorry, apologize for the delay in replying  :-)


On 09/07/2015 04:20 PM, Thierry Reding wrote:
> On Sun, Sep 06, 2015 at 11:59:08AM +0800, Yakir Yang wrote:
>> Hi Thierry,
>>
>> 在 09/03/2015 05:04 PM, Thierry Reding 写道:
>>> On Thu, Sep 03, 2015 at 12:27:47PM +0800, Yakir Yang wrote:
>>>> Hi Rob,
>>>>
>>>> 在 09/03/2015 04:17 AM, Rob Herring 写道:
>>>>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>>>>>> Some edp screen do not have hpd signal, so we can't just return
>>>>>> failed when hpd plug in detect failed.
>>>>> This is a property of the panel (or connector perhaps), so this
>>>>> property should be located there. At least, it is a common issue and
>>>>> not specific to this chip. We could have an HDMI connector and failed
>>>>> to hook up HPD for example. A connector node is also where hpd-gpios
>>>>> should be located instead (and are already defined by
>>>>> ../bindings/video/hdmi-connector.txt). Perhaps we need a eDP connector
>>>>> binding, too.
>>>> Yep, I agree with your front point, it is a property of panel, not specific
>>>> to eDP controller, so this code should handle in connector logic.
>>>  From your description it sounds more like this is in fact a property of
>>> the panel. Or maybe I should say "quirk". If the panel doesn't generate
>>> the HPD signal, then that should be a property of the panel, not the
>>> connector. The eDP specification mandates that connectors have a HPD
>>> signal, though it allows the "HPD conductor in the connector cable" to
>>> be omitted if not used by the source. I'd consider the cable to belong
>>> to the panel rather than the connector, so absence of HPD, either
>>> because the cable doesn't have the conductor or because the panel does
>>> not generate the signal, should be a quirk of the panel.
>>>
>>> That said you could have a panel that supports HPD connected via a cable
>>> that doesn't transmit it, so this would be a per-board variant and hence
>>> should be a device tree property rather than hard-coded in some panel
>>> driver.
>>>
>>> Conversely, if the panel isn't capable of generating an HPD signal, then
>>> I don't think it would be appropriate to make it a DT property. It would
>>> be better to hard-code it in the driver, lest someone forget to set the
>>> property in DT and get stuck with a device that isn't operational.
>> Oh, you're right, if it's a cable quirk, then DT property would be okay, if
>> it
>> is a problem of panel, then maybe hard-code in driver would be better.
>>
>> After look up for the document of panel "innolux,n116bge", I haven't see
>> any description of hot plug signal, and even not found in PIN ASSIGNMENT.
>> So I believe it's a panel problem, that's to say it should handle in panel
>> driver.
> The datasheet that I have for that panel lists HPD as pin 17. Also I
> used to have a setup with that panel and I distinctly remember hotplug
> working just fine. Perhaps this is an issue with a specific variant of
> the panel? Or perhaps this is indeed a problem with the cable that's
> connecting the panel to the board. It could be one of those cases where
> they left out the HPD conductor to save money.

You're right, I guess I just download the wrong datasheet "N116BGE-L41.pdf"
which the video interfaces is "LVDS", thanks for you point out.

And I double checked with the guys who work with this screen vendor, he said
that it's the fault that vendor missed HPD pin on the screen board, and 
vendor
have fixed this problem later.

But there are still some machine didn't contain the HPD signal, and you also
mention that in some cases where vendor would left out the HPD conductor,
so I still wish to support those "quirk" screen in the later version. 
But I wish
you could share your opinion whether this could exist in the mainline
kernel.

If the answer is no, okay, I would remove this from the next versions. 
but If
the answer is yes, wow, I may still can use the DT property to satisfied 
this
demand (I guess it's okay to keep the DT property way from previous 
discussion).

Thanks,
- Yakir

>
> Thierry
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


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_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver
  2015-09-21  8:45     ` Yakir Yang
@ 2015-09-21  9:15         ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-21  9:15 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Krzysztof Kozlowski, s.infradead.org,
	David Airlie, dri-devel, Andrzej Hajda, Gustavo Padovan, architt,
	linux-samsung-soc, seanpaul, djkurtz, Kishon Vijay Abraham I,
	linux-rockchip, Kukjin Kim, robherring2, Russell King,
	linux-arm-kernel, devicetree, Pawel Moll, Ian Campbell, Inki Dae,
	joe, Rob Herring, dianders, Mark Yao, Jingoo Han, linux-kernel,
	Kyungmin Park, Kumar Gala, ajaynumb, Andy Yan

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On Mon, Sep 21, 2015 at 04:45:44PM +0800, Yakir Yang wrote:
> Hi Heiko,
> 
> On 09/02/2015 10:15 AM, Yakir Yang wrote:
> >Hi Heiko,
> >
> >在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
> >>Hi Yakir,
> >>
> >>Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
> >>>    The Samsung Exynos eDP controller and Rockchip RK3288 eDP
> >>>controller
> >>>share the same IP, so a lot of parts can be re-used. I split the common
> >>>code into bridge directory, then rk3288 and exynos only need to keep
> >>>some platform code. Cause I can't find the exact IP name of exynos dp
> >>>controller, so I decide to name dp core driver with "analogix" which I
> >>>find in rk3288 eDP TRM ;)
> >>>
> >>>Beyond that, there are three light registers setting differents bewteen
> >>>exynos and rk3288.
> >>>1. RK3288 have five special pll resigters which not indicata in exynos
> >>>    dp controller.
> >>>2. The address of DP_PHY_PD(dp phy power manager register) are
> >>>different
> >>>    between rk3288 and exynos.
> >>>3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp
> >>>debug
> >>>    register).
> >>>
> >>>I have verified this series on two kinds of rockchip platform board,
> >>>one
> >>>is rk3288 sdk board which connect with a 2K display port monitor, the
> >>>other
> >>>is google jerry chromebook which connect with a eDP screen
> >>>"cnm,n116bgeea2",
> >>>both of them works rightlly.
> >>it looks like during the rebase something did go wrong and I found some
> >>issues
> >>I mentioned in the replies to individual patches.
> >>
> >>I did prepare a branch based on mainline [0] with both the old and the
> >>new edp
> >>driver - rk3288_veyron_defconfig build both drivers into the image.
> >>
> >>While the old driver still works, I wasn't able to make the new one work
> >>yet
> >>... the drm core does find the connector, but not that anything is
> >>connected
> >>to it. I'll try to dig deeper tomorrow, but maybe you'll see anything
> >>interesting before then.
> >
> >Many thanks for your comment and debug, I would rebase on your
> >"edp-with-veyron" branch and fix the broken, make sure v6 would
> >work rightly at least in your side and my side.
> 
> Just like we talk off line, I guess there are two tricky questions which
> make analogix_dp just crash/failed on rockchip platform:
> 
> -  One is how to reach a agreement with the common way to register
> connector. There would be a conflict with Exynos & IMX & Rockchip.
>      On analogix_dp thread, Exynos want to register connector when that
> connector is ready.
>      On dw_hdmi thread, IMX want to register connector when all component is
> already.
>      So Exynos & IMX & Rockchip should reach a common way to register
> connector to fix this issue.
> 
> -  The other is atomic API.
>       The rockchip drm haven't implemented the atomic API, but the original
> exynos_dp have used the atomic API on connector helper function. That's why
> analogix_dp just keep crash on your side.

There's really no reason not to convert Rockchip to atomic. It will have
to happen eventually anyway.

That said, there's another option that would allow you to side-step both
of the above problems at the same time. If you turn the common code into
a helper library that should give you enough flexibility to integrate it
into all existing users. For example you could leave out the connector
registration and let the drivers do that. Similarly since the helpers
are only hooked up at registration time you could probably find a way to
share the low-level code but again leave it up to the drivers to glue it
all together at registration time (drivers could wrap the low-level code
with atomic or non-atomic callbacks).

This option may also have the benefit of loosening the coupling between
DRM drivers and the helper code for this IP, which may be handy in case
the drivers diverge again in the future, or ease transitions to new API.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver
@ 2015-09-21  9:15         ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-21  9:15 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Krzysztof Kozlowski, s.infradead.org,
	David Airlie, dri-devel, Andrzej Hajda, Gustavo Padovan, architt,
	linux-samsung-soc, seanpaul, djkurtz, Kishon Vijay Abraham I,
	linux-rockchip, Kukjin Kim, robherring2, Russell King,
	linux-arm-kernel, devicetree, Pawel Moll, Ian Campbell, Inki Dae,
	joe, Rob Herring, dianders, Mark Yao, Jingoo Han

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On Mon, Sep 21, 2015 at 04:45:44PM +0800, Yakir Yang wrote:
> Hi Heiko,
> 
> On 09/02/2015 10:15 AM, Yakir Yang wrote:
> >Hi Heiko,
> >
> >在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
> >>Hi Yakir,
> >>
> >>Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
> >>>    The Samsung Exynos eDP controller and Rockchip RK3288 eDP
> >>>controller
> >>>share the same IP, so a lot of parts can be re-used. I split the common
> >>>code into bridge directory, then rk3288 and exynos only need to keep
> >>>some platform code. Cause I can't find the exact IP name of exynos dp
> >>>controller, so I decide to name dp core driver with "analogix" which I
> >>>find in rk3288 eDP TRM ;)
> >>>
> >>>Beyond that, there are three light registers setting differents bewteen
> >>>exynos and rk3288.
> >>>1. RK3288 have five special pll resigters which not indicata in exynos
> >>>    dp controller.
> >>>2. The address of DP_PHY_PD(dp phy power manager register) are
> >>>different
> >>>    between rk3288 and exynos.
> >>>3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp
> >>>debug
> >>>    register).
> >>>
> >>>I have verified this series on two kinds of rockchip platform board,
> >>>one
> >>>is rk3288 sdk board which connect with a 2K display port monitor, the
> >>>other
> >>>is google jerry chromebook which connect with a eDP screen
> >>>"cnm,n116bgeea2",
> >>>both of them works rightlly.
> >>it looks like during the rebase something did go wrong and I found some
> >>issues
> >>I mentioned in the replies to individual patches.
> >>
> >>I did prepare a branch based on mainline [0] with both the old and the
> >>new edp
> >>driver - rk3288_veyron_defconfig build both drivers into the image.
> >>
> >>While the old driver still works, I wasn't able to make the new one work
> >>yet
> >>... the drm core does find the connector, but not that anything is
> >>connected
> >>to it. I'll try to dig deeper tomorrow, but maybe you'll see anything
> >>interesting before then.
> >
> >Many thanks for your comment and debug, I would rebase on your
> >"edp-with-veyron" branch and fix the broken, make sure v6 would
> >work rightly at least in your side and my side.
> 
> Just like we talk off line, I guess there are two tricky questions which
> make analogix_dp just crash/failed on rockchip platform:
> 
> -  One is how to reach a agreement with the common way to register
> connector. There would be a conflict with Exynos & IMX & Rockchip.
>      On analogix_dp thread, Exynos want to register connector when that
> connector is ready.
>      On dw_hdmi thread, IMX want to register connector when all component is
> already.
>      So Exynos & IMX & Rockchip should reach a common way to register
> connector to fix this issue.
> 
> -  The other is atomic API.
>       The rockchip drm haven't implemented the atomic API, but the original
> exynos_dp have used the atomic API on connector helper function. That's why
> analogix_dp just keep crash on your side.

There's really no reason not to convert Rockchip to atomic. It will have
to happen eventually anyway.

That said, there's another option that would allow you to side-step both
of the above problems at the same time. If you turn the common code into
a helper library that should give you enough flexibility to integrate it
into all existing users. For example you could leave out the connector
registration and let the drivers do that. Similarly since the helpers
are only hooked up at registration time you could probably find a way to
share the low-level code but again leave it up to the drivers to glue it
all together at registration time (drivers could wrap the low-level code
with atomic or non-atomic callbacks).

This option may also have the benefit of loosening the coupling between
DRM drivers and the helper code for this IP, which may be handy in case
the drivers diverge again in the future, or ease transitions to new API.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver
  2015-09-21  9:15         ` Thierry Reding
@ 2015-09-21 10:27           ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-21 10:27 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Heiko Stuebner, Krzysztof Kozlowski, s.infradead.org,
	David Airlie, dri-devel, Andrzej Hajda, Gustavo Padovan, architt,
	linux-samsung-soc, seanpaul, djkurtz, Kishon Vijay Abraham I,
	linux-rockchip, Kukjin Kim, robherring2, Russell King,
	linux-arm-kernel, devicetree, Pawel Moll, Ian Campbell, Inki Dae,
	joe, Rob Herring, dianders, Mark Yao, Jingoo Han, linux-kernel,
	Kyungmin Park, Kumar Gala, ajaynumb, Andy Yan

Hi Thierry,

Thanks for your suggest :)

On 09/21/2015 05:15 PM, Thierry Reding wrote:
> On Mon, Sep 21, 2015 at 04:45:44PM +0800, Yakir Yang wrote:
>> Hi Heiko,
>>
>> On 09/02/2015 10:15 AM, Yakir Yang wrote:
>>> Hi Heiko,
>>>
>>> 在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
>>>> Hi Yakir,
>>>>
>>>> Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>>>>>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP
>>>>> controller
>>>>> share the same IP, so a lot of parts can be re-used. I split the common
>>>>> code into bridge directory, then rk3288 and exynos only need to keep
>>>>> some platform code. Cause I can't find the exact IP name of exynos dp
>>>>> controller, so I decide to name dp core driver with "analogix" which I
>>>>> find in rk3288 eDP TRM ;)
>>>>>
>>>>> Beyond that, there are three light registers setting differents bewteen
>>>>> exynos and rk3288.
>>>>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>>>>     dp controller.
>>>>> 2. The address of DP_PHY_PD(dp phy power manager register) are
>>>>> different
>>>>>     between rk3288 and exynos.
>>>>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp
>>>>> debug
>>>>>     register).
>>>>>
>>>>> I have verified this series on two kinds of rockchip platform board,
>>>>> one
>>>>> is rk3288 sdk board which connect with a 2K display port monitor, the
>>>>> other
>>>>> is google jerry chromebook which connect with a eDP screen
>>>>> "cnm,n116bgeea2",
>>>>> both of them works rightlly.
>>>> it looks like during the rebase something did go wrong and I found some
>>>> issues
>>>> I mentioned in the replies to individual patches.
>>>>
>>>> I did prepare a branch based on mainline [0] with both the old and the
>>>> new edp
>>>> driver - rk3288_veyron_defconfig build both drivers into the image.
>>>>
>>>> While the old driver still works, I wasn't able to make the new one work
>>>> yet
>>>> ... the drm core does find the connector, but not that anything is
>>>> connected
>>>> to it. I'll try to dig deeper tomorrow, but maybe you'll see anything
>>>> interesting before then.
>>> Many thanks for your comment and debug, I would rebase on your
>>> "edp-with-veyron" branch and fix the broken, make sure v6 would
>>> work rightly at least in your side and my side.
>> Just like we talk off line, I guess there are two tricky questions which
>> make analogix_dp just crash/failed on rockchip platform:
>>
>> -  One is how to reach a agreement with the common way to register
>> connector. There would be a conflict with Exynos & IMX & Rockchip.
>>       On analogix_dp thread, Exynos want to register connector when that
>> connector is ready.
>>       On dw_hdmi thread, IMX want to register connector when all component is
>> already.
>>       So Exynos & IMX & Rockchip should reach a common way to register
>> connector to fix this issue.
>>
>> -  The other is atomic API.
>>        The rockchip drm haven't implemented the atomic API, but the original
>> exynos_dp have used the atomic API on connector helper function. That's why
>> analogix_dp just keep crash on your side.
> There's really no reason not to convert Rockchip to atomic. It will have
> to happen eventually anyway.

Do agree on this point, and I see Tomasz Figa have done some WIP
works on implementing the atomic_commit, maybe would upstream
in further.(https://chromium-review.googlesource.com/#/c/284560/1)


> That said, there's another option that would allow you to side-step both
> of the above problems at the same time. If you turn the common code into
> a helper library that should give you enough flexibility to integrate it
> into all existing users. For example you could leave out the connector
> registration and let the drivers do that. Similarly since the helpers
> are only hooked up at registration time you could probably find a way to
> share the low-level code but again leave it up to the drivers to glue it
> all together at registration time (drivers could wrap the low-level code
> with atomic or non-atomic callbacks).

Wow, sounds good, but I'm not sure I understand this rightly. Do you
mean that I could support two kinds of callbacks in analogix_dp_core
driver, and export them out. And move the connector registration code
into the helper driver (like exynos_dp.c), so helper driver could chose to
use the atomic or non-atomic callbacks. like:

-- analogix_dp_core.c 
--------------------------------------------------------------------
...
struct drm_connector_funcs analogix_dp_connector_atomic_funcs = {
         .dpms = drm_atomic_helper_connector_dpms,
         .fill_modes = drm_helper_probe_single_connector_modes,
         .detect = analogix_dp_detect,
         .destroy = analogix_dp_connector_destroy,
         .reset = drm_atomic_helper_connector_reset,
         .atomic_duplicate_state = 
drm_atomic_helper_connector_duplicate_state,
         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
EXPORT_SYMBOL(analogix_dp_connector_atomic_funcs);

struct drm_connector_funcs analogix_dp_connector_funcs = {
         .dpms = drm_helper_connector_dpms,
         .fill_modes = drm_helper_probe_single_connector_modes,
         .detect = analogix_dp_detect,
         .destroy = analogix_dp_connector_destroy,
};
EXPORT_SYMBOL(analogix_dp_connector_funcs);

struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
         .get_modes = analogix_dp_get_modes,
         .best_encoder = analogix_dp_best_encoder,
};
EXPORT_SYMBOL(analogix_dp_connector_helper_funcs);
...

-- exynos_dp 
----------------------------------------------------------------------------
         ret = drm_connector_init(dp->drm_dev, connector,
&analogix_dp_connector_atomic_funcs,
                                  DRM_MODE_CONNECTOR_eDP);
         if (ret) {
                 DRM_ERROR("Failed to initialize connector with drm\n");
                 return ret;
         }

         drm_connector_helper_add(connector, 
&analogix_dp_connector_helper_funcs);
         drm_connector_register(connector);
         drm_mode_connector_attach_encoder(connector, encoder);

-- analogix_dp-rockchip 
----------------------------------------------------------------------------
         ret = drm_connector_init(dp->drm_dev, connector,
                                  &analogix_dp_connector_funcs,
                                  DRM_MODE_CONNECTOR_eDP);
         if (ret) {
                 DRM_ERROR("Failed to initialize connector with drm\n");
                 return ret;
         }

         drm_connector_helper_add(connector, 
&analogix_dp_connector_helper_funcs);
         drm_mode_connector_attach_encoder(connector, encoder);


Are those code corresponding to your suggestion.   :)

Thanks
- Yakir

> This option may also have the benefit of loosening the coupling between
> DRM drivers and the helper code for this IP, which may be handy in case
> the drivers diverge again in the future, or ease transitions to new API.
>
> Thierry



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver
@ 2015-09-21 10:27           ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-21 10:27 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Heiko Stuebner, Krzysztof Kozlowski, s.infradead.org,
	David Airlie, dri-devel, Andrzej Hajda, Gustavo Padovan, architt,
	linux-samsung-soc, seanpaul, djkurtz, Kishon Vijay Abraham I,
	linux-rockchip, Kukjin Kim, robherring2, Russell King,
	linux-arm-kernel, devicetree, Pawel Moll, Ian Campbell, Inki Dae,
	joe, Rob Herring, dianders, Mark Yao, Jingoo Han, linux-kernel

Hi Thierry,

Thanks for your suggest :)

On 09/21/2015 05:15 PM, Thierry Reding wrote:
> On Mon, Sep 21, 2015 at 04:45:44PM +0800, Yakir Yang wrote:
>> Hi Heiko,
>>
>> On 09/02/2015 10:15 AM, Yakir Yang wrote:
>>> Hi Heiko,
>>>
>>> 在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
>>>> Hi Yakir,
>>>>
>>>> Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>>>>>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP
>>>>> controller
>>>>> share the same IP, so a lot of parts can be re-used. I split the common
>>>>> code into bridge directory, then rk3288 and exynos only need to keep
>>>>> some platform code. Cause I can't find the exact IP name of exynos dp
>>>>> controller, so I decide to name dp core driver with "analogix" which I
>>>>> find in rk3288 eDP TRM ;)
>>>>>
>>>>> Beyond that, there are three light registers setting differents bewteen
>>>>> exynos and rk3288.
>>>>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>>>>     dp controller.
>>>>> 2. The address of DP_PHY_PD(dp phy power manager register) are
>>>>> different
>>>>>     between rk3288 and exynos.
>>>>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp
>>>>> debug
>>>>>     register).
>>>>>
>>>>> I have verified this series on two kinds of rockchip platform board,
>>>>> one
>>>>> is rk3288 sdk board which connect with a 2K display port monitor, the
>>>>> other
>>>>> is google jerry chromebook which connect with a eDP screen
>>>>> "cnm,n116bgeea2",
>>>>> both of them works rightlly.
>>>> it looks like during the rebase something did go wrong and I found some
>>>> issues
>>>> I mentioned in the replies to individual patches.
>>>>
>>>> I did prepare a branch based on mainline [0] with both the old and the
>>>> new edp
>>>> driver - rk3288_veyron_defconfig build both drivers into the image.
>>>>
>>>> While the old driver still works, I wasn't able to make the new one work
>>>> yet
>>>> ... the drm core does find the connector, but not that anything is
>>>> connected
>>>> to it. I'll try to dig deeper tomorrow, but maybe you'll see anything
>>>> interesting before then.
>>> Many thanks for your comment and debug, I would rebase on your
>>> "edp-with-veyron" branch and fix the broken, make sure v6 would
>>> work rightly at least in your side and my side.
>> Just like we talk off line, I guess there are two tricky questions which
>> make analogix_dp just crash/failed on rockchip platform:
>>
>> -  One is how to reach a agreement with the common way to register
>> connector. There would be a conflict with Exynos & IMX & Rockchip.
>>       On analogix_dp thread, Exynos want to register connector when that
>> connector is ready.
>>       On dw_hdmi thread, IMX want to register connector when all component is
>> already.
>>       So Exynos & IMX & Rockchip should reach a common way to register
>> connector to fix this issue.
>>
>> -  The other is atomic API.
>>        The rockchip drm haven't implemented the atomic API, but the original
>> exynos_dp have used the atomic API on connector helper function. That's why
>> analogix_dp just keep crash on your side.
> There's really no reason not to convert Rockchip to atomic. It will have
> to happen eventually anyway.

Do agree on this point, and I see Tomasz Figa have done some WIP
works on implementing the atomic_commit, maybe would upstream
in further.(https://chromium-review.googlesource.com/#/c/284560/1)


> That said, there's another option that would allow you to side-step both
> of the above problems at the same time. If you turn the common code into
> a helper library that should give you enough flexibility to integrate it
> into all existing users. For example you could leave out the connector
> registration and let the drivers do that. Similarly since the helpers
> are only hooked up at registration time you could probably find a way to
> share the low-level code but again leave it up to the drivers to glue it
> all together at registration time (drivers could wrap the low-level code
> with atomic or non-atomic callbacks).

Wow, sounds good, but I'm not sure I understand this rightly. Do you
mean that I could support two kinds of callbacks in analogix_dp_core
driver, and export them out. And move the connector registration code
into the helper driver (like exynos_dp.c), so helper driver could chose to
use the atomic or non-atomic callbacks. like:

-- analogix_dp_core.c 
--------------------------------------------------------------------
...
struct drm_connector_funcs analogix_dp_connector_atomic_funcs = {
         .dpms = drm_atomic_helper_connector_dpms,
         .fill_modes = drm_helper_probe_single_connector_modes,
         .detect = analogix_dp_detect,
         .destroy = analogix_dp_connector_destroy,
         .reset = drm_atomic_helper_connector_reset,
         .atomic_duplicate_state = 
drm_atomic_helper_connector_duplicate_state,
         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
EXPORT_SYMBOL(analogix_dp_connector_atomic_funcs);

struct drm_connector_funcs analogix_dp_connector_funcs = {
         .dpms = drm_helper_connector_dpms,
         .fill_modes = drm_helper_probe_single_connector_modes,
         .detect = analogix_dp_detect,
         .destroy = analogix_dp_connector_destroy,
};
EXPORT_SYMBOL(analogix_dp_connector_funcs);

struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
         .get_modes = analogix_dp_get_modes,
         .best_encoder = analogix_dp_best_encoder,
};
EXPORT_SYMBOL(analogix_dp_connector_helper_funcs);
...

-- exynos_dp 
----------------------------------------------------------------------------
         ret = drm_connector_init(dp->drm_dev, connector,
&analogix_dp_connector_atomic_funcs,
                                  DRM_MODE_CONNECTOR_eDP);
         if (ret) {
                 DRM_ERROR("Failed to initialize connector with drm\n");
                 return ret;
         }

         drm_connector_helper_add(connector, 
&analogix_dp_connector_helper_funcs);
         drm_connector_register(connector);
         drm_mode_connector_attach_encoder(connector, encoder);

-- analogix_dp-rockchip 
----------------------------------------------------------------------------
         ret = drm_connector_init(dp->drm_dev, connector,
                                  &analogix_dp_connector_funcs,
                                  DRM_MODE_CONNECTOR_eDP);
         if (ret) {
                 DRM_ERROR("Failed to initialize connector with drm\n");
                 return ret;
         }

         drm_connector_helper_add(connector, 
&analogix_dp_connector_helper_funcs);
         drm_mode_connector_attach_encoder(connector, encoder);


Are those code corresponding to your suggestion.   :)

Thanks
- Yakir

> This option may also have the benefit of loosening the coupling between
> DRM drivers and the helper code for this IP, which may be handy in case
> the drivers diverge again in the future, or ease transitions to new API.
>
> Thierry

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver
  2015-09-21 10:27           ` Yakir Yang
@ 2015-09-21 11:22             ` Thierry Reding
  -1 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-21 11:22 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Krzysztof Kozlowski, s.infradead.org,
	David Airlie, dri-devel, Andrzej Hajda, Gustavo Padovan, architt,
	linux-samsung-soc, seanpaul, djkurtz, Kishon Vijay Abraham I,
	linux-rockchip, Kukjin Kim, robherring2, Russell King,
	linux-arm-kernel, devicetree, Pawel Moll, Ian Campbell, Inki Dae,
	joe, Rob Herring, dianders, Mark Yao, Jingoo Han, linux-kernel,
	Kyungmin Park, Kumar Gala, ajaynumb, Andy Yan

[-- Attachment #1: Type: text/plain, Size: 7521 bytes --]

On Mon, Sep 21, 2015 at 06:27:40PM +0800, Yakir Yang wrote:
> Hi Thierry,
> 
> Thanks for your suggest :)
> 
> On 09/21/2015 05:15 PM, Thierry Reding wrote:
> >On Mon, Sep 21, 2015 at 04:45:44PM +0800, Yakir Yang wrote:
> >>Hi Heiko,
> >>
> >>On 09/02/2015 10:15 AM, Yakir Yang wrote:
> >>>Hi Heiko,
> >>>
> >>>在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
> >>>>Hi Yakir,
> >>>>
> >>>>Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
> >>>>>    The Samsung Exynos eDP controller and Rockchip RK3288 eDP
> >>>>>controller
> >>>>>share the same IP, so a lot of parts can be re-used. I split the common
> >>>>>code into bridge directory, then rk3288 and exynos only need to keep
> >>>>>some platform code. Cause I can't find the exact IP name of exynos dp
> >>>>>controller, so I decide to name dp core driver with "analogix" which I
> >>>>>find in rk3288 eDP TRM ;)
> >>>>>
> >>>>>Beyond that, there are three light registers setting differents bewteen
> >>>>>exynos and rk3288.
> >>>>>1. RK3288 have five special pll resigters which not indicata in exynos
> >>>>>    dp controller.
> >>>>>2. The address of DP_PHY_PD(dp phy power manager register) are
> >>>>>different
> >>>>>    between rk3288 and exynos.
> >>>>>3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp
> >>>>>debug
> >>>>>    register).
> >>>>>
> >>>>>I have verified this series on two kinds of rockchip platform board,
> >>>>>one
> >>>>>is rk3288 sdk board which connect with a 2K display port monitor, the
> >>>>>other
> >>>>>is google jerry chromebook which connect with a eDP screen
> >>>>>"cnm,n116bgeea2",
> >>>>>both of them works rightlly.
> >>>>it looks like during the rebase something did go wrong and I found some
> >>>>issues
> >>>>I mentioned in the replies to individual patches.
> >>>>
> >>>>I did prepare a branch based on mainline [0] with both the old and the
> >>>>new edp
> >>>>driver - rk3288_veyron_defconfig build both drivers into the image.
> >>>>
> >>>>While the old driver still works, I wasn't able to make the new one work
> >>>>yet
> >>>>... the drm core does find the connector, but not that anything is
> >>>>connected
> >>>>to it. I'll try to dig deeper tomorrow, but maybe you'll see anything
> >>>>interesting before then.
> >>>Many thanks for your comment and debug, I would rebase on your
> >>>"edp-with-veyron" branch and fix the broken, make sure v6 would
> >>>work rightly at least in your side and my side.
> >>Just like we talk off line, I guess there are two tricky questions which
> >>make analogix_dp just crash/failed on rockchip platform:
> >>
> >>-  One is how to reach a agreement with the common way to register
> >>connector. There would be a conflict with Exynos & IMX & Rockchip.
> >>      On analogix_dp thread, Exynos want to register connector when that
> >>connector is ready.
> >>      On dw_hdmi thread, IMX want to register connector when all component is
> >>already.
> >>      So Exynos & IMX & Rockchip should reach a common way to register
> >>connector to fix this issue.
> >>
> >>-  The other is atomic API.
> >>       The rockchip drm haven't implemented the atomic API, but the original
> >>exynos_dp have used the atomic API on connector helper function. That's why
> >>analogix_dp just keep crash on your side.
> >There's really no reason not to convert Rockchip to atomic. It will have
> >to happen eventually anyway.
> 
> Do agree on this point, and I see Tomasz Figa have done some WIP
> works on implementing the atomic_commit, maybe would upstream
> in further.(https://chromium-review.googlesource.com/#/c/284560/1)
> 
> 
> >That said, there's another option that would allow you to side-step both
> >of the above problems at the same time. If you turn the common code into
> >a helper library that should give you enough flexibility to integrate it
> >into all existing users. For example you could leave out the connector
> >registration and let the drivers do that. Similarly since the helpers
> >are only hooked up at registration time you could probably find a way to
> >share the low-level code but again leave it up to the drivers to glue it
> >all together at registration time (drivers could wrap the low-level code
> >with atomic or non-atomic callbacks).
> 
> Wow, sounds good, but I'm not sure I understand this rightly. Do you
> mean that I could support two kinds of callbacks in analogix_dp_core
> driver, and export them out. And move the connector registration code
> into the helper driver (like exynos_dp.c), so helper driver could chose to
> use the atomic or non-atomic callbacks. like:
> 
> -- analogix_dp_core.c
> --------------------------------------------------------------------
> ...
> struct drm_connector_funcs analogix_dp_connector_atomic_funcs = {
>         .dpms = drm_atomic_helper_connector_dpms,
>         .fill_modes = drm_helper_probe_single_connector_modes,
>         .detect = analogix_dp_detect,
>         .destroy = analogix_dp_connector_destroy,
>         .reset = drm_atomic_helper_connector_reset,
>         .atomic_duplicate_state =
> drm_atomic_helper_connector_duplicate_state,
>         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> };
> EXPORT_SYMBOL(analogix_dp_connector_atomic_funcs);
> 
> struct drm_connector_funcs analogix_dp_connector_funcs = {
>         .dpms = drm_helper_connector_dpms,
>         .fill_modes = drm_helper_probe_single_connector_modes,
>         .detect = analogix_dp_detect,
>         .destroy = analogix_dp_connector_destroy,
> };
> EXPORT_SYMBOL(analogix_dp_connector_funcs);
> 
> struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
>         .get_modes = analogix_dp_get_modes,
>         .best_encoder = analogix_dp_best_encoder,
> };
> EXPORT_SYMBOL(analogix_dp_connector_helper_funcs);
> ...
> 
> -- exynos_dp
> ----------------------------------------------------------------------------
>         ret = drm_connector_init(dp->drm_dev, connector,
> &analogix_dp_connector_atomic_funcs,
>                                  DRM_MODE_CONNECTOR_eDP);
>         if (ret) {
>                 DRM_ERROR("Failed to initialize connector with drm\n");
>                 return ret;
>         }
> 
>         drm_connector_helper_add(connector,
> &analogix_dp_connector_helper_funcs);
>         drm_connector_register(connector);
>         drm_mode_connector_attach_encoder(connector, encoder);
> 
> -- analogix_dp-rockchip
> ----------------------------------------------------------------------------
>         ret = drm_connector_init(dp->drm_dev, connector,
>                                  &analogix_dp_connector_funcs,
>                                  DRM_MODE_CONNECTOR_eDP);
>         if (ret) {
>                 DRM_ERROR("Failed to initialize connector with drm\n");
>                 return ret;
>         }
> 
>         drm_connector_helper_add(connector,
> &analogix_dp_connector_helper_funcs);
>         drm_mode_connector_attach_encoder(connector, encoder);
> 
> 
> Are those code corresponding to your suggestion.   :)

Yes, that looks about right. You could also move the implementations
into the Exynos and Rockchip drivers, respectively, if they're only used
from one place. Then you can simply export the low-level analogix_dp_*()
functions. That might give you even more flexibility, but the above
would probably work well enough.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver
@ 2015-09-21 11:22             ` Thierry Reding
  0 siblings, 0 replies; 370+ messages in thread
From: Thierry Reding @ 2015-09-21 11:22 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Heiko Stuebner, Krzysztof Kozlowski, s.infradead.org,
	David Airlie, dri-devel, Andrzej Hajda, Gustavo Padovan, architt,
	linux-samsung-soc, seanpaul, djkurtz, Kishon Vijay Abraham I,
	linux-rockchip, Kukjin Kim, robherring2, Russell King,
	linux-arm-kernel, devicetree, Pawel Moll, Ian Campbell, Inki Dae,
	joe, Rob Herring, dianders, Mark Yao, Jingoo Han

[-- Attachment #1: Type: text/plain, Size: 7521 bytes --]

On Mon, Sep 21, 2015 at 06:27:40PM +0800, Yakir Yang wrote:
> Hi Thierry,
> 
> Thanks for your suggest :)
> 
> On 09/21/2015 05:15 PM, Thierry Reding wrote:
> >On Mon, Sep 21, 2015 at 04:45:44PM +0800, Yakir Yang wrote:
> >>Hi Heiko,
> >>
> >>On 09/02/2015 10:15 AM, Yakir Yang wrote:
> >>>Hi Heiko,
> >>>
> >>>在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
> >>>>Hi Yakir,
> >>>>
> >>>>Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
> >>>>>    The Samsung Exynos eDP controller and Rockchip RK3288 eDP
> >>>>>controller
> >>>>>share the same IP, so a lot of parts can be re-used. I split the common
> >>>>>code into bridge directory, then rk3288 and exynos only need to keep
> >>>>>some platform code. Cause I can't find the exact IP name of exynos dp
> >>>>>controller, so I decide to name dp core driver with "analogix" which I
> >>>>>find in rk3288 eDP TRM ;)
> >>>>>
> >>>>>Beyond that, there are three light registers setting differents bewteen
> >>>>>exynos and rk3288.
> >>>>>1. RK3288 have five special pll resigters which not indicata in exynos
> >>>>>    dp controller.
> >>>>>2. The address of DP_PHY_PD(dp phy power manager register) are
> >>>>>different
> >>>>>    between rk3288 and exynos.
> >>>>>3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp
> >>>>>debug
> >>>>>    register).
> >>>>>
> >>>>>I have verified this series on two kinds of rockchip platform board,
> >>>>>one
> >>>>>is rk3288 sdk board which connect with a 2K display port monitor, the
> >>>>>other
> >>>>>is google jerry chromebook which connect with a eDP screen
> >>>>>"cnm,n116bgeea2",
> >>>>>both of them works rightlly.
> >>>>it looks like during the rebase something did go wrong and I found some
> >>>>issues
> >>>>I mentioned in the replies to individual patches.
> >>>>
> >>>>I did prepare a branch based on mainline [0] with both the old and the
> >>>>new edp
> >>>>driver - rk3288_veyron_defconfig build both drivers into the image.
> >>>>
> >>>>While the old driver still works, I wasn't able to make the new one work
> >>>>yet
> >>>>... the drm core does find the connector, but not that anything is
> >>>>connected
> >>>>to it. I'll try to dig deeper tomorrow, but maybe you'll see anything
> >>>>interesting before then.
> >>>Many thanks for your comment and debug, I would rebase on your
> >>>"edp-with-veyron" branch and fix the broken, make sure v6 would
> >>>work rightly at least in your side and my side.
> >>Just like we talk off line, I guess there are two tricky questions which
> >>make analogix_dp just crash/failed on rockchip platform:
> >>
> >>-  One is how to reach a agreement with the common way to register
> >>connector. There would be a conflict with Exynos & IMX & Rockchip.
> >>      On analogix_dp thread, Exynos want to register connector when that
> >>connector is ready.
> >>      On dw_hdmi thread, IMX want to register connector when all component is
> >>already.
> >>      So Exynos & IMX & Rockchip should reach a common way to register
> >>connector to fix this issue.
> >>
> >>-  The other is atomic API.
> >>       The rockchip drm haven't implemented the atomic API, but the original
> >>exynos_dp have used the atomic API on connector helper function. That's why
> >>analogix_dp just keep crash on your side.
> >There's really no reason not to convert Rockchip to atomic. It will have
> >to happen eventually anyway.
> 
> Do agree on this point, and I see Tomasz Figa have done some WIP
> works on implementing the atomic_commit, maybe would upstream
> in further.(https://chromium-review.googlesource.com/#/c/284560/1)
> 
> 
> >That said, there's another option that would allow you to side-step both
> >of the above problems at the same time. If you turn the common code into
> >a helper library that should give you enough flexibility to integrate it
> >into all existing users. For example you could leave out the connector
> >registration and let the drivers do that. Similarly since the helpers
> >are only hooked up at registration time you could probably find a way to
> >share the low-level code but again leave it up to the drivers to glue it
> >all together at registration time (drivers could wrap the low-level code
> >with atomic or non-atomic callbacks).
> 
> Wow, sounds good, but I'm not sure I understand this rightly. Do you
> mean that I could support two kinds of callbacks in analogix_dp_core
> driver, and export them out. And move the connector registration code
> into the helper driver (like exynos_dp.c), so helper driver could chose to
> use the atomic or non-atomic callbacks. like:
> 
> -- analogix_dp_core.c
> --------------------------------------------------------------------
> ...
> struct drm_connector_funcs analogix_dp_connector_atomic_funcs = {
>         .dpms = drm_atomic_helper_connector_dpms,
>         .fill_modes = drm_helper_probe_single_connector_modes,
>         .detect = analogix_dp_detect,
>         .destroy = analogix_dp_connector_destroy,
>         .reset = drm_atomic_helper_connector_reset,
>         .atomic_duplicate_state =
> drm_atomic_helper_connector_duplicate_state,
>         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> };
> EXPORT_SYMBOL(analogix_dp_connector_atomic_funcs);
> 
> struct drm_connector_funcs analogix_dp_connector_funcs = {
>         .dpms = drm_helper_connector_dpms,
>         .fill_modes = drm_helper_probe_single_connector_modes,
>         .detect = analogix_dp_detect,
>         .destroy = analogix_dp_connector_destroy,
> };
> EXPORT_SYMBOL(analogix_dp_connector_funcs);
> 
> struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
>         .get_modes = analogix_dp_get_modes,
>         .best_encoder = analogix_dp_best_encoder,
> };
> EXPORT_SYMBOL(analogix_dp_connector_helper_funcs);
> ...
> 
> -- exynos_dp
> ----------------------------------------------------------------------------
>         ret = drm_connector_init(dp->drm_dev, connector,
> &analogix_dp_connector_atomic_funcs,
>                                  DRM_MODE_CONNECTOR_eDP);
>         if (ret) {
>                 DRM_ERROR("Failed to initialize connector with drm\n");
>                 return ret;
>         }
> 
>         drm_connector_helper_add(connector,
> &analogix_dp_connector_helper_funcs);
>         drm_connector_register(connector);
>         drm_mode_connector_attach_encoder(connector, encoder);
> 
> -- analogix_dp-rockchip
> ----------------------------------------------------------------------------
>         ret = drm_connector_init(dp->drm_dev, connector,
>                                  &analogix_dp_connector_funcs,
>                                  DRM_MODE_CONNECTOR_eDP);
>         if (ret) {
>                 DRM_ERROR("Failed to initialize connector with drm\n");
>                 return ret;
>         }
> 
>         drm_connector_helper_add(connector,
> &analogix_dp_connector_helper_funcs);
>         drm_mode_connector_attach_encoder(connector, encoder);
> 
> 
> Are those code corresponding to your suggestion.   :)

Yes, that looks about right. You could also move the implementations
into the Exynos and Rockchip drivers, respectively, if they're only used
from one place. Then you can simply export the low-level analogix_dp_*()
functions. That might give you even more flexibility, but the above
would probably work well enough.

Thierry

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v4 0/16] Add Analogix Core Display Port Driver
  2015-09-21 11:22             ` Thierry Reding
  (?)
@ 2015-09-21 11:43             ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-21 11:43 UTC (permalink / raw)
  To: Thierry Reding
  Cc: Krzysztof Kozlowski, s.infradead.org, dri-devel, Andrzej Hajda,
	Gustavo Padovan, linux-samsung-soc, seanpaul, djkurtz,
	Kishon Vijay Abraham I, linux-rockchip, Kukjin Kim, robherring2,
	Russell King, linux-arm-kernel, devicetree, Pawel Moll,
	Ian Campbell, ajaynumb, Rob Herring, dianders, Jingoo Han,
	linux-kernel, Kyungmin Park, Kumar Gala, joe, Andy Yan


[-- Attachment #1.1: Type: text/plain, Size: 7919 bytes --]

Hi Thierry,

On 09/21/2015 07:22 PM, Thierry Reding wrote:
> On Mon, Sep 21, 2015 at 06:27:40PM +0800, Yakir Yang wrote:
>> Hi Thierry,
>>
>> Thanks for your suggest :)
>>
>> On 09/21/2015 05:15 PM, Thierry Reding wrote:
>>> On Mon, Sep 21, 2015 at 04:45:44PM +0800, Yakir Yang wrote:
>>>> Hi Heiko,
>>>>
>>>> On 09/02/2015 10:15 AM, Yakir Yang wrote:
>>>>> Hi Heiko,
>>>>>
>>>>> 在 09/02/2015 05:47 AM, Heiko Stuebner 写道:
>>>>>> Hi Yakir,
>>>>>>
>>>>>> Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>>>>>>>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP
>>>>>>> controller
>>>>>>> share the same IP, so a lot of parts can be re-used. I split the common
>>>>>>> code into bridge directory, then rk3288 and exynos only need to keep
>>>>>>> some platform code. Cause I can't find the exact IP name of exynos dp
>>>>>>> controller, so I decide to name dp core driver with "analogix" which I
>>>>>>> find in rk3288 eDP TRM ;)
>>>>>>>
>>>>>>> Beyond that, there are three light registers setting differents bewteen
>>>>>>> exynos and rk3288.
>>>>>>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>>>>>>     dp controller.
>>>>>>> 2. The address of DP_PHY_PD(dp phy power manager register) are
>>>>>>> different
>>>>>>>     between rk3288 and exynos.
>>>>>>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp
>>>>>>> debug
>>>>>>>     register).
>>>>>>>
>>>>>>> I have verified this series on two kinds of rockchip platform board,
>>>>>>> one
>>>>>>> is rk3288 sdk board which connect with a 2K display port monitor, the
>>>>>>> other
>>>>>>> is google jerry chromebook which connect with a eDP screen
>>>>>>> "cnm,n116bgeea2",
>>>>>>> both of them works rightlly.
>>>>>> it looks like during the rebase something did go wrong and I found some
>>>>>> issues
>>>>>> I mentioned in the replies to individual patches.
>>>>>>
>>>>>> I did prepare a branch based on mainline [0] with both the old and the
>>>>>> new edp
>>>>>> driver - rk3288_veyron_defconfig build both drivers into the image.
>>>>>>
>>>>>> While the old driver still works, I wasn't able to make the new one work
>>>>>> yet
>>>>>> ... the drm core does find the connector, but not that anything is
>>>>>> connected
>>>>>> to it. I'll try to dig deeper tomorrow, but maybe you'll see anything
>>>>>> interesting before then.
>>>>> Many thanks for your comment and debug, I would rebase on your
>>>>> "edp-with-veyron" branch and fix the broken, make sure v6 would
>>>>> work rightly at least in your side and my side.
>>>> Just like we talk off line, I guess there are two tricky questions which
>>>> make analogix_dp just crash/failed on rockchip platform:
>>>>
>>>> -  One is how to reach a agreement with the common way to register
>>>> connector. There would be a conflict with Exynos & IMX & Rockchip.
>>>>       On analogix_dp thread, Exynos want to register connector when that
>>>> connector is ready.
>>>>       On dw_hdmi thread, IMX want to register connector when all component is
>>>> already.
>>>>       So Exynos & IMX & Rockchip should reach a common way to register
>>>> connector to fix this issue.
>>>>
>>>> -  The other is atomic API.
>>>>        The rockchip drm haven't implemented the atomic API, but the original
>>>> exynos_dp have used the atomic API on connector helper function. That's why
>>>> analogix_dp just keep crash on your side.
>>> There's really no reason not to convert Rockchip to atomic. It will have
>>> to happen eventually anyway.
>> Do agree on this point, and I see Tomasz Figa have done some WIP
>> works on implementing the atomic_commit, maybe would upstream
>> in further.(https://chromium-review.googlesource.com/#/c/284560/1)
>>
>>
>>> That said, there's another option that would allow you to side-step both
>>> of the above problems at the same time. If you turn the common code into
>>> a helper library that should give you enough flexibility to integrate it
>>> into all existing users. For example you could leave out the connector
>>> registration and let the drivers do that. Similarly since the helpers
>>> are only hooked up at registration time you could probably find a way to
>>> share the low-level code but again leave it up to the drivers to glue it
>>> all together at registration time (drivers could wrap the low-level code
>>> with atomic or non-atomic callbacks).
>> Wow, sounds good, but I'm not sure I understand this rightly. Do you
>> mean that I could support two kinds of callbacks in analogix_dp_core
>> driver, and export them out. And move the connector registration code
>> into the helper driver (like exynos_dp.c), so helper driver could chose to
>> use the atomic or non-atomic callbacks. like:
>>
>> -- analogix_dp_core.c
>> --------------------------------------------------------------------
>> ...
>> struct drm_connector_funcs analogix_dp_connector_atomic_funcs = {
>>          .dpms = drm_atomic_helper_connector_dpms,
>>          .fill_modes = drm_helper_probe_single_connector_modes,
>>          .detect = analogix_dp_detect,
>>          .destroy = analogix_dp_connector_destroy,
>>          .reset = drm_atomic_helper_connector_reset,
>>          .atomic_duplicate_state =
>> drm_atomic_helper_connector_duplicate_state,
>>          .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>> };
>> EXPORT_SYMBOL(analogix_dp_connector_atomic_funcs);
>>
>> struct drm_connector_funcs analogix_dp_connector_funcs = {
>>          .dpms = drm_helper_connector_dpms,
>>          .fill_modes = drm_helper_probe_single_connector_modes,
>>          .detect = analogix_dp_detect,
>>          .destroy = analogix_dp_connector_destroy,
>> };
>> EXPORT_SYMBOL(analogix_dp_connector_funcs);
>>
>> struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
>>          .get_modes = analogix_dp_get_modes,
>>          .best_encoder = analogix_dp_best_encoder,
>> };
>> EXPORT_SYMBOL(analogix_dp_connector_helper_funcs);
>> ...
>>
>> -- exynos_dp
>> ----------------------------------------------------------------------------
>>          ret = drm_connector_init(dp->drm_dev, connector,
>> &analogix_dp_connector_atomic_funcs,
>>                                   DRM_MODE_CONNECTOR_eDP);
>>          if (ret) {
>>                  DRM_ERROR("Failed to initialize connector with drm\n");
>>                  return ret;
>>          }
>>
>>          drm_connector_helper_add(connector,
>> &analogix_dp_connector_helper_funcs);
>>          drm_connector_register(connector);
>>          drm_mode_connector_attach_encoder(connector, encoder);
>>
>> -- analogix_dp-rockchip
>> ----------------------------------------------------------------------------
>>          ret = drm_connector_init(dp->drm_dev, connector,
>>                                   &analogix_dp_connector_funcs,
>>                                   DRM_MODE_CONNECTOR_eDP);
>>          if (ret) {
>>                  DRM_ERROR("Failed to initialize connector with drm\n");
>>                  return ret;
>>          }
>>
>>          drm_connector_helper_add(connector,
>> &analogix_dp_connector_helper_funcs);
>>          drm_mode_connector_attach_encoder(connector, encoder);
>>
>>
>> Are those code corresponding to your suggestion.   :)
> Yes, that looks about right. You could also move the implementations
> into the Exynos and Rockchip drivers, respectively, if they're only used
> from one place. Then you can simply export the low-level analogix_dp_*()
> functions. That might give you even more flexibility, but the above
> would probably work well enough.

Wow, much better, so I just need to export two low-level functions,

  * analogix_dp_detect()
  * analogix_dp_get_modes()

Pretty cool.

Thanks,
- Yakir

> Thierry


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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 0/17] Add Analogix Core Display Port Driver
  2015-09-01  5:46 ` Yakir Yang
@ 2015-09-22  7:20   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:20 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi all,

   The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
controller, so I decide to name dp core driver with "analogix" which I
find in rk3288 eDP TRM :)

This time I create this version on linux-next branch (tag is next-20150918),
and also applied this version to Heiko github eDP branch to verify the function.
(https://github.com/mmind/linux-rockchip/tree/tmp/edp-with-veyron)
Glad to say my chromebook "cnm,n116bgeea2" eDP panel just lighted rightly on
Heiko branch. And after back port this series to chromeos-3.14 tree, my rk3288
SDK board still can light my 2K DisplayPort monitor. So this time would be okay
on mainline kernel and chromeos-3.14 tree. ;)

Due to no Exynos board in my side, so I haven't verified the eDP function on
samsung platform, I only ensure that there are no obvious compiled error. Any
help would be greatly appreciated. :)

Thanks,
- Yakir

Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
  the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
  attch function. Cause once platform failed at attach, core driver should
  still failed, so no need to init connector before platform attached (Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
  patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)
- Resequence this patch after analogix_dp driver have been split
  from exynos_dp code, and rephrase reasonable commit message, and
  remove some controversial style (Krzysztof)
    -		analogix_dp_write_byte_to_dpcd(
    - 				dp, DP_TEST_RESPONSE,
    +		analogix_dp_write_byte_to_dpcd(dp,
    +				DP_TEST_RESPONSE,
				DP_TEST_EDID_CHECKSUM_WRITE);
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).
- Correct the misspell in commit message. (Krzysztof)
- Remove the empty line at the end of document, and correct the endpoint
  numbers in the example DT node, and remove the regulator iomux setting
  in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
  support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
  the exist "grf" syscon already. And rename the example DT node from
  "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
  struct" to "static const struct". And correct the input paramters of
  devm_phy_create() interfaces. (Heiko)
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
  elemets in document. (Rob & Heiko)
- Fix compiled error (Heiko)
- Using the connector display info message to configure eDP driver input
  video mode, but hard code CRTC video output mode to RGBaaa.

Changes in v4:
- Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
- Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
- Create a separate folder for analogix code in bridge/ (Archit)
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
- Provide backword compatibility with samsung. (Krzysztof)
- Split all DTS changes, and provide backward compatibility. Mark old
  properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"
- Separate all DTS changes to a separate patch. (Krzysztof)
- Remove some deprecated DT properties in rockchip dp document.
- Add commit message, and remove the redundant rockchip_dp_phy_init()
  function, move those code to probe() method. And remove driver .owner
  number. (Kishon)
- Seprate the link-rate and lane-count limit out with the device_type
  flag. (Thierry)
- Take Jingoo suggest, add commit messages.
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Move exynos's video_timing code to analogix_dp-exynos platform driver,
  add get_modes method to struct analogix_dp_plat_data. (Thierry)
- Rename some "samsung*" dts propery to "analogix*". (Heiko)
- The link_rate and lane_count shouldn't config to the DT property value
  directly, but we can take those as hardware limite. For example, RK3288
  only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
  like "link-rate = 0x0a" "lane-count = 4". (Thierry)
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
  devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
  and leave "sclk_edp" to analogix dp core driver which name to "dp",
  and leave "pclk_edp" to rockchip dp platform driver which name to
  "pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
  node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.
- Suggest, add rockchip dp phy driver, collect the phy clocks and
  power control. (Heiko)
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.
- move dp hpd detect to connector detect function.
- Add edid modes parse support

Changes in v2:
- Keep author name list no changed (Jingoo)
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
  uncommon style like bellow: (Joe Preches)
    -  retval = exynos_dp_read_bytes_from_i2c(...
  				  ...);
    +  retval =
    +  exynos_dp_read_bytes_from_i2c(......);
- Get panel node with remote-endpoint method, and create devicetree binding
  for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.
- Fix compile failed dut to phy_pd_addr variable misspell error

Mark Yao (1):
  drm: rockchip: vop: add bpc and color mode setting

Yakir Yang (16):
  drm: exynos: dp: convert to drm bridge mode
  drm: bridge: analogix/dp: split exynos dp driver to bridge directory
  drm: bridge: analogix/dp: fix some obvious code style
  drm: bridge: analogix/dp: remove duplicate configuration of link rate
    and link count
  drm: bridge: analogix/dp: dynamic parse sync_pol & interlace &
    dynamic_range
  Documentation: drm/bridge: add document for analogix_dp
  ARM: dts: exynos/dp: remove some properties that deprecated by
    analogix_dp driver
  drm: rockchip: dp: add rockchip platform dp driver
  Documentation: drm/bridge: add document for analogix_dp
  phy: Add driver for rockchip Display Port PHY
  Documentation: phy: add document for rockchip dp phy
  drm: bridge: analogix/dp: add some rk3288 special registers setting
  drm: bridge: analogix/dp: add max link rate and lane count limit for
    RK3288
  drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  drm: bridge: analogix/dp: move hpd detect to connector detect function
  drm: bridge: analogix/dp: add edid modes parse in get_modes method

 .../devicetree/bindings/drm/bridge/analogix_dp.txt |   52 +
 .../devicetree/bindings/phy/rockchip-dp-phy.txt    |   22 +
 .../bindings/video/analogix_dp-rockchip.txt        |   91 ++
 .../devicetree/bindings/video/exynos_dp.txt        |   64 +-
 arch/arm/boot/dts/exynos5250-arndale.dts           |    2 -
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 -
 arch/arm/boot/dts/exynos5250-snow.dts              |    4 +-
 arch/arm/boot/dts/exynos5250-spring.dts            |    4 +-
 arch/arm/boot/dts/exynos5420-peach-pit.dts         |    4 +-
 arch/arm/boot/dts/exynos5420-smdk5420.dts          |    2 -
 arch/arm/boot/dts/exynos5800-peach-pi.dts          |    4 +-
 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1372 +++++++++++++++++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  286 ++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1294 ++++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  270 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  366 +++++
 drivers/gpu/drm/exynos/exynos_dp_core.c            | 1427 --------------------
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  281 ----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 -----------------
 drivers/gpu/drm/rockchip/Kconfig                   |    9 +
 drivers/gpu/drm/rockchip/Makefile                  |    1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    |  457 +++++++
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c        |    2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h        |    2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c        |   32 +-
 drivers/phy/Kconfig                                |    7 +
 drivers/phy/Makefile                               |    1 +
 drivers/phy/phy-rockchip-dp.c                      |  151 +++
 include/drm/bridge/analogix_dp.h                   |   42 +
 35 files changed, 4360 insertions(+), 3167 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (62%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 create mode 100644 drivers/phy/phy-rockchip-dp.c
 create mode 100644 include/drm/bridge/analogix_dp.h

-- 
1.9.1



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-09-22  7:20   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:20 UTC (permalink / raw)
  To: linux-arm-kernel

Hi all,

   The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
controller, so I decide to name dp core driver with "analogix" which I
find in rk3288 eDP TRM :)

This time I create this version on linux-next branch (tag is next-20150918),
and also applied this version to Heiko github eDP branch to verify the function.
(https://github.com/mmind/linux-rockchip/tree/tmp/edp-with-veyron)
Glad to say my chromebook "cnm,n116bgeea2" eDP panel just lighted rightly on
Heiko branch. And after back port this series to chromeos-3.14 tree, my rk3288
SDK board still can light my 2K DisplayPort monitor. So this time would be okay
on mainline kernel and chromeos-3.14 tree. ;)

Due to no Exynos board in my side, so I haven't verified the eDP function on
samsung platform, I only ensure that there are no obvious compiled error. Any
help would be greatly appreciated. :)

Thanks,
- Yakir

Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
  the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
  attch function. Cause once platform failed at attach, core driver should
  still failed, so no need to init connector before platform attached (Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
  patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)
- Resequence this patch after analogix_dp driver have been split
  from exynos_dp code, and rephrase reasonable commit message, and
  remove some controversial style (Krzysztof)
    -		analogix_dp_write_byte_to_dpcd(
    - 				dp, DP_TEST_RESPONSE,
    +		analogix_dp_write_byte_to_dpcd(dp,
    +				DP_TEST_RESPONSE,
				DP_TEST_EDID_CHECKSUM_WRITE);
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).
- Correct the misspell in commit message. (Krzysztof)
- Remove the empty line at the end of document, and correct the endpoint
  numbers in the example DT node, and remove the regulator iomux setting
  in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
  support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
  the exist "grf" syscon already. And rename the example DT node from
  "edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
  struct" to "static const struct". And correct the input paramters of
  devm_phy_create() interfaces. (Heiko)
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
  elemets in document. (Rob & Heiko)
- Fix compiled error (Heiko)
- Using the connector display info message to configure eDP driver input
  video mode, but hard code CRTC video output mode to RGBaaa.

Changes in v4:
- Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
- Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
- Create a separate folder for analogix code in bridge/ (Archit)
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
- Provide backword compatibility with samsung. (Krzysztof)
- Split all DTS changes, and provide backward compatibility. Mark old
  properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"
- Separate all DTS changes to a separate patch. (Krzysztof)
- Remove some deprecated DT properties in rockchip dp document.
- Add commit message, and remove the redundant rockchip_dp_phy_init()
  function, move those code to probe() method. And remove driver .owner
  number. (Kishon)
- Seprate the link-rate and lane-count limit out with the device_type
  flag. (Thierry)
- Take Jingoo suggest, add commit messages.
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Move exynos's video_timing code to analogix_dp-exynos platform driver,
  add get_modes method to struct analogix_dp_plat_data. (Thierry)
- Rename some "samsung*" dts propery to "analogix*". (Heiko)
- The link_rate and lane_count shouldn't config to the DT property value
  directly, but we can take those as hardware limite. For example, RK3288
  only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
  like "link-rate = 0x0a" "lane-count = 4". (Thierry)
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
  devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
  and leave "sclk_edp" to analogix dp core driver which name to "dp",
  and leave "pclk_edp" to rockchip dp platform driver which name to
  "pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
  node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.
- Suggest, add rockchip dp phy driver, collect the phy clocks and
  power control. (Heiko)
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.
- move dp hpd detect to connector detect function.
- Add edid modes parse support

Changes in v2:
- Keep author name list no changed (Jingoo)
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
  uncommon style like bellow: (Joe Preches)
    -  retval = exynos_dp_read_bytes_from_i2c(...
  				  ...);
    +  retval =
    +  exynos_dp_read_bytes_from_i2c(......);
- Get panel node with remote-endpoint method, and create devicetree binding
  for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.
- Fix compile failed dut to phy_pd_addr variable misspell error

Mark Yao (1):
  drm: rockchip: vop: add bpc and color mode setting

Yakir Yang (16):
  drm: exynos: dp: convert to drm bridge mode
  drm: bridge: analogix/dp: split exynos dp driver to bridge directory
  drm: bridge: analogix/dp: fix some obvious code style
  drm: bridge: analogix/dp: remove duplicate configuration of link rate
    and link count
  drm: bridge: analogix/dp: dynamic parse sync_pol & interlace &
    dynamic_range
  Documentation: drm/bridge: add document for analogix_dp
  ARM: dts: exynos/dp: remove some properties that deprecated by
    analogix_dp driver
  drm: rockchip: dp: add rockchip platform dp driver
  Documentation: drm/bridge: add document for analogix_dp
  phy: Add driver for rockchip Display Port PHY
  Documentation: phy: add document for rockchip dp phy
  drm: bridge: analogix/dp: add some rk3288 special registers setting
  drm: bridge: analogix/dp: add max link rate and lane count limit for
    RK3288
  drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  drm: bridge: analogix/dp: move hpd detect to connector detect function
  drm: bridge: analogix/dp: add edid modes parse in get_modes method

 .../devicetree/bindings/drm/bridge/analogix_dp.txt |   52 +
 .../devicetree/bindings/phy/rockchip-dp-phy.txt    |   22 +
 .../bindings/video/analogix_dp-rockchip.txt        |   91 ++
 .../devicetree/bindings/video/exynos_dp.txt        |   64 +-
 arch/arm/boot/dts/exynos5250-arndale.dts           |    2 -
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 -
 arch/arm/boot/dts/exynos5250-snow.dts              |    4 +-
 arch/arm/boot/dts/exynos5250-spring.dts            |    4 +-
 arch/arm/boot/dts/exynos5420-peach-pit.dts         |    4 +-
 arch/arm/boot/dts/exynos5420-smdk5420.dts          |    2 -
 arch/arm/boot/dts/exynos5800-peach-pi.dts          |    4 +-
 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1372 +++++++++++++++++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  286 ++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1294 ++++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  270 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  366 +++++
 drivers/gpu/drm/exynos/exynos_dp_core.c            | 1427 --------------------
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  281 ----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 -----------------
 drivers/gpu/drm/rockchip/Kconfig                   |    9 +
 drivers/gpu/drm/rockchip/Makefile                  |    1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    |  457 +++++++
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c        |    2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h        |    2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c        |   32 +-
 drivers/phy/Kconfig                                |    7 +
 drivers/phy/Makefile                               |    1 +
 drivers/phy/phy-rockchip-dp.c                      |  151 +++
 include/drm/bridge/analogix_dp.h                   |   42 +
 35 files changed, 4360 insertions(+), 3167 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (62%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 create mode 100644 drivers/phy/phy-rockchip-dp.c
 create mode 100644 include/drm/bridge/analogix_dp.h

-- 
1.9.1

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 01/17] drm: exynos: dp: convert to drm bridge mode
  2015-09-22  7:20   ` Yakir Yang
@ 2015-09-22  7:26     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:26 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Keep author name list no changed (Jingoo)

 drivers/gpu/drm/exynos/exynos_dp_core.c | 104 +++++++++++++++++++++++---------
 drivers/gpu/drm/exynos/exynos_dp_core.h |   1 +
 2 files changed, 78 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index d66ade0..e0818c1 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -1009,9 +1009,9 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
 {
 	int ret;
 
-	encoder->bridge = dp->bridge;
-	dp->bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->bridge);
+	encoder->bridge->next = dp->ptn_bridge;
+	dp->ptn_bridge->encoder = encoder;
+	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
 	if (ret) {
 		DRM_ERROR("Failed to attach bridge to drm\n");
 		return ret;
@@ -1020,14 +1020,15 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
 	return 0;
 }
 
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = &dp->encoder;
 	struct drm_connector *connector = &dp->connector;
 	int ret;
 
 	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->bridge) {
+	if (dp->ptn_bridge) {
 		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
 		if (!ret)
 			return 0;
@@ -1052,22 +1053,9 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	return ret;
 }
 
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
-				 const struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
 	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
 
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
@@ -1092,9 +1080,9 @@ static void exynos_dp_enable(struct drm_encoder *encoder)
 	dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
-static void exynos_dp_disable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
 	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
 
 	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
@@ -1123,6 +1111,68 @@ static void exynos_dp_disable(struct drm_encoder *encoder)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+{
+	/* do nothing */
+}
+
+static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
+	.enable = exynos_dp_bridge_enable,
+	.disable = exynos_dp_bridge_disable,
+	.pre_enable = exynos_dp_bridge_nop,
+	.post_disable = exynos_dp_bridge_nop,
+	.attach = exynos_dp_bridge_attach,
+};
+
+static int exynos_dp_create_connector(struct drm_encoder *encoder)
+{
+	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct drm_bridge *bridge;
+	int ret;
+
+	bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
+	if (!bridge) {
+		DRM_ERROR("failed to allocate for drm bridge\n");
+		return -ENOMEM;
+	}
+
+	dp->bridge = bridge;
+
+	bridge->driver_private = dp;
+	bridge->encoder = encoder;
+	bridge->funcs = &exynos_dp_bridge_funcs;
+
+	ret = drm_bridge_attach(drm_dev, bridge);
+	if (ret) {
+		DRM_ERROR("failed to attach drm bridge\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+				 const struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
 static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
 	.mode_fixup = exynos_dp_mode_fixup,
 	.mode_set = exynos_dp_mode_set,
@@ -1365,9 +1415,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	if (endpoint) {
 		bridge_node = of_graph_get_remote_port_parent(endpoint);
 		if (bridge_node) {
-			dp->bridge = of_drm_find_bridge(bridge_node);
+			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
 			of_node_put(bridge_node);
-			if (!dp->bridge)
+			if (!dp->ptn_bridge)
 				return -EPROBE_DEFER;
 		} else
 			return -EPROBE_DEFER;
@@ -1388,7 +1438,7 @@ static int exynos_dp_suspend(struct device *dev)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_disable(&dp->encoder);
+	exynos_dp_bridge_disable(dp->bridge);
 	return 0;
 }
 
@@ -1396,7 +1446,7 @@ static int exynos_dp_resume(struct device *dev)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_enable(&dp->encoder);
+	exynos_dp_bridge_enable(dp->bridge);
 	return 0;
 }
 #endif
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
index e413b6f..66eec4b 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
@@ -153,6 +153,7 @@ struct exynos_dp_device {
 	struct drm_connector	connector;
 	struct drm_panel	*panel;
 	struct drm_bridge	*bridge;
+	struct drm_bridge	*ptn_bridge;
 	struct clk		*clock;
 	unsigned int		irq;
 	void __iomem		*reg_base;
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 01/17] drm: exynos: dp: convert to drm bridge mode
@ 2015-09-22  7:26     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:26 UTC (permalink / raw)
  To: linux-arm-kernel

In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Keep author name list no changed (Jingoo)

 drivers/gpu/drm/exynos/exynos_dp_core.c | 104 +++++++++++++++++++++++---------
 drivers/gpu/drm/exynos/exynos_dp_core.h |   1 +
 2 files changed, 78 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index d66ade0..e0818c1 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -1009,9 +1009,9 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
 {
 	int ret;
 
-	encoder->bridge = dp->bridge;
-	dp->bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->bridge);
+	encoder->bridge->next = dp->ptn_bridge;
+	dp->ptn_bridge->encoder = encoder;
+	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
 	if (ret) {
 		DRM_ERROR("Failed to attach bridge to drm\n");
 		return ret;
@@ -1020,14 +1020,15 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
 	return 0;
 }
 
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = &dp->encoder;
 	struct drm_connector *connector = &dp->connector;
 	int ret;
 
 	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->bridge) {
+	if (dp->ptn_bridge) {
 		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
 		if (!ret)
 			return 0;
@@ -1052,22 +1053,9 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	return ret;
 }
 
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
-				 const struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
 	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
 
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
@@ -1092,9 +1080,9 @@ static void exynos_dp_enable(struct drm_encoder *encoder)
 	dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
-static void exynos_dp_disable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
 	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
 
 	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
@@ -1123,6 +1111,68 @@ static void exynos_dp_disable(struct drm_encoder *encoder)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+{
+	/* do nothing */
+}
+
+static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
+	.enable = exynos_dp_bridge_enable,
+	.disable = exynos_dp_bridge_disable,
+	.pre_enable = exynos_dp_bridge_nop,
+	.post_disable = exynos_dp_bridge_nop,
+	.attach = exynos_dp_bridge_attach,
+};
+
+static int exynos_dp_create_connector(struct drm_encoder *encoder)
+{
+	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct drm_bridge *bridge;
+	int ret;
+
+	bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
+	if (!bridge) {
+		DRM_ERROR("failed to allocate for drm bridge\n");
+		return -ENOMEM;
+	}
+
+	dp->bridge = bridge;
+
+	bridge->driver_private = dp;
+	bridge->encoder = encoder;
+	bridge->funcs = &exynos_dp_bridge_funcs;
+
+	ret = drm_bridge_attach(drm_dev, bridge);
+	if (ret) {
+		DRM_ERROR("failed to attach drm bridge\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+				 const struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
 static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
 	.mode_fixup = exynos_dp_mode_fixup,
 	.mode_set = exynos_dp_mode_set,
@@ -1365,9 +1415,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	if (endpoint) {
 		bridge_node = of_graph_get_remote_port_parent(endpoint);
 		if (bridge_node) {
-			dp->bridge = of_drm_find_bridge(bridge_node);
+			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
 			of_node_put(bridge_node);
-			if (!dp->bridge)
+			if (!dp->ptn_bridge)
 				return -EPROBE_DEFER;
 		} else
 			return -EPROBE_DEFER;
@@ -1388,7 +1438,7 @@ static int exynos_dp_suspend(struct device *dev)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_disable(&dp->encoder);
+	exynos_dp_bridge_disable(dp->bridge);
 	return 0;
 }
 
@@ -1396,7 +1446,7 @@ static int exynos_dp_resume(struct device *dev)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_enable(&dp->encoder);
+	exynos_dp_bridge_enable(dp->bridge);
 	return 0;
 }
 #endif
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
index e413b6f..66eec4b 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
@@ -153,6 +153,7 @@ struct exynos_dp_device {
 	struct drm_connector	connector;
 	struct drm_panel	*panel;
 	struct drm_bridge	*bridge;
+	struct drm_bridge	*ptn_bridge;
 	struct clk		*clock;
 	unsigned int		irq;
 	void __iomem		*reg_base;
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
@ 2015-09-22  7:29     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:29 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.

Beside the new analogix_dp driver would export four hooks.
"analogix_dp_bind()" and "analogix_dp_unbind()"
"analogix_dp_detect()" and "analogix_dp_get_modes()"

The bind/unbind symbols is used for analogix platform driver to connect
with analogix_dp core driver. And the detect/get_modes is used for analogix
platform driver to init the connector.

They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
  the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
  attch function. Cause once platform failed at attach, core driver should
  still failed, so no need to init connector before platform attached (Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
  patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)

Changes in v4:
- Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
- Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
- Create a separate folder for analogix code in bridge/ (Archit)

Changes in v3:
- Move exynos's video_timing code to analogix_dp-exynos platform driver,
  add get_modes method to struct analogix_dp_plat_data. (Thierry)
- Rename some "samsung*" dts propery to "analogix*". (Heiko)

Changes in v2:
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell

 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 .../analogix/analogix_dp_core.c}                   |  768 +++++-------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  277 +++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1263 ++++++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  258 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  366 ++++++
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 -----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 --------------------
 include/drm/bridge/analogix_dp.h                   |   41 +
 14 files changed, 2379 insertions(+), 2152 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 rename drivers/gpu/drm/{exynos/exynos_dp_core.c => bridge/analogix/analogix_dp_core.c} (50%)
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (64%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 include/drm/bridge/analogix_dp.h

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 2de52a5..7b5b77a 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -29,4 +29,6 @@ config DRM_PARADE_PS8622
 	---help---
 	  Parade eDP-LVDS bridge chip driver.
 
+source "drivers/gpu/drm/bridge/analogix/Kconfig"
+
 endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index e2eef1c..5366c6b 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -3,3 +3,4 @@ ccflags-y := -Iinclude/drm
 obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
new file mode 100644
index 0000000..5ff6551
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -0,0 +1,4 @@
+config DRM_ANALOGIX_DP
+	tristate
+	depends on DRM
+	select DRM_KMS_HELPER
diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
new file mode 100644
index 0000000..9107b86
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
similarity index 50%
rename from drivers/gpu/drm/exynos/exynos_dp_core.c
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index e0818c1..8a7ba12 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1,14 +1,14 @@
 /*
- * Samsung SoC DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
+* Analogix DP (Display Port) core interface driver.
+*
+* Copyright (C) 2012 Samsung Electronics Co., Ltd.
+* Author: Jingoo Han <jg1.han@samsung.com>
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2 of the License, or (at your
+* option) any later version.
+*/
 
 #include <linux/module.h>
 #include <linux/platform_device.h>
@@ -18,65 +18,48 @@
 #include <linux/interrupt.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
-#include <linux/of_graph.h>
 #include <linux/gpio.h>
 #include <linux/component.h>
 #include <linux/phy/phy.h>
-#include <video/of_display_timing.h>
-#include <video/of_videomode.h>
 
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
-#include <drm/drm_atomic_helper.h>
 #include <drm/drm_panel.h>
 
-#include "exynos_dp_core.h"
-#include "exynos_drm_crtc.h"
+#include <drm/bridge/analogix_dp.h>
 
-#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
-					connector)
-
-static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
-{
-	return to_exynos_crtc(dp->encoder.crtc);
-}
-
-static inline struct exynos_dp_device *encoder_to_dp(
-						struct drm_encoder *e)
-{
-	return container_of(e, struct exynos_dp_device, encoder);
-}
+#include "analogix_dp_core.h"
 
 struct bridge_init {
 	struct i2c_client *client;
 	struct device_node *node;
 };
 
-static void exynos_dp_init_dp(struct exynos_dp_device *dp)
+static void analogix_dp_init_dp(struct analogix_dp_device *dp)
 {
-	exynos_dp_reset(dp);
+	analogix_dp_reset(dp);
 
-	exynos_dp_swreset(dp);
+	analogix_dp_swreset(dp);
 
-	exynos_dp_init_analog_param(dp);
-	exynos_dp_init_interrupt(dp);
+	analogix_dp_init_analog_param(dp);
+	analogix_dp_init_interrupt(dp);
 
 	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_function(dp);
+	analogix_dp_enable_sw_function(dp);
 
-	exynos_dp_config_interrupt(dp);
-	exynos_dp_init_analog_func(dp);
+	analogix_dp_config_interrupt(dp);
+	analogix_dp_init_analog_func(dp);
 
-	exynos_dp_init_hpd(dp);
-	exynos_dp_init_aux(dp);
+	analogix_dp_init_hpd(dp);
+	analogix_dp_init_aux(dp);
 }
 
-static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
+static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (exynos_dp_get_plug_in_status(dp) != 0) {
+	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
@@ -88,7 +71,7 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
 	return 0;
 }
 
-static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
+static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 {
 	int i;
 	unsigned char sum = 0;
@@ -99,7 +82,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
 	return sum;
 }
 
-static int exynos_dp_read_edid(struct exynos_dp_device *dp)
+static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
 	unsigned char edid[EDID_BLOCK_LENGTH * 2];
 	unsigned int extend_block = 0;
@@ -114,7 +97,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 	 */
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 				EDID_EXTENSION_FLAG,
 				&extend_block);
 	if (retval)
@@ -124,7 +107,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -132,14 +115,14 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
+		sum = analogix_dp_calc_edid_check_sum(edid);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
 				I2C_EDID_DEVICE_ADDR,
 				EDID_BLOCK_LENGTH,
 				EDID_BLOCK_LENGTH,
@@ -148,19 +131,19 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
+		sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
 					&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_RESPONSE,
 				DP_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -168,7 +151,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_info(dp->dev, "EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
 				I2C_EDID_DEVICE_ADDR,
 				EDID_HEADER_PATTERN,
 				EDID_BLOCK_LENGTH,
@@ -177,20 +160,20 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
+		sum = analogix_dp_calc_edid_check_sum(edid);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp,
+		analogix_dp_read_byte_from_dpcd(dp,
 			DP_TEST_REQUEST,
 			&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
 				edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_RESPONSE,
 				DP_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -200,21 +183,21 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 	return 0;
 }
 
-static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
+static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 {
 	u8 buf[12];
 	int i;
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
 				12, buf);
 	if (retval)
 		return retval;
 
 	/* Read EDID */
 	for (i = 0; i < 3; i++) {
-		retval = exynos_dp_read_edid(dp);
+		retval = analogix_dp_read_edid(dp);
 		if (!retval)
 			break;
 	}
@@ -222,73 +205,73 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
+static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
 						bool enable)
 {
 	u8 data;
 
-	exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
 
 	if (enable)
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 			DP_LANE_COUNT_ENHANCED_FRAME_EN |
 			DPCD_LANE_COUNT_SET(data));
 	else
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 			DPCD_LANE_COUNT_SET(data));
 }
 
-static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
+static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
 {
 	u8 data;
 	int retval;
 
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 	retval = DPCD_ENHANCED_FRAME_CAP(data);
 
 	return retval;
 }
 
-static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
+static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 {
 	u8 data;
 
-	data = exynos_dp_is_enhanced_mode_available(dp);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, data);
-	exynos_dp_enable_enhanced_mode(dp, data);
+	data = analogix_dp_is_enhanced_mode_available(dp);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, data);
+	analogix_dp_enable_enhanced_mode(dp, data);
 }
 
-static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
+static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
-	exynos_dp_set_training_pattern(dp, DP_NONE);
+	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	exynos_dp_write_byte_to_dpcd(dp,
+	analogix_dp_write_byte_to_dpcd(dp,
 		DP_TRAINING_PATTERN_SET,
 		DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
+static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
 					int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
-		exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 		break;
 	case 1:
-		exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 		break;
 
 	case 2:
-		exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 		break;
 
 	case 3:
-		exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 		break;
 	}
 }
 
-static int exynos_dp_link_start(struct exynos_dp_device *dp)
+static int analogix_dp_link_start(struct analogix_dp_device *dp)
 {
 	u8 buf[4];
 	int lane, lane_count, pll_tries, retval;
@@ -302,25 +285,25 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		dp->link_train.cr_loop[lane] = 0;
 
 	/* Set link rate and count as you want to establish*/
-	exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
-	exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
+	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
 				2, buf);
 	if (retval)
 		return retval;
 
 	/* Set TX pre-emphasis to minimum */
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_lane_pre_emphasis(dp,
+		analogix_dp_set_lane_lane_pre_emphasis(dp,
 			PRE_EMPHASIS_LEVEL_0, lane);
 
 	/* Wait for PLL lock */
 	pll_tries = 0;
-	while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+	while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 		if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Wait for PLL lock timed out\n");
 			return -ETIMEDOUT;
@@ -331,10 +314,10 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 	}
 
 	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
+	analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 
 	/* Set RX training pattern */
-	retval = exynos_dp_write_byte_to_dpcd(dp,
+	retval = analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
 	if (retval)
@@ -344,13 +327,13 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 			lane_count, buf);
 
 	return retval;
 }
 
-static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
+static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
 	u8 link_value = link_status[lane>>1];
@@ -358,20 +341,20 @@ static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
 	return (link_value >> shift) & 0xf;
 }
 
-static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
+static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 {
 	int lane;
 	u8 lane_status;
 
 	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
 		if ((lane_status & DP_LANE_CR_DONE) == 0)
 			return -EINVAL;
 	}
 	return 0;
 }
 
-static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
+static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 				int lane_count)
 {
 	int lane;
@@ -381,7 +364,7 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 		return -EINVAL;
 
 	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
 		lane_status &= DP_CHANNEL_EQ_BITS;
 		if (lane_status != DP_CHANNEL_EQ_BITS)
 			return -EINVAL;
@@ -390,7 +373,7 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
+static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
 							int lane)
 {
 	int shift = (lane & 1) * 4;
@@ -399,7 +382,7 @@ static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 	return (link_value >> shift) & 0x3;
 }
 
-static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
+static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					u8 adjust_request[2],
 					int lane)
 {
@@ -409,45 +392,45 @@ static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
-static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
+static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 					u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
-		exynos_dp_set_lane0_link_training(dp, training_lane_set);
+		analogix_dp_set_lane0_link_training(dp, training_lane_set);
 		break;
 	case 1:
-		exynos_dp_set_lane1_link_training(dp, training_lane_set);
+		analogix_dp_set_lane1_link_training(dp, training_lane_set);
 		break;
 
 	case 2:
-		exynos_dp_set_lane2_link_training(dp, training_lane_set);
+		analogix_dp_set_lane2_link_training(dp, training_lane_set);
 		break;
 
 	case 3:
-		exynos_dp_set_lane3_link_training(dp, training_lane_set);
+		analogix_dp_set_lane3_link_training(dp, training_lane_set);
 		break;
 	}
 }
 
-static unsigned int exynos_dp_get_lane_link_training(
-				struct exynos_dp_device *dp,
+static unsigned int analogix_dp_get_lane_link_training(
+				struct analogix_dp_device *dp,
 				int lane)
 {
 	u32 reg;
 
 	switch (lane) {
 	case 0:
-		reg = exynos_dp_get_lane0_link_training(dp);
+		reg = analogix_dp_get_lane0_link_training(dp);
 		break;
 	case 1:
-		reg = exynos_dp_get_lane1_link_training(dp);
+		reg = analogix_dp_get_lane1_link_training(dp);
 		break;
 	case 2:
-		reg = exynos_dp_get_lane2_link_training(dp);
+		reg = analogix_dp_get_lane2_link_training(dp);
 		break;
 	case 3:
-		reg = exynos_dp_get_lane3_link_training(dp);
+		reg = analogix_dp_get_lane3_link_training(dp);
 		break;
 	default:
 		WARN_ON(1);
@@ -457,15 +440,15 @@ static unsigned int exynos_dp_get_lane_link_training(
 	return reg;
 }
 
-static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
+static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 {
-	exynos_dp_training_pattern_dis(dp);
-	exynos_dp_set_enhanced_mode(dp);
+	analogix_dp_training_pattern_dis(dp);
+	analogix_dp_set_enhanced_mode(dp);
 
 	dp->link_train.lt_state = FAILED;
 }
 
-static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
+static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
 					u8 adjust_request[2])
 {
 	int lane, lane_count;
@@ -473,9 +456,9 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
 
 	lane_count = dp->link_train.lane_count;
 	for (lane = 0; lane < lane_count; lane++) {
-		voltage_swing = exynos_dp_get_adjust_request_voltage(
+		voltage_swing = analogix_dp_get_adjust_request_voltage(
 						adjust_request, lane);
-		pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
+		pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 						adjust_request, lane);
 		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
@@ -489,7 +472,7 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
 	}
 }
 
-static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
+static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 {
 	int lane, lane_count, retval;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -499,21 +482,21 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
+	retval =  analogix_dp_read_bytes_from_dpcd(dp,
 			DP_LANE0_1_STATUS, 2, link_status);
 	if (retval)
 		return retval;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
+	retval =  analogix_dp_read_bytes_from_dpcd(dp,
 			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 	if (retval)
 		return retval;
 
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 		/* set training pattern 2 for EQ */
-		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
+		analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 
-		retval = exynos_dp_write_byte_to_dpcd(dp,
+		retval = analogix_dp_write_byte_to_dpcd(dp,
 				DP_TRAINING_PATTERN_SET,
 				DP_LINK_SCRAMBLING_DISABLE |
 				DP_TRAINING_PATTERN_2);
@@ -524,11 +507,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 		dp->link_train.lt_state = EQUALIZER_TRAINING;
 	} else {
 		for (lane = 0; lane < lane_count; lane++) {
-			training_lane = exynos_dp_get_lane_link_training(
+			training_lane = analogix_dp_get_lane_link_training(
 							dp, lane);
-			voltage_swing = exynos_dp_get_adjust_request_voltage(
+			voltage_swing = analogix_dp_get_adjust_request_voltage(
 							adjust_request, lane);
-			pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
+			pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 							adjust_request, lane);
 
 			if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
@@ -543,19 +526,19 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 				dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 					dp->link_train.cr_loop[lane],
 					voltage_swing, pre_emphasis);
-				exynos_dp_reduce_link_rate(dp);
+				analogix_dp_reduce_link_rate(dp);
 				return -EIO;
 			}
 		}
 	}
 
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
+		analogix_dp_set_lane_link_training(dp,
 			dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp,
+	retval = analogix_dp_write_bytes_to_dpcd(dp,
 			DP_TRAINING_LANE0_SET, lane_count,
 			dp->link_train.training_lane);
 	if (retval)
@@ -564,7 +547,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
+static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 {
 	int lane, lane_count, retval;
 	u32 reg;
@@ -574,46 +557,46 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
+	retval = analogix_dp_read_bytes_from_dpcd(dp,
 			DP_LANE0_1_STATUS, 2, link_status);
 	if (retval)
 		return retval;
 
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
-		exynos_dp_reduce_link_rate(dp);
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
+		analogix_dp_reduce_link_rate(dp);
 		return -EIO;
 	}
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
+	retval = analogix_dp_read_bytes_from_dpcd(dp,
 			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 	if (retval)
 		return retval;
 
-	retval = exynos_dp_read_byte_from_dpcd(dp,
+	retval = analogix_dp_read_byte_from_dpcd(dp,
 			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
 	if (retval)
 		return retval;
 
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 
-	if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
+	if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 		/* traing pattern Set to Normal */
-		exynos_dp_training_pattern_dis(dp);
+		analogix_dp_training_pattern_dis(dp);
 
 		dev_info(dp->dev, "Link Training success!\n");
 
-		exynos_dp_get_link_bandwidth(dp, &reg);
+		analogix_dp_get_link_bandwidth(dp, &reg);
 		dp->link_train.link_rate = reg;
 		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 			dp->link_train.link_rate);
 
-		exynos_dp_get_lane_count(dp, &reg);
+		analogix_dp_get_lane_count(dp, &reg);
 		dp->link_train.lane_count = reg;
 		dev_dbg(dp->dev, "final lane count = %.2x\n",
 			dp->link_train.lane_count);
 
 		/* set enhanced mode if available */
-		exynos_dp_set_enhanced_mode(dp);
+		analogix_dp_set_enhanced_mode(dp);
 		dp->link_train.lt_state = FINISHED;
 
 		return 0;
@@ -624,21 +607,21 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 		dev_err(dp->dev, "EQ Max loop\n");
-		exynos_dp_reduce_link_rate(dp);
+		analogix_dp_reduce_link_rate(dp);
 		return -EIO;
 	}
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
+		analogix_dp_set_lane_link_training(dp,
 			dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 			lane_count, dp->link_train.training_lane);
 
 	return retval;
 }
 
-static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
+static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 					u8 *bandwidth)
 {
 	u8 data;
@@ -647,11 +630,11 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
 }
 
-static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
+static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 					u8 *lane_count)
 {
 	u8 data;
@@ -660,11 +643,11 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 	 * For DP rev.1.1, Maximum number of Main Link lanes
 	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 	*lane_count = DPCD_MAX_LANE_COUNT(data);
 }
 
-static void exynos_dp_init_training(struct exynos_dp_device *dp,
+static void analogix_dp_init_training(struct analogix_dp_device *dp,
 			enum link_lane_count_type max_lane,
 			enum link_rate_type max_rate)
 {
@@ -672,11 +655,11 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 	 * the DP inter pair skew issue for at least 10 us
 	 */
-	exynos_dp_reset_macro(dp);
+	analogix_dp_reset_macro(dp);
 
 	/* Initialize by reading RX's DPCD */
-	exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
-	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
+	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
+	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
@@ -698,10 +681,10 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
 		dp->link_train.link_rate = max_rate;
 
 	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 }
 
-static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
+static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 {
 	int retval = 0, training_finished = 0;
 
@@ -711,17 +694,17 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 	while (!retval && !training_finished) {
 		switch (dp->link_train.lt_state) {
 		case START:
-			retval = exynos_dp_link_start(dp);
+			retval = analogix_dp_link_start(dp);
 			if (retval)
 				dev_err(dp->dev, "LT link start failed!\n");
 			break;
 		case CLOCK_RECOVERY:
-			retval = exynos_dp_process_clock_recovery(dp);
+			retval = analogix_dp_process_clock_recovery(dp);
 			if (retval)
 				dev_err(dp->dev, "LT CR failed!\n");
 			break;
 		case EQUALIZER_TRAINING:
-			retval = exynos_dp_process_equalizer_training(dp);
+			retval = analogix_dp_process_equalizer_training(dp);
 			if (retval)
 				dev_err(dp->dev, "LT EQ failed!\n");
 			break;
@@ -738,7 +721,7 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
+static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
 				u32 count,
 				u32 bwtype)
 {
@@ -746,8 +729,8 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 	int retval;
 
 	for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
-		exynos_dp_init_training(dp, count, bwtype);
-		retval = exynos_dp_sw_link_training(dp);
+		analogix_dp_init_training(dp, count, bwtype);
+		retval = analogix_dp_sw_link_training(dp);
 		if (retval == 0)
 			break;
 
@@ -757,24 +740,24 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 	return retval;
 }
 
-static int exynos_dp_config_video(struct exynos_dp_device *dp)
+static int analogix_dp_config_video(struct analogix_dp_device *dp)
 {
 	int retval = 0;
 	int timeout_loop = 0;
 	int done_count = 0;
 
-	exynos_dp_config_video_slave_mode(dp);
+	analogix_dp_config_video_slave_mode(dp);
 
-	exynos_dp_set_video_color_format(dp);
+	analogix_dp_set_video_color_format(dp);
 
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 		dev_err(dp->dev, "PLL is not locked yet.\n");
 		return -EINVAL;
 	}
 
 	for (;;) {
 		timeout_loop++;
-		if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
+		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
@@ -785,22 +768,22 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
 	}
 
 	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
+	analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 
 	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
+	analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 
 	/* Disable video mute */
-	exynos_dp_enable_video_mute(dp, 0);
+	analogix_dp_enable_video_mute(dp, 0);
 
 	/* Configure video slave mode */
-	exynos_dp_enable_video_master(dp, 0);
+	analogix_dp_enable_video_master(dp, 0);
 
 	timeout_loop = 0;
 
 	for (;;) {
 		timeout_loop++;
-		if (exynos_dp_is_video_stream_on(dp) == 0) {
+		if (analogix_dp_is_video_stream_on(dp) == 0) {
 			done_count++;
 			if (done_count > 10)
 				break;
@@ -821,47 +804,47 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
 {
 	u8 data;
 
 	if (enable) {
-		exynos_dp_enable_scrambling(dp);
+		analogix_dp_enable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp,
+		analogix_dp_read_byte_from_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
+		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
-		exynos_dp_disable_scrambling(dp);
+		analogix_dp_disable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp,
+		analogix_dp_read_byte_from_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
+		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 	}
 }
 
-static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
+static irqreturn_t analogix_dp_irq_handler(int irq, void *arg)
 {
-	struct exynos_dp_device *dp = arg;
+	struct analogix_dp_device *dp = arg;
 
 	enum dp_irq_type irq_type;
 
-	irq_type = exynos_dp_get_irq_type(dp);
+	irq_type = analogix_dp_get_irq_type(dp);
 	switch (irq_type) {
 	case DP_IRQ_TYPE_HP_CABLE_IN:
 		dev_dbg(dp->dev, "Received irq - cable in\n");
 		schedule_work(&dp->hotplug_work);
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	case DP_IRQ_TYPE_HP_CABLE_OUT:
 		dev_dbg(dp->dev, "Received irq - cable out\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	case DP_IRQ_TYPE_HP_CHANGE:
 		/*
@@ -870,7 +853,7 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 		 * only handle cable changes.
 		 */
 		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	default:
 		dev_err(dp->dev, "Received irq - unknown type!\n");
@@ -879,217 +862,160 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
-static void exynos_dp_hotplug(struct work_struct *work)
+static void analogix_dp_hotplug(struct work_struct *work)
 {
-	struct exynos_dp_device *dp;
+	struct analogix_dp_device *dp;
 
-	dp = container_of(work, struct exynos_dp_device, hotplug_work);
+	dp = container_of(work, struct analogix_dp_device, hotplug_work);
 
 	if (dp->drm_dev)
 		drm_helper_hpd_irq_event(dp->drm_dev);
 }
 
-static void exynos_dp_commit(struct drm_encoder *encoder)
+static void analogix_dp_commit(struct analogix_dp_device *dp)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
 	int ret;
 
 	/* Keep the panel disabled while we configure video */
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel))
+	if (dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel))
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = exynos_dp_detect_hpd(dp);
+	ret = analogix_dp_detect_hpd(dp);
 	if (ret) {
 		/* Cable has been disconnected, we're done */
 		return;
 	}
 
-	ret = exynos_dp_handle_edid(dp);
+	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
 		return;
 	}
 
-	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
+	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
 					dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
 	}
 
-	exynos_dp_enable_scramble(dp, 1);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
-	exynos_dp_enable_enhanced_mode(dp, 1);
+	analogix_dp_enable_scramble(dp, 1);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
+	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
-	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
+	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 
-	exynos_dp_init_video(dp);
-	ret = exynos_dp_config_video(dp);
+	analogix_dp_init_video(dp);
+	ret = analogix_dp_config_video(dp);
 	if (ret)
 		dev_err(dp->dev, "unable to config video\n");
 
 	/* Safe to enable the panel now */
-	if (dp->panel) {
-		if (drm_panel_enable(dp->panel))
+	if (dp->plat_data->panel) {
+		if (drm_panel_enable(dp->plat_data->panel))
 			DRM_ERROR("failed to enable the panel\n");
 	}
 
 	/* Enable video */
-	exynos_dp_start_video(dp);
+	analogix_dp_start_video(dp);
 }
 
-static enum drm_connector_status exynos_dp_detect(
-				struct drm_connector *connector, bool force)
+enum drm_connector_status analogix_dp_detect(struct device *dev, bool force)
 {
 	return connector_status_connected;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_detect);
 
-static void exynos_dp_connector_destroy(struct drm_connector *connector)
-{
-	drm_connector_unregister(connector);
-	drm_connector_cleanup(connector);
-}
-
-static struct drm_connector_funcs exynos_dp_connector_funcs = {
-	.dpms = drm_atomic_helper_connector_dpms,
-	.fill_modes = drm_helper_probe_single_connector_modes,
-	.detect = exynos_dp_detect,
-	.destroy = exynos_dp_connector_destroy,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static int exynos_dp_get_modes(struct drm_connector *connector)
+int analogix_dp_get_modes(struct device *dev)
 {
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
-	struct drm_display_mode *mode;
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+	int num_modes = 0;
 
-	if (dp->panel)
-		return drm_panel_get_modes(dp->panel);
-
-	mode = drm_mode_create(connector->dev);
-	if (!mode) {
-		DRM_ERROR("failed to create a new display mode.\n");
-		return 0;
-	}
+	if (dp->plat_data->panel)
+		num_modes += drm_panel_get_modes(dp->plat_data->panel);
 
-	drm_display_mode_from_videomode(&dp->priv.vm, mode);
-	mode->width_mm = dp->priv.width_mm;
-	mode->height_mm = dp->priv.height_mm;
-	connector->display_info.width_mm = mode->width_mm;
-	connector->display_info.height_mm = mode->height_mm;
-
-	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-	drm_mode_set_name(mode);
-	drm_mode_probed_add(connector, mode);
-
-	return 1;
+	return num_modes;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_get_modes);
 
-static struct drm_encoder *exynos_dp_best_encoder(
-			struct drm_connector *connector)
-{
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
-
-	return &dp->encoder;
-}
-
-static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
-	.get_modes = exynos_dp_get_modes,
-	.best_encoder = exynos_dp_best_encoder,
-};
-
-/* returns the number of bridges attached */
-static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
-		struct drm_encoder *encoder)
+static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
 {
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = dp->encoder;
 	int ret;
 
-	encoder->bridge->next = dp->ptn_bridge;
-	dp->ptn_bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
-	if (ret) {
-		DRM_ERROR("Failed to attach bridge to drm\n");
-		return ret;
+	if (!bridge->encoder) {
+		DRM_ERROR("Parent encoder object not found");
+		return -ENODEV;
 	}
 
-	return 0;
-}
+	encoder->bridge = bridge;
 
-static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
-{
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct drm_encoder *encoder = &dp->encoder;
-	struct drm_connector *connector = &dp->connector;
-	int ret;
-
-	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->ptn_bridge) {
-		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
-		if (!ret)
-			return 0;
+	/*
+	 * NOTE: the connector registration is implemented in analogix
+	 * platform driver, that to say connector would be exist after
+	 * plat_data->attch return, that's why we record the connector
+	 * point after plat attached.
+	 */
+	 if (dp->plat_data->attach) {
+		 ret = dp->plat_data->attach(dp->plat_data, bridge);
+		 if (ret) {
+			 DRM_ERROR("Failed at platform attch func\n");
+			 return ret;
+		 }
 	}
 
-	connector->polled = DRM_CONNECTOR_POLL_HPD;
+	dp->connector = dp->plat_data->connector;
 
-	ret = drm_connector_init(dp->drm_dev, connector,
-			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
-	if (ret) {
-		DRM_ERROR("Failed to initialize connector with drm\n");
-		return ret;
+	if (dp->plat_data->panel) {
+		ret = drm_panel_attach(dp->plat_data->panel, dp->connector);
+		if (ret) {
+			DRM_ERROR("Failed to attach panel\n");
+			return ret;
+		}
 	}
 
-	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
-	drm_connector_register(connector);
-	drm_mode_connector_attach_encoder(connector, encoder);
-
-	if (dp->panel)
-		ret = drm_panel_attach(dp->panel, &dp->connector);
-
-	return ret;
+	return 0;
 }
 
-static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
+static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
+	struct analogix_dp_device *dp = bridge->driver_private;
 
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->panel) {
-		if (drm_panel_prepare(dp->panel)) {
+	if (dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
 			DRM_ERROR("failed to setup the panel\n");
 			return;
 		}
 	}
 
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), true);
+	if (dp->plat_data->power_on)
+		dp->plat_data->power_on(dp->plat_data);
 
 	clk_prepare_enable(dp->clock);
 	phy_power_on(dp->phy);
-	exynos_dp_init_dp(dp);
+	analogix_dp_init_dp(dp);
 	enable_irq(dp->irq);
-	exynos_dp_commit(&dp->encoder);
+	analogix_dp_commit(dp);
 
 	dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
-static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
+static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
+	struct analogix_dp_device *dp = bridge->driver_private;
 
 	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel)) {
+	if (dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel)) {
 			DRM_ERROR("failed to disable the panel\n");
 			return;
 		}
@@ -1100,34 +1026,33 @@ static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 	phy_power_off(dp->phy);
 	clk_disable_unprepare(dp->clock);
 
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), false);
+	if (dp->plat_data->power_off)
+		dp->plat_data->power_off(dp->plat_data);
 
-	if (dp->panel) {
-		if (drm_panel_unprepare(dp->panel))
+	if (dp->plat_data->panel) {
+		if (drm_panel_unprepare(dp->plat_data->panel))
 			DRM_ERROR("failed to turnoff the panel\n");
 	}
 
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
-static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
 }
 
-static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
-	.enable = exynos_dp_bridge_enable,
-	.disable = exynos_dp_bridge_disable,
-	.pre_enable = exynos_dp_bridge_nop,
-	.post_disable = exynos_dp_bridge_nop,
-	.attach = exynos_dp_bridge_attach,
+static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
+	.enable = analogix_dp_bridge_enable,
+	.disable = analogix_dp_bridge_disable,
+	.pre_enable = analogix_dp_bridge_nop,
+	.post_disable = analogix_dp_bridge_nop,
+	.attach = analogix_dp_bridge_attach,
 };
 
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int analogix_dp_create_bridge(struct drm_device *drm_dev,
+				     struct analogix_dp_device *dp)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
-	struct drm_device *drm_dev = dp->drm_dev;
 	struct drm_bridge *bridge;
 	int ret;
 
@@ -1140,8 +1065,8 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	dp->bridge = bridge;
 
 	bridge->driver_private = dp;
-	bridge->encoder = encoder;
-	bridge->funcs = &exynos_dp_bridge_funcs;
+	bridge->encoder = dp->encoder;
+	bridge->funcs = &analogix_dp_bridge_funcs;
 
 	ret = drm_bridge_attach(drm_dev, bridge);
 	if (ret) {
@@ -1152,39 +1077,7 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	return 0;
 }
 
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
-				 const struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
-{
-}
-
-static void exynos_dp_disable(struct drm_encoder *encoder)
-{
-}
-
-static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
-	.mode_fixup = exynos_dp_mode_fixup,
-	.mode_set = exynos_dp_mode_set,
-	.enable = exynos_dp_enable,
-	.disable = exynos_dp_disable,
-};
-
-static struct drm_encoder_funcs exynos_dp_encoder_funcs = {
-	.destroy = drm_encoder_cleanup,
-};
-
-static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
+static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 {
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
@@ -1242,33 +1135,37 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
 	return dp_video_config;
 }
 
-static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct analogix_dp_plat_data *plat_data)
 {
+	struct platform_device *pdev = to_platform_device(dev);
+	struct analogix_dp_device *dp;
+	struct resource *res;
+	unsigned int irq_flags;
 	int ret;
 
-	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
-			OF_USE_NATIVE_MODE);
-	if (ret) {
-		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
-		return ret;
+	if (!plat_data) {
+		dev_err(dev, "Invalided input plat_data\n");
+		return -EINVAL;
 	}
-	return 0;
-}
 
-static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
-{
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-	struct platform_device *pdev = to_platform_device(dev);
-	struct drm_device *drm_dev = data;
-	struct drm_encoder *encoder = &dp->encoder;
-	struct resource *res;
-	unsigned int irq_flags;
-	int pipe, ret = 0;
+	dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, dp);
 
 	dp->dev = &pdev->dev;
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 
-	dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
+	/*
+	 * platform dp driver need containor_of the plat_data to get
+	 * the driver private data, so we need to store the point of
+	 * plat_data, not the context of plat_data.
+	 */
+	dp->plat_data = plat_data;
+
+	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
 	if (IS_ERR(dp->video_info))
 		return PTR_ERR(dp->video_info);
 
@@ -1288,12 +1185,6 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		}
 	}
 
-	if (!dp->panel && !dp->bridge) {
-		ret = exynos_dp_dt_parse_panel(dp);
-		if (ret)
-			return ret;
-	}
-
 	dp->clock = devm_clk_get(&pdev->dev, "dp");
 	if (IS_ERR(dp->clock)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
@@ -1308,7 +1199,10 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
-	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
+	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
+	if (!gpio_is_valid(dp->hpd_gpio))
+		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
+						 "samsung,hpd-gpio", 0);
 
 	if (gpio_is_valid(dp->hpd_gpio)) {
 		/*
@@ -1337,14 +1231,14 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		return -ENODEV;
 	}
 
-	INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
+	INIT_WORK(&dp->hotplug_work, analogix_dp_hotplug);
 
 	phy_power_on(dp->phy);
 
-	exynos_dp_init_dp(dp);
+	analogix_dp_init_dp(dp);
 
-	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
-			irq_flags, "exynos-dp", dp);
+	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
+			irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		return ret;
@@ -1352,126 +1246,48 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	disable_irq(dp->irq);
 
 	dp->drm_dev = drm_dev;
+	dp->encoder = dp->plat_data->encoder;
 
-	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
-						  EXYNOS_DISPLAY_TYPE_LCD);
-	if (pipe < 0)
-		return pipe;
-
-	encoder->possible_crtcs = 1 << pipe;
-
-	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
-
-	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
-			 DRM_MODE_ENCODER_TMDS);
-
-	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
-
-	ret = exynos_dp_create_connector(encoder);
+	ret = analogix_dp_create_bridge(drm_dev, dp);
 	if (ret) {
-		DRM_ERROR("failed to create connector ret = %d\n", ret);
-		drm_encoder_cleanup(encoder);
+		DRM_ERROR("failed to create bridge (%d)\n", ret);
+		drm_encoder_cleanup(dp->encoder);
 		return ret;
 	}
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_bind);
 
-static void exynos_dp_unbind(struct device *dev, struct device *master,
-				void *data)
-{
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-
-	exynos_dp_disable(&dp->encoder);
-}
-
-static const struct component_ops exynos_dp_ops = {
-	.bind	= exynos_dp_bind,
-	.unbind	= exynos_dp_unbind,
-};
-
-static int exynos_dp_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct device_node *panel_node, *bridge_node, *endpoint;
-	struct exynos_dp_device *dp;
-
-	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
-				GFP_KERNEL);
-	if (!dp)
-		return -ENOMEM;
-
-	platform_set_drvdata(pdev, dp);
-
-	panel_node = of_parse_phandle(dev->of_node, "panel", 0);
-	if (panel_node) {
-		dp->panel = of_drm_find_panel(panel_node);
-		of_node_put(panel_node);
-		if (!dp->panel)
-			return -EPROBE_DEFER;
-	}
-
-	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
-	if (endpoint) {
-		bridge_node = of_graph_get_remote_port_parent(endpoint);
-		if (bridge_node) {
-			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
-			of_node_put(bridge_node);
-			if (!dp->ptn_bridge)
-				return -EPROBE_DEFER;
-		} else
-			return -EPROBE_DEFER;
-	}
-
-	return component_add(&pdev->dev, &exynos_dp_ops);
-}
-
-static int exynos_dp_remove(struct platform_device *pdev)
+void analogix_dp_unbind(struct device *dev, struct device *master,
+			void *data)
 {
-	component_del(&pdev->dev, &exynos_dp_ops);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	return 0;
+	analogix_dp_bridge_disable(dp->bridge);
 }
+EXPORT_SYMBOL_GPL(analogix_dp_unbind);
 
 #ifdef CONFIG_PM_SLEEP
-static int exynos_dp_suspend(struct device *dev)
+int analogix_dp_suspend(struct device *dev)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_bridge_disable(dp->bridge);
+	analogix_dp_bridge_disable(dp->bridge);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_suspend);
 
-static int exynos_dp_resume(struct device *dev)
+int analogix_dp_resume(struct device *dev)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_bridge_enable(dp->bridge);
+	analogix_dp_bridge_enable(dp->bridge);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_resume);
 #endif
 
-static const struct dev_pm_ops exynos_dp_pm_ops = {
-	SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
-};
-
-static const struct of_device_id exynos_dp_match[] = {
-	{ .compatible = "samsung,exynos5-dp" },
-	{},
-};
-MODULE_DEVICE_TABLE(of, exynos_dp_match);
-
-struct platform_driver dp_driver = {
-	.probe		= exynos_dp_probe,
-	.remove		= exynos_dp_remove,
-	.driver		= {
-		.name	= "exynos-dp",
-		.owner	= THIS_MODULE,
-		.pm	= &exynos_dp_pm_ops,
-		.of_match_table = exynos_dp_match,
-	},
-};
-
 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
-MODULE_DESCRIPTION("Samsung SoC DP Driver");
+MODULE_DESCRIPTION("Analogix DP Core Driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
new file mode 100644
index 0000000..65ce7f1
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -0,0 +1,277 @@
+/*
+ * Header file for Analogix DP (Display Port) core interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _ANALOGIX_DP_CORE_H
+#define _ANALOGIX_DP_CORE_H
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_dp_helper.h>
+
+#define DP_TIMEOUT_LOOP_COUNT 100
+#define MAX_CR_LOOP 5
+#define MAX_EQ_LOOP 5
+
+enum link_rate_type {
+	LINK_RATE_1_62GBPS = 0x06,
+	LINK_RATE_2_70GBPS = 0x0a
+};
+
+enum link_lane_count_type {
+	LANE_COUNT1 = 1,
+	LANE_COUNT2 = 2,
+	LANE_COUNT4 = 4
+};
+
+enum link_training_state {
+	START,
+	CLOCK_RECOVERY,
+	EQUALIZER_TRAINING,
+	FINISHED,
+	FAILED
+};
+
+enum voltage_swing_level {
+	VOLTAGE_LEVEL_0,
+	VOLTAGE_LEVEL_1,
+	VOLTAGE_LEVEL_2,
+	VOLTAGE_LEVEL_3,
+};
+
+enum pre_emphasis_level {
+	PRE_EMPHASIS_LEVEL_0,
+	PRE_EMPHASIS_LEVEL_1,
+	PRE_EMPHASIS_LEVEL_2,
+	PRE_EMPHASIS_LEVEL_3,
+};
+
+enum pattern_set {
+	PRBS7,
+	D10_2,
+	TRAINING_PTN1,
+	TRAINING_PTN2,
+	DP_NONE
+};
+
+enum color_space {
+	COLOR_RGB,
+	COLOR_YCBCR422,
+	COLOR_YCBCR444
+};
+
+enum color_depth {
+	COLOR_6,
+	COLOR_8,
+	COLOR_10,
+	COLOR_12
+};
+
+enum color_coefficient {
+	COLOR_YCBCR601,
+	COLOR_YCBCR709
+};
+
+enum dynamic_range {
+	VESA,
+	CEA
+};
+
+enum pll_status {
+	PLL_UNLOCKED,
+	PLL_LOCKED
+};
+
+enum clock_recovery_m_value_type {
+	CALCULATED_M,
+	REGISTER_M
+};
+
+enum video_timing_recognition_type {
+	VIDEO_TIMING_FROM_CAPTURE,
+	VIDEO_TIMING_FROM_REGISTER
+};
+
+enum analog_power_block {
+	AUX_BLOCK,
+	CH0_BLOCK,
+	CH1_BLOCK,
+	CH2_BLOCK,
+	CH3_BLOCK,
+	ANALOG_TOTAL,
+	POWER_ALL
+};
+
+enum dp_irq_type {
+	DP_IRQ_TYPE_HP_CABLE_IN,
+	DP_IRQ_TYPE_HP_CABLE_OUT,
+	DP_IRQ_TYPE_HP_CHANGE,
+	DP_IRQ_TYPE_UNKNOWN,
+};
+
+struct video_info {
+	char *name;
+
+	bool h_sync_polarity;
+	bool v_sync_polarity;
+	bool interlaced;
+
+	enum color_space color_space;
+	enum dynamic_range dynamic_range;
+	enum color_coefficient ycbcr_coeff;
+	enum color_depth color_depth;
+
+	enum link_rate_type link_rate;
+	enum link_lane_count_type lane_count;
+};
+
+struct link_train {
+	int eq_loop;
+	int cr_loop[4];
+
+	u8 link_rate;
+	u8 lane_count;
+	u8 training_lane[4];
+
+	enum link_training_state lt_state;
+};
+
+struct analogix_dp_device {
+	struct drm_encoder	*encoder;
+	struct drm_connector	*connector;
+	struct device		*dev;
+	struct drm_device	*drm_dev;
+	struct drm_bridge	*bridge;
+	struct clk		*clock;
+	unsigned int		irq;
+	void __iomem		*reg_base;
+
+	struct video_info	*video_info;
+	struct link_train	link_train;
+	struct work_struct	hotplug_work;
+	struct phy		*phy;
+	int			dpms_mode;
+	int			hpd_gpio;
+
+	struct analogix_dp_plat_data *plat_data;
+};
+
+/* analogix_dp_reg.c */
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_stop_video(struct analogix_dp_device *dp);
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
+void analogix_dp_reset(struct analogix_dp_device *dp);
+void analogix_dp_swreset(struct analogix_dp_device *dp);
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				       enum analog_power_block block,
+				       bool enable);
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
+void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
+void analogix_dp_reset_aux(struct analogix_dp_device *dp);
+void analogix_dp_init_aux(struct analogix_dp_device *dp);
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char data);
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char *data);
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[]);
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[]);
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr);
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int *data);
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char edid[]);
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
+void analogix_dp_reset_macro(struct analogix_dp_device *dp);
+void analogix_dp_init_video(struct analogix_dp_device *dp);
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+			enum clock_recovery_m_value_type type,
+			u32 m_value,
+			u32 n_value);
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_start_video(struct analogix_dp_device *dp);
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
+#endif /* _ANALOGIX_DP_CORE_H */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
new file mode 100644
index 0000000..442cc66
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -0,0 +1,1263 @@
+/*
+ * Analogix DP (Display port) core register interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include "analogix_dp_core.h"
+#include "analogix_dp_reg.h"
+
+#define COMMON_INT_MASK_1	0
+#define COMMON_INT_MASK_2	0
+#define COMMON_INT_MASK_3	0
+#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
+#define INT_STA_MASK		INT_HPD
+
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+		reg |= HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+		reg &= ~HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	}
+}
+
+void analogix_dp_stop_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	reg &= ~VIDEO_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+}
+
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable)
+		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
+			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+	else
+		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
+			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
+}
+
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = TX_TERMINAL_CTRL_50_OHM;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
+
+	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
+
+	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
+
+	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
+		TX_CUR1_2X | TX_CUR_16_MA;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
+
+	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
+		CH1_AMP_400_MV | CH0_AMP_400_MV;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
+}
+
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
+{
+	/* Set interrupt pin assertion polarity as high */
+	writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
+
+	/* Clear pending regisers */
+	writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+	writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
+	writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
+	writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+	writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	/* 0:mask,1: unmask */
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+void analogix_dp_reset(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	analogix_dp_stop_video(dp);
+	analogix_dp_enable_video_mute(dp, 0);
+
+	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
+		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
+		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+
+	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
+		SERDES_FIFO_FUNC_EN_N |
+		LS_CLK_DOMAIN_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+
+	usleep_range(20, 30);
+
+	analogix_dp_lane_swap(dp, 0);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
+
+	writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
+	writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
+
+	writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
+	writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
+
+	writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
+	writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
+
+	writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_swreset(struct analogix_dp_device *dp)
+{
+	writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
+}
+
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* 0: mask, 1: unmask */
+	reg = COMMON_INT_MASK_1;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+
+	reg = COMMON_INT_MASK_2;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+
+	reg = COMMON_INT_MASK_3;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+
+	reg = COMMON_INT_MASK_4;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+
+	reg = INT_STA_MASK;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+	if (reg & PLL_LOCK)
+		return PLL_LOCKED;
+	else
+		return PLL_UNLOCKED;
+}
+
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
+		reg |= DP_PLL_PD;
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
+		reg &= ~DP_PLL_PD;
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+	}
+}
+
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				enum analog_power_block block,
+				bool enable)
+{
+	u32 reg;
+
+	switch (block) {
+	case AUX_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= AUX_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~AUX_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH0_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH1_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH1_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH1_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH2_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH2_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH2_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH3_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH3_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH3_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case ANALOG_TOTAL:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= DP_PHY_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~DP_PHY_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case POWER_ALL:
+		if (enable) {
+			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
+				CH1_PD | CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
+{
+	u32 reg;
+	int timeout_loop = 0;
+
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
+
+	reg = PLL_LOCK_CHG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+
+	/* Power up PLL */
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		analogix_dp_set_pll_power_down(dp, 0);
+
+		while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+			timeout_loop++;
+			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+				dev_err(dp->dev, "failed to get pll lock status\n");
+				return;
+			}
+			usleep_range(10, 20);
+		}
+	}
+
+	/* Enable Serdes FIFO function and Link symbol clock domain module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
+		| AUX_FUNC_EN_N);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+
+	reg = INT_HPD;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+}
+
+void analogix_dp_init_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	analogix_dp_clear_hotplug_interrupts(dp);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg &= ~(F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		reg = gpio_get_value(dp->hpd_gpio);
+		if (reg)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+		else
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+	} else {
+		/* Parse hotplug interrupt status register */
+		reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+
+		if (reg & PLUG)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+
+		if (reg & HPD_LOST)
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+
+		if (reg & HOTPLUG_CHG)
+			return DP_IRQ_TYPE_HP_CHANGE;
+
+		return DP_IRQ_TYPE_UNKNOWN;
+	}
+}
+
+void analogix_dp_reset_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Disable AUX channel module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg |= AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+void analogix_dp_init_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Clear inerrupts related to AUX channel */
+	reg = RPLY_RECEIV | AUX_ERR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	analogix_dp_reset_aux(dp);
+
+	/* Disable AUX transaction H/W retry */
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
+		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
+
+	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
+	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
+
+	/* Enable AUX channel module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg &= ~AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		if (gpio_get_value(dp->hpd_gpio))
+			return 0;
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+		if (reg & HPD_STATUS)
+			return 0;
+	}
+
+	return -EINVAL;
+}
+
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+	reg &= ~SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+}
+
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
+{
+	int reg;
+	int retval = 0;
+	int timeout_loop = 0;
+
+	/* Enable AUX CH operation */
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+	reg |= AUX_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+
+	/* Is AUX CH command reply received? */
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+	while (!(reg & RPLY_RECEIV)) {
+		timeout_loop++;
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "AUX CH command reply failed!\n");
+			return -ETIMEDOUT;
+		}
+		reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+		usleep_range(10, 11);
+	}
+
+	/* Clear interrupt source for AUX CH command reply */
+	writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	/* Clear interrupt source for AUX CH access error */
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+	if (reg & AUX_ERR) {
+		writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
+		return -EREMOTEIO;
+	}
+
+	/* Check AUX CH error access status */
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
+	if ((reg & AUX_STATUS_MASK) != 0) {
+		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
+			reg & AUX_STATUS_MASK);
+		return -EREMOTEIO;
+	}
+
+	return retval;
+}
+
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+		/* Write data buffer */
+		reg = (unsigned int)data;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+		/*
+		 * Set DisplayPort transaction and write 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+		/*
+		 * Set DisplayPort transaction and read 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	/* Read data buffer */
+	reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+	*data = (unsigned char)(reg & 0xff);
+
+	return retval;
+}
+
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+			     cur_data_idx++) {
+				reg = data[start_offset + cur_data_idx];
+				writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+							  + 4 * cur_data_idx);
+			}
+
+			/*
+			 * Set DisplayPort transaction and write
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+			else
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		/* AUX CH Request Transaction process */
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+			/*
+			 * Set DisplayPort transaction and read
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+			else
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+		    cur_data_idx++) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			data[start_offset + cur_data_idx] =
+				(unsigned char)reg;
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr)
+{
+	u32 reg;
+	int retval;
+
+	/* Set EDID device address */
+	reg = device_addr;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+	/* Set offset from base address of EDID device */
+	writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+	/*
+	 * Set I2C transaction and write address
+	 * If bit 3 is 1, DisplayPort transaction.
+	 * If Bit 3 is 0, I2C transaction.
+	 */
+	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
+		AUX_TX_COMM_WRITE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+	/* Start AUX transaction */
+	retval = analogix_dp_start_aux_transaction(dp);
+	if (retval != 0)
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select EDID device */
+		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+		if (retval != 0)
+			continue;
+
+		/*
+		 * Set I2C transaction and read data
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_I2C_TRANSACTION |
+			AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	/* Read data */
+	if (retval == 0)
+		*data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char edid[])
+{
+	u32 reg;
+	unsigned int i, j;
+	unsigned int cur_data_idx;
+	unsigned int defer = 0;
+	int retval = 0;
+
+	for (i = 0; i < count; i += 16) {
+		for (j = 0; j < 3; j++) {
+			/* Clear AUX CH data buffer */
+			reg = BUF_CLR;
+			writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+			/* Set normal AUX CH command */
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+			reg &= ~ADDR_ONLY;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+
+			/*
+			 * If Rx sends defer, Tx sends only reads
+			 * request without sending address
+			 */
+			if (!defer)
+				retval = analogix_dp_select_i2c_device(dp,
+						device_addr, reg_addr + i);
+			else
+				defer = 0;
+
+			if (retval == 0) {
+				/*
+				 * Set I2C transaction and write data
+				 * If bit 3 is 1, DisplayPort transaction.
+				 * If Bit 3 is 0, I2C transaction.
+				 */
+				reg = AUX_LENGTH(16) |
+					AUX_TX_COMM_I2C_TRANSACTION |
+					AUX_TX_COMM_READ;
+				writel(reg, dp->reg_base +
+					ANALOGIX_DP_AUX_CH_CTL_1);
+
+				/* Start AUX transaction */
+				retval = analogix_dp_start_aux_transaction(dp);
+				if (retval == 0)
+					break;
+				else
+					dev_dbg(dp->dev,
+						"%s: Aux Transaction fail!\n",
+						__func__);
+			}
+			/* Check if Rx sends defer */
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
+			if (reg == AUX_RX_COMM_AUX_DEFER ||
+				reg == AUX_RX_COMM_I2C_DEFER) {
+				dev_err(dp->dev, "Defer: %d\n\n", reg);
+				defer = 1;
+			}
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			edid[i + cur_data_idx] = (unsigned char)reg;
+		}
+	}
+
+	return retval;
+}
+
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
+{
+	u32 reg;
+
+	reg = bwtype;
+	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
+		writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
+}
+
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
+	*bwtype = reg;
+}
+
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
+{
+	u32 reg;
+
+	reg = count;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
+}
+
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
+	*count = reg;
+}
+
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg |= ENHANCED;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg &= ~ENHANCED;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+	}
+}
+
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				enum pattern_set pattern)
+{
+	u32 reg;
+
+	switch (pattern) {
+	case PRBS7:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case D10_2:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN1:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN2:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case DP_NONE:
+		reg = SCRAMBLING_ENABLE |
+			LINK_QUAL_PATTERN_SET_DISABLE |
+			SW_TRAINING_PATTERN_SET_NORMAL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+}
+
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+	return reg;
+}
+
+void analogix_dp_reset_macro(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
+	reg |= MACRO_RST;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+
+	/* 10 us is the minimum reset time. */
+	usleep_range(10, 20);
+
+	reg &= ~MACRO_RST;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+}
+
+void analogix_dp_init_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	reg = CHA_CRI(4) | CHA_CTRL;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+
+	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
+}
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Configure the input color depth, color space, dynamic range */
+	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info->color_depth << IN_BPC_SHIFT) |
+		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
+
+	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
+	reg &= ~IN_YC_COEFFI_MASK;
+	if (dp->video_info->ycbcr_coeff)
+		reg |= IN_YC_COEFFI_ITU709;
+	else
+		reg |= IN_YC_COEFFI_ITU601;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
+}
+
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	if (!(reg & DET_STA)) {
+		dev_dbg(dp->dev, "Input stream clock not detected.\n");
+		return -EINVAL;
+	}
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
+
+	if (reg & CHA_STA) {
+		dev_dbg(dp->dev, "Input stream clk is changing\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+		enum clock_recovery_m_value_type type,
+		u32 m_value,
+		u32 n_value)
+{
+	u32 reg;
+
+	if (type == REGISTER_M) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg |= FIX_M_VID;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg = m_value & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
+		reg = (m_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
+		reg = (m_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
+
+		reg = n_value & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		reg = (n_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		reg = (n_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
+	} else  {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg &= ~FIX_M_VID;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
+	}
+}
+
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
+{
+	u32 reg;
+
+	if (type == VIDEO_TIMING_FROM_CAPTURE) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+		reg &= ~FORMAT_SEL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+		reg |= FORMAT_SEL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	}
+}
+
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MODE_SLAVE_MODE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+	}
+}
+
+void analogix_dp_start_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	reg |= VIDEO_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+}
+
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	if (!(reg & STRM_VALID)) {
+		dev_dbg(dp->dev, "Input video stream is not detected.\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg |= MASTER_VID_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~INTERACE_SCAN_CFG;
+	reg |= (dp->video_info->interlaced << 2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~VSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->v_sync_polarity << 1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~HSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->h_sync_polarity << 0);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+	reg &= ~SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+}
+
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+	reg |= SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
similarity index 64%
rename from drivers/gpu/drm/exynos/exynos_dp_reg.h
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 2e9bd0e..738db4c 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -1,5 +1,5 @@
 /*
- * Register definition file for Samsung DP driver
+ * Register definition file for Analogix DP core driver
  *
  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  * Author: Jingoo Han <jg1.han@samsung.com>
@@ -9,96 +9,96 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef _EXYNOS_DP_REG_H
-#define _EXYNOS_DP_REG_H
-
-#define EXYNOS_DP_TX_SW_RESET			0x14
-#define EXYNOS_DP_FUNC_EN_1			0x18
-#define EXYNOS_DP_FUNC_EN_2			0x1C
-#define EXYNOS_DP_VIDEO_CTL_1			0x20
-#define EXYNOS_DP_VIDEO_CTL_2			0x24
-#define EXYNOS_DP_VIDEO_CTL_3			0x28
-
-#define EXYNOS_DP_VIDEO_CTL_8			0x3C
-#define EXYNOS_DP_VIDEO_CTL_10			0x44
-
-#define EXYNOS_DP_LANE_MAP			0x35C
-
-#define EXYNOS_DP_ANALOG_CTL_1			0x370
-#define EXYNOS_DP_ANALOG_CTL_2			0x374
-#define EXYNOS_DP_ANALOG_CTL_3			0x378
-#define EXYNOS_DP_PLL_FILTER_CTL_1		0x37C
-#define EXYNOS_DP_TX_AMP_TUNING_CTL		0x380
-
-#define EXYNOS_DP_AUX_HW_RETRY_CTL		0x390
-
-#define EXYNOS_DP_COMMON_INT_STA_1		0x3C4
-#define EXYNOS_DP_COMMON_INT_STA_2		0x3C8
-#define EXYNOS_DP_COMMON_INT_STA_3		0x3CC
-#define EXYNOS_DP_COMMON_INT_STA_4		0x3D0
-#define EXYNOS_DP_INT_STA			0x3DC
-#define EXYNOS_DP_COMMON_INT_MASK_1		0x3E0
-#define EXYNOS_DP_COMMON_INT_MASK_2		0x3E4
-#define EXYNOS_DP_COMMON_INT_MASK_3		0x3E8
-#define EXYNOS_DP_COMMON_INT_MASK_4		0x3EC
-#define EXYNOS_DP_INT_STA_MASK			0x3F8
-#define EXYNOS_DP_INT_CTL			0x3FC
-
-#define EXYNOS_DP_SYS_CTL_1			0x600
-#define EXYNOS_DP_SYS_CTL_2			0x604
-#define EXYNOS_DP_SYS_CTL_3			0x608
-#define EXYNOS_DP_SYS_CTL_4			0x60C
-
-#define EXYNOS_DP_PKT_SEND_CTL			0x640
-#define EXYNOS_DP_HDCP_CTL			0x648
-
-#define EXYNOS_DP_LINK_BW_SET			0x680
-#define EXYNOS_DP_LANE_COUNT_SET		0x684
-#define EXYNOS_DP_TRAINING_PTN_SET		0x688
-#define EXYNOS_DP_LN0_LINK_TRAINING_CTL		0x68C
-#define EXYNOS_DP_LN1_LINK_TRAINING_CTL		0x690
-#define EXYNOS_DP_LN2_LINK_TRAINING_CTL		0x694
-#define EXYNOS_DP_LN3_LINK_TRAINING_CTL		0x698
-
-#define EXYNOS_DP_DEBUG_CTL			0x6C0
-#define EXYNOS_DP_HPD_DEGLITCH_L		0x6C4
-#define EXYNOS_DP_HPD_DEGLITCH_H		0x6C8
-#define EXYNOS_DP_LINK_DEBUG_CTL		0x6E0
-
-#define EXYNOS_DP_M_VID_0			0x700
-#define EXYNOS_DP_M_VID_1			0x704
-#define EXYNOS_DP_M_VID_2			0x708
-#define EXYNOS_DP_N_VID_0			0x70C
-#define EXYNOS_DP_N_VID_1			0x710
-#define EXYNOS_DP_N_VID_2			0x714
-
-#define EXYNOS_DP_PLL_CTL			0x71C
-#define EXYNOS_DP_PHY_PD			0x720
-#define EXYNOS_DP_PHY_TEST			0x724
-
-#define EXYNOS_DP_VIDEO_FIFO_THRD		0x730
-#define EXYNOS_DP_AUDIO_MARGIN			0x73C
-
-#define EXYNOS_DP_M_VID_GEN_FILTER_TH		0x764
-#define EXYNOS_DP_M_AUD_GEN_FILTER_TH		0x778
-#define EXYNOS_DP_AUX_CH_STA			0x780
-#define EXYNOS_DP_AUX_CH_DEFER_CTL		0x788
-#define EXYNOS_DP_AUX_RX_COMM			0x78C
-#define EXYNOS_DP_BUFFER_DATA_CTL		0x790
-#define EXYNOS_DP_AUX_CH_CTL_1			0x794
-#define EXYNOS_DP_AUX_ADDR_7_0			0x798
-#define EXYNOS_DP_AUX_ADDR_15_8			0x79C
-#define EXYNOS_DP_AUX_ADDR_19_16		0x7A0
-#define EXYNOS_DP_AUX_CH_CTL_2			0x7A4
-
-#define EXYNOS_DP_BUF_DATA_0			0x7C0
-
-#define EXYNOS_DP_SOC_GENERAL_CTL		0x800
-
-/* EXYNOS_DP_TX_SW_RESET */
+#ifndef _ANALOGIX_DP_REG_H
+#define _ANALOGIX_DP_REG_H
+
+#define ANALOGIX_DP_TX_SW_RESET			0x14
+#define ANALOGIX_DP_FUNC_EN_1			0x18
+#define ANALOGIX_DP_FUNC_EN_2			0x1C
+#define ANALOGIX_DP_VIDEO_CTL_1			0x20
+#define ANALOGIX_DP_VIDEO_CTL_2			0x24
+#define ANALOGIX_DP_VIDEO_CTL_3			0x28
+
+#define ANALOGIX_DP_VIDEO_CTL_8			0x3C
+#define ANALOGIX_DP_VIDEO_CTL_10		0x44
+
+#define ANALOGIX_DP_LANE_MAP			0x35C
+
+#define ANALOGIX_DP_ANALOG_CTL_1		0x370
+#define ANALOGIX_DP_ANALOG_CTL_2		0x374
+#define ANALOGIX_DP_ANALOG_CTL_3		0x378
+#define ANALOGIX_DP_PLL_FILTER_CTL_1		0x37C
+#define ANALOGIX_DP_TX_AMP_TUNING_CTL		0x380
+
+#define ANALOGIX_DP_AUX_HW_RETRY_CTL		0x390
+
+#define ANALOGIX_DP_COMMON_INT_STA_1		0x3C4
+#define ANALOGIX_DP_COMMON_INT_STA_2		0x3C8
+#define ANALOGIX_DP_COMMON_INT_STA_3		0x3CC
+#define ANALOGIX_DP_COMMON_INT_STA_4		0x3D0
+#define ANALOGIX_DP_INT_STA			0x3DC
+#define ANALOGIX_DP_COMMON_INT_MASK_1		0x3E0
+#define ANALOGIX_DP_COMMON_INT_MASK_2		0x3E4
+#define ANALOGIX_DP_COMMON_INT_MASK_3		0x3E8
+#define ANALOGIX_DP_COMMON_INT_MASK_4		0x3EC
+#define ANALOGIX_DP_INT_STA_MASK		0x3F8
+#define ANALOGIX_DP_INT_CTL			0x3FC
+
+#define ANALOGIX_DP_SYS_CTL_1			0x600
+#define ANALOGIX_DP_SYS_CTL_2			0x604
+#define ANALOGIX_DP_SYS_CTL_3			0x608
+#define ANALOGIX_DP_SYS_CTL_4			0x60C
+
+#define ANALOGIX_DP_PKT_SEND_CTL		0x640
+#define ANALOGIX_DP_HDCP_CTL			0x648
+
+#define ANALOGIX_DP_LINK_BW_SET			0x680
+#define ANALOGIX_DP_LANE_COUNT_SET		0x684
+#define ANALOGIX_DP_TRAINING_PTN_SET		0x688
+#define ANALOGIX_DP_LN0_LINK_TRAINING_CTL	0x68C
+#define ANALOGIX_DP_LN1_LINK_TRAINING_CTL	0x690
+#define ANALOGIX_DP_LN2_LINK_TRAINING_CTL	0x694
+#define ANALOGIX_DP_LN3_LINK_TRAINING_CTL	0x698
+
+#define ANALOGIX_DP_DEBUG_CTL			0x6C0
+#define ANALOGIX_DP_HPD_DEGLITCH_L		0x6C4
+#define ANALOGIX_DP_HPD_DEGLITCH_H		0x6C8
+#define ANALOGIX_DP_LINK_DEBUG_CTL		0x6E0
+
+#define ANALOGIX_DP_M_VID_0			0x700
+#define ANALOGIX_DP_M_VID_1			0x704
+#define ANALOGIX_DP_M_VID_2			0x708
+#define ANALOGIX_DP_N_VID_0			0x70C
+#define ANALOGIX_DP_N_VID_1			0x710
+#define ANALOGIX_DP_N_VID_2			0x714
+
+#define ANALOGIX_DP_PLL_CTL			0x71C
+#define ANALOGIX_DP_PHY_PD			0x720
+#define ANALOGIX_DP_PHY_TEST			0x724
+
+#define ANALOGIX_DP_VIDEO_FIFO_THRD		0x730
+#define ANALOGIX_DP_AUDIO_MARGIN		0x73C
+
+#define ANALOGIX_DP_M_VID_GEN_FILTER_TH		0x764
+#define ANALOGIX_DP_M_AUD_GEN_FILTER_TH		0x778
+#define ANALOGIX_DP_AUX_CH_STA			0x780
+#define ANALOGIX_DP_AUX_CH_DEFER_CTL		0x788
+#define ANALOGIX_DP_AUX_RX_COMM			0x78C
+#define ANALOGIX_DP_BUFFER_DATA_CTL		0x790
+#define ANALOGIX_DP_AUX_CH_CTL_1		0x794
+#define ANALOGIX_DP_AUX_ADDR_7_0		0x798
+#define ANALOGIX_DP_AUX_ADDR_15_8		0x79C
+#define ANALOGIX_DP_AUX_ADDR_19_16		0x7A0
+#define ANALOGIX_DP_AUX_CH_CTL_2		0x7A4
+
+#define ANALOGIX_DP_BUF_DATA_0			0x7C0
+
+#define ANALOGIX_DP_SOC_GENERAL_CTL		0x800
+
+/* ANALOGIX_DP_TX_SW_RESET */
 #define RESET_DP_TX				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_1 */
+/* ANALOGIX_DP_FUNC_EN_1 */
 #define MASTER_VID_FUNC_EN_N			(0x1 << 7)
 #define SLAVE_VID_FUNC_EN_N			(0x1 << 5)
 #define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
@@ -107,17 +107,17 @@
 #define CRC_FUNC_EN_N				(0x1 << 1)
 #define SW_FUNC_EN_N				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_2 */
+/* ANALOGIX_DP_FUNC_EN_2 */
 #define SSC_FUNC_EN_N				(0x1 << 7)
 #define AUX_FUNC_EN_N				(0x1 << 2)
 #define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
 #define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define VIDEO_EN				(0x1 << 7)
 #define HDCP_VIDEO_MUTE				(0x1 << 6)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define IN_D_RANGE_MASK				(0x1 << 7)
 #define IN_D_RANGE_SHIFT			(7)
 #define IN_D_RANGE_CEA				(0x1 << 7)
@@ -134,7 +134,7 @@
 #define IN_COLOR_F_YCBCR422			(0x1 << 0)
 #define IN_COLOR_F_RGB				(0x0 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_3 */
+/* ANALOGIX_DP_VIDEO_CTL_3 */
 #define IN_YC_COEFFI_MASK			(0x1 << 7)
 #define IN_YC_COEFFI_SHIFT			(7)
 #define IN_YC_COEFFI_ITU709			(0x1 << 7)
@@ -144,17 +144,17 @@
 #define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
 #define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
 
-/* EXYNOS_DP_VIDEO_CTL_8 */
+/* ANALOGIX_DP_VIDEO_CTL_8 */
 #define VID_HRES_TH(x)				(((x) & 0xf) << 4)
 #define VID_VRES_TH(x)				(((x) & 0xf) << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_10 */
+/* ANALOGIX_DP_VIDEO_CTL_10 */
 #define FORMAT_SEL				(0x1 << 4)
 #define INTERACE_SCAN_CFG			(0x1 << 2)
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
-/* EXYNOS_DP_LANE_MAP */
+/* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
 #define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
@@ -172,30 +172,30 @@
 #define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
 #define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_1 */
+/* ANALOGIX_DP_ANALOG_CTL_1 */
 #define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
 
-/* EXYNOS_DP_ANALOG_CTL_2 */
+/* ANALOGIX_DP_ANALOG_CTL_2 */
 #define SEL_24M					(0x1 << 3)
 #define TX_DVDD_BIT_1_0625V			(0x4 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_3 */
+/* ANALOGIX_DP_ANALOG_CTL_3 */
 #define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
 #define VCO_BIT_600_MICRO			(0x5 << 0)
 
-/* EXYNOS_DP_PLL_FILTER_CTL_1 */
+/* ANALOGIX_DP_PLL_FILTER_CTL_1 */
 #define PD_RING_OSC				(0x1 << 6)
 #define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
 #define TX_CUR1_2X				(0x1 << 2)
 #define TX_CUR_16_MA				(0x3 << 0)
 
-/* EXYNOS_DP_TX_AMP_TUNING_CTL */
+/* ANALOGIX_DP_TX_AMP_TUNING_CTL */
 #define CH3_AMP_400_MV				(0x0 << 24)
 #define CH2_AMP_400_MV				(0x0 << 16)
 #define CH1_AMP_400_MV				(0x0 << 8)
 #define CH0_AMP_400_MV				(0x0 << 0)
 
-/* EXYNOS_DP_AUX_HW_RETRY_CTL */
+/* ANALOGIX_DP_AUX_HW_RETRY_CTL */
 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x)	(((x) & 0x7) << 8)
 #define AUX_HW_RETRY_INTERVAL_MASK		(0x3 << 3)
 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS	(0x0 << 3)
@@ -204,7 +204,7 @@
 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS	(0x3 << 3)
 #define AUX_HW_RETRY_COUNT_SEL(x)		(((x) & 0x7) << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_1 */
+/* ANALOGIX_DP_COMMON_INT_STA_1 */
 #define VSYNC_DET				(0x1 << 7)
 #define PLL_LOCK_CHG				(0x1 << 6)
 #define SPDIF_ERR				(0x1 << 5)
@@ -214,19 +214,19 @@
 #define VID_CLK_CHG				(0x1 << 1)
 #define SW_INT					(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_2 */
+/* ANALOGIX_DP_COMMON_INT_STA_2 */
 #define ENC_EN_CHG				(0x1 << 6)
 #define HW_BKSV_RDY				(0x1 << 3)
 #define HW_SHA_DONE				(0x1 << 2)
 #define HW_AUTH_STATE_CHG			(0x1 << 1)
 #define HW_AUTH_DONE				(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_3 */
+/* ANALOGIX_DP_COMMON_INT_STA_3 */
 #define AFIFO_UNDER				(0x1 << 7)
 #define AFIFO_OVER				(0x1 << 6)
 #define R0_CHK_FLAG				(0x1 << 5)
 
-/* EXYNOS_DP_COMMON_INT_STA_4 */
+/* ANALOGIX_DP_COMMON_INT_STA_4 */
 #define PSR_ACTIVE				(0x1 << 7)
 #define PSR_INACTIVE				(0x1 << 6)
 #define SPDIF_BI_PHASE_ERR			(0x1 << 5)
@@ -234,29 +234,29 @@
 #define HPD_LOST				(0x1 << 1)
 #define PLUG					(0x1 << 0)
 
-/* EXYNOS_DP_INT_STA */
+/* ANALOGIX_DP_INT_STA */
 #define INT_HPD					(0x1 << 6)
 #define HW_TRAINING_FINISH			(0x1 << 5)
 #define RPLY_RECEIV				(0x1 << 1)
 #define AUX_ERR					(0x1 << 0)
 
-/* EXYNOS_DP_INT_CTL */
+/* ANALOGIX_DP_INT_CTL */
 #define SOFT_INT_CTRL				(0x1 << 2)
 #define INT_POL1				(0x1 << 1)
 #define INT_POL0				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_1 */
+/* ANALOGIX_DP_SYS_CTL_1 */
 #define DET_STA					(0x1 << 2)
 #define FORCE_DET				(0x1 << 1)
 #define DET_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_2 */
+/* ANALOGIX_DP_SYS_CTL_2 */
 #define CHA_CRI(x)				(((x) & 0xf) << 4)
 #define CHA_STA					(0x1 << 2)
 #define FORCE_CHA				(0x1 << 1)
 #define CHA_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_3 */
+/* ANALOGIX_DP_SYS_CTL_3 */
 #define HPD_STATUS				(0x1 << 6)
 #define F_HPD					(0x1 << 5)
 #define HPD_CTRL				(0x1 << 4)
@@ -265,13 +265,13 @@
 #define F_VALID					(0x1 << 1)
 #define VALID_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_4 */
+/* ANALOGIX_DP_SYS_CTL_4 */
 #define FIX_M_AUD				(0x1 << 4)
 #define ENHANCED				(0x1 << 3)
 #define FIX_M_VID				(0x1 << 2)
 #define M_VID_UPDATE_CTRL			(0x3 << 0)
 
-/* EXYNOS_DP_TRAINING_PTN_SET */
+/* ANALOGIX_DP_TRAINING_PTN_SET */
 #define SCRAMBLER_TYPE				(0x1 << 9)
 #define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
 #define SCRAMBLING_DISABLE			(0x1 << 5)
@@ -285,24 +285,24 @@
 #define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
 #define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
 
-/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+/* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */
 #define PRE_EMPHASIS_SET_MASK			(0x3 << 3)
 #define PRE_EMPHASIS_SET_SHIFT			(3)
 
-/* EXYNOS_DP_DEBUG_CTL */
+/* ANALOGIX_DP_DEBUG_CTL */
 #define PLL_LOCK				(0x1 << 4)
 #define F_PLL_LOCK				(0x1 << 3)
 #define PLL_LOCK_CTRL				(0x1 << 2)
 #define PN_INV					(0x1 << 0)
 
-/* EXYNOS_DP_PLL_CTL */
+/* ANALOGIX_DP_PLL_CTL */
 #define DP_PLL_PD				(0x1 << 7)
 #define DP_PLL_RESET				(0x1 << 6)
 #define DP_PLL_LOOP_BIT_DEFAULT			(0x1 << 4)
 #define DP_PLL_REF_BIT_1_1250V			(0x5 << 0)
 #define DP_PLL_REF_BIT_1_2500V			(0x7 << 0)
 
-/* EXYNOS_DP_PHY_PD */
+/* ANALOGIX_DP_PHY_PD */
 #define DP_PHY_PD				(0x1 << 5)
 #define AUX_PD					(0x1 << 4)
 #define CH3_PD					(0x1 << 3)
@@ -310,28 +310,28 @@
 #define CH1_PD					(0x1 << 1)
 #define CH0_PD					(0x1 << 0)
 
-/* EXYNOS_DP_PHY_TEST */
+/* ANALOGIX_DP_PHY_TEST */
 #define MACRO_RST				(0x1 << 5)
 #define CH1_TEST				(0x1 << 1)
 #define CH0_TEST				(0x1 << 0)
 
-/* EXYNOS_DP_AUX_CH_STA */
+/* ANALOGIX_DP_AUX_CH_STA */
 #define AUX_BUSY				(0x1 << 4)
 #define AUX_STATUS_MASK				(0xf << 0)
 
-/* EXYNOS_DP_AUX_CH_DEFER_CTL */
+/* ANALOGIX_DP_AUX_CH_DEFER_CTL */
 #define DEFER_CTRL_EN				(0x1 << 7)
 #define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
 
-/* EXYNOS_DP_AUX_RX_COMM */
+/* ANALOGIX_DP_AUX_RX_COMM */
 #define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
 #define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
 
-/* EXYNOS_DP_BUFFER_DATA_CTL */
+/* ANALOGIX_DP_BUFFER_DATA_CTL */
 #define BUF_CLR					(0x1 << 7)
 #define BUF_DATA_COUNT(x)			(((x) & 0x1f) << 0)
 
-/* EXYNOS_DP_AUX_CH_CTL_1 */
+/* ANALOGIX_DP_AUX_CH_CTL_1 */
 #define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
 #define AUX_TX_COMM_MASK			(0xf << 0)
 #define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
@@ -340,20 +340,20 @@
 #define AUX_TX_COMM_WRITE			(0x0 << 0)
 #define AUX_TX_COMM_READ			(0x1 << 0)
 
-/* EXYNOS_DP_AUX_ADDR_7_0 */
+/* ANALOGIX_DP_AUX_ADDR_7_0 */
 #define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_15_8 */
+/* ANALOGIX_DP_AUX_ADDR_15_8 */
 #define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_19_16 */
+/* ANALOGIX_DP_AUX_ADDR_19_16 */
 #define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
 
-/* EXYNOS_DP_AUX_CH_CTL_2 */
+/* ANALOGIX_DP_AUX_CH_CTL_2 */
 #define ADDR_ONLY				(0x1 << 1)
 #define AUX_EN					(0x1 << 0)
 
-/* EXYNOS_DP_SOC_GENERAL_CTL */
+/* ANALOGIX_DP_SOC_GENERAL_CTL */
 #define AUDIO_MODE_SPDIF_MODE			(0x1 << 8)
 #define AUDIO_MODE_MASTER_MODE			(0x0 << 8)
 #define MASTER_VIDEO_INTERLACE_EN		(0x1 << 4)
@@ -363,4 +363,4 @@
 #define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
 #define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
 
-#endif /* _EXYNOS_DP_REG_H */
+#endif /* _ANALOGIX_DP_REG_H */
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index bd1a415..5f74f80 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -55,8 +55,9 @@ config DRM_EXYNOS_DSI
 	  This enables support for Exynos MIPI-DSI device.
 
 config DRM_EXYNOS_DP
-	bool "EXYNOS DRM DP driver support"
+	bool "EXYNOS specific extensions for Analogix DP driver"
 	depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON)
+	select DRM_ANALOGIX_DP
 	default DRM_EXYNOS
 	select DRM_PANEL
 	help
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index 02aecfe..4453798 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -13,7 +13,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON)	+= exynos5433_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON)	+= exynos7_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DPI)	+= exynos_drm_dpi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DSI)	+= exynos_drm_dsi.o
-exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o exynos_dp_reg.o
+exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)	+= exynos_hdmi.o exynos_mixer.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI)	+= exynos_drm_vidi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_G2D)	+= exynos_drm_g2d.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
new file mode 100644
index 0000000..726d5b5
--- /dev/null
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -0,0 +1,366 @@
+/*
+ * Samsung SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_graph.h>
+#include <video/of_display_timing.h>
+#include <video/of_videomode.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+
+#include <drm/bridge/analogix_dp.h>
+#include <drm/exynos_drm.h>
+
+#include "exynos_drm_crtc.h"
+
+#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
+
+struct exynos_dp_device {
+	struct drm_encoder         encoder;
+	struct drm_connector       connector;
+	struct drm_bridge          *ptn_bridge;
+	struct drm_device          *drm_dev;
+	struct device              *dev;
+
+	struct exynos_drm_panel_info priv;
+	struct analogix_dp_plat_data plat_data;
+};
+
+int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
+				bool enable)
+{
+	struct exynos_dp_device *dp = to_dp(plat_data);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct exynos_drm_crtc *crtc;
+
+	if (!encoder)
+		return -1;
+
+	crtc = to_exynos_crtc(encoder->crtc);
+	if (crtc && crtc->ops && crtc->ops->clock_enable)
+		crtc->ops->clock_enable(crtc, enable);
+
+	return 0;
+}
+
+static int exynos_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	return exynos_dp_crtc_clock_enable(plat_data, true);
+}
+
+static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
+{
+	return exynos_dp_crtc_clock_enable(plat_data, false);
+}
+
+static int exynos_dp_get_modes(struct drm_connector *connector)
+{
+	struct exynos_dp_device *dp = to_dp(connector);
+	struct drm_display_mode *mode;
+	int num_modes = 0;
+
+	num_modes += analogix_dp_get_modes(dp->dev);
+
+	if (dp->plat_data.panel)
+		return num_modes;
+
+	mode = drm_mode_create(connector->dev);
+	if (!mode) {
+		DRM_ERROR("failed to create a new display mode.\n");
+		return num_modes;
+	}
+
+	drm_display_mode_from_videomode(&dp->priv.vm, mode);
+	mode->width_mm = dp->priv.width_mm;
+	mode->height_mm = dp->priv.height_mm;
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_set_name(mode);
+	drm_mode_probed_add(connector, mode);
+
+	return num_modes + 1;
+}
+
+static struct drm_encoder *
+exynos_dp_best_encoder(struct drm_connector *connector)
+{
+	struct exynos_dp_device *dp = to_dp(connector);
+
+	return &dp->encoder;
+}
+
+static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
+	.get_modes = exynos_dp_get_modes,
+	.best_encoder = exynos_dp_best_encoder,
+};
+
+static enum drm_connector_status
+exynos_dp_detect(struct drm_connector *connector, bool force)
+{
+	struct exynos_dp_device *dp = to_dp(connector);
+
+	return analogix_dp_detect(dp->dev, force);
+}
+
+static void exynos_dp_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static struct drm_connector_funcs exynos_dp_connector_funcs = {
+	.dpms = drm_atomic_helper_connector_dpms,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.detect = exynos_dp_detect,
+	.destroy = exynos_dp_connector_destroy,
+	.reset = drm_atomic_helper_connector_reset,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+				   struct drm_bridge *bridge)
+{
+	struct exynos_dp_device *dp = to_dp(plat_data);
+	struct drm_connector *connector = &dp->connector;
+	struct drm_encoder *encoder = &dp->encoder;
+	int ret;
+
+	/* Pre-empt DP connector creation if there's a bridge */
+	if (dp->ptn_bridge) {
+		bridge->next = dp->ptn_bridge;
+		dp->ptn_bridge->encoder = encoder;
+		ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
+		if (ret) {
+			DRM_ERROR("Failed to attach bridge to drm\n");
+			bridge->next = NULL;
+			return ret;
+		}
+	}
+
+	connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+	ret = drm_connector_init(dp->drm_dev, connector,
+				 &exynos_dp_connector_funcs,
+				 DRM_MODE_CONNECTOR_eDP);
+	if (ret) {
+		DRM_ERROR("Failed to initialize connector with drm\n");
+		return ret;
+	}
+
+	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
+	drm_connector_register(connector);
+	drm_mode_connector_attach_encoder(connector, encoder);
+
+	dp->plat_data.connector = connector;
+
+	return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+				 const struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
+static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
+	.mode_fixup = exynos_dp_mode_fixup,
+	.mode_set = exynos_dp_mode_set,
+	.enable = exynos_dp_enable,
+	.disable = exynos_dp_disable,
+};
+
+static struct drm_encoder_funcs exynos_dp_encoder_funcs = {
+	.destroy = drm_encoder_cleanup,
+};
+
+static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
+{
+	int ret;
+
+	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
+			       OF_USE_NATIVE_MODE);
+	if (ret) {
+		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
+		return ret;
+	}
+	return 0;
+}
+
+static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
+{
+	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = data;
+	int pipe, ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	dp->dev = dev;
+	dp->drm_dev = drm_dev;
+
+	dp->plat_data.dev_type = EXYNOS_DP;
+	dp->plat_data.power_on = exynos_dp_poweron;
+	dp->plat_data.power_off = exynos_dp_poweroff;
+	dp->plat_data.attach = exynos_dp_bridge_attach;
+
+	if (!dp->plat_data.panel || !dp->ptn_bridge) {
+		ret = exynos_dp_dt_parse_panel(dp);
+		if (ret)
+			return ret;
+	}
+
+	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
+						  EXYNOS_DISPLAY_TYPE_LCD);
+	if (pipe < 0)
+		return pipe;
+
+	encoder->possible_crtcs = 1 << pipe;
+
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
+			 DRM_MODE_ENCODER_TMDS);
+
+	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
+
+	dp->plat_data.encoder = encoder;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
+}
+
+static void exynos_dp_unbind(struct device *dev, struct device *master,
+			     void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops exynos_dp_ops = {
+	.bind	= exynos_dp_bind,
+	.unbind	= exynos_dp_unbind,
+};
+
+static int exynos_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *bridge_node, *endpoint;
+	struct exynos_dp_device *dp;
+
+	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
+			  GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver would take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	panel_node = of_parse_phandle(dev->of_node, "panel", 0);
+	if (panel_node) {
+		dp->plat_data.panel = of_drm_find_panel(panel_node);
+		of_node_put(panel_node);
+		if (!dp->plat_data.panel)
+			return -EPROBE_DEFER;
+	}
+
+	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
+	if (endpoint) {
+		bridge_node = of_graph_get_remote_port_parent(endpoint);
+		if (bridge_node) {
+			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
+			of_node_put(bridge_node);
+			if (!dp->ptn_bridge)
+				return -EPROBE_DEFER;
+		} else {
+			return -EPROBE_DEFER;
+		}
+	}
+
+	return component_add(&pdev->dev, &exynos_dp_ops);
+}
+
+static int exynos_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &exynos_dp_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int exynos_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops exynos_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
+};
+
+static const struct of_device_id exynos_dp_match[] = {
+	{ .compatible = "samsung,exynos5-dp" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, exynos_dp_match);
+
+struct platform_driver dp_driver = {
+	.probe		= exynos_dp_probe,
+	.remove		= exynos_dp_remove,
+	.driver		= {
+		.name	= "exynos-dp",
+		.owner	= THIS_MODULE,
+		.pm	= &exynos_dp_pm_ops,
+		.of_match_table = exynos_dp_match,
+	},
+};
+
+MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
+MODULE_DESCRIPTION("Samsung Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
deleted file mode 100644
index 66eec4b..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Header file for Samsung DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef _EXYNOS_DP_CORE_H
-#define _EXYNOS_DP_CORE_H
-
-#include <drm/drm_crtc.h>
-#include <drm/drm_dp_helper.h>
-#include <drm/exynos_drm.h>
-
-#include "exynos_drm_drv.h"
-
-#define DP_TIMEOUT_LOOP_COUNT 100
-#define MAX_CR_LOOP 5
-#define MAX_EQ_LOOP 5
-
-enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
-};
-
-enum link_lane_count_type {
-	LANE_COUNT1 = 1,
-	LANE_COUNT2 = 2,
-	LANE_COUNT4 = 4
-};
-
-enum link_training_state {
-	START,
-	CLOCK_RECOVERY,
-	EQUALIZER_TRAINING,
-	FINISHED,
-	FAILED
-};
-
-enum voltage_swing_level {
-	VOLTAGE_LEVEL_0,
-	VOLTAGE_LEVEL_1,
-	VOLTAGE_LEVEL_2,
-	VOLTAGE_LEVEL_3,
-};
-
-enum pre_emphasis_level {
-	PRE_EMPHASIS_LEVEL_0,
-	PRE_EMPHASIS_LEVEL_1,
-	PRE_EMPHASIS_LEVEL_2,
-	PRE_EMPHASIS_LEVEL_3,
-};
-
-enum pattern_set {
-	PRBS7,
-	D10_2,
-	TRAINING_PTN1,
-	TRAINING_PTN2,
-	DP_NONE
-};
-
-enum color_space {
-	COLOR_RGB,
-	COLOR_YCBCR422,
-	COLOR_YCBCR444
-};
-
-enum color_depth {
-	COLOR_6,
-	COLOR_8,
-	COLOR_10,
-	COLOR_12
-};
-
-enum color_coefficient {
-	COLOR_YCBCR601,
-	COLOR_YCBCR709
-};
-
-enum dynamic_range {
-	VESA,
-	CEA
-};
-
-enum pll_status {
-	PLL_UNLOCKED,
-	PLL_LOCKED
-};
-
-enum clock_recovery_m_value_type {
-	CALCULATED_M,
-	REGISTER_M
-};
-
-enum video_timing_recognition_type {
-	VIDEO_TIMING_FROM_CAPTURE,
-	VIDEO_TIMING_FROM_REGISTER
-};
-
-enum analog_power_block {
-	AUX_BLOCK,
-	CH0_BLOCK,
-	CH1_BLOCK,
-	CH2_BLOCK,
-	CH3_BLOCK,
-	ANALOG_TOTAL,
-	POWER_ALL
-};
-
-enum dp_irq_type {
-	DP_IRQ_TYPE_HP_CABLE_IN,
-	DP_IRQ_TYPE_HP_CABLE_OUT,
-	DP_IRQ_TYPE_HP_CHANGE,
-	DP_IRQ_TYPE_UNKNOWN,
-};
-
-struct video_info {
-	char *name;
-
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
-
-	enum color_space color_space;
-	enum dynamic_range dynamic_range;
-	enum color_coefficient ycbcr_coeff;
-	enum color_depth color_depth;
-
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
-};
-
-struct link_train {
-	int eq_loop;
-	int cr_loop[4];
-
-	u8 link_rate;
-	u8 lane_count;
-	u8 training_lane[4];
-
-	enum link_training_state lt_state;
-};
-
-struct exynos_dp_device {
-	struct drm_encoder	encoder;
-	struct device		*dev;
-	struct drm_device	*drm_dev;
-	struct drm_connector	connector;
-	struct drm_panel	*panel;
-	struct drm_bridge	*bridge;
-	struct drm_bridge	*ptn_bridge;
-	struct clk		*clock;
-	unsigned int		irq;
-	void __iomem		*reg_base;
-
-	struct video_info	*video_info;
-	struct link_train	link_train;
-	struct work_struct	hotplug_work;
-	struct phy		*phy;
-	int			dpms_mode;
-	int			hpd_gpio;
-
-	struct exynos_drm_panel_info priv;
-};
-
-/* exynos_dp_reg.c */
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_stop_video(struct exynos_dp_device *dp);
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
-void exynos_dp_reset(struct exynos_dp_device *dp);
-void exynos_dp_swreset(struct exynos_dp_device *dp);
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable);
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
-void exynos_dp_init_hpd(struct exynos_dp_device *dp);
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
-void exynos_dp_reset_aux(struct exynos_dp_device *dp);
-void exynos_dp_init_aux(struct exynos_dp_device *dp);
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern);
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
-void exynos_dp_reset_macro(struct exynos_dp_device *dp);
-void exynos_dp_init_video(struct exynos_dp_device *dp);
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_start_video(struct exynos_dp_device *dp);
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
-#endif /* _EXYNOS_DP_CORE_H */
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
deleted file mode 100644
index c1f87a2..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
+++ /dev/null
@@ -1,1263 +0,0 @@
-/*
- * Samsung DP (Display port) register interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-
-#include "exynos_dp_core.h"
-#include "exynos_dp_reg.h"
-
-#define COMMON_INT_MASK_1	0
-#define COMMON_INT_MASK_2	0
-#define COMMON_INT_MASK_3	0
-#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
-#define INT_STA_MASK		INT_HPD
-
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg |= HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg &= ~HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	}
-}
-
-void exynos_dp_stop_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg &= ~VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable)
-		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
-	else
-		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
-
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
-}
-
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = TX_TERMINAL_CTRL_50_OHM;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
-
-	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
-
-	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
-
-	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
-		TX_CUR1_2X | TX_CUR_16_MA;
-	writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
-
-	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
-		CH1_AMP_400_MV | CH0_AMP_400_MV;
-	writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
-}
-
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
-{
-	/* Set interrupt pin assertion polarity as high */
-	writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
-
-	/* Clear pending regisers */
-	writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-	writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
-	writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
-	writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-	writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* 0:mask,1: unmask */
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-	writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-void exynos_dp_reset(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	exynos_dp_stop_video(dp);
-	exynos_dp_enable_video_mute(dp, 0);
-
-	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
-		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
-		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
-		SERDES_FIFO_FUNC_EN_N |
-		LS_CLK_DOMAIN_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-
-	usleep_range(20, 30);
-
-	exynos_dp_lane_swap(dp, 0);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
-	writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
-
-	writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
-	writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
-
-	writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
-	writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
-
-	writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
-	writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
-
-	writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_swreset(struct exynos_dp_device *dp)
-{
-	writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
-}
-
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* 0: mask, 1: unmask */
-	reg = COMMON_INT_MASK_1;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-
-	reg = COMMON_INT_MASK_2;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-
-	reg = COMMON_INT_MASK_3;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-
-	reg = COMMON_INT_MASK_4;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-
-	reg = INT_STA_MASK;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	if (reg & PLL_LOCK)
-		return PLL_LOCKED;
-	else
-		return PLL_UNLOCKED;
-}
-
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg |= DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg &= ~DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	}
-}
-
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
-{
-	u32 reg;
-
-	switch (block) {
-	case AUX_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH0_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH1_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH2_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH3_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case ANALOG_TOTAL:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case POWER_ALL:
-		if (enable) {
-			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
-				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
-{
-	u32 reg;
-	int timeout_loop = 0;
-
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
-
-	reg = PLL_LOCK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-
-	/* Power up PLL */
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-		exynos_dp_set_pll_power_down(dp, 0);
-
-		while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-			timeout_loop++;
-			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-				dev_err(dp->dev, "failed to get pll lock status\n");
-				return;
-			}
-			usleep_range(10, 20);
-		}
-	}
-
-	/* Enable Serdes FIFO function and Link symbol clock domain module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
-		| AUX_FUNC_EN_N);
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-	reg = INT_HPD;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-}
-
-void exynos_dp_init_hpd(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	exynos_dp_clear_hotplug_interrupts(dp);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	reg &= ~(F_HPD | HPD_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-}
-
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		reg = gpio_get_value(dp->hpd_gpio);
-		if (reg)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-		else
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-	} else {
-		/* Parse hotplug interrupt status register */
-		reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-		if (reg & PLUG)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-
-		if (reg & HPD_LOST)
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-
-		if (reg & HOTPLUG_CHG)
-			return DP_IRQ_TYPE_HP_CHANGE;
-
-		return DP_IRQ_TYPE_UNKNOWN;
-	}
-}
-
-void exynos_dp_reset_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Disable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg |= AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_init_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Clear inerrupts related to AUX channel */
-	reg = RPLY_RECEIV | AUX_ERR;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	exynos_dp_reset_aux(dp);
-
-	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
-
-	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
-	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
-
-	/* Enable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		if (gpio_get_value(dp->hpd_gpio))
-			return 0;
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-		if (reg & HPD_STATUS)
-			return 0;
-	}
-
-	return -EINVAL;
-}
-
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-}
-
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
-{
-	int reg;
-	int retval = 0;
-	int timeout_loop = 0;
-
-	/* Enable AUX CH operation */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-	reg |= AUX_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-	/* Is AUX CH command reply received? */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	while (!(reg & RPLY_RECEIV)) {
-		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "AUX CH command reply failed!\n");
-			return -ETIMEDOUT;
-		}
-		reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-		usleep_range(10, 11);
-	}
-
-	/* Clear interrupt source for AUX CH command reply */
-	writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* Clear interrupt source for AUX CH access error */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	if (reg & AUX_ERR) {
-		writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
-		return -EREMOTEIO;
-	}
-
-	/* Check AUX CH error access status */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
-	if ((reg & AUX_STATUS_MASK) != 0) {
-		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
-			reg & AUX_STATUS_MASK);
-		return -EREMOTEIO;
-	}
-
-	return retval;
-}
-
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/* Write data buffer */
-		reg = (unsigned int)data;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-		/*
-		 * Set DisplayPort transaction and write 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/*
-		 * Set DisplayPort transaction and read 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	/* Read data buffer */
-	reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-	*data = (unsigned char)(reg & 0xff);
-
-	return retval;
-}
-
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-			     cur_data_idx++) {
-				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
-			}
-
-			/*
-			 * Set DisplayPort transaction and write
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		/* AUX CH Request Transaction process */
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			/*
-			 * Set DisplayPort transaction and read
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-		    cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			data[start_offset + cur_data_idx] =
-				(unsigned char)reg;
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
-{
-	u32 reg;
-	int retval;
-
-	/* Set EDID device address */
-	reg = device_addr;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-	/* Set offset from base address of EDID device */
-	writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	/*
-	 * Set I2C transaction and write address
-	 * If bit 3 is 1, DisplayPort transaction.
-	 * If Bit 3 is 0, I2C transaction.
-	 */
-	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
-		AUX_TX_COMM_WRITE;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction(dp);
-	if (retval != 0)
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select EDID device */
-		retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
-		if (retval != 0)
-			continue;
-
-		/*
-		 * Set I2C transaction and read data
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_I2C_TRANSACTION |
-			AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	/* Read data */
-	if (retval == 0)
-		*data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
-{
-	u32 reg;
-	unsigned int i, j;
-	unsigned int cur_data_idx;
-	unsigned int defer = 0;
-	int retval = 0;
-
-	for (i = 0; i < count; i += 16) {
-		for (j = 0; j < 3; j++) {
-			/* Clear AUX CH data buffer */
-			reg = BUF_CLR;
-			writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-			/* Set normal AUX CH command */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-			reg &= ~ADDR_ONLY;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-			/*
-			 * If Rx sends defer, Tx sends only reads
-			 * request without sending address
-			 */
-			if (!defer)
-				retval = exynos_dp_select_i2c_device(dp,
-						device_addr, reg_addr + i);
-			else
-				defer = 0;
-
-			if (retval == 0) {
-				/*
-				 * Set I2C transaction and write data
-				 * If bit 3 is 1, DisplayPort transaction.
-				 * If Bit 3 is 0, I2C transaction.
-				 */
-				reg = AUX_LENGTH(16) |
-					AUX_TX_COMM_I2C_TRANSACTION |
-					AUX_TX_COMM_READ;
-				writel(reg, dp->reg_base +
-					EXYNOS_DP_AUX_CH_CTL_1);
-
-				/* Start AUX transaction */
-				retval = exynos_dp_start_aux_transaction(dp);
-				if (retval == 0)
-					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
-			}
-			/* Check if Rx sends defer */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
-			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
-				dev_err(dp->dev, "Defer: %d\n\n", reg);
-				defer = 1;
-			}
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			edid[i + cur_data_idx] = (unsigned char)reg;
-		}
-	}
-
-	return retval;
-}
-
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
-{
-	u32 reg;
-
-	reg = bwtype;
-	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
-		writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-}
-
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-	*bwtype = reg;
-}
-
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
-{
-	u32 reg;
-
-	reg = count;
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-}
-
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-	*count = reg;
-}
-
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	}
-}
-
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern)
-{
-	u32 reg;
-
-	switch (pattern) {
-	case PRBS7:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case D10_2:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN1:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN2:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case DP_NONE:
-		reg = SCRAMBLING_ENABLE |
-			LINK_QUAL_PATTERN_SET_DISABLE |
-			SW_TRAINING_PATTERN_SET_NORMAL;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	return reg;
-}
-
-void exynos_dp_reset_macro(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
-	reg |= MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	/* 10 us is the minimum reset time. */
-	usleep_range(10, 20);
-
-	reg &= ~MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-}
-
-void exynos_dp_init_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = CHA_CRI(4) | CHA_CTRL;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
-}
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
-
-	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
-		reg |= IN_YC_COEFFI_ITU709;
-	else
-		reg |= IN_YC_COEFFI_ITU601;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-}
-
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	if (!(reg & DET_STA)) {
-		dev_dbg(dp->dev, "Input stream clock not detected.\n");
-		return -EINVAL;
-	}
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
-
-	if (reg & CHA_STA) {
-		dev_dbg(dp->dev, "Input stream clk is changing\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
-{
-	u32 reg;
-
-	if (type == REGISTER_M) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg = m_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
-		reg = (m_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
-		reg = (m_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
-
-		reg = n_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
-		reg = (n_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
-		reg = (n_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
-	} else  {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
-		writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
-	}
-}
-
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
-{
-	u32 reg;
-
-	if (type == VIDEO_TIMING_FROM_CAPTURE) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg &= ~FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg |= FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	}
-}
-
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MODE_SLAVE_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	}
-}
-
-void exynos_dp_start_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg |= VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	if (!(reg & STRM_VALID)) {
-		dev_dbg(dp->dev, "Input video stream is not detected.\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
-	reg |= MASTER_VID_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-	writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg &= ~SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
-
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg |= SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
new file mode 100644
index 0000000..134638af
--- /dev/null
+++ b/include/drm/bridge/analogix_dp.h
@@ -0,0 +1,41 @@
+/*
+ * Analogix DP (Display Port) Core interface driver.
+ *
+ * Copyright (C) 2015 Rockchip Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _ANALOGIX_DP_H_
+#define _ANALOGIX_DP_H_
+
+#include <drm/drm_crtc.h>
+
+enum analogix_dp_devtype {
+	EXYNOS_DP,
+};
+
+struct analogix_dp_plat_data {
+	enum analogix_dp_devtype dev_type;
+	struct drm_panel *panel;
+	struct drm_encoder *encoder;
+	struct drm_connector *connector;
+
+	int (*power_on)(struct analogix_dp_plat_data *);
+	int (*power_off)(struct analogix_dp_plat_data *);
+	int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *);
+};
+
+enum drm_connector_status analogix_dp_detect(struct device *dev, bool force);
+int analogix_dp_get_modes(struct device *dev);
+
+int analogix_dp_resume(struct device *dev);
+int analogix_dp_suspend(struct device *dev);
+
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct analogix_dp_plat_data *plat_data);
+void analogix_dp_unbind(struct device *dev, struct device *master, void *data);
+
+#endif /* _ANALOGIX_DP_H_ */
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
@ 2015-09-22  7:29     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:29 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe-6d6DIl74uiNBDgjK7y7TUQ, Krzysztof Kozlowski,
	Rob Herring
  Cc: David Airlie, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Yakir Yang, Gustavo Padovan,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Russell King,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Sean Paul, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kumar Gala,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan

Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.

Beside the new analogix_dp driver would export four hooks.
"analogix_dp_bind()" and "analogix_dp_unbind()"
"analogix_dp_detect()" and "analogix_dp_get_modes()"

The bind/unbind symbols is used for analogix platform driver to connect
with analogix_dp core driver. And the detect/get_modes is used for analogix
platform driver to init the connector.

They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
  the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
  attch function. Cause once platform failed at attach, core driver should
  still failed, so no need to init connector before platform attached (Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
  patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)

Changes in v4:
- Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
- Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
- Create a separate folder for analogix code in bridge/ (Archit)

Changes in v3:
- Move exynos's video_timing code to analogix_dp-exynos platform driver,
  add get_modes method to struct analogix_dp_plat_data. (Thierry)
- Rename some "samsung*" dts propery to "analogix*". (Heiko)

Changes in v2:
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell

 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 .../analogix/analogix_dp_core.c}                   |  768 +++++-------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  277 +++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1263 ++++++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  258 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  366 ++++++
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 -----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 --------------------
 include/drm/bridge/analogix_dp.h                   |   41 +
 14 files changed, 2379 insertions(+), 2152 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 rename drivers/gpu/drm/{exynos/exynos_dp_core.c => bridge/analogix/analogix_dp_core.c} (50%)
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (64%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 include/drm/bridge/analogix_dp.h

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 2de52a5..7b5b77a 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -29,4 +29,6 @@ config DRM_PARADE_PS8622
 	---help---
 	  Parade eDP-LVDS bridge chip driver.
 
+source "drivers/gpu/drm/bridge/analogix/Kconfig"
+
 endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index e2eef1c..5366c6b 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -3,3 +3,4 @@ ccflags-y := -Iinclude/drm
 obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
new file mode 100644
index 0000000..5ff6551
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -0,0 +1,4 @@
+config DRM_ANALOGIX_DP
+	tristate
+	depends on DRM
+	select DRM_KMS_HELPER
diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
new file mode 100644
index 0000000..9107b86
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
similarity index 50%
rename from drivers/gpu/drm/exynos/exynos_dp_core.c
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index e0818c1..8a7ba12 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1,14 +1,14 @@
 /*
- * Samsung SoC DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
+* Analogix DP (Display Port) core interface driver.
+*
+* Copyright (C) 2012 Samsung Electronics Co., Ltd.
+* Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2 of the License, or (at your
+* option) any later version.
+*/
 
 #include <linux/module.h>
 #include <linux/platform_device.h>
@@ -18,65 +18,48 @@
 #include <linux/interrupt.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
-#include <linux/of_graph.h>
 #include <linux/gpio.h>
 #include <linux/component.h>
 #include <linux/phy/phy.h>
-#include <video/of_display_timing.h>
-#include <video/of_videomode.h>
 
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
-#include <drm/drm_atomic_helper.h>
 #include <drm/drm_panel.h>
 
-#include "exynos_dp_core.h"
-#include "exynos_drm_crtc.h"
+#include <drm/bridge/analogix_dp.h>
 
-#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
-					connector)
-
-static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
-{
-	return to_exynos_crtc(dp->encoder.crtc);
-}
-
-static inline struct exynos_dp_device *encoder_to_dp(
-						struct drm_encoder *e)
-{
-	return container_of(e, struct exynos_dp_device, encoder);
-}
+#include "analogix_dp_core.h"
 
 struct bridge_init {
 	struct i2c_client *client;
 	struct device_node *node;
 };
 
-static void exynos_dp_init_dp(struct exynos_dp_device *dp)
+static void analogix_dp_init_dp(struct analogix_dp_device *dp)
 {
-	exynos_dp_reset(dp);
+	analogix_dp_reset(dp);
 
-	exynos_dp_swreset(dp);
+	analogix_dp_swreset(dp);
 
-	exynos_dp_init_analog_param(dp);
-	exynos_dp_init_interrupt(dp);
+	analogix_dp_init_analog_param(dp);
+	analogix_dp_init_interrupt(dp);
 
 	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_function(dp);
+	analogix_dp_enable_sw_function(dp);
 
-	exynos_dp_config_interrupt(dp);
-	exynos_dp_init_analog_func(dp);
+	analogix_dp_config_interrupt(dp);
+	analogix_dp_init_analog_func(dp);
 
-	exynos_dp_init_hpd(dp);
-	exynos_dp_init_aux(dp);
+	analogix_dp_init_hpd(dp);
+	analogix_dp_init_aux(dp);
 }
 
-static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
+static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (exynos_dp_get_plug_in_status(dp) != 0) {
+	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
@@ -88,7 +71,7 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
 	return 0;
 }
 
-static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
+static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 {
 	int i;
 	unsigned char sum = 0;
@@ -99,7 +82,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
 	return sum;
 }
 
-static int exynos_dp_read_edid(struct exynos_dp_device *dp)
+static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
 	unsigned char edid[EDID_BLOCK_LENGTH * 2];
 	unsigned int extend_block = 0;
@@ -114,7 +97,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 	 */
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 				EDID_EXTENSION_FLAG,
 				&extend_block);
 	if (retval)
@@ -124,7 +107,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -132,14 +115,14 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
+		sum = analogix_dp_calc_edid_check_sum(edid);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
 				I2C_EDID_DEVICE_ADDR,
 				EDID_BLOCK_LENGTH,
 				EDID_BLOCK_LENGTH,
@@ -148,19 +131,19 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
+		sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
 					&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_RESPONSE,
 				DP_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -168,7 +151,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_info(dp->dev, "EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
 				I2C_EDID_DEVICE_ADDR,
 				EDID_HEADER_PATTERN,
 				EDID_BLOCK_LENGTH,
@@ -177,20 +160,20 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
+		sum = analogix_dp_calc_edid_check_sum(edid);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp,
+		analogix_dp_read_byte_from_dpcd(dp,
 			DP_TEST_REQUEST,
 			&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
 				edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_RESPONSE,
 				DP_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -200,21 +183,21 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 	return 0;
 }
 
-static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
+static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 {
 	u8 buf[12];
 	int i;
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
 				12, buf);
 	if (retval)
 		return retval;
 
 	/* Read EDID */
 	for (i = 0; i < 3; i++) {
-		retval = exynos_dp_read_edid(dp);
+		retval = analogix_dp_read_edid(dp);
 		if (!retval)
 			break;
 	}
@@ -222,73 +205,73 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
+static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
 						bool enable)
 {
 	u8 data;
 
-	exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
 
 	if (enable)
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 			DP_LANE_COUNT_ENHANCED_FRAME_EN |
 			DPCD_LANE_COUNT_SET(data));
 	else
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 			DPCD_LANE_COUNT_SET(data));
 }
 
-static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
+static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
 {
 	u8 data;
 	int retval;
 
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 	retval = DPCD_ENHANCED_FRAME_CAP(data);
 
 	return retval;
 }
 
-static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
+static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 {
 	u8 data;
 
-	data = exynos_dp_is_enhanced_mode_available(dp);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, data);
-	exynos_dp_enable_enhanced_mode(dp, data);
+	data = analogix_dp_is_enhanced_mode_available(dp);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, data);
+	analogix_dp_enable_enhanced_mode(dp, data);
 }
 
-static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
+static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
-	exynos_dp_set_training_pattern(dp, DP_NONE);
+	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	exynos_dp_write_byte_to_dpcd(dp,
+	analogix_dp_write_byte_to_dpcd(dp,
 		DP_TRAINING_PATTERN_SET,
 		DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
+static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
 					int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
-		exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 		break;
 	case 1:
-		exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 		break;
 
 	case 2:
-		exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 		break;
 
 	case 3:
-		exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 		break;
 	}
 }
 
-static int exynos_dp_link_start(struct exynos_dp_device *dp)
+static int analogix_dp_link_start(struct analogix_dp_device *dp)
 {
 	u8 buf[4];
 	int lane, lane_count, pll_tries, retval;
@@ -302,25 +285,25 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		dp->link_train.cr_loop[lane] = 0;
 
 	/* Set link rate and count as you want to establish*/
-	exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
-	exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
+	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
 				2, buf);
 	if (retval)
 		return retval;
 
 	/* Set TX pre-emphasis to minimum */
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_lane_pre_emphasis(dp,
+		analogix_dp_set_lane_lane_pre_emphasis(dp,
 			PRE_EMPHASIS_LEVEL_0, lane);
 
 	/* Wait for PLL lock */
 	pll_tries = 0;
-	while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+	while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 		if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Wait for PLL lock timed out\n");
 			return -ETIMEDOUT;
@@ -331,10 +314,10 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 	}
 
 	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
+	analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 
 	/* Set RX training pattern */
-	retval = exynos_dp_write_byte_to_dpcd(dp,
+	retval = analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
 	if (retval)
@@ -344,13 +327,13 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 			lane_count, buf);
 
 	return retval;
 }
 
-static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
+static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
 	u8 link_value = link_status[lane>>1];
@@ -358,20 +341,20 @@ static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
 	return (link_value >> shift) & 0xf;
 }
 
-static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
+static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 {
 	int lane;
 	u8 lane_status;
 
 	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
 		if ((lane_status & DP_LANE_CR_DONE) == 0)
 			return -EINVAL;
 	}
 	return 0;
 }
 
-static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
+static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 				int lane_count)
 {
 	int lane;
@@ -381,7 +364,7 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 		return -EINVAL;
 
 	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
 		lane_status &= DP_CHANNEL_EQ_BITS;
 		if (lane_status != DP_CHANNEL_EQ_BITS)
 			return -EINVAL;
@@ -390,7 +373,7 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
+static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
 							int lane)
 {
 	int shift = (lane & 1) * 4;
@@ -399,7 +382,7 @@ static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 	return (link_value >> shift) & 0x3;
 }
 
-static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
+static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					u8 adjust_request[2],
 					int lane)
 {
@@ -409,45 +392,45 @@ static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
-static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
+static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 					u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
-		exynos_dp_set_lane0_link_training(dp, training_lane_set);
+		analogix_dp_set_lane0_link_training(dp, training_lane_set);
 		break;
 	case 1:
-		exynos_dp_set_lane1_link_training(dp, training_lane_set);
+		analogix_dp_set_lane1_link_training(dp, training_lane_set);
 		break;
 
 	case 2:
-		exynos_dp_set_lane2_link_training(dp, training_lane_set);
+		analogix_dp_set_lane2_link_training(dp, training_lane_set);
 		break;
 
 	case 3:
-		exynos_dp_set_lane3_link_training(dp, training_lane_set);
+		analogix_dp_set_lane3_link_training(dp, training_lane_set);
 		break;
 	}
 }
 
-static unsigned int exynos_dp_get_lane_link_training(
-				struct exynos_dp_device *dp,
+static unsigned int analogix_dp_get_lane_link_training(
+				struct analogix_dp_device *dp,
 				int lane)
 {
 	u32 reg;
 
 	switch (lane) {
 	case 0:
-		reg = exynos_dp_get_lane0_link_training(dp);
+		reg = analogix_dp_get_lane0_link_training(dp);
 		break;
 	case 1:
-		reg = exynos_dp_get_lane1_link_training(dp);
+		reg = analogix_dp_get_lane1_link_training(dp);
 		break;
 	case 2:
-		reg = exynos_dp_get_lane2_link_training(dp);
+		reg = analogix_dp_get_lane2_link_training(dp);
 		break;
 	case 3:
-		reg = exynos_dp_get_lane3_link_training(dp);
+		reg = analogix_dp_get_lane3_link_training(dp);
 		break;
 	default:
 		WARN_ON(1);
@@ -457,15 +440,15 @@ static unsigned int exynos_dp_get_lane_link_training(
 	return reg;
 }
 
-static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
+static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 {
-	exynos_dp_training_pattern_dis(dp);
-	exynos_dp_set_enhanced_mode(dp);
+	analogix_dp_training_pattern_dis(dp);
+	analogix_dp_set_enhanced_mode(dp);
 
 	dp->link_train.lt_state = FAILED;
 }
 
-static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
+static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
 					u8 adjust_request[2])
 {
 	int lane, lane_count;
@@ -473,9 +456,9 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
 
 	lane_count = dp->link_train.lane_count;
 	for (lane = 0; lane < lane_count; lane++) {
-		voltage_swing = exynos_dp_get_adjust_request_voltage(
+		voltage_swing = analogix_dp_get_adjust_request_voltage(
 						adjust_request, lane);
-		pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
+		pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 						adjust_request, lane);
 		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
@@ -489,7 +472,7 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
 	}
 }
 
-static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
+static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 {
 	int lane, lane_count, retval;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -499,21 +482,21 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
+	retval =  analogix_dp_read_bytes_from_dpcd(dp,
 			DP_LANE0_1_STATUS, 2, link_status);
 	if (retval)
 		return retval;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
+	retval =  analogix_dp_read_bytes_from_dpcd(dp,
 			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 	if (retval)
 		return retval;
 
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 		/* set training pattern 2 for EQ */
-		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
+		analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 
-		retval = exynos_dp_write_byte_to_dpcd(dp,
+		retval = analogix_dp_write_byte_to_dpcd(dp,
 				DP_TRAINING_PATTERN_SET,
 				DP_LINK_SCRAMBLING_DISABLE |
 				DP_TRAINING_PATTERN_2);
@@ -524,11 +507,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 		dp->link_train.lt_state = EQUALIZER_TRAINING;
 	} else {
 		for (lane = 0; lane < lane_count; lane++) {
-			training_lane = exynos_dp_get_lane_link_training(
+			training_lane = analogix_dp_get_lane_link_training(
 							dp, lane);
-			voltage_swing = exynos_dp_get_adjust_request_voltage(
+			voltage_swing = analogix_dp_get_adjust_request_voltage(
 							adjust_request, lane);
-			pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
+			pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 							adjust_request, lane);
 
 			if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
@@ -543,19 +526,19 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 				dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 					dp->link_train.cr_loop[lane],
 					voltage_swing, pre_emphasis);
-				exynos_dp_reduce_link_rate(dp);
+				analogix_dp_reduce_link_rate(dp);
 				return -EIO;
 			}
 		}
 	}
 
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
+		analogix_dp_set_lane_link_training(dp,
 			dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp,
+	retval = analogix_dp_write_bytes_to_dpcd(dp,
 			DP_TRAINING_LANE0_SET, lane_count,
 			dp->link_train.training_lane);
 	if (retval)
@@ -564,7 +547,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
+static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 {
 	int lane, lane_count, retval;
 	u32 reg;
@@ -574,46 +557,46 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
+	retval = analogix_dp_read_bytes_from_dpcd(dp,
 			DP_LANE0_1_STATUS, 2, link_status);
 	if (retval)
 		return retval;
 
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
-		exynos_dp_reduce_link_rate(dp);
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
+		analogix_dp_reduce_link_rate(dp);
 		return -EIO;
 	}
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
+	retval = analogix_dp_read_bytes_from_dpcd(dp,
 			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 	if (retval)
 		return retval;
 
-	retval = exynos_dp_read_byte_from_dpcd(dp,
+	retval = analogix_dp_read_byte_from_dpcd(dp,
 			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
 	if (retval)
 		return retval;
 
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 
-	if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
+	if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 		/* traing pattern Set to Normal */
-		exynos_dp_training_pattern_dis(dp);
+		analogix_dp_training_pattern_dis(dp);
 
 		dev_info(dp->dev, "Link Training success!\n");
 
-		exynos_dp_get_link_bandwidth(dp, &reg);
+		analogix_dp_get_link_bandwidth(dp, &reg);
 		dp->link_train.link_rate = reg;
 		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 			dp->link_train.link_rate);
 
-		exynos_dp_get_lane_count(dp, &reg);
+		analogix_dp_get_lane_count(dp, &reg);
 		dp->link_train.lane_count = reg;
 		dev_dbg(dp->dev, "final lane count = %.2x\n",
 			dp->link_train.lane_count);
 
 		/* set enhanced mode if available */
-		exynos_dp_set_enhanced_mode(dp);
+		analogix_dp_set_enhanced_mode(dp);
 		dp->link_train.lt_state = FINISHED;
 
 		return 0;
@@ -624,21 +607,21 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 		dev_err(dp->dev, "EQ Max loop\n");
-		exynos_dp_reduce_link_rate(dp);
+		analogix_dp_reduce_link_rate(dp);
 		return -EIO;
 	}
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
+		analogix_dp_set_lane_link_training(dp,
 			dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 			lane_count, dp->link_train.training_lane);
 
 	return retval;
 }
 
-static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
+static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 					u8 *bandwidth)
 {
 	u8 data;
@@ -647,11 +630,11 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
 }
 
-static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
+static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 					u8 *lane_count)
 {
 	u8 data;
@@ -660,11 +643,11 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 	 * For DP rev.1.1, Maximum number of Main Link lanes
 	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 	*lane_count = DPCD_MAX_LANE_COUNT(data);
 }
 
-static void exynos_dp_init_training(struct exynos_dp_device *dp,
+static void analogix_dp_init_training(struct analogix_dp_device *dp,
 			enum link_lane_count_type max_lane,
 			enum link_rate_type max_rate)
 {
@@ -672,11 +655,11 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 	 * the DP inter pair skew issue for at least 10 us
 	 */
-	exynos_dp_reset_macro(dp);
+	analogix_dp_reset_macro(dp);
 
 	/* Initialize by reading RX's DPCD */
-	exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
-	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
+	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
+	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
@@ -698,10 +681,10 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
 		dp->link_train.link_rate = max_rate;
 
 	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 }
 
-static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
+static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 {
 	int retval = 0, training_finished = 0;
 
@@ -711,17 +694,17 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 	while (!retval && !training_finished) {
 		switch (dp->link_train.lt_state) {
 		case START:
-			retval = exynos_dp_link_start(dp);
+			retval = analogix_dp_link_start(dp);
 			if (retval)
 				dev_err(dp->dev, "LT link start failed!\n");
 			break;
 		case CLOCK_RECOVERY:
-			retval = exynos_dp_process_clock_recovery(dp);
+			retval = analogix_dp_process_clock_recovery(dp);
 			if (retval)
 				dev_err(dp->dev, "LT CR failed!\n");
 			break;
 		case EQUALIZER_TRAINING:
-			retval = exynos_dp_process_equalizer_training(dp);
+			retval = analogix_dp_process_equalizer_training(dp);
 			if (retval)
 				dev_err(dp->dev, "LT EQ failed!\n");
 			break;
@@ -738,7 +721,7 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
+static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
 				u32 count,
 				u32 bwtype)
 {
@@ -746,8 +729,8 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 	int retval;
 
 	for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
-		exynos_dp_init_training(dp, count, bwtype);
-		retval = exynos_dp_sw_link_training(dp);
+		analogix_dp_init_training(dp, count, bwtype);
+		retval = analogix_dp_sw_link_training(dp);
 		if (retval == 0)
 			break;
 
@@ -757,24 +740,24 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 	return retval;
 }
 
-static int exynos_dp_config_video(struct exynos_dp_device *dp)
+static int analogix_dp_config_video(struct analogix_dp_device *dp)
 {
 	int retval = 0;
 	int timeout_loop = 0;
 	int done_count = 0;
 
-	exynos_dp_config_video_slave_mode(dp);
+	analogix_dp_config_video_slave_mode(dp);
 
-	exynos_dp_set_video_color_format(dp);
+	analogix_dp_set_video_color_format(dp);
 
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 		dev_err(dp->dev, "PLL is not locked yet.\n");
 		return -EINVAL;
 	}
 
 	for (;;) {
 		timeout_loop++;
-		if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
+		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
@@ -785,22 +768,22 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
 	}
 
 	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
+	analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 
 	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
+	analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 
 	/* Disable video mute */
-	exynos_dp_enable_video_mute(dp, 0);
+	analogix_dp_enable_video_mute(dp, 0);
 
 	/* Configure video slave mode */
-	exynos_dp_enable_video_master(dp, 0);
+	analogix_dp_enable_video_master(dp, 0);
 
 	timeout_loop = 0;
 
 	for (;;) {
 		timeout_loop++;
-		if (exynos_dp_is_video_stream_on(dp) == 0) {
+		if (analogix_dp_is_video_stream_on(dp) == 0) {
 			done_count++;
 			if (done_count > 10)
 				break;
@@ -821,47 +804,47 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
 {
 	u8 data;
 
 	if (enable) {
-		exynos_dp_enable_scrambling(dp);
+		analogix_dp_enable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp,
+		analogix_dp_read_byte_from_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
+		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
-		exynos_dp_disable_scrambling(dp);
+		analogix_dp_disable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp,
+		analogix_dp_read_byte_from_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
+		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 	}
 }
 
-static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
+static irqreturn_t analogix_dp_irq_handler(int irq, void *arg)
 {
-	struct exynos_dp_device *dp = arg;
+	struct analogix_dp_device *dp = arg;
 
 	enum dp_irq_type irq_type;
 
-	irq_type = exynos_dp_get_irq_type(dp);
+	irq_type = analogix_dp_get_irq_type(dp);
 	switch (irq_type) {
 	case DP_IRQ_TYPE_HP_CABLE_IN:
 		dev_dbg(dp->dev, "Received irq - cable in\n");
 		schedule_work(&dp->hotplug_work);
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	case DP_IRQ_TYPE_HP_CABLE_OUT:
 		dev_dbg(dp->dev, "Received irq - cable out\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	case DP_IRQ_TYPE_HP_CHANGE:
 		/*
@@ -870,7 +853,7 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 		 * only handle cable changes.
 		 */
 		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	default:
 		dev_err(dp->dev, "Received irq - unknown type!\n");
@@ -879,217 +862,160 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
-static void exynos_dp_hotplug(struct work_struct *work)
+static void analogix_dp_hotplug(struct work_struct *work)
 {
-	struct exynos_dp_device *dp;
+	struct analogix_dp_device *dp;
 
-	dp = container_of(work, struct exynos_dp_device, hotplug_work);
+	dp = container_of(work, struct analogix_dp_device, hotplug_work);
 
 	if (dp->drm_dev)
 		drm_helper_hpd_irq_event(dp->drm_dev);
 }
 
-static void exynos_dp_commit(struct drm_encoder *encoder)
+static void analogix_dp_commit(struct analogix_dp_device *dp)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
 	int ret;
 
 	/* Keep the panel disabled while we configure video */
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel))
+	if (dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel))
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = exynos_dp_detect_hpd(dp);
+	ret = analogix_dp_detect_hpd(dp);
 	if (ret) {
 		/* Cable has been disconnected, we're done */
 		return;
 	}
 
-	ret = exynos_dp_handle_edid(dp);
+	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
 		return;
 	}
 
-	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
+	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
 					dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
 	}
 
-	exynos_dp_enable_scramble(dp, 1);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
-	exynos_dp_enable_enhanced_mode(dp, 1);
+	analogix_dp_enable_scramble(dp, 1);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
+	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
-	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
+	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 
-	exynos_dp_init_video(dp);
-	ret = exynos_dp_config_video(dp);
+	analogix_dp_init_video(dp);
+	ret = analogix_dp_config_video(dp);
 	if (ret)
 		dev_err(dp->dev, "unable to config video\n");
 
 	/* Safe to enable the panel now */
-	if (dp->panel) {
-		if (drm_panel_enable(dp->panel))
+	if (dp->plat_data->panel) {
+		if (drm_panel_enable(dp->plat_data->panel))
 			DRM_ERROR("failed to enable the panel\n");
 	}
 
 	/* Enable video */
-	exynos_dp_start_video(dp);
+	analogix_dp_start_video(dp);
 }
 
-static enum drm_connector_status exynos_dp_detect(
-				struct drm_connector *connector, bool force)
+enum drm_connector_status analogix_dp_detect(struct device *dev, bool force)
 {
 	return connector_status_connected;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_detect);
 
-static void exynos_dp_connector_destroy(struct drm_connector *connector)
-{
-	drm_connector_unregister(connector);
-	drm_connector_cleanup(connector);
-}
-
-static struct drm_connector_funcs exynos_dp_connector_funcs = {
-	.dpms = drm_atomic_helper_connector_dpms,
-	.fill_modes = drm_helper_probe_single_connector_modes,
-	.detect = exynos_dp_detect,
-	.destroy = exynos_dp_connector_destroy,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static int exynos_dp_get_modes(struct drm_connector *connector)
+int analogix_dp_get_modes(struct device *dev)
 {
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
-	struct drm_display_mode *mode;
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+	int num_modes = 0;
 
-	if (dp->panel)
-		return drm_panel_get_modes(dp->panel);
-
-	mode = drm_mode_create(connector->dev);
-	if (!mode) {
-		DRM_ERROR("failed to create a new display mode.\n");
-		return 0;
-	}
+	if (dp->plat_data->panel)
+		num_modes += drm_panel_get_modes(dp->plat_data->panel);
 
-	drm_display_mode_from_videomode(&dp->priv.vm, mode);
-	mode->width_mm = dp->priv.width_mm;
-	mode->height_mm = dp->priv.height_mm;
-	connector->display_info.width_mm = mode->width_mm;
-	connector->display_info.height_mm = mode->height_mm;
-
-	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-	drm_mode_set_name(mode);
-	drm_mode_probed_add(connector, mode);
-
-	return 1;
+	return num_modes;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_get_modes);
 
-static struct drm_encoder *exynos_dp_best_encoder(
-			struct drm_connector *connector)
-{
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
-
-	return &dp->encoder;
-}
-
-static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
-	.get_modes = exynos_dp_get_modes,
-	.best_encoder = exynos_dp_best_encoder,
-};
-
-/* returns the number of bridges attached */
-static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
-		struct drm_encoder *encoder)
+static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
 {
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = dp->encoder;
 	int ret;
 
-	encoder->bridge->next = dp->ptn_bridge;
-	dp->ptn_bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
-	if (ret) {
-		DRM_ERROR("Failed to attach bridge to drm\n");
-		return ret;
+	if (!bridge->encoder) {
+		DRM_ERROR("Parent encoder object not found");
+		return -ENODEV;
 	}
 
-	return 0;
-}
+	encoder->bridge = bridge;
 
-static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
-{
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct drm_encoder *encoder = &dp->encoder;
-	struct drm_connector *connector = &dp->connector;
-	int ret;
-
-	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->ptn_bridge) {
-		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
-		if (!ret)
-			return 0;
+	/*
+	 * NOTE: the connector registration is implemented in analogix
+	 * platform driver, that to say connector would be exist after
+	 * plat_data->attch return, that's why we record the connector
+	 * point after plat attached.
+	 */
+	 if (dp->plat_data->attach) {
+		 ret = dp->plat_data->attach(dp->plat_data, bridge);
+		 if (ret) {
+			 DRM_ERROR("Failed at platform attch func\n");
+			 return ret;
+		 }
 	}
 
-	connector->polled = DRM_CONNECTOR_POLL_HPD;
+	dp->connector = dp->plat_data->connector;
 
-	ret = drm_connector_init(dp->drm_dev, connector,
-			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
-	if (ret) {
-		DRM_ERROR("Failed to initialize connector with drm\n");
-		return ret;
+	if (dp->plat_data->panel) {
+		ret = drm_panel_attach(dp->plat_data->panel, dp->connector);
+		if (ret) {
+			DRM_ERROR("Failed to attach panel\n");
+			return ret;
+		}
 	}
 
-	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
-	drm_connector_register(connector);
-	drm_mode_connector_attach_encoder(connector, encoder);
-
-	if (dp->panel)
-		ret = drm_panel_attach(dp->panel, &dp->connector);
-
-	return ret;
+	return 0;
 }
 
-static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
+static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
+	struct analogix_dp_device *dp = bridge->driver_private;
 
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->panel) {
-		if (drm_panel_prepare(dp->panel)) {
+	if (dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
 			DRM_ERROR("failed to setup the panel\n");
 			return;
 		}
 	}
 
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), true);
+	if (dp->plat_data->power_on)
+		dp->plat_data->power_on(dp->plat_data);
 
 	clk_prepare_enable(dp->clock);
 	phy_power_on(dp->phy);
-	exynos_dp_init_dp(dp);
+	analogix_dp_init_dp(dp);
 	enable_irq(dp->irq);
-	exynos_dp_commit(&dp->encoder);
+	analogix_dp_commit(dp);
 
 	dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
-static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
+static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
+	struct analogix_dp_device *dp = bridge->driver_private;
 
 	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel)) {
+	if (dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel)) {
 			DRM_ERROR("failed to disable the panel\n");
 			return;
 		}
@@ -1100,34 +1026,33 @@ static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 	phy_power_off(dp->phy);
 	clk_disable_unprepare(dp->clock);
 
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), false);
+	if (dp->plat_data->power_off)
+		dp->plat_data->power_off(dp->plat_data);
 
-	if (dp->panel) {
-		if (drm_panel_unprepare(dp->panel))
+	if (dp->plat_data->panel) {
+		if (drm_panel_unprepare(dp->plat_data->panel))
 			DRM_ERROR("failed to turnoff the panel\n");
 	}
 
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
-static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
 }
 
-static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
-	.enable = exynos_dp_bridge_enable,
-	.disable = exynos_dp_bridge_disable,
-	.pre_enable = exynos_dp_bridge_nop,
-	.post_disable = exynos_dp_bridge_nop,
-	.attach = exynos_dp_bridge_attach,
+static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
+	.enable = analogix_dp_bridge_enable,
+	.disable = analogix_dp_bridge_disable,
+	.pre_enable = analogix_dp_bridge_nop,
+	.post_disable = analogix_dp_bridge_nop,
+	.attach = analogix_dp_bridge_attach,
 };
 
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int analogix_dp_create_bridge(struct drm_device *drm_dev,
+				     struct analogix_dp_device *dp)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
-	struct drm_device *drm_dev = dp->drm_dev;
 	struct drm_bridge *bridge;
 	int ret;
 
@@ -1140,8 +1065,8 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	dp->bridge = bridge;
 
 	bridge->driver_private = dp;
-	bridge->encoder = encoder;
-	bridge->funcs = &exynos_dp_bridge_funcs;
+	bridge->encoder = dp->encoder;
+	bridge->funcs = &analogix_dp_bridge_funcs;
 
 	ret = drm_bridge_attach(drm_dev, bridge);
 	if (ret) {
@@ -1152,39 +1077,7 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	return 0;
 }
 
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
-				 const struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
-{
-}
-
-static void exynos_dp_disable(struct drm_encoder *encoder)
-{
-}
-
-static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
-	.mode_fixup = exynos_dp_mode_fixup,
-	.mode_set = exynos_dp_mode_set,
-	.enable = exynos_dp_enable,
-	.disable = exynos_dp_disable,
-};
-
-static struct drm_encoder_funcs exynos_dp_encoder_funcs = {
-	.destroy = drm_encoder_cleanup,
-};
-
-static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
+static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 {
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
@@ -1242,33 +1135,37 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
 	return dp_video_config;
 }
 
-static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct analogix_dp_plat_data *plat_data)
 {
+	struct platform_device *pdev = to_platform_device(dev);
+	struct analogix_dp_device *dp;
+	struct resource *res;
+	unsigned int irq_flags;
 	int ret;
 
-	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
-			OF_USE_NATIVE_MODE);
-	if (ret) {
-		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
-		return ret;
+	if (!plat_data) {
+		dev_err(dev, "Invalided input plat_data\n");
+		return -EINVAL;
 	}
-	return 0;
-}
 
-static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
-{
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-	struct platform_device *pdev = to_platform_device(dev);
-	struct drm_device *drm_dev = data;
-	struct drm_encoder *encoder = &dp->encoder;
-	struct resource *res;
-	unsigned int irq_flags;
-	int pipe, ret = 0;
+	dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, dp);
 
 	dp->dev = &pdev->dev;
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 
-	dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
+	/*
+	 * platform dp driver need containor_of the plat_data to get
+	 * the driver private data, so we need to store the point of
+	 * plat_data, not the context of plat_data.
+	 */
+	dp->plat_data = plat_data;
+
+	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
 	if (IS_ERR(dp->video_info))
 		return PTR_ERR(dp->video_info);
 
@@ -1288,12 +1185,6 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		}
 	}
 
-	if (!dp->panel && !dp->bridge) {
-		ret = exynos_dp_dt_parse_panel(dp);
-		if (ret)
-			return ret;
-	}
-
 	dp->clock = devm_clk_get(&pdev->dev, "dp");
 	if (IS_ERR(dp->clock)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
@@ -1308,7 +1199,10 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
-	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
+	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
+	if (!gpio_is_valid(dp->hpd_gpio))
+		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
+						 "samsung,hpd-gpio", 0);
 
 	if (gpio_is_valid(dp->hpd_gpio)) {
 		/*
@@ -1337,14 +1231,14 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		return -ENODEV;
 	}
 
-	INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
+	INIT_WORK(&dp->hotplug_work, analogix_dp_hotplug);
 
 	phy_power_on(dp->phy);
 
-	exynos_dp_init_dp(dp);
+	analogix_dp_init_dp(dp);
 
-	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
-			irq_flags, "exynos-dp", dp);
+	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
+			irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		return ret;
@@ -1352,126 +1246,48 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	disable_irq(dp->irq);
 
 	dp->drm_dev = drm_dev;
+	dp->encoder = dp->plat_data->encoder;
 
-	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
-						  EXYNOS_DISPLAY_TYPE_LCD);
-	if (pipe < 0)
-		return pipe;
-
-	encoder->possible_crtcs = 1 << pipe;
-
-	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
-
-	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
-			 DRM_MODE_ENCODER_TMDS);
-
-	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
-
-	ret = exynos_dp_create_connector(encoder);
+	ret = analogix_dp_create_bridge(drm_dev, dp);
 	if (ret) {
-		DRM_ERROR("failed to create connector ret = %d\n", ret);
-		drm_encoder_cleanup(encoder);
+		DRM_ERROR("failed to create bridge (%d)\n", ret);
+		drm_encoder_cleanup(dp->encoder);
 		return ret;
 	}
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_bind);
 
-static void exynos_dp_unbind(struct device *dev, struct device *master,
-				void *data)
-{
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-
-	exynos_dp_disable(&dp->encoder);
-}
-
-static const struct component_ops exynos_dp_ops = {
-	.bind	= exynos_dp_bind,
-	.unbind	= exynos_dp_unbind,
-};
-
-static int exynos_dp_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct device_node *panel_node, *bridge_node, *endpoint;
-	struct exynos_dp_device *dp;
-
-	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
-				GFP_KERNEL);
-	if (!dp)
-		return -ENOMEM;
-
-	platform_set_drvdata(pdev, dp);
-
-	panel_node = of_parse_phandle(dev->of_node, "panel", 0);
-	if (panel_node) {
-		dp->panel = of_drm_find_panel(panel_node);
-		of_node_put(panel_node);
-		if (!dp->panel)
-			return -EPROBE_DEFER;
-	}
-
-	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
-	if (endpoint) {
-		bridge_node = of_graph_get_remote_port_parent(endpoint);
-		if (bridge_node) {
-			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
-			of_node_put(bridge_node);
-			if (!dp->ptn_bridge)
-				return -EPROBE_DEFER;
-		} else
-			return -EPROBE_DEFER;
-	}
-
-	return component_add(&pdev->dev, &exynos_dp_ops);
-}
-
-static int exynos_dp_remove(struct platform_device *pdev)
+void analogix_dp_unbind(struct device *dev, struct device *master,
+			void *data)
 {
-	component_del(&pdev->dev, &exynos_dp_ops);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	return 0;
+	analogix_dp_bridge_disable(dp->bridge);
 }
+EXPORT_SYMBOL_GPL(analogix_dp_unbind);
 
 #ifdef CONFIG_PM_SLEEP
-static int exynos_dp_suspend(struct device *dev)
+int analogix_dp_suspend(struct device *dev)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_bridge_disable(dp->bridge);
+	analogix_dp_bridge_disable(dp->bridge);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_suspend);
 
-static int exynos_dp_resume(struct device *dev)
+int analogix_dp_resume(struct device *dev)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_bridge_enable(dp->bridge);
+	analogix_dp_bridge_enable(dp->bridge);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_resume);
 #endif
 
-static const struct dev_pm_ops exynos_dp_pm_ops = {
-	SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
-};
-
-static const struct of_device_id exynos_dp_match[] = {
-	{ .compatible = "samsung,exynos5-dp" },
-	{},
-};
-MODULE_DEVICE_TABLE(of, exynos_dp_match);
-
-struct platform_driver dp_driver = {
-	.probe		= exynos_dp_probe,
-	.remove		= exynos_dp_remove,
-	.driver		= {
-		.name	= "exynos-dp",
-		.owner	= THIS_MODULE,
-		.pm	= &exynos_dp_pm_ops,
-		.of_match_table = exynos_dp_match,
-	},
-};
-
 MODULE_AUTHOR("Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
-MODULE_DESCRIPTION("Samsung SoC DP Driver");
+MODULE_DESCRIPTION("Analogix DP Core Driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
new file mode 100644
index 0000000..65ce7f1
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -0,0 +1,277 @@
+/*
+ * Header file for Analogix DP (Display Port) core interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _ANALOGIX_DP_CORE_H
+#define _ANALOGIX_DP_CORE_H
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_dp_helper.h>
+
+#define DP_TIMEOUT_LOOP_COUNT 100
+#define MAX_CR_LOOP 5
+#define MAX_EQ_LOOP 5
+
+enum link_rate_type {
+	LINK_RATE_1_62GBPS = 0x06,
+	LINK_RATE_2_70GBPS = 0x0a
+};
+
+enum link_lane_count_type {
+	LANE_COUNT1 = 1,
+	LANE_COUNT2 = 2,
+	LANE_COUNT4 = 4
+};
+
+enum link_training_state {
+	START,
+	CLOCK_RECOVERY,
+	EQUALIZER_TRAINING,
+	FINISHED,
+	FAILED
+};
+
+enum voltage_swing_level {
+	VOLTAGE_LEVEL_0,
+	VOLTAGE_LEVEL_1,
+	VOLTAGE_LEVEL_2,
+	VOLTAGE_LEVEL_3,
+};
+
+enum pre_emphasis_level {
+	PRE_EMPHASIS_LEVEL_0,
+	PRE_EMPHASIS_LEVEL_1,
+	PRE_EMPHASIS_LEVEL_2,
+	PRE_EMPHASIS_LEVEL_3,
+};
+
+enum pattern_set {
+	PRBS7,
+	D10_2,
+	TRAINING_PTN1,
+	TRAINING_PTN2,
+	DP_NONE
+};
+
+enum color_space {
+	COLOR_RGB,
+	COLOR_YCBCR422,
+	COLOR_YCBCR444
+};
+
+enum color_depth {
+	COLOR_6,
+	COLOR_8,
+	COLOR_10,
+	COLOR_12
+};
+
+enum color_coefficient {
+	COLOR_YCBCR601,
+	COLOR_YCBCR709
+};
+
+enum dynamic_range {
+	VESA,
+	CEA
+};
+
+enum pll_status {
+	PLL_UNLOCKED,
+	PLL_LOCKED
+};
+
+enum clock_recovery_m_value_type {
+	CALCULATED_M,
+	REGISTER_M
+};
+
+enum video_timing_recognition_type {
+	VIDEO_TIMING_FROM_CAPTURE,
+	VIDEO_TIMING_FROM_REGISTER
+};
+
+enum analog_power_block {
+	AUX_BLOCK,
+	CH0_BLOCK,
+	CH1_BLOCK,
+	CH2_BLOCK,
+	CH3_BLOCK,
+	ANALOG_TOTAL,
+	POWER_ALL
+};
+
+enum dp_irq_type {
+	DP_IRQ_TYPE_HP_CABLE_IN,
+	DP_IRQ_TYPE_HP_CABLE_OUT,
+	DP_IRQ_TYPE_HP_CHANGE,
+	DP_IRQ_TYPE_UNKNOWN,
+};
+
+struct video_info {
+	char *name;
+
+	bool h_sync_polarity;
+	bool v_sync_polarity;
+	bool interlaced;
+
+	enum color_space color_space;
+	enum dynamic_range dynamic_range;
+	enum color_coefficient ycbcr_coeff;
+	enum color_depth color_depth;
+
+	enum link_rate_type link_rate;
+	enum link_lane_count_type lane_count;
+};
+
+struct link_train {
+	int eq_loop;
+	int cr_loop[4];
+
+	u8 link_rate;
+	u8 lane_count;
+	u8 training_lane[4];
+
+	enum link_training_state lt_state;
+};
+
+struct analogix_dp_device {
+	struct drm_encoder	*encoder;
+	struct drm_connector	*connector;
+	struct device		*dev;
+	struct drm_device	*drm_dev;
+	struct drm_bridge	*bridge;
+	struct clk		*clock;
+	unsigned int		irq;
+	void __iomem		*reg_base;
+
+	struct video_info	*video_info;
+	struct link_train	link_train;
+	struct work_struct	hotplug_work;
+	struct phy		*phy;
+	int			dpms_mode;
+	int			hpd_gpio;
+
+	struct analogix_dp_plat_data *plat_data;
+};
+
+/* analogix_dp_reg.c */
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_stop_video(struct analogix_dp_device *dp);
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
+void analogix_dp_reset(struct analogix_dp_device *dp);
+void analogix_dp_swreset(struct analogix_dp_device *dp);
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				       enum analog_power_block block,
+				       bool enable);
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
+void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
+void analogix_dp_reset_aux(struct analogix_dp_device *dp);
+void analogix_dp_init_aux(struct analogix_dp_device *dp);
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char data);
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char *data);
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[]);
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[]);
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr);
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int *data);
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char edid[]);
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
+void analogix_dp_reset_macro(struct analogix_dp_device *dp);
+void analogix_dp_init_video(struct analogix_dp_device *dp);
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+			enum clock_recovery_m_value_type type,
+			u32 m_value,
+			u32 n_value);
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_start_video(struct analogix_dp_device *dp);
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
+#endif /* _ANALOGIX_DP_CORE_H */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
new file mode 100644
index 0000000..442cc66
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -0,0 +1,1263 @@
+/*
+ * Analogix DP (Display port) core register interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include "analogix_dp_core.h"
+#include "analogix_dp_reg.h"
+
+#define COMMON_INT_MASK_1	0
+#define COMMON_INT_MASK_2	0
+#define COMMON_INT_MASK_3	0
+#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
+#define INT_STA_MASK		INT_HPD
+
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+		reg |= HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+		reg &= ~HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	}
+}
+
+void analogix_dp_stop_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	reg &= ~VIDEO_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+}
+
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable)
+		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
+			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+	else
+		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
+			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
+}
+
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = TX_TERMINAL_CTRL_50_OHM;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
+
+	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
+
+	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
+
+	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
+		TX_CUR1_2X | TX_CUR_16_MA;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
+
+	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
+		CH1_AMP_400_MV | CH0_AMP_400_MV;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
+}
+
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
+{
+	/* Set interrupt pin assertion polarity as high */
+	writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
+
+	/* Clear pending regisers */
+	writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+	writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
+	writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
+	writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+	writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	/* 0:mask,1: unmask */
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+void analogix_dp_reset(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	analogix_dp_stop_video(dp);
+	analogix_dp_enable_video_mute(dp, 0);
+
+	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
+		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
+		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+
+	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
+		SERDES_FIFO_FUNC_EN_N |
+		LS_CLK_DOMAIN_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+
+	usleep_range(20, 30);
+
+	analogix_dp_lane_swap(dp, 0);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
+
+	writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
+	writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
+
+	writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
+	writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
+
+	writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
+	writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
+
+	writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_swreset(struct analogix_dp_device *dp)
+{
+	writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
+}
+
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* 0: mask, 1: unmask */
+	reg = COMMON_INT_MASK_1;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+
+	reg = COMMON_INT_MASK_2;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+
+	reg = COMMON_INT_MASK_3;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+
+	reg = COMMON_INT_MASK_4;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+
+	reg = INT_STA_MASK;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+	if (reg & PLL_LOCK)
+		return PLL_LOCKED;
+	else
+		return PLL_UNLOCKED;
+}
+
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
+		reg |= DP_PLL_PD;
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
+		reg &= ~DP_PLL_PD;
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+	}
+}
+
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				enum analog_power_block block,
+				bool enable)
+{
+	u32 reg;
+
+	switch (block) {
+	case AUX_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= AUX_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~AUX_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH0_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH1_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH1_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH1_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH2_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH2_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH2_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH3_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH3_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH3_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case ANALOG_TOTAL:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= DP_PHY_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~DP_PHY_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case POWER_ALL:
+		if (enable) {
+			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
+				CH1_PD | CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
+{
+	u32 reg;
+	int timeout_loop = 0;
+
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
+
+	reg = PLL_LOCK_CHG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+
+	/* Power up PLL */
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		analogix_dp_set_pll_power_down(dp, 0);
+
+		while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+			timeout_loop++;
+			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+				dev_err(dp->dev, "failed to get pll lock status\n");
+				return;
+			}
+			usleep_range(10, 20);
+		}
+	}
+
+	/* Enable Serdes FIFO function and Link symbol clock domain module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
+		| AUX_FUNC_EN_N);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+
+	reg = INT_HPD;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+}
+
+void analogix_dp_init_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	analogix_dp_clear_hotplug_interrupts(dp);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg &= ~(F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		reg = gpio_get_value(dp->hpd_gpio);
+		if (reg)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+		else
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+	} else {
+		/* Parse hotplug interrupt status register */
+		reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+
+		if (reg & PLUG)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+
+		if (reg & HPD_LOST)
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+
+		if (reg & HOTPLUG_CHG)
+			return DP_IRQ_TYPE_HP_CHANGE;
+
+		return DP_IRQ_TYPE_UNKNOWN;
+	}
+}
+
+void analogix_dp_reset_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Disable AUX channel module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg |= AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+void analogix_dp_init_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Clear inerrupts related to AUX channel */
+	reg = RPLY_RECEIV | AUX_ERR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	analogix_dp_reset_aux(dp);
+
+	/* Disable AUX transaction H/W retry */
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
+		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
+
+	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
+	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
+
+	/* Enable AUX channel module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg &= ~AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		if (gpio_get_value(dp->hpd_gpio))
+			return 0;
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+		if (reg & HPD_STATUS)
+			return 0;
+	}
+
+	return -EINVAL;
+}
+
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+	reg &= ~SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+}
+
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
+{
+	int reg;
+	int retval = 0;
+	int timeout_loop = 0;
+
+	/* Enable AUX CH operation */
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+	reg |= AUX_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+
+	/* Is AUX CH command reply received? */
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+	while (!(reg & RPLY_RECEIV)) {
+		timeout_loop++;
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "AUX CH command reply failed!\n");
+			return -ETIMEDOUT;
+		}
+		reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+		usleep_range(10, 11);
+	}
+
+	/* Clear interrupt source for AUX CH command reply */
+	writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	/* Clear interrupt source for AUX CH access error */
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+	if (reg & AUX_ERR) {
+		writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
+		return -EREMOTEIO;
+	}
+
+	/* Check AUX CH error access status */
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
+	if ((reg & AUX_STATUS_MASK) != 0) {
+		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
+			reg & AUX_STATUS_MASK);
+		return -EREMOTEIO;
+	}
+
+	return retval;
+}
+
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+		/* Write data buffer */
+		reg = (unsigned int)data;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+		/*
+		 * Set DisplayPort transaction and write 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+		/*
+		 * Set DisplayPort transaction and read 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	/* Read data buffer */
+	reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+	*data = (unsigned char)(reg & 0xff);
+
+	return retval;
+}
+
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+			     cur_data_idx++) {
+				reg = data[start_offset + cur_data_idx];
+				writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+							  + 4 * cur_data_idx);
+			}
+
+			/*
+			 * Set DisplayPort transaction and write
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+			else
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		/* AUX CH Request Transaction process */
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+			/*
+			 * Set DisplayPort transaction and read
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+			else
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+		    cur_data_idx++) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			data[start_offset + cur_data_idx] =
+				(unsigned char)reg;
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr)
+{
+	u32 reg;
+	int retval;
+
+	/* Set EDID device address */
+	reg = device_addr;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+	/* Set offset from base address of EDID device */
+	writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+	/*
+	 * Set I2C transaction and write address
+	 * If bit 3 is 1, DisplayPort transaction.
+	 * If Bit 3 is 0, I2C transaction.
+	 */
+	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
+		AUX_TX_COMM_WRITE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+	/* Start AUX transaction */
+	retval = analogix_dp_start_aux_transaction(dp);
+	if (retval != 0)
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select EDID device */
+		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+		if (retval != 0)
+			continue;
+
+		/*
+		 * Set I2C transaction and read data
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_I2C_TRANSACTION |
+			AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	/* Read data */
+	if (retval == 0)
+		*data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char edid[])
+{
+	u32 reg;
+	unsigned int i, j;
+	unsigned int cur_data_idx;
+	unsigned int defer = 0;
+	int retval = 0;
+
+	for (i = 0; i < count; i += 16) {
+		for (j = 0; j < 3; j++) {
+			/* Clear AUX CH data buffer */
+			reg = BUF_CLR;
+			writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+			/* Set normal AUX CH command */
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+			reg &= ~ADDR_ONLY;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+
+			/*
+			 * If Rx sends defer, Tx sends only reads
+			 * request without sending address
+			 */
+			if (!defer)
+				retval = analogix_dp_select_i2c_device(dp,
+						device_addr, reg_addr + i);
+			else
+				defer = 0;
+
+			if (retval == 0) {
+				/*
+				 * Set I2C transaction and write data
+				 * If bit 3 is 1, DisplayPort transaction.
+				 * If Bit 3 is 0, I2C transaction.
+				 */
+				reg = AUX_LENGTH(16) |
+					AUX_TX_COMM_I2C_TRANSACTION |
+					AUX_TX_COMM_READ;
+				writel(reg, dp->reg_base +
+					ANALOGIX_DP_AUX_CH_CTL_1);
+
+				/* Start AUX transaction */
+				retval = analogix_dp_start_aux_transaction(dp);
+				if (retval == 0)
+					break;
+				else
+					dev_dbg(dp->dev,
+						"%s: Aux Transaction fail!\n",
+						__func__);
+			}
+			/* Check if Rx sends defer */
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
+			if (reg == AUX_RX_COMM_AUX_DEFER ||
+				reg == AUX_RX_COMM_I2C_DEFER) {
+				dev_err(dp->dev, "Defer: %d\n\n", reg);
+				defer = 1;
+			}
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			edid[i + cur_data_idx] = (unsigned char)reg;
+		}
+	}
+
+	return retval;
+}
+
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
+{
+	u32 reg;
+
+	reg = bwtype;
+	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
+		writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
+}
+
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
+	*bwtype = reg;
+}
+
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
+{
+	u32 reg;
+
+	reg = count;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
+}
+
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
+	*count = reg;
+}
+
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg |= ENHANCED;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg &= ~ENHANCED;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+	}
+}
+
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				enum pattern_set pattern)
+{
+	u32 reg;
+
+	switch (pattern) {
+	case PRBS7:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case D10_2:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN1:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN2:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case DP_NONE:
+		reg = SCRAMBLING_ENABLE |
+			LINK_QUAL_PATTERN_SET_DISABLE |
+			SW_TRAINING_PATTERN_SET_NORMAL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+}
+
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+	return reg;
+}
+
+void analogix_dp_reset_macro(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
+	reg |= MACRO_RST;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+
+	/* 10 us is the minimum reset time. */
+	usleep_range(10, 20);
+
+	reg &= ~MACRO_RST;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+}
+
+void analogix_dp_init_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	reg = CHA_CRI(4) | CHA_CTRL;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+
+	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
+}
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Configure the input color depth, color space, dynamic range */
+	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info->color_depth << IN_BPC_SHIFT) |
+		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
+
+	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
+	reg &= ~IN_YC_COEFFI_MASK;
+	if (dp->video_info->ycbcr_coeff)
+		reg |= IN_YC_COEFFI_ITU709;
+	else
+		reg |= IN_YC_COEFFI_ITU601;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
+}
+
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	if (!(reg & DET_STA)) {
+		dev_dbg(dp->dev, "Input stream clock not detected.\n");
+		return -EINVAL;
+	}
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
+
+	if (reg & CHA_STA) {
+		dev_dbg(dp->dev, "Input stream clk is changing\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+		enum clock_recovery_m_value_type type,
+		u32 m_value,
+		u32 n_value)
+{
+	u32 reg;
+
+	if (type == REGISTER_M) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg |= FIX_M_VID;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg = m_value & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
+		reg = (m_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
+		reg = (m_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
+
+		reg = n_value & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		reg = (n_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		reg = (n_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
+	} else  {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg &= ~FIX_M_VID;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
+	}
+}
+
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
+{
+	u32 reg;
+
+	if (type == VIDEO_TIMING_FROM_CAPTURE) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+		reg &= ~FORMAT_SEL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+		reg |= FORMAT_SEL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	}
+}
+
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MODE_SLAVE_MODE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+	}
+}
+
+void analogix_dp_start_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	reg |= VIDEO_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+}
+
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	if (!(reg & STRM_VALID)) {
+		dev_dbg(dp->dev, "Input video stream is not detected.\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg |= MASTER_VID_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~INTERACE_SCAN_CFG;
+	reg |= (dp->video_info->interlaced << 2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~VSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->v_sync_polarity << 1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~HSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->h_sync_polarity << 0);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+	reg &= ~SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+}
+
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+	reg |= SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
similarity index 64%
rename from drivers/gpu/drm/exynos/exynos_dp_reg.h
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 2e9bd0e..738db4c 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -1,5 +1,5 @@
 /*
- * Register definition file for Samsung DP driver
+ * Register definition file for Analogix DP core driver
  *
  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
@@ -9,96 +9,96 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef _EXYNOS_DP_REG_H
-#define _EXYNOS_DP_REG_H
-
-#define EXYNOS_DP_TX_SW_RESET			0x14
-#define EXYNOS_DP_FUNC_EN_1			0x18
-#define EXYNOS_DP_FUNC_EN_2			0x1C
-#define EXYNOS_DP_VIDEO_CTL_1			0x20
-#define EXYNOS_DP_VIDEO_CTL_2			0x24
-#define EXYNOS_DP_VIDEO_CTL_3			0x28
-
-#define EXYNOS_DP_VIDEO_CTL_8			0x3C
-#define EXYNOS_DP_VIDEO_CTL_10			0x44
-
-#define EXYNOS_DP_LANE_MAP			0x35C
-
-#define EXYNOS_DP_ANALOG_CTL_1			0x370
-#define EXYNOS_DP_ANALOG_CTL_2			0x374
-#define EXYNOS_DP_ANALOG_CTL_3			0x378
-#define EXYNOS_DP_PLL_FILTER_CTL_1		0x37C
-#define EXYNOS_DP_TX_AMP_TUNING_CTL		0x380
-
-#define EXYNOS_DP_AUX_HW_RETRY_CTL		0x390
-
-#define EXYNOS_DP_COMMON_INT_STA_1		0x3C4
-#define EXYNOS_DP_COMMON_INT_STA_2		0x3C8
-#define EXYNOS_DP_COMMON_INT_STA_3		0x3CC
-#define EXYNOS_DP_COMMON_INT_STA_4		0x3D0
-#define EXYNOS_DP_INT_STA			0x3DC
-#define EXYNOS_DP_COMMON_INT_MASK_1		0x3E0
-#define EXYNOS_DP_COMMON_INT_MASK_2		0x3E4
-#define EXYNOS_DP_COMMON_INT_MASK_3		0x3E8
-#define EXYNOS_DP_COMMON_INT_MASK_4		0x3EC
-#define EXYNOS_DP_INT_STA_MASK			0x3F8
-#define EXYNOS_DP_INT_CTL			0x3FC
-
-#define EXYNOS_DP_SYS_CTL_1			0x600
-#define EXYNOS_DP_SYS_CTL_2			0x604
-#define EXYNOS_DP_SYS_CTL_3			0x608
-#define EXYNOS_DP_SYS_CTL_4			0x60C
-
-#define EXYNOS_DP_PKT_SEND_CTL			0x640
-#define EXYNOS_DP_HDCP_CTL			0x648
-
-#define EXYNOS_DP_LINK_BW_SET			0x680
-#define EXYNOS_DP_LANE_COUNT_SET		0x684
-#define EXYNOS_DP_TRAINING_PTN_SET		0x688
-#define EXYNOS_DP_LN0_LINK_TRAINING_CTL		0x68C
-#define EXYNOS_DP_LN1_LINK_TRAINING_CTL		0x690
-#define EXYNOS_DP_LN2_LINK_TRAINING_CTL		0x694
-#define EXYNOS_DP_LN3_LINK_TRAINING_CTL		0x698
-
-#define EXYNOS_DP_DEBUG_CTL			0x6C0
-#define EXYNOS_DP_HPD_DEGLITCH_L		0x6C4
-#define EXYNOS_DP_HPD_DEGLITCH_H		0x6C8
-#define EXYNOS_DP_LINK_DEBUG_CTL		0x6E0
-
-#define EXYNOS_DP_M_VID_0			0x700
-#define EXYNOS_DP_M_VID_1			0x704
-#define EXYNOS_DP_M_VID_2			0x708
-#define EXYNOS_DP_N_VID_0			0x70C
-#define EXYNOS_DP_N_VID_1			0x710
-#define EXYNOS_DP_N_VID_2			0x714
-
-#define EXYNOS_DP_PLL_CTL			0x71C
-#define EXYNOS_DP_PHY_PD			0x720
-#define EXYNOS_DP_PHY_TEST			0x724
-
-#define EXYNOS_DP_VIDEO_FIFO_THRD		0x730
-#define EXYNOS_DP_AUDIO_MARGIN			0x73C
-
-#define EXYNOS_DP_M_VID_GEN_FILTER_TH		0x764
-#define EXYNOS_DP_M_AUD_GEN_FILTER_TH		0x778
-#define EXYNOS_DP_AUX_CH_STA			0x780
-#define EXYNOS_DP_AUX_CH_DEFER_CTL		0x788
-#define EXYNOS_DP_AUX_RX_COMM			0x78C
-#define EXYNOS_DP_BUFFER_DATA_CTL		0x790
-#define EXYNOS_DP_AUX_CH_CTL_1			0x794
-#define EXYNOS_DP_AUX_ADDR_7_0			0x798
-#define EXYNOS_DP_AUX_ADDR_15_8			0x79C
-#define EXYNOS_DP_AUX_ADDR_19_16		0x7A0
-#define EXYNOS_DP_AUX_CH_CTL_2			0x7A4
-
-#define EXYNOS_DP_BUF_DATA_0			0x7C0
-
-#define EXYNOS_DP_SOC_GENERAL_CTL		0x800
-
-/* EXYNOS_DP_TX_SW_RESET */
+#ifndef _ANALOGIX_DP_REG_H
+#define _ANALOGIX_DP_REG_H
+
+#define ANALOGIX_DP_TX_SW_RESET			0x14
+#define ANALOGIX_DP_FUNC_EN_1			0x18
+#define ANALOGIX_DP_FUNC_EN_2			0x1C
+#define ANALOGIX_DP_VIDEO_CTL_1			0x20
+#define ANALOGIX_DP_VIDEO_CTL_2			0x24
+#define ANALOGIX_DP_VIDEO_CTL_3			0x28
+
+#define ANALOGIX_DP_VIDEO_CTL_8			0x3C
+#define ANALOGIX_DP_VIDEO_CTL_10		0x44
+
+#define ANALOGIX_DP_LANE_MAP			0x35C
+
+#define ANALOGIX_DP_ANALOG_CTL_1		0x370
+#define ANALOGIX_DP_ANALOG_CTL_2		0x374
+#define ANALOGIX_DP_ANALOG_CTL_3		0x378
+#define ANALOGIX_DP_PLL_FILTER_CTL_1		0x37C
+#define ANALOGIX_DP_TX_AMP_TUNING_CTL		0x380
+
+#define ANALOGIX_DP_AUX_HW_RETRY_CTL		0x390
+
+#define ANALOGIX_DP_COMMON_INT_STA_1		0x3C4
+#define ANALOGIX_DP_COMMON_INT_STA_2		0x3C8
+#define ANALOGIX_DP_COMMON_INT_STA_3		0x3CC
+#define ANALOGIX_DP_COMMON_INT_STA_4		0x3D0
+#define ANALOGIX_DP_INT_STA			0x3DC
+#define ANALOGIX_DP_COMMON_INT_MASK_1		0x3E0
+#define ANALOGIX_DP_COMMON_INT_MASK_2		0x3E4
+#define ANALOGIX_DP_COMMON_INT_MASK_3		0x3E8
+#define ANALOGIX_DP_COMMON_INT_MASK_4		0x3EC
+#define ANALOGIX_DP_INT_STA_MASK		0x3F8
+#define ANALOGIX_DP_INT_CTL			0x3FC
+
+#define ANALOGIX_DP_SYS_CTL_1			0x600
+#define ANALOGIX_DP_SYS_CTL_2			0x604
+#define ANALOGIX_DP_SYS_CTL_3			0x608
+#define ANALOGIX_DP_SYS_CTL_4			0x60C
+
+#define ANALOGIX_DP_PKT_SEND_CTL		0x640
+#define ANALOGIX_DP_HDCP_CTL			0x648
+
+#define ANALOGIX_DP_LINK_BW_SET			0x680
+#define ANALOGIX_DP_LANE_COUNT_SET		0x684
+#define ANALOGIX_DP_TRAINING_PTN_SET		0x688
+#define ANALOGIX_DP_LN0_LINK_TRAINING_CTL	0x68C
+#define ANALOGIX_DP_LN1_LINK_TRAINING_CTL	0x690
+#define ANALOGIX_DP_LN2_LINK_TRAINING_CTL	0x694
+#define ANALOGIX_DP_LN3_LINK_TRAINING_CTL	0x698
+
+#define ANALOGIX_DP_DEBUG_CTL			0x6C0
+#define ANALOGIX_DP_HPD_DEGLITCH_L		0x6C4
+#define ANALOGIX_DP_HPD_DEGLITCH_H		0x6C8
+#define ANALOGIX_DP_LINK_DEBUG_CTL		0x6E0
+
+#define ANALOGIX_DP_M_VID_0			0x700
+#define ANALOGIX_DP_M_VID_1			0x704
+#define ANALOGIX_DP_M_VID_2			0x708
+#define ANALOGIX_DP_N_VID_0			0x70C
+#define ANALOGIX_DP_N_VID_1			0x710
+#define ANALOGIX_DP_N_VID_2			0x714
+
+#define ANALOGIX_DP_PLL_CTL			0x71C
+#define ANALOGIX_DP_PHY_PD			0x720
+#define ANALOGIX_DP_PHY_TEST			0x724
+
+#define ANALOGIX_DP_VIDEO_FIFO_THRD		0x730
+#define ANALOGIX_DP_AUDIO_MARGIN		0x73C
+
+#define ANALOGIX_DP_M_VID_GEN_FILTER_TH		0x764
+#define ANALOGIX_DP_M_AUD_GEN_FILTER_TH		0x778
+#define ANALOGIX_DP_AUX_CH_STA			0x780
+#define ANALOGIX_DP_AUX_CH_DEFER_CTL		0x788
+#define ANALOGIX_DP_AUX_RX_COMM			0x78C
+#define ANALOGIX_DP_BUFFER_DATA_CTL		0x790
+#define ANALOGIX_DP_AUX_CH_CTL_1		0x794
+#define ANALOGIX_DP_AUX_ADDR_7_0		0x798
+#define ANALOGIX_DP_AUX_ADDR_15_8		0x79C
+#define ANALOGIX_DP_AUX_ADDR_19_16		0x7A0
+#define ANALOGIX_DP_AUX_CH_CTL_2		0x7A4
+
+#define ANALOGIX_DP_BUF_DATA_0			0x7C0
+
+#define ANALOGIX_DP_SOC_GENERAL_CTL		0x800
+
+/* ANALOGIX_DP_TX_SW_RESET */
 #define RESET_DP_TX				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_1 */
+/* ANALOGIX_DP_FUNC_EN_1 */
 #define MASTER_VID_FUNC_EN_N			(0x1 << 7)
 #define SLAVE_VID_FUNC_EN_N			(0x1 << 5)
 #define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
@@ -107,17 +107,17 @@
 #define CRC_FUNC_EN_N				(0x1 << 1)
 #define SW_FUNC_EN_N				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_2 */
+/* ANALOGIX_DP_FUNC_EN_2 */
 #define SSC_FUNC_EN_N				(0x1 << 7)
 #define AUX_FUNC_EN_N				(0x1 << 2)
 #define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
 #define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define VIDEO_EN				(0x1 << 7)
 #define HDCP_VIDEO_MUTE				(0x1 << 6)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define IN_D_RANGE_MASK				(0x1 << 7)
 #define IN_D_RANGE_SHIFT			(7)
 #define IN_D_RANGE_CEA				(0x1 << 7)
@@ -134,7 +134,7 @@
 #define IN_COLOR_F_YCBCR422			(0x1 << 0)
 #define IN_COLOR_F_RGB				(0x0 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_3 */
+/* ANALOGIX_DP_VIDEO_CTL_3 */
 #define IN_YC_COEFFI_MASK			(0x1 << 7)
 #define IN_YC_COEFFI_SHIFT			(7)
 #define IN_YC_COEFFI_ITU709			(0x1 << 7)
@@ -144,17 +144,17 @@
 #define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
 #define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
 
-/* EXYNOS_DP_VIDEO_CTL_8 */
+/* ANALOGIX_DP_VIDEO_CTL_8 */
 #define VID_HRES_TH(x)				(((x) & 0xf) << 4)
 #define VID_VRES_TH(x)				(((x) & 0xf) << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_10 */
+/* ANALOGIX_DP_VIDEO_CTL_10 */
 #define FORMAT_SEL				(0x1 << 4)
 #define INTERACE_SCAN_CFG			(0x1 << 2)
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
-/* EXYNOS_DP_LANE_MAP */
+/* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
 #define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
@@ -172,30 +172,30 @@
 #define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
 #define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_1 */
+/* ANALOGIX_DP_ANALOG_CTL_1 */
 #define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
 
-/* EXYNOS_DP_ANALOG_CTL_2 */
+/* ANALOGIX_DP_ANALOG_CTL_2 */
 #define SEL_24M					(0x1 << 3)
 #define TX_DVDD_BIT_1_0625V			(0x4 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_3 */
+/* ANALOGIX_DP_ANALOG_CTL_3 */
 #define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
 #define VCO_BIT_600_MICRO			(0x5 << 0)
 
-/* EXYNOS_DP_PLL_FILTER_CTL_1 */
+/* ANALOGIX_DP_PLL_FILTER_CTL_1 */
 #define PD_RING_OSC				(0x1 << 6)
 #define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
 #define TX_CUR1_2X				(0x1 << 2)
 #define TX_CUR_16_MA				(0x3 << 0)
 
-/* EXYNOS_DP_TX_AMP_TUNING_CTL */
+/* ANALOGIX_DP_TX_AMP_TUNING_CTL */
 #define CH3_AMP_400_MV				(0x0 << 24)
 #define CH2_AMP_400_MV				(0x0 << 16)
 #define CH1_AMP_400_MV				(0x0 << 8)
 #define CH0_AMP_400_MV				(0x0 << 0)
 
-/* EXYNOS_DP_AUX_HW_RETRY_CTL */
+/* ANALOGIX_DP_AUX_HW_RETRY_CTL */
 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x)	(((x) & 0x7) << 8)
 #define AUX_HW_RETRY_INTERVAL_MASK		(0x3 << 3)
 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS	(0x0 << 3)
@@ -204,7 +204,7 @@
 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS	(0x3 << 3)
 #define AUX_HW_RETRY_COUNT_SEL(x)		(((x) & 0x7) << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_1 */
+/* ANALOGIX_DP_COMMON_INT_STA_1 */
 #define VSYNC_DET				(0x1 << 7)
 #define PLL_LOCK_CHG				(0x1 << 6)
 #define SPDIF_ERR				(0x1 << 5)
@@ -214,19 +214,19 @@
 #define VID_CLK_CHG				(0x1 << 1)
 #define SW_INT					(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_2 */
+/* ANALOGIX_DP_COMMON_INT_STA_2 */
 #define ENC_EN_CHG				(0x1 << 6)
 #define HW_BKSV_RDY				(0x1 << 3)
 #define HW_SHA_DONE				(0x1 << 2)
 #define HW_AUTH_STATE_CHG			(0x1 << 1)
 #define HW_AUTH_DONE				(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_3 */
+/* ANALOGIX_DP_COMMON_INT_STA_3 */
 #define AFIFO_UNDER				(0x1 << 7)
 #define AFIFO_OVER				(0x1 << 6)
 #define R0_CHK_FLAG				(0x1 << 5)
 
-/* EXYNOS_DP_COMMON_INT_STA_4 */
+/* ANALOGIX_DP_COMMON_INT_STA_4 */
 #define PSR_ACTIVE				(0x1 << 7)
 #define PSR_INACTIVE				(0x1 << 6)
 #define SPDIF_BI_PHASE_ERR			(0x1 << 5)
@@ -234,29 +234,29 @@
 #define HPD_LOST				(0x1 << 1)
 #define PLUG					(0x1 << 0)
 
-/* EXYNOS_DP_INT_STA */
+/* ANALOGIX_DP_INT_STA */
 #define INT_HPD					(0x1 << 6)
 #define HW_TRAINING_FINISH			(0x1 << 5)
 #define RPLY_RECEIV				(0x1 << 1)
 #define AUX_ERR					(0x1 << 0)
 
-/* EXYNOS_DP_INT_CTL */
+/* ANALOGIX_DP_INT_CTL */
 #define SOFT_INT_CTRL				(0x1 << 2)
 #define INT_POL1				(0x1 << 1)
 #define INT_POL0				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_1 */
+/* ANALOGIX_DP_SYS_CTL_1 */
 #define DET_STA					(0x1 << 2)
 #define FORCE_DET				(0x1 << 1)
 #define DET_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_2 */
+/* ANALOGIX_DP_SYS_CTL_2 */
 #define CHA_CRI(x)				(((x) & 0xf) << 4)
 #define CHA_STA					(0x1 << 2)
 #define FORCE_CHA				(0x1 << 1)
 #define CHA_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_3 */
+/* ANALOGIX_DP_SYS_CTL_3 */
 #define HPD_STATUS				(0x1 << 6)
 #define F_HPD					(0x1 << 5)
 #define HPD_CTRL				(0x1 << 4)
@@ -265,13 +265,13 @@
 #define F_VALID					(0x1 << 1)
 #define VALID_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_4 */
+/* ANALOGIX_DP_SYS_CTL_4 */
 #define FIX_M_AUD				(0x1 << 4)
 #define ENHANCED				(0x1 << 3)
 #define FIX_M_VID				(0x1 << 2)
 #define M_VID_UPDATE_CTRL			(0x3 << 0)
 
-/* EXYNOS_DP_TRAINING_PTN_SET */
+/* ANALOGIX_DP_TRAINING_PTN_SET */
 #define SCRAMBLER_TYPE				(0x1 << 9)
 #define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
 #define SCRAMBLING_DISABLE			(0x1 << 5)
@@ -285,24 +285,24 @@
 #define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
 #define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
 
-/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+/* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */
 #define PRE_EMPHASIS_SET_MASK			(0x3 << 3)
 #define PRE_EMPHASIS_SET_SHIFT			(3)
 
-/* EXYNOS_DP_DEBUG_CTL */
+/* ANALOGIX_DP_DEBUG_CTL */
 #define PLL_LOCK				(0x1 << 4)
 #define F_PLL_LOCK				(0x1 << 3)
 #define PLL_LOCK_CTRL				(0x1 << 2)
 #define PN_INV					(0x1 << 0)
 
-/* EXYNOS_DP_PLL_CTL */
+/* ANALOGIX_DP_PLL_CTL */
 #define DP_PLL_PD				(0x1 << 7)
 #define DP_PLL_RESET				(0x1 << 6)
 #define DP_PLL_LOOP_BIT_DEFAULT			(0x1 << 4)
 #define DP_PLL_REF_BIT_1_1250V			(0x5 << 0)
 #define DP_PLL_REF_BIT_1_2500V			(0x7 << 0)
 
-/* EXYNOS_DP_PHY_PD */
+/* ANALOGIX_DP_PHY_PD */
 #define DP_PHY_PD				(0x1 << 5)
 #define AUX_PD					(0x1 << 4)
 #define CH3_PD					(0x1 << 3)
@@ -310,28 +310,28 @@
 #define CH1_PD					(0x1 << 1)
 #define CH0_PD					(0x1 << 0)
 
-/* EXYNOS_DP_PHY_TEST */
+/* ANALOGIX_DP_PHY_TEST */
 #define MACRO_RST				(0x1 << 5)
 #define CH1_TEST				(0x1 << 1)
 #define CH0_TEST				(0x1 << 0)
 
-/* EXYNOS_DP_AUX_CH_STA */
+/* ANALOGIX_DP_AUX_CH_STA */
 #define AUX_BUSY				(0x1 << 4)
 #define AUX_STATUS_MASK				(0xf << 0)
 
-/* EXYNOS_DP_AUX_CH_DEFER_CTL */
+/* ANALOGIX_DP_AUX_CH_DEFER_CTL */
 #define DEFER_CTRL_EN				(0x1 << 7)
 #define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
 
-/* EXYNOS_DP_AUX_RX_COMM */
+/* ANALOGIX_DP_AUX_RX_COMM */
 #define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
 #define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
 
-/* EXYNOS_DP_BUFFER_DATA_CTL */
+/* ANALOGIX_DP_BUFFER_DATA_CTL */
 #define BUF_CLR					(0x1 << 7)
 #define BUF_DATA_COUNT(x)			(((x) & 0x1f) << 0)
 
-/* EXYNOS_DP_AUX_CH_CTL_1 */
+/* ANALOGIX_DP_AUX_CH_CTL_1 */
 #define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
 #define AUX_TX_COMM_MASK			(0xf << 0)
 #define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
@@ -340,20 +340,20 @@
 #define AUX_TX_COMM_WRITE			(0x0 << 0)
 #define AUX_TX_COMM_READ			(0x1 << 0)
 
-/* EXYNOS_DP_AUX_ADDR_7_0 */
+/* ANALOGIX_DP_AUX_ADDR_7_0 */
 #define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_15_8 */
+/* ANALOGIX_DP_AUX_ADDR_15_8 */
 #define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_19_16 */
+/* ANALOGIX_DP_AUX_ADDR_19_16 */
 #define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
 
-/* EXYNOS_DP_AUX_CH_CTL_2 */
+/* ANALOGIX_DP_AUX_CH_CTL_2 */
 #define ADDR_ONLY				(0x1 << 1)
 #define AUX_EN					(0x1 << 0)
 
-/* EXYNOS_DP_SOC_GENERAL_CTL */
+/* ANALOGIX_DP_SOC_GENERAL_CTL */
 #define AUDIO_MODE_SPDIF_MODE			(0x1 << 8)
 #define AUDIO_MODE_MASTER_MODE			(0x0 << 8)
 #define MASTER_VIDEO_INTERLACE_EN		(0x1 << 4)
@@ -363,4 +363,4 @@
 #define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
 #define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
 
-#endif /* _EXYNOS_DP_REG_H */
+#endif /* _ANALOGIX_DP_REG_H */
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index bd1a415..5f74f80 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -55,8 +55,9 @@ config DRM_EXYNOS_DSI
 	  This enables support for Exynos MIPI-DSI device.
 
 config DRM_EXYNOS_DP
-	bool "EXYNOS DRM DP driver support"
+	bool "EXYNOS specific extensions for Analogix DP driver"
 	depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON)
+	select DRM_ANALOGIX_DP
 	default DRM_EXYNOS
 	select DRM_PANEL
 	help
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index 02aecfe..4453798 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -13,7 +13,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON)	+= exynos5433_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON)	+= exynos7_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DPI)	+= exynos_drm_dpi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DSI)	+= exynos_drm_dsi.o
-exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o exynos_dp_reg.o
+exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)	+= exynos_hdmi.o exynos_mixer.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI)	+= exynos_drm_vidi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_G2D)	+= exynos_drm_g2d.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
new file mode 100644
index 0000000..726d5b5
--- /dev/null
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -0,0 +1,366 @@
+/*
+ * Samsung SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_graph.h>
+#include <video/of_display_timing.h>
+#include <video/of_videomode.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+
+#include <drm/bridge/analogix_dp.h>
+#include <drm/exynos_drm.h>
+
+#include "exynos_drm_crtc.h"
+
+#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
+
+struct exynos_dp_device {
+	struct drm_encoder         encoder;
+	struct drm_connector       connector;
+	struct drm_bridge          *ptn_bridge;
+	struct drm_device          *drm_dev;
+	struct device              *dev;
+
+	struct exynos_drm_panel_info priv;
+	struct analogix_dp_plat_data plat_data;
+};
+
+int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
+				bool enable)
+{
+	struct exynos_dp_device *dp = to_dp(plat_data);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct exynos_drm_crtc *crtc;
+
+	if (!encoder)
+		return -1;
+
+	crtc = to_exynos_crtc(encoder->crtc);
+	if (crtc && crtc->ops && crtc->ops->clock_enable)
+		crtc->ops->clock_enable(crtc, enable);
+
+	return 0;
+}
+
+static int exynos_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	return exynos_dp_crtc_clock_enable(plat_data, true);
+}
+
+static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
+{
+	return exynos_dp_crtc_clock_enable(plat_data, false);
+}
+
+static int exynos_dp_get_modes(struct drm_connector *connector)
+{
+	struct exynos_dp_device *dp = to_dp(connector);
+	struct drm_display_mode *mode;
+	int num_modes = 0;
+
+	num_modes += analogix_dp_get_modes(dp->dev);
+
+	if (dp->plat_data.panel)
+		return num_modes;
+
+	mode = drm_mode_create(connector->dev);
+	if (!mode) {
+		DRM_ERROR("failed to create a new display mode.\n");
+		return num_modes;
+	}
+
+	drm_display_mode_from_videomode(&dp->priv.vm, mode);
+	mode->width_mm = dp->priv.width_mm;
+	mode->height_mm = dp->priv.height_mm;
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_set_name(mode);
+	drm_mode_probed_add(connector, mode);
+
+	return num_modes + 1;
+}
+
+static struct drm_encoder *
+exynos_dp_best_encoder(struct drm_connector *connector)
+{
+	struct exynos_dp_device *dp = to_dp(connector);
+
+	return &dp->encoder;
+}
+
+static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
+	.get_modes = exynos_dp_get_modes,
+	.best_encoder = exynos_dp_best_encoder,
+};
+
+static enum drm_connector_status
+exynos_dp_detect(struct drm_connector *connector, bool force)
+{
+	struct exynos_dp_device *dp = to_dp(connector);
+
+	return analogix_dp_detect(dp->dev, force);
+}
+
+static void exynos_dp_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static struct drm_connector_funcs exynos_dp_connector_funcs = {
+	.dpms = drm_atomic_helper_connector_dpms,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.detect = exynos_dp_detect,
+	.destroy = exynos_dp_connector_destroy,
+	.reset = drm_atomic_helper_connector_reset,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+				   struct drm_bridge *bridge)
+{
+	struct exynos_dp_device *dp = to_dp(plat_data);
+	struct drm_connector *connector = &dp->connector;
+	struct drm_encoder *encoder = &dp->encoder;
+	int ret;
+
+	/* Pre-empt DP connector creation if there's a bridge */
+	if (dp->ptn_bridge) {
+		bridge->next = dp->ptn_bridge;
+		dp->ptn_bridge->encoder = encoder;
+		ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
+		if (ret) {
+			DRM_ERROR("Failed to attach bridge to drm\n");
+			bridge->next = NULL;
+			return ret;
+		}
+	}
+
+	connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+	ret = drm_connector_init(dp->drm_dev, connector,
+				 &exynos_dp_connector_funcs,
+				 DRM_MODE_CONNECTOR_eDP);
+	if (ret) {
+		DRM_ERROR("Failed to initialize connector with drm\n");
+		return ret;
+	}
+
+	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
+	drm_connector_register(connector);
+	drm_mode_connector_attach_encoder(connector, encoder);
+
+	dp->plat_data.connector = connector;
+
+	return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+				 const struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
+static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
+	.mode_fixup = exynos_dp_mode_fixup,
+	.mode_set = exynos_dp_mode_set,
+	.enable = exynos_dp_enable,
+	.disable = exynos_dp_disable,
+};
+
+static struct drm_encoder_funcs exynos_dp_encoder_funcs = {
+	.destroy = drm_encoder_cleanup,
+};
+
+static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
+{
+	int ret;
+
+	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
+			       OF_USE_NATIVE_MODE);
+	if (ret) {
+		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
+		return ret;
+	}
+	return 0;
+}
+
+static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
+{
+	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = data;
+	int pipe, ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	dp->dev = dev;
+	dp->drm_dev = drm_dev;
+
+	dp->plat_data.dev_type = EXYNOS_DP;
+	dp->plat_data.power_on = exynos_dp_poweron;
+	dp->plat_data.power_off = exynos_dp_poweroff;
+	dp->plat_data.attach = exynos_dp_bridge_attach;
+
+	if (!dp->plat_data.panel || !dp->ptn_bridge) {
+		ret = exynos_dp_dt_parse_panel(dp);
+		if (ret)
+			return ret;
+	}
+
+	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
+						  EXYNOS_DISPLAY_TYPE_LCD);
+	if (pipe < 0)
+		return pipe;
+
+	encoder->possible_crtcs = 1 << pipe;
+
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
+			 DRM_MODE_ENCODER_TMDS);
+
+	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
+
+	dp->plat_data.encoder = encoder;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
+}
+
+static void exynos_dp_unbind(struct device *dev, struct device *master,
+			     void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops exynos_dp_ops = {
+	.bind	= exynos_dp_bind,
+	.unbind	= exynos_dp_unbind,
+};
+
+static int exynos_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *bridge_node, *endpoint;
+	struct exynos_dp_device *dp;
+
+	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
+			  GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver would take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	panel_node = of_parse_phandle(dev->of_node, "panel", 0);
+	if (panel_node) {
+		dp->plat_data.panel = of_drm_find_panel(panel_node);
+		of_node_put(panel_node);
+		if (!dp->plat_data.panel)
+			return -EPROBE_DEFER;
+	}
+
+	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
+	if (endpoint) {
+		bridge_node = of_graph_get_remote_port_parent(endpoint);
+		if (bridge_node) {
+			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
+			of_node_put(bridge_node);
+			if (!dp->ptn_bridge)
+				return -EPROBE_DEFER;
+		} else {
+			return -EPROBE_DEFER;
+		}
+	}
+
+	return component_add(&pdev->dev, &exynos_dp_ops);
+}
+
+static int exynos_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &exynos_dp_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int exynos_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops exynos_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
+};
+
+static const struct of_device_id exynos_dp_match[] = {
+	{ .compatible = "samsung,exynos5-dp" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, exynos_dp_match);
+
+struct platform_driver dp_driver = {
+	.probe		= exynos_dp_probe,
+	.remove		= exynos_dp_remove,
+	.driver		= {
+		.name	= "exynos-dp",
+		.owner	= THIS_MODULE,
+		.pm	= &exynos_dp_pm_ops,
+		.of_match_table = exynos_dp_match,
+	},
+};
+
+MODULE_AUTHOR("Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
+MODULE_DESCRIPTION("Samsung Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
deleted file mode 100644
index 66eec4b..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Header file for Samsung DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef _EXYNOS_DP_CORE_H
-#define _EXYNOS_DP_CORE_H
-
-#include <drm/drm_crtc.h>
-#include <drm/drm_dp_helper.h>
-#include <drm/exynos_drm.h>
-
-#include "exynos_drm_drv.h"
-
-#define DP_TIMEOUT_LOOP_COUNT 100
-#define MAX_CR_LOOP 5
-#define MAX_EQ_LOOP 5
-
-enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
-};
-
-enum link_lane_count_type {
-	LANE_COUNT1 = 1,
-	LANE_COUNT2 = 2,
-	LANE_COUNT4 = 4
-};
-
-enum link_training_state {
-	START,
-	CLOCK_RECOVERY,
-	EQUALIZER_TRAINING,
-	FINISHED,
-	FAILED
-};
-
-enum voltage_swing_level {
-	VOLTAGE_LEVEL_0,
-	VOLTAGE_LEVEL_1,
-	VOLTAGE_LEVEL_2,
-	VOLTAGE_LEVEL_3,
-};
-
-enum pre_emphasis_level {
-	PRE_EMPHASIS_LEVEL_0,
-	PRE_EMPHASIS_LEVEL_1,
-	PRE_EMPHASIS_LEVEL_2,
-	PRE_EMPHASIS_LEVEL_3,
-};
-
-enum pattern_set {
-	PRBS7,
-	D10_2,
-	TRAINING_PTN1,
-	TRAINING_PTN2,
-	DP_NONE
-};
-
-enum color_space {
-	COLOR_RGB,
-	COLOR_YCBCR422,
-	COLOR_YCBCR444
-};
-
-enum color_depth {
-	COLOR_6,
-	COLOR_8,
-	COLOR_10,
-	COLOR_12
-};
-
-enum color_coefficient {
-	COLOR_YCBCR601,
-	COLOR_YCBCR709
-};
-
-enum dynamic_range {
-	VESA,
-	CEA
-};
-
-enum pll_status {
-	PLL_UNLOCKED,
-	PLL_LOCKED
-};
-
-enum clock_recovery_m_value_type {
-	CALCULATED_M,
-	REGISTER_M
-};
-
-enum video_timing_recognition_type {
-	VIDEO_TIMING_FROM_CAPTURE,
-	VIDEO_TIMING_FROM_REGISTER
-};
-
-enum analog_power_block {
-	AUX_BLOCK,
-	CH0_BLOCK,
-	CH1_BLOCK,
-	CH2_BLOCK,
-	CH3_BLOCK,
-	ANALOG_TOTAL,
-	POWER_ALL
-};
-
-enum dp_irq_type {
-	DP_IRQ_TYPE_HP_CABLE_IN,
-	DP_IRQ_TYPE_HP_CABLE_OUT,
-	DP_IRQ_TYPE_HP_CHANGE,
-	DP_IRQ_TYPE_UNKNOWN,
-};
-
-struct video_info {
-	char *name;
-
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
-
-	enum color_space color_space;
-	enum dynamic_range dynamic_range;
-	enum color_coefficient ycbcr_coeff;
-	enum color_depth color_depth;
-
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
-};
-
-struct link_train {
-	int eq_loop;
-	int cr_loop[4];
-
-	u8 link_rate;
-	u8 lane_count;
-	u8 training_lane[4];
-
-	enum link_training_state lt_state;
-};
-
-struct exynos_dp_device {
-	struct drm_encoder	encoder;
-	struct device		*dev;
-	struct drm_device	*drm_dev;
-	struct drm_connector	connector;
-	struct drm_panel	*panel;
-	struct drm_bridge	*bridge;
-	struct drm_bridge	*ptn_bridge;
-	struct clk		*clock;
-	unsigned int		irq;
-	void __iomem		*reg_base;
-
-	struct video_info	*video_info;
-	struct link_train	link_train;
-	struct work_struct	hotplug_work;
-	struct phy		*phy;
-	int			dpms_mode;
-	int			hpd_gpio;
-
-	struct exynos_drm_panel_info priv;
-};
-
-/* exynos_dp_reg.c */
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_stop_video(struct exynos_dp_device *dp);
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
-void exynos_dp_reset(struct exynos_dp_device *dp);
-void exynos_dp_swreset(struct exynos_dp_device *dp);
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable);
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
-void exynos_dp_init_hpd(struct exynos_dp_device *dp);
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
-void exynos_dp_reset_aux(struct exynos_dp_device *dp);
-void exynos_dp_init_aux(struct exynos_dp_device *dp);
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern);
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
-void exynos_dp_reset_macro(struct exynos_dp_device *dp);
-void exynos_dp_init_video(struct exynos_dp_device *dp);
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_start_video(struct exynos_dp_device *dp);
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
-#endif /* _EXYNOS_DP_CORE_H */
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
deleted file mode 100644
index c1f87a2..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
+++ /dev/null
@@ -1,1263 +0,0 @@
-/*
- * Samsung DP (Display port) register interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-
-#include "exynos_dp_core.h"
-#include "exynos_dp_reg.h"
-
-#define COMMON_INT_MASK_1	0
-#define COMMON_INT_MASK_2	0
-#define COMMON_INT_MASK_3	0
-#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
-#define INT_STA_MASK		INT_HPD
-
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg |= HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg &= ~HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	}
-}
-
-void exynos_dp_stop_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg &= ~VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable)
-		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
-	else
-		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
-
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
-}
-
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = TX_TERMINAL_CTRL_50_OHM;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
-
-	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
-
-	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
-
-	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
-		TX_CUR1_2X | TX_CUR_16_MA;
-	writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
-
-	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
-		CH1_AMP_400_MV | CH0_AMP_400_MV;
-	writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
-}
-
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
-{
-	/* Set interrupt pin assertion polarity as high */
-	writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
-
-	/* Clear pending regisers */
-	writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-	writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
-	writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
-	writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-	writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* 0:mask,1: unmask */
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-	writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-void exynos_dp_reset(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	exynos_dp_stop_video(dp);
-	exynos_dp_enable_video_mute(dp, 0);
-
-	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
-		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
-		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
-		SERDES_FIFO_FUNC_EN_N |
-		LS_CLK_DOMAIN_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-
-	usleep_range(20, 30);
-
-	exynos_dp_lane_swap(dp, 0);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
-	writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
-
-	writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
-	writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
-
-	writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
-	writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
-
-	writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
-	writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
-
-	writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_swreset(struct exynos_dp_device *dp)
-{
-	writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
-}
-
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* 0: mask, 1: unmask */
-	reg = COMMON_INT_MASK_1;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-
-	reg = COMMON_INT_MASK_2;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-
-	reg = COMMON_INT_MASK_3;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-
-	reg = COMMON_INT_MASK_4;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-
-	reg = INT_STA_MASK;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	if (reg & PLL_LOCK)
-		return PLL_LOCKED;
-	else
-		return PLL_UNLOCKED;
-}
-
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg |= DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg &= ~DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	}
-}
-
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
-{
-	u32 reg;
-
-	switch (block) {
-	case AUX_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH0_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH1_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH2_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH3_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case ANALOG_TOTAL:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case POWER_ALL:
-		if (enable) {
-			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
-				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
-{
-	u32 reg;
-	int timeout_loop = 0;
-
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
-
-	reg = PLL_LOCK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-
-	/* Power up PLL */
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-		exynos_dp_set_pll_power_down(dp, 0);
-
-		while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-			timeout_loop++;
-			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-				dev_err(dp->dev, "failed to get pll lock status\n");
-				return;
-			}
-			usleep_range(10, 20);
-		}
-	}
-
-	/* Enable Serdes FIFO function and Link symbol clock domain module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
-		| AUX_FUNC_EN_N);
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-	reg = INT_HPD;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-}
-
-void exynos_dp_init_hpd(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	exynos_dp_clear_hotplug_interrupts(dp);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	reg &= ~(F_HPD | HPD_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-}
-
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		reg = gpio_get_value(dp->hpd_gpio);
-		if (reg)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-		else
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-	} else {
-		/* Parse hotplug interrupt status register */
-		reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-		if (reg & PLUG)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-
-		if (reg & HPD_LOST)
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-
-		if (reg & HOTPLUG_CHG)
-			return DP_IRQ_TYPE_HP_CHANGE;
-
-		return DP_IRQ_TYPE_UNKNOWN;
-	}
-}
-
-void exynos_dp_reset_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Disable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg |= AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_init_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Clear inerrupts related to AUX channel */
-	reg = RPLY_RECEIV | AUX_ERR;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	exynos_dp_reset_aux(dp);
-
-	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
-
-	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
-	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
-
-	/* Enable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		if (gpio_get_value(dp->hpd_gpio))
-			return 0;
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-		if (reg & HPD_STATUS)
-			return 0;
-	}
-
-	return -EINVAL;
-}
-
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-}
-
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
-{
-	int reg;
-	int retval = 0;
-	int timeout_loop = 0;
-
-	/* Enable AUX CH operation */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-	reg |= AUX_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-	/* Is AUX CH command reply received? */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	while (!(reg & RPLY_RECEIV)) {
-		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "AUX CH command reply failed!\n");
-			return -ETIMEDOUT;
-		}
-		reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-		usleep_range(10, 11);
-	}
-
-	/* Clear interrupt source for AUX CH command reply */
-	writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* Clear interrupt source for AUX CH access error */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	if (reg & AUX_ERR) {
-		writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
-		return -EREMOTEIO;
-	}
-
-	/* Check AUX CH error access status */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
-	if ((reg & AUX_STATUS_MASK) != 0) {
-		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
-			reg & AUX_STATUS_MASK);
-		return -EREMOTEIO;
-	}
-
-	return retval;
-}
-
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/* Write data buffer */
-		reg = (unsigned int)data;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-		/*
-		 * Set DisplayPort transaction and write 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/*
-		 * Set DisplayPort transaction and read 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	/* Read data buffer */
-	reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-	*data = (unsigned char)(reg & 0xff);
-
-	return retval;
-}
-
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-			     cur_data_idx++) {
-				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
-			}
-
-			/*
-			 * Set DisplayPort transaction and write
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		/* AUX CH Request Transaction process */
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			/*
-			 * Set DisplayPort transaction and read
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-		    cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			data[start_offset + cur_data_idx] =
-				(unsigned char)reg;
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
-{
-	u32 reg;
-	int retval;
-
-	/* Set EDID device address */
-	reg = device_addr;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-	/* Set offset from base address of EDID device */
-	writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	/*
-	 * Set I2C transaction and write address
-	 * If bit 3 is 1, DisplayPort transaction.
-	 * If Bit 3 is 0, I2C transaction.
-	 */
-	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
-		AUX_TX_COMM_WRITE;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction(dp);
-	if (retval != 0)
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select EDID device */
-		retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
-		if (retval != 0)
-			continue;
-
-		/*
-		 * Set I2C transaction and read data
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_I2C_TRANSACTION |
-			AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	/* Read data */
-	if (retval == 0)
-		*data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
-{
-	u32 reg;
-	unsigned int i, j;
-	unsigned int cur_data_idx;
-	unsigned int defer = 0;
-	int retval = 0;
-
-	for (i = 0; i < count; i += 16) {
-		for (j = 0; j < 3; j++) {
-			/* Clear AUX CH data buffer */
-			reg = BUF_CLR;
-			writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-			/* Set normal AUX CH command */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-			reg &= ~ADDR_ONLY;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-			/*
-			 * If Rx sends defer, Tx sends only reads
-			 * request without sending address
-			 */
-			if (!defer)
-				retval = exynos_dp_select_i2c_device(dp,
-						device_addr, reg_addr + i);
-			else
-				defer = 0;
-
-			if (retval == 0) {
-				/*
-				 * Set I2C transaction and write data
-				 * If bit 3 is 1, DisplayPort transaction.
-				 * If Bit 3 is 0, I2C transaction.
-				 */
-				reg = AUX_LENGTH(16) |
-					AUX_TX_COMM_I2C_TRANSACTION |
-					AUX_TX_COMM_READ;
-				writel(reg, dp->reg_base +
-					EXYNOS_DP_AUX_CH_CTL_1);
-
-				/* Start AUX transaction */
-				retval = exynos_dp_start_aux_transaction(dp);
-				if (retval == 0)
-					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
-			}
-			/* Check if Rx sends defer */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
-			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
-				dev_err(dp->dev, "Defer: %d\n\n", reg);
-				defer = 1;
-			}
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			edid[i + cur_data_idx] = (unsigned char)reg;
-		}
-	}
-
-	return retval;
-}
-
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
-{
-	u32 reg;
-
-	reg = bwtype;
-	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
-		writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-}
-
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-	*bwtype = reg;
-}
-
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
-{
-	u32 reg;
-
-	reg = count;
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-}
-
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-	*count = reg;
-}
-
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	}
-}
-
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern)
-{
-	u32 reg;
-
-	switch (pattern) {
-	case PRBS7:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case D10_2:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN1:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN2:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case DP_NONE:
-		reg = SCRAMBLING_ENABLE |
-			LINK_QUAL_PATTERN_SET_DISABLE |
-			SW_TRAINING_PATTERN_SET_NORMAL;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	return reg;
-}
-
-void exynos_dp_reset_macro(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
-	reg |= MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	/* 10 us is the minimum reset time. */
-	usleep_range(10, 20);
-
-	reg &= ~MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-}
-
-void exynos_dp_init_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = CHA_CRI(4) | CHA_CTRL;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
-}
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
-
-	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
-		reg |= IN_YC_COEFFI_ITU709;
-	else
-		reg |= IN_YC_COEFFI_ITU601;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-}
-
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	if (!(reg & DET_STA)) {
-		dev_dbg(dp->dev, "Input stream clock not detected.\n");
-		return -EINVAL;
-	}
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
-
-	if (reg & CHA_STA) {
-		dev_dbg(dp->dev, "Input stream clk is changing\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
-{
-	u32 reg;
-
-	if (type == REGISTER_M) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg = m_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
-		reg = (m_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
-		reg = (m_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
-
-		reg = n_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
-		reg = (n_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
-		reg = (n_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
-	} else  {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
-		writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
-	}
-}
-
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
-{
-	u32 reg;
-
-	if (type == VIDEO_TIMING_FROM_CAPTURE) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg &= ~FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg |= FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	}
-}
-
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MODE_SLAVE_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	}
-}
-
-void exynos_dp_start_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg |= VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	if (!(reg & STRM_VALID)) {
-		dev_dbg(dp->dev, "Input video stream is not detected.\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
-	reg |= MASTER_VID_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-	writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg &= ~SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
-
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg |= SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
new file mode 100644
index 0000000..134638af
--- /dev/null
+++ b/include/drm/bridge/analogix_dp.h
@@ -0,0 +1,41 @@
+/*
+ * Analogix DP (Display Port) Core interface driver.
+ *
+ * Copyright (C) 2015 Rockchip Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _ANALOGIX_DP_H_
+#define _ANALOGIX_DP_H_
+
+#include <drm/drm_crtc.h>
+
+enum analogix_dp_devtype {
+	EXYNOS_DP,
+};
+
+struct analogix_dp_plat_data {
+	enum analogix_dp_devtype dev_type;
+	struct drm_panel *panel;
+	struct drm_encoder *encoder;
+	struct drm_connector *connector;
+
+	int (*power_on)(struct analogix_dp_plat_data *);
+	int (*power_off)(struct analogix_dp_plat_data *);
+	int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *);
+};
+
+enum drm_connector_status analogix_dp_detect(struct device *dev, bool force);
+int analogix_dp_get_modes(struct device *dev);
+
+int analogix_dp_resume(struct device *dev);
+int analogix_dp_suspend(struct device *dev);
+
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct analogix_dp_plat_data *plat_data);
+void analogix_dp_unbind(struct device *dev, struct device *master, void *data);
+
+#endif /* _ANALOGIX_DP_H_ */
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 03/17] drm: bridge: analogix/dp: fix some obvious code style
  2015-09-22  7:20   ` Yakir Yang
@ 2015-09-22  7:34     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:34 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
  from exynos_dp code, and rephrase reasonable commit message, and
  remove some controversial style (Krzysztof)
    -		analogix_dp_write_byte_to_dpcd(
    - 				dp, DP_TEST_RESPONSE,
    +		analogix_dp_write_byte_to_dpcd(dp,
    +				DP_TEST_RESPONSE,
				DP_TEST_EDID_CHECKSUM_WRITE);

Changes in v4: None
Changes in v3: None
Changes in v2:
- Improved commit message more readable, and avoid using some
  uncommon style like bellow: (Joe Preches)
    -  retval = exynos_dp_read_bytes_from_i2c(...
  				  ...);
    +  retval =
    +  exynos_dp_read_bytes_from_i2c(......);

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++++++++++-----------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  72 ++++++------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 124 ++++++++++----------
 3 files changed, 163 insertions(+), 162 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 8a7ba12..fa9eb19 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -61,7 +61,7 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 
 	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
 			return -ETIMEDOUT;
 		}
@@ -98,8 +98,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
 	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-				EDID_EXTENSION_FLAG,
-				&extend_block);
+						EDID_EXTENSION_FLAG,
+						&extend_block);
 	if (retval)
 		return retval;
 
@@ -107,7 +107,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
+						I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -138,7 +139,7 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		}
 
 		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					&test_vector);
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
@@ -152,10 +153,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 		/* Read EDID data */
 		retval = analogix_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_HEADER_PATTERN,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_HEADER_PATTERN]);
+				I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
+				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -166,16 +165,13 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 			return -EIO;
 		}
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TEST_REQUEST,
-			&test_vector);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
+				DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
+				DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE);
 		}
 	}
 
@@ -190,8 +186,7 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
-				12, buf);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
 	if (retval)
 		return retval;
 
@@ -205,8 +200,9 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
-						bool enable)
+static void
+analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
+				       bool enable)
 {
 	u8 data;
 
@@ -214,11 +210,11 @@ static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp
 
 	if (enable)
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DP_LANE_COUNT_ENHANCED_FRAME_EN |
-			DPCD_LANE_COUNT_SET(data));
+					       DP_LANE_COUNT_ENHANCED_FRAME_EN |
+					       DPCD_LANE_COUNT_SET(data));
 	else
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DPCD_LANE_COUNT_SET(data));
+					       DPCD_LANE_COUNT_SET(data));
 }
 
 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
@@ -245,13 +241,13 @@ static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
 	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	analogix_dp_write_byte_to_dpcd(dp,
-		DP_TRAINING_PATTERN_SET,
-		DP_TRAINING_PATTERN_DISABLE);
+	analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+				       DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
-					int pre_emphasis, int lane)
+static void
+analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
+				       int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -291,8 +287,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
-				2, buf);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
 	if (retval)
 		return retval;
 
@@ -328,7 +323,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
 	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, buf);
+						 lane_count, buf);
 
 	return retval;
 }
@@ -336,7 +331,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = link_status[lane>>1];
+	u8 link_value = link_status[lane >> 1];
 
 	return (link_value >> shift) & 0xf;
 }
@@ -355,7 +350,7 @@ static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 }
 
 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				int lane_count)
+				     int lane_count)
 {
 	int lane;
 	u8 lane_status;
@@ -373,11 +368,11 @@ static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							int lane)
+static unsigned char
+analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return (link_value >> shift) & 0x3;
 }
@@ -387,13 +382,13 @@ static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
-					u8 training_lane_set, int lane)
+					       u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -413,9 +408,9 @@ static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 	}
 }
 
-static unsigned int analogix_dp_get_lane_link_training(
-				struct analogix_dp_device *dp,
-				int lane)
+static unsigned int
+analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
+				   int lane)
 {
 	u32 reg;
 
@@ -449,7 +444,7 @@ static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
-					u8 adjust_request[2])
+						 u8 adjust_request[2])
 {
 	int lane, lane_count;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -622,7 +617,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
-					u8 *bandwidth)
+					     u8 *bandwidth)
 {
 	u8 data;
 
@@ -635,7 +630,7 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
-					u8 *lane_count)
+					      u8 *lane_count)
 {
 	u8 data;
 
@@ -648,8 +643,8 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_init_training(struct analogix_dp_device *dp,
-			enum link_lane_count_type max_lane,
-			enum link_rate_type max_rate)
+				      enum link_lane_count_type max_lane,
+				      enum link_rate_type max_rate)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
@@ -662,7 +657,7 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -722,8 +717,7 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 }
 
 static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
-				u32 count,
-				u32 bwtype)
+				      u32 count, u32 bwtype)
 {
 	int i;
 	int retval;
@@ -759,7 +753,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		timeout_loop++;
 		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -790,7 +784,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		} else if (done_count) {
 			done_count = 0;
 		}
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -804,25 +798,24 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
+					bool enable)
 {
 	u8 data;
 
 	if (enable) {
 		analogix_dp_enable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
 		analogix_dp_disable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
@@ -895,7 +888,7 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	}
 
 	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					dp->video_info->link_rate);
+					 dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1082,8 +1075,8 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
 
-	dp_video_config = devm_kzalloc(dev,
-				sizeof(*dp_video_config), GFP_KERNEL);
+	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
+				       GFP_KERNEL);
 	if (!dp_video_config)
 		return ERR_PTR(-ENOMEM);
 
@@ -1097,37 +1090,37 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 		of_property_read_bool(dp_node, "interlaced");
 
 	if (of_property_read_u32(dp_node, "samsung,color-space",
-				&dp_video_config->color_space)) {
+				 &dp_video_config->color_space)) {
 		dev_err(dev, "failed to get color-space\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				&dp_video_config->dynamic_range)) {
+				 &dp_video_config->dynamic_range)) {
 		dev_err(dev, "failed to get dynamic-range\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				&dp_video_config->ycbcr_coeff)) {
+				 &dp_video_config->ycbcr_coeff)) {
 		dev_err(dev, "failed to get ycbcr-coeff\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				&dp_video_config->color_depth)) {
+				 &dp_video_config->color_depth)) {
 		dev_err(dev, "failed to get color-depth\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				&dp_video_config->link_rate)) {
+				 &dp_video_config->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				&dp_video_config->lane_count)) {
+				 &dp_video_config->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
 		return ERR_PTR(-EINVAL);
 	}
@@ -1238,7 +1231,7 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	analogix_dp_init_dp(dp);
 
 	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
-			irq_flags, "analogix-dp", dp);
+			       irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		return ret;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 65ce7f1..14d20be 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -187,50 +187,55 @@ int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
+				   unsigned int reg_addr,
+				   unsigned char data);
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
+				    unsigned int reg_addr,
+				    unsigned char *data);
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[]);
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[]);
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
+				  unsigned int device_addr,
+				  unsigned int reg_addr);
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data);
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[]);
 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable);
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern);
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+				      enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
@@ -241,11 +246,12 @@ void analogix_dp_init_video(struct analogix_dp_device *dp);
 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value,
+				 u32 n_value);
 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
-void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
+				     bool enable);
 void analogix_dp_start_video(struct analogix_dp_device *dp);
 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 442cc66..a388c0a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -54,10 +54,10 @@ void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
 
 	if (enable)
 		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+		      LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
 	else
 		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+		      LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
 
 	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
 }
@@ -202,8 +202,8 @@ void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
 }
 
 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
+				       enum analog_power_block block,
+				       bool enable)
 {
 	u32 reg;
 
@@ -399,8 +399,8 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
+	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
@@ -483,8 +483,8 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
 }
 
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
+				   unsigned int reg_addr,
+				   unsigned char data)
 {
 	u32 reg;
 	int i;
@@ -519,17 +519,16 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	return retval;
 }
 
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
+				    unsigned int reg_addr,
+				    unsigned char *data)
 {
 	u32 reg;
 	int i;
@@ -560,9 +559,8 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data buffer */
@@ -573,9 +571,9 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -608,8 +606,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 			     cur_data_idx++) {
 				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
+				writel(reg, dp->reg_base +
+				       ANALOGIX_DP_BUF_DATA_0 +
+				       4 * cur_data_idx);
 			}
 
 			/*
@@ -625,9 +624,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		start_offset += cur_data_count;
@@ -637,9 +636,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -683,9 +682,9 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
@@ -703,8 +702,8 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
+				  unsigned int device_addr,
+				  unsigned int reg_addr)
 {
 	u32 reg;
 	int retval;
@@ -736,9 +735,9 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data)
 {
 	u32 reg;
 	int i;
@@ -750,7 +749,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 		/* Select EDID device */
-		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+		retval = analogix_dp_select_i2c_device(dp, device_addr,
+						       reg_addr);
 		if (retval != 0)
 			continue;
 
@@ -767,9 +767,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data */
@@ -780,10 +779,10 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[])
 {
 	u32 reg;
 	unsigned int i, j;
@@ -828,15 +827,14 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 				retval = analogix_dp_start_aux_transaction(dp);
 				if (retval == 0)
 					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
+
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
 			}
 			/* Check if Rx sends defer */
 			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
 			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
+			    reg == AUX_RX_COMM_I2C_DEFER) {
 				dev_err(dp->dev, "Defer: %d\n\n", reg);
 				defer = 1;
 			}
@@ -885,7 +883,8 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
 	*count = reg;
 }
 
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable)
 {
 	u32 reg;
 
@@ -901,7 +900,7 @@ void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable
 }
 
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern)
+				      enum pattern_set pattern)
 {
 	u32 reg;
 
@@ -933,7 +932,8 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
 	}
 }
 
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -943,7 +943,8 @@ void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -953,7 +954,8 @@ void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -963,7 +965,8 @@ void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -974,7 +977,7 @@ void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level
 }
 
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -983,7 +986,7 @@ void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1001,7 +1004,7 @@ void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1125,9 +1128,8 @@ int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
 }
 
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value, u32 n_value)
 {
 	u32 reg;
 
@@ -1221,7 +1223,7 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 	u32 reg;
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
 	reg |= MASTER_VID_FUNC_EN_N;
 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 03/17] drm: bridge: analogix/dp: fix some obvious code style
@ 2015-09-22  7:34     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:34 UTC (permalink / raw)
  To: linux-arm-kernel

Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
  from exynos_dp code, and rephrase reasonable commit message, and
  remove some controversial style (Krzysztof)
    -		analogix_dp_write_byte_to_dpcd(
    - 				dp, DP_TEST_RESPONSE,
    +		analogix_dp_write_byte_to_dpcd(dp,
    +				DP_TEST_RESPONSE,
				DP_TEST_EDID_CHECKSUM_WRITE);

Changes in v4: None
Changes in v3: None
Changes in v2:
- Improved commit message more readable, and avoid using some
  uncommon style like bellow: (Joe Preches)
    -  retval = exynos_dp_read_bytes_from_i2c(...
  				  ...);
    +  retval =
    +  exynos_dp_read_bytes_from_i2c(......);

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++++++++++-----------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  72 ++++++------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 124 ++++++++++----------
 3 files changed, 163 insertions(+), 162 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 8a7ba12..fa9eb19 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -61,7 +61,7 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 
 	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
 			return -ETIMEDOUT;
 		}
@@ -98,8 +98,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
 	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-				EDID_EXTENSION_FLAG,
-				&extend_block);
+						EDID_EXTENSION_FLAG,
+						&extend_block);
 	if (retval)
 		return retval;
 
@@ -107,7 +107,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
+						I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -138,7 +139,7 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		}
 
 		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					&test_vector);
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
@@ -152,10 +153,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 		/* Read EDID data */
 		retval = analogix_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_HEADER_PATTERN,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_HEADER_PATTERN]);
+				I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
+				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -166,16 +165,13 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 			return -EIO;
 		}
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TEST_REQUEST,
-			&test_vector);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
+				DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
+				DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE);
 		}
 	}
 
@@ -190,8 +186,7 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
-				12, buf);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
 	if (retval)
 		return retval;
 
@@ -205,8 +200,9 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
-						bool enable)
+static void
+analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
+				       bool enable)
 {
 	u8 data;
 
@@ -214,11 +210,11 @@ static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp
 
 	if (enable)
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DP_LANE_COUNT_ENHANCED_FRAME_EN |
-			DPCD_LANE_COUNT_SET(data));
+					       DP_LANE_COUNT_ENHANCED_FRAME_EN |
+					       DPCD_LANE_COUNT_SET(data));
 	else
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DPCD_LANE_COUNT_SET(data));
+					       DPCD_LANE_COUNT_SET(data));
 }
 
 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
@@ -245,13 +241,13 @@ static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
 	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	analogix_dp_write_byte_to_dpcd(dp,
-		DP_TRAINING_PATTERN_SET,
-		DP_TRAINING_PATTERN_DISABLE);
+	analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+				       DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
-					int pre_emphasis, int lane)
+static void
+analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
+				       int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -291,8 +287,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
-				2, buf);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
 	if (retval)
 		return retval;
 
@@ -328,7 +323,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
 	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, buf);
+						 lane_count, buf);
 
 	return retval;
 }
@@ -336,7 +331,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = link_status[lane>>1];
+	u8 link_value = link_status[lane >> 1];
 
 	return (link_value >> shift) & 0xf;
 }
@@ -355,7 +350,7 @@ static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 }
 
 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				int lane_count)
+				     int lane_count)
 {
 	int lane;
 	u8 lane_status;
@@ -373,11 +368,11 @@ static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							int lane)
+static unsigned char
+analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return (link_value >> shift) & 0x3;
 }
@@ -387,13 +382,13 @@ static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
-					u8 training_lane_set, int lane)
+					       u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -413,9 +408,9 @@ static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 	}
 }
 
-static unsigned int analogix_dp_get_lane_link_training(
-				struct analogix_dp_device *dp,
-				int lane)
+static unsigned int
+analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
+				   int lane)
 {
 	u32 reg;
 
@@ -449,7 +444,7 @@ static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
-					u8 adjust_request[2])
+						 u8 adjust_request[2])
 {
 	int lane, lane_count;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -622,7 +617,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
-					u8 *bandwidth)
+					     u8 *bandwidth)
 {
 	u8 data;
 
@@ -635,7 +630,7 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
-					u8 *lane_count)
+					      u8 *lane_count)
 {
 	u8 data;
 
@@ -648,8 +643,8 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_init_training(struct analogix_dp_device *dp,
-			enum link_lane_count_type max_lane,
-			enum link_rate_type max_rate)
+				      enum link_lane_count_type max_lane,
+				      enum link_rate_type max_rate)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
@@ -662,7 +657,7 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -722,8 +717,7 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 }
 
 static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
-				u32 count,
-				u32 bwtype)
+				      u32 count, u32 bwtype)
 {
 	int i;
 	int retval;
@@ -759,7 +753,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		timeout_loop++;
 		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -790,7 +784,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		} else if (done_count) {
 			done_count = 0;
 		}
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -804,25 +798,24 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
+					bool enable)
 {
 	u8 data;
 
 	if (enable) {
 		analogix_dp_enable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
 		analogix_dp_disable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
@@ -895,7 +888,7 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	}
 
 	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					dp->video_info->link_rate);
+					 dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1082,8 +1075,8 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
 
-	dp_video_config = devm_kzalloc(dev,
-				sizeof(*dp_video_config), GFP_KERNEL);
+	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
+				       GFP_KERNEL);
 	if (!dp_video_config)
 		return ERR_PTR(-ENOMEM);
 
@@ -1097,37 +1090,37 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 		of_property_read_bool(dp_node, "interlaced");
 
 	if (of_property_read_u32(dp_node, "samsung,color-space",
-				&dp_video_config->color_space)) {
+				 &dp_video_config->color_space)) {
 		dev_err(dev, "failed to get color-space\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				&dp_video_config->dynamic_range)) {
+				 &dp_video_config->dynamic_range)) {
 		dev_err(dev, "failed to get dynamic-range\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				&dp_video_config->ycbcr_coeff)) {
+				 &dp_video_config->ycbcr_coeff)) {
 		dev_err(dev, "failed to get ycbcr-coeff\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				&dp_video_config->color_depth)) {
+				 &dp_video_config->color_depth)) {
 		dev_err(dev, "failed to get color-depth\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				&dp_video_config->link_rate)) {
+				 &dp_video_config->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				&dp_video_config->lane_count)) {
+				 &dp_video_config->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
 		return ERR_PTR(-EINVAL);
 	}
@@ -1238,7 +1231,7 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	analogix_dp_init_dp(dp);
 
 	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
-			irq_flags, "analogix-dp", dp);
+			       irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		return ret;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 65ce7f1..14d20be 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -187,50 +187,55 @@ int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
+				   unsigned int reg_addr,
+				   unsigned char data);
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
+				    unsigned int reg_addr,
+				    unsigned char *data);
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[]);
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[]);
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
+				  unsigned int device_addr,
+				  unsigned int reg_addr);
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data);
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[]);
 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable);
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern);
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+				      enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
@@ -241,11 +246,12 @@ void analogix_dp_init_video(struct analogix_dp_device *dp);
 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value,
+				 u32 n_value);
 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
-void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
+				     bool enable);
 void analogix_dp_start_video(struct analogix_dp_device *dp);
 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 442cc66..a388c0a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -54,10 +54,10 @@ void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
 
 	if (enable)
 		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+		      LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
 	else
 		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+		      LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
 
 	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
 }
@@ -202,8 +202,8 @@ void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
 }
 
 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
+				       enum analog_power_block block,
+				       bool enable)
 {
 	u32 reg;
 
@@ -399,8 +399,8 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
+	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
@@ -483,8 +483,8 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
 }
 
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
+				   unsigned int reg_addr,
+				   unsigned char data)
 {
 	u32 reg;
 	int i;
@@ -519,17 +519,16 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	return retval;
 }
 
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
+				    unsigned int reg_addr,
+				    unsigned char *data)
 {
 	u32 reg;
 	int i;
@@ -560,9 +559,8 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data buffer */
@@ -573,9 +571,9 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -608,8 +606,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 			     cur_data_idx++) {
 				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
+				writel(reg, dp->reg_base +
+				       ANALOGIX_DP_BUF_DATA_0 +
+				       4 * cur_data_idx);
 			}
 
 			/*
@@ -625,9 +624,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		start_offset += cur_data_count;
@@ -637,9 +636,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -683,9 +682,9 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
@@ -703,8 +702,8 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
+				  unsigned int device_addr,
+				  unsigned int reg_addr)
 {
 	u32 reg;
 	int retval;
@@ -736,9 +735,9 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data)
 {
 	u32 reg;
 	int i;
@@ -750,7 +749,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 		/* Select EDID device */
-		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+		retval = analogix_dp_select_i2c_device(dp, device_addr,
+						       reg_addr);
 		if (retval != 0)
 			continue;
 
@@ -767,9 +767,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data */
@@ -780,10 +779,10 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[])
 {
 	u32 reg;
 	unsigned int i, j;
@@ -828,15 +827,14 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 				retval = analogix_dp_start_aux_transaction(dp);
 				if (retval == 0)
 					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
+
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
 			}
 			/* Check if Rx sends defer */
 			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
 			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
+			    reg == AUX_RX_COMM_I2C_DEFER) {
 				dev_err(dp->dev, "Defer: %d\n\n", reg);
 				defer = 1;
 			}
@@ -885,7 +883,8 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
 	*count = reg;
 }
 
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable)
 {
 	u32 reg;
 
@@ -901,7 +900,7 @@ void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable
 }
 
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern)
+				      enum pattern_set pattern)
 {
 	u32 reg;
 
@@ -933,7 +932,8 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
 	}
 }
 
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -943,7 +943,8 @@ void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -953,7 +954,8 @@ void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -963,7 +965,8 @@ void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -974,7 +977,7 @@ void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level
 }
 
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -983,7 +986,7 @@ void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1001,7 +1004,7 @@ void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1125,9 +1128,8 @@ int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
 }
 
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value, u32 n_value)
 {
 	u32 reg;
 
@@ -1221,7 +1223,7 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 	u32 reg;
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
 	reg |= MASTER_VID_FUNC_EN_N;
 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
@ 2015-09-22  7:35     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:35 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.

Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04

Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
  directly, but we can take those as hardware limite. For example, RK3288
  only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
  like "link-rate = 0x0a" "lane-count = 4". (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index fa9eb19..1e3c8d3 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -624,6 +624,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 	/*
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+	 * For DP rev.1.2, Maximum link rate of Main Link lanes
+	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 	 */
 	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
@@ -657,7 +659,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS) &&
+	    (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -898,9 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
 	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
-	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
 	analogix_dp_init_video(dp);
 	ret = analogix_dp_config_video(dp);
 	if (ret)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 14d20be..9a90a18 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -21,8 +21,9 @@
 #define MAX_EQ_LOOP 5
 
 enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
+	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
+	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
+	LINK_RATE_5_40GBPS = DP_LINK_BW_5_4,
 };
 
 enum link_lane_count_type {
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
@ 2015-09-22  7:35     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:35 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe-6d6DIl74uiNBDgjK7y7TUQ, Krzysztof Kozlowski,
	Rob Herring
  Cc: David Airlie, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Yakir Yang, Gustavo Padovan,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Russell King,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Sean Paul, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kumar Gala,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan

link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.

Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04

Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
  directly, but we can take those as hardware limite. For example, RK3288
  only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
  like "link-rate = 0x0a" "lane-count = 4". (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index fa9eb19..1e3c8d3 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -624,6 +624,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 	/*
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+	 * For DP rev.1.2, Maximum link rate of Main Link lanes
+	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 	 */
 	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
@@ -657,7 +659,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS) &&
+	    (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -898,9 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
 	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
-	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
 	analogix_dp_init_video(dp);
 	ret = analogix_dp_config_video(dp);
 	if (ret)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 14d20be..9a90a18 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -21,8 +21,9 @@
 #define MAX_EQ_LOOP 5
 
 enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
+	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
+	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
+	LINK_RATE_5_40GBPS = DP_LINK_BW_5_4,
 };
 
 enum link_lane_count_type {
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
@ 2015-09-22  7:35     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:35 UTC (permalink / raw)
  To: linux-arm-kernel

link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.

Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04

Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
  directly, but we can take those as hardware limite. For example, RK3288
  only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
  like "link-rate = 0x0a" "lane-count = 4". (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index fa9eb19..1e3c8d3 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -624,6 +624,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 	/*
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+	 * For DP rev.1.2, Maximum link rate of Main Link lanes
+	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 	 */
 	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
@@ -657,7 +659,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS) &&
+	    (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -898,9 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
 	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
-	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
 	analogix_dp_init_video(dp);
 	ret = analogix_dp_config_video(dp);
 	if (ret)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 14d20be..9a90a18 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -21,8 +21,9 @@
 #define MAX_EQ_LOOP 5
 
 enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
+	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
+	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
+	LINK_RATE_5_40GBPS = DP_LINK_BW_5_4,
 };
 
 enum link_lane_count_type {
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-09-22  7:37     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:37 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.

But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).

Changes in v4:
- Provide backword compatibility with samsung. (Krzysztof)

Changes in v3:
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 144 +++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   8 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
 3 files changed, 104 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 1e3c8d3..6be139b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					 dp->video_info->link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
+					 dp->video_info.link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
+					struct drm_display_mode *orig_mode,
+					struct drm_display_mode *mode)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_display_info *display_info = &dp->connector->display_info;
+	struct video_info *video = &dp->video_info;
+	struct device_node *dp_node = dp->dev->of_node;
+	int vic;
+
+	/* Input video interlaces & hsync pol & vsync pol */
+	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+	/* Input video dynamic_range & colorimetry */
+	vic = drm_match_cea_mode(mode);
+	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
+	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR601;
+	} else if (vic) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	} else {
+		video->dynamic_range = VESA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	}
+
+	/* Input vide bpc and color_formats */
+	switch (display_info->bpc) {
+	case 12:
+		video->color_depth = COLOR_12;
+		break;
+	case 10:
+		video->color_depth = COLOR_10;
+		break;
+	case 8:
+		video->color_depth = COLOR_8;
+		break;
+	case 6:
+		video->color_depth = COLOR_6;
+		break;
+	default:
+		video->color_depth = COLOR_8;
+		break;
+	}
+	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
+		video->color_space = COLOR_YCBCR444;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
+		video->color_space = COLOR_YCBCR422;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
+		video->color_space = COLOR_RGB;
+	else
+		video->color_space = COLOR_RGB;
+
+	/*
+	 * NOTE: those property parsing code is used for providing backward
+	 * compatibility for samsung platform.
+	 * Due to we used the "of_property_read_u32" interfaces, when this
+	 * property isn't present, the "video_info" can keep the original
+	 * values and wouldn't be modified.
+	 */
+	of_property_read_u32(dp_node, "samsung,color-space",
+			     &video->color_space);
+	of_property_read_u32(dp_node, "samsung,dynamic-range",
+			     &video->dynamic_range);
+	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+			     &video->ycbcr_coeff);
+	of_property_read_u32(dp_node, "samsung,color-depth",
+			     &video->color_depth);
+	of_property_read_u32(dp_node, "hsync-active-high",
+			     &video->h_sync_polarity);
+	of_property_read_u32(dp_node, "vsync-active-high",
+			     &video->v_sync_polarity);
+	of_property_read_u32(dp_node, "interlaced",
+			     &video->interlaced);
+}
+
 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
@@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
 	.disable = analogix_dp_bridge_disable,
 	.pre_enable = analogix_dp_bridge_nop,
 	.post_disable = analogix_dp_bridge_nop,
+	.mode_set = analogix_dp_bridge_mode_set,
 	.attach = analogix_dp_bridge_attach,
 };
 
@@ -1070,62 +1150,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 	return 0;
 }
 
-static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
-	struct device_node *dp_node = dev->of_node;
-	struct video_info *dp_video_config;
-
-	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
-				       GFP_KERNEL);
-	if (!dp_video_config)
-		return ERR_PTR(-ENOMEM);
-
-	dp_video_config->h_sync_polarity =
-		of_property_read_bool(dp_node, "hsync-active-high");
-
-	dp_video_config->v_sync_polarity =
-		of_property_read_bool(dp_node, "vsync-active-high");
-
-	dp_video_config->interlaced =
-		of_property_read_bool(dp_node, "interlaced");
-
-	if (of_property_read_u32(dp_node, "samsung,color-space",
-				 &dp_video_config->color_space)) {
-		dev_err(dev, "failed to get color-space\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				 &dp_video_config->dynamic_range)) {
-		dev_err(dev, "failed to get dynamic-range\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				 &dp_video_config->ycbcr_coeff)) {
-		dev_err(dev, "failed to get ycbcr-coeff\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				 &dp_video_config->color_depth)) {
-		dev_err(dev, "failed to get color-depth\n");
-		return ERR_PTR(-EINVAL);
-	}
+	struct device_node *dp_node = dp->dev->of_node;
+	struct video_info *video_info = &dp->video_info
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &dp_video_config->link_rate)) {
+				 &video_info->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
-		return ERR_PTR(-EINVAL);
+		return -EINVAL;
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &dp_video_config->lane_count)) {
+				 &video_info->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
-		return ERR_PTR(-EINVAL);
+		return -EINVAL;
 	}
 
-	return dp_video_config;
+	return 0;
 }
 
 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
@@ -1158,9 +1200,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	 */
 	dp->plat_data = plat_data;
 
-	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
-	if (IS_ERR(dp->video_info))
-		return PTR_ERR(dp->video_info);
+	ret = analogix_dp_dt_parse_pdata(dp);
+	if (ret)
+		return ret;
 
 	dp->phy = devm_phy_get(dp->dev, "dp");
 	if (IS_ERR(dp->phy)) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 9a90a18..730486d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -120,9 +120,9 @@ enum dp_irq_type {
 struct video_info {
 	char *name;
 
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
+	u32 h_sync_polarity;
+	u32 v_sync_polarity;
+	u32 interlaced;
 
 	enum color_space color_space;
 	enum dynamic_range dynamic_range;
@@ -154,7 +154,7 @@ struct analogix_dp_device {
 	unsigned int		irq;
 	void __iomem		*reg_base;
 
-	struct video_info	*video_info;
+	struct video_info	video_info;
 	struct link_train	link_train;
 	struct work_struct	hotplug_work;
 	struct phy		*phy;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index a388c0a..861097a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
 	u32 reg;
 
 	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info.color_depth << IN_BPC_SHIFT) |
+		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
 	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
+	if (dp->video_info.ycbcr_coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
@@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
+	reg |= (dp->video_info.interlaced << 2);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
+	reg |= (dp->video_info.v_sync_polarity << 1);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
+	reg |= (dp->video_info.h_sync_polarity << 0);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-09-22  7:37     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:37 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe-6d6DIl74uiNBDgjK7y7TUQ, Krzysztof Kozlowski,
	Rob Herring
  Cc: David Airlie, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Yakir Yang, Gustavo Padovan,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Russell King,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Sean Paul, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kumar Gala,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.

But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).

Changes in v4:
- Provide backword compatibility with samsung. (Krzysztof)

Changes in v3:
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 144 +++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   8 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
 3 files changed, 104 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 1e3c8d3..6be139b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					 dp->video_info->link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
+					 dp->video_info.link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
+					struct drm_display_mode *orig_mode,
+					struct drm_display_mode *mode)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_display_info *display_info = &dp->connector->display_info;
+	struct video_info *video = &dp->video_info;
+	struct device_node *dp_node = dp->dev->of_node;
+	int vic;
+
+	/* Input video interlaces & hsync pol & vsync pol */
+	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+	/* Input video dynamic_range & colorimetry */
+	vic = drm_match_cea_mode(mode);
+	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
+	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR601;
+	} else if (vic) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	} else {
+		video->dynamic_range = VESA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	}
+
+	/* Input vide bpc and color_formats */
+	switch (display_info->bpc) {
+	case 12:
+		video->color_depth = COLOR_12;
+		break;
+	case 10:
+		video->color_depth = COLOR_10;
+		break;
+	case 8:
+		video->color_depth = COLOR_8;
+		break;
+	case 6:
+		video->color_depth = COLOR_6;
+		break;
+	default:
+		video->color_depth = COLOR_8;
+		break;
+	}
+	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
+		video->color_space = COLOR_YCBCR444;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
+		video->color_space = COLOR_YCBCR422;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
+		video->color_space = COLOR_RGB;
+	else
+		video->color_space = COLOR_RGB;
+
+	/*
+	 * NOTE: those property parsing code is used for providing backward
+	 * compatibility for samsung platform.
+	 * Due to we used the "of_property_read_u32" interfaces, when this
+	 * property isn't present, the "video_info" can keep the original
+	 * values and wouldn't be modified.
+	 */
+	of_property_read_u32(dp_node, "samsung,color-space",
+			     &video->color_space);
+	of_property_read_u32(dp_node, "samsung,dynamic-range",
+			     &video->dynamic_range);
+	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+			     &video->ycbcr_coeff);
+	of_property_read_u32(dp_node, "samsung,color-depth",
+			     &video->color_depth);
+	of_property_read_u32(dp_node, "hsync-active-high",
+			     &video->h_sync_polarity);
+	of_property_read_u32(dp_node, "vsync-active-high",
+			     &video->v_sync_polarity);
+	of_property_read_u32(dp_node, "interlaced",
+			     &video->interlaced);
+}
+
 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
@@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
 	.disable = analogix_dp_bridge_disable,
 	.pre_enable = analogix_dp_bridge_nop,
 	.post_disable = analogix_dp_bridge_nop,
+	.mode_set = analogix_dp_bridge_mode_set,
 	.attach = analogix_dp_bridge_attach,
 };
 
@@ -1070,62 +1150,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 	return 0;
 }
 
-static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
-	struct device_node *dp_node = dev->of_node;
-	struct video_info *dp_video_config;
-
-	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
-				       GFP_KERNEL);
-	if (!dp_video_config)
-		return ERR_PTR(-ENOMEM);
-
-	dp_video_config->h_sync_polarity =
-		of_property_read_bool(dp_node, "hsync-active-high");
-
-	dp_video_config->v_sync_polarity =
-		of_property_read_bool(dp_node, "vsync-active-high");
-
-	dp_video_config->interlaced =
-		of_property_read_bool(dp_node, "interlaced");
-
-	if (of_property_read_u32(dp_node, "samsung,color-space",
-				 &dp_video_config->color_space)) {
-		dev_err(dev, "failed to get color-space\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				 &dp_video_config->dynamic_range)) {
-		dev_err(dev, "failed to get dynamic-range\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				 &dp_video_config->ycbcr_coeff)) {
-		dev_err(dev, "failed to get ycbcr-coeff\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				 &dp_video_config->color_depth)) {
-		dev_err(dev, "failed to get color-depth\n");
-		return ERR_PTR(-EINVAL);
-	}
+	struct device_node *dp_node = dp->dev->of_node;
+	struct video_info *video_info = &dp->video_info
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &dp_video_config->link_rate)) {
+				 &video_info->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
-		return ERR_PTR(-EINVAL);
+		return -EINVAL;
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &dp_video_config->lane_count)) {
+				 &video_info->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
-		return ERR_PTR(-EINVAL);
+		return -EINVAL;
 	}
 
-	return dp_video_config;
+	return 0;
 }
 
 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
@@ -1158,9 +1200,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	 */
 	dp->plat_data = plat_data;
 
-	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
-	if (IS_ERR(dp->video_info))
-		return PTR_ERR(dp->video_info);
+	ret = analogix_dp_dt_parse_pdata(dp);
+	if (ret)
+		return ret;
 
 	dp->phy = devm_phy_get(dp->dev, "dp");
 	if (IS_ERR(dp->phy)) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 9a90a18..730486d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -120,9 +120,9 @@ enum dp_irq_type {
 struct video_info {
 	char *name;
 
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
+	u32 h_sync_polarity;
+	u32 v_sync_polarity;
+	u32 interlaced;
 
 	enum color_space color_space;
 	enum dynamic_range dynamic_range;
@@ -154,7 +154,7 @@ struct analogix_dp_device {
 	unsigned int		irq;
 	void __iomem		*reg_base;
 
-	struct video_info	*video_info;
+	struct video_info	video_info;
 	struct link_train	link_train;
 	struct work_struct	hotplug_work;
 	struct phy		*phy;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index a388c0a..861097a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
 	u32 reg;
 
 	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info.color_depth << IN_BPC_SHIFT) |
+		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
 	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
+	if (dp->video_info.ycbcr_coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
@@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
+	reg |= (dp->video_info.interlaced << 2);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
+	reg |= (dp->video_info.v_sync_polarity << 1);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
+	reg |= (dp->video_info.h_sync_polarity << 0);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-09-22  7:37     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:37 UTC (permalink / raw)
  To: linux-arm-kernel

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.

But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).

Changes in v4:
- Provide backword compatibility with samsung. (Krzysztof)

Changes in v3:
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 144 +++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   8 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
 3 files changed, 104 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 1e3c8d3..6be139b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					 dp->video_info->link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
+					 dp->video_info.link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
+					struct drm_display_mode *orig_mode,
+					struct drm_display_mode *mode)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_display_info *display_info = &dp->connector->display_info;
+	struct video_info *video = &dp->video_info;
+	struct device_node *dp_node = dp->dev->of_node;
+	int vic;
+
+	/* Input video interlaces & hsync pol & vsync pol */
+	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+	/* Input video dynamic_range & colorimetry */
+	vic = drm_match_cea_mode(mode);
+	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
+	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR601;
+	} else if (vic) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	} else {
+		video->dynamic_range = VESA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	}
+
+	/* Input vide bpc and color_formats */
+	switch (display_info->bpc) {
+	case 12:
+		video->color_depth = COLOR_12;
+		break;
+	case 10:
+		video->color_depth = COLOR_10;
+		break;
+	case 8:
+		video->color_depth = COLOR_8;
+		break;
+	case 6:
+		video->color_depth = COLOR_6;
+		break;
+	default:
+		video->color_depth = COLOR_8;
+		break;
+	}
+	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
+		video->color_space = COLOR_YCBCR444;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
+		video->color_space = COLOR_YCBCR422;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
+		video->color_space = COLOR_RGB;
+	else
+		video->color_space = COLOR_RGB;
+
+	/*
+	 * NOTE: those property parsing code is used for providing backward
+	 * compatibility for samsung platform.
+	 * Due to we used the "of_property_read_u32" interfaces, when this
+	 * property isn't present, the "video_info" can keep the original
+	 * values and wouldn't be modified.
+	 */
+	of_property_read_u32(dp_node, "samsung,color-space",
+			     &video->color_space);
+	of_property_read_u32(dp_node, "samsung,dynamic-range",
+			     &video->dynamic_range);
+	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+			     &video->ycbcr_coeff);
+	of_property_read_u32(dp_node, "samsung,color-depth",
+			     &video->color_depth);
+	of_property_read_u32(dp_node, "hsync-active-high",
+			     &video->h_sync_polarity);
+	of_property_read_u32(dp_node, "vsync-active-high",
+			     &video->v_sync_polarity);
+	of_property_read_u32(dp_node, "interlaced",
+			     &video->interlaced);
+}
+
 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
@@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
 	.disable = analogix_dp_bridge_disable,
 	.pre_enable = analogix_dp_bridge_nop,
 	.post_disable = analogix_dp_bridge_nop,
+	.mode_set = analogix_dp_bridge_mode_set,
 	.attach = analogix_dp_bridge_attach,
 };
 
@@ -1070,62 +1150,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 	return 0;
 }
 
-static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
-	struct device_node *dp_node = dev->of_node;
-	struct video_info *dp_video_config;
-
-	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
-				       GFP_KERNEL);
-	if (!dp_video_config)
-		return ERR_PTR(-ENOMEM);
-
-	dp_video_config->h_sync_polarity =
-		of_property_read_bool(dp_node, "hsync-active-high");
-
-	dp_video_config->v_sync_polarity =
-		of_property_read_bool(dp_node, "vsync-active-high");
-
-	dp_video_config->interlaced =
-		of_property_read_bool(dp_node, "interlaced");
-
-	if (of_property_read_u32(dp_node, "samsung,color-space",
-				 &dp_video_config->color_space)) {
-		dev_err(dev, "failed to get color-space\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				 &dp_video_config->dynamic_range)) {
-		dev_err(dev, "failed to get dynamic-range\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				 &dp_video_config->ycbcr_coeff)) {
-		dev_err(dev, "failed to get ycbcr-coeff\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				 &dp_video_config->color_depth)) {
-		dev_err(dev, "failed to get color-depth\n");
-		return ERR_PTR(-EINVAL);
-	}
+	struct device_node *dp_node = dp->dev->of_node;
+	struct video_info *video_info = &dp->video_info
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &dp_video_config->link_rate)) {
+				 &video_info->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
-		return ERR_PTR(-EINVAL);
+		return -EINVAL;
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &dp_video_config->lane_count)) {
+				 &video_info->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
-		return ERR_PTR(-EINVAL);
+		return -EINVAL;
 	}
 
-	return dp_video_config;
+	return 0;
 }
 
 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
@@ -1158,9 +1200,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	 */
 	dp->plat_data = plat_data;
 
-	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
-	if (IS_ERR(dp->video_info))
-		return PTR_ERR(dp->video_info);
+	ret = analogix_dp_dt_parse_pdata(dp);
+	if (ret)
+		return ret;
 
 	dp->phy = devm_phy_get(dp->dev, "dp");
 	if (IS_ERR(dp->phy)) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 9a90a18..730486d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -120,9 +120,9 @@ enum dp_irq_type {
 struct video_info {
 	char *name;
 
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
+	u32 h_sync_polarity;
+	u32 v_sync_polarity;
+	u32 interlaced;
 
 	enum color_space color_space;
 	enum dynamic_range dynamic_range;
@@ -154,7 +154,7 @@ struct analogix_dp_device {
 	unsigned int		irq;
 	void __iomem		*reg_base;
 
-	struct video_info	*video_info;
+	struct video_info	video_info;
 	struct link_train	link_train;
 	struct work_struct	hotplug_work;
 	struct phy		*phy;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index a388c0a..861097a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
 	u32 reg;
 
 	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info.color_depth << IN_BPC_SHIFT) |
+		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
 	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
+	if (dp->video_info.ycbcr_coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
@@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
+	reg |= (dp->video_info.interlaced << 2);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
+	reg |= (dp->video_info.v_sync_polarity << 1);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
+	reg |= (dp->video_info.h_sync_polarity << 0);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 06/17] Documentation: drm/bridge: add document for analogix_dp
  2015-09-22  7:20   ` Yakir Yang
@ 2015-09-22  7:40     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:40 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt

Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Split all DTS changes, and provide backward compatibility. Mark old
  properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"

Changes in v3:
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
  devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.

Changes in v2: None

 .../devicetree/bindings/drm/bridge/analogix_dp.txt | 50 +++++++++++++++++
 .../devicetree/bindings/video/exynos_dp.txt        | 63 ++++++++--------------
 2 files changed, 71 insertions(+), 42 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt

diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
new file mode 100644
index 0000000..f54dc3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -0,0 +1,50 @@
+Analogix Display Port bridge bindings
+
+Required properties for dp-controller:
+	-compatible:
+		platform specific such as:
+		 * "samsung,exynos5-dp"
+		 * "rockchip,rk3288-dp"
+	-reg:
+		physical base address of the controller and length
+		of memory mapped region.
+	-interrupts:
+		interrupt combiner values.
+	-clocks:
+		from common clock binding: handle to dp clock.
+	-clock-names:
+		from common clock binding: Shall be "dp".
+	-interrupt-parent:
+		phandle to Interrupt combiner node.
+	-phys:
+		from general PHY binding: the phandle for the PHY device.
+	-phy-names:
+		from general PHY binding: Should be "dp".
+
+Optional properties for dp-controller:
+	-hpd-gpios:
+		Hotplug detect GPIO.
+		Indicates which GPIO should be used for hotplug detection
+	-port@[X]: SoC specific port nodes with endpoint definitions as defined
+		in Documentation/devicetree/bindings/media/video-interfaces.txt,
+		please refer to the SoC specific binding document:
+		* Documentation/devicetree/bindings/video/exynos_dp.txt
+		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+-------------------------------------------------------------------------------
+
+Example:
+
+	dp-controller {
+		compatible = "samsung,exynos5-dp";
+		reg = <0x145b0000 0x10000>;
+		interrupts = <10 3>;
+		interrupt-parent = <&combiner>;
+		clocks = <&clock 342>;
+		clock-names = "dp";
+
+		phys = <&dp_phy>;
+		phy-names = "dp";
+	};
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index 7a3a9cd..ea03b3a 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -31,45 +31,31 @@ Required properties for dp-controller:
 		from general PHY binding: the phandle for the PHY device.
 	-phy-names:
 		from general PHY binding: Should be "dp".
-	-samsung,color-space:
-		input video data format.
-			COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
-	-samsung,dynamic-range:
-		dynamic range for input video data.
-			VESA = 0, CEA = 1
-	-samsung,ycbcr-coeff:
-		YCbCr co-efficients for input video.
-			COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
-	-samsung,color-depth:
-		number of bits per colour component.
-			COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
-	-samsung,link-rate:
-		link rate supported by the panel.
-			LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
-	-samsung,lane-count:
-		number of lanes supported by the panel.
-			LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
+
+Optional properties for dp-controller:
 	- display-timings: timings for the connected panel as described by
 		Documentation/devicetree/bindings/video/display-timing.txt
 
-Optional properties for dp-controller:
-	-interlaced:
-		interlace scan mode.
-			Progressive if defined, Interlaced if not defined
-	-vsync-active-high:
-		VSYNC polarity configuration.
-			High if defined, Low if not defined
-	-hsync-active-high:
-		HSYNC polarity configuration.
-			High if defined, Low if not defined
-	-samsung,hpd-gpio:
-		Hotplug detect GPIO.
-			Indicates which GPIO should be used for hotplug
-			detection
-	-video interfaces: Device node can contain video interface port
-			    nodes according to [1].
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+	-phys (required)
+	-phy-names (required)
+	-hpd-gpios (optional)
+	-video interfaces (optional)
 
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+Deprecated properties for DisplayPort:
+-interlaced:            deprecated prop that can parsed frm drm_display_mode.
+-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-samsung,ycbcr-coeff:   deprecated prop that can parsed frm drm_display_mode.
+-samsung,dynamic-range: deprecated prop that can parsed frm drm_display_mode.
+-samsung,color-space:   deprecated prop that can parsed from drm_display_info.
+-samsung,color-depth:   deprecated prop that can parsed from drm_display_info.
+-samsung,link-rate:     deprecated prop that can reading from monitor by dpcd method.
+-samsung,lane-count:    deprecated prop that can reading from monitor by dpcd method.
+-samsung,hpd-gpio:      deprecated name for hpd-gpios.
+
+-------------------------------------------------------------------------------
 
 Example:
 
@@ -88,13 +74,6 @@ SOC specific portion:
 
 Board Specific portion:
 	dp-controller {
-		samsung,color-space = <0>;
-		samsung,dynamic-range = <0>;
-		samsung,ycbcr-coeff = <0>;
-		samsung,color-depth = <1>;
-		samsung,link-rate = <0x0a>;
-		samsung,lane-count = <4>;
-
 		display-timings {
 			native-mode = <&lcd_timing>;
 			lcd_timing: 1366x768 {
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 06/17] Documentation: drm/bridge: add document for analogix_dp
@ 2015-09-22  7:40     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:40 UTC (permalink / raw)
  To: linux-arm-kernel

Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt

Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Split all DTS changes, and provide backward compatibility. Mark old
  properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"

Changes in v3:
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
  devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.

Changes in v2: None

 .../devicetree/bindings/drm/bridge/analogix_dp.txt | 50 +++++++++++++++++
 .../devicetree/bindings/video/exynos_dp.txt        | 63 ++++++++--------------
 2 files changed, 71 insertions(+), 42 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt

diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
new file mode 100644
index 0000000..f54dc3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -0,0 +1,50 @@
+Analogix Display Port bridge bindings
+
+Required properties for dp-controller:
+	-compatible:
+		platform specific such as:
+		 * "samsung,exynos5-dp"
+		 * "rockchip,rk3288-dp"
+	-reg:
+		physical base address of the controller and length
+		of memory mapped region.
+	-interrupts:
+		interrupt combiner values.
+	-clocks:
+		from common clock binding: handle to dp clock.
+	-clock-names:
+		from common clock binding: Shall be "dp".
+	-interrupt-parent:
+		phandle to Interrupt combiner node.
+	-phys:
+		from general PHY binding: the phandle for the PHY device.
+	-phy-names:
+		from general PHY binding: Should be "dp".
+
+Optional properties for dp-controller:
+	-hpd-gpios:
+		Hotplug detect GPIO.
+		Indicates which GPIO should be used for hotplug detection
+	-port@[X]: SoC specific port nodes with endpoint definitions as defined
+		in Documentation/devicetree/bindings/media/video-interfaces.txt,
+		please refer to the SoC specific binding document:
+		* Documentation/devicetree/bindings/video/exynos_dp.txt
+		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+-------------------------------------------------------------------------------
+
+Example:
+
+	dp-controller {
+		compatible = "samsung,exynos5-dp";
+		reg = <0x145b0000 0x10000>;
+		interrupts = <10 3>;
+		interrupt-parent = <&combiner>;
+		clocks = <&clock 342>;
+		clock-names = "dp";
+
+		phys = <&dp_phy>;
+		phy-names = "dp";
+	};
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index 7a3a9cd..ea03b3a 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -31,45 +31,31 @@ Required properties for dp-controller:
 		from general PHY binding: the phandle for the PHY device.
 	-phy-names:
 		from general PHY binding: Should be "dp".
-	-samsung,color-space:
-		input video data format.
-			COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
-	-samsung,dynamic-range:
-		dynamic range for input video data.
-			VESA = 0, CEA = 1
-	-samsung,ycbcr-coeff:
-		YCbCr co-efficients for input video.
-			COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
-	-samsung,color-depth:
-		number of bits per colour component.
-			COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
-	-samsung,link-rate:
-		link rate supported by the panel.
-			LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
-	-samsung,lane-count:
-		number of lanes supported by the panel.
-			LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
+
+Optional properties for dp-controller:
 	- display-timings: timings for the connected panel as described by
 		Documentation/devicetree/bindings/video/display-timing.txt
 
-Optional properties for dp-controller:
-	-interlaced:
-		interlace scan mode.
-			Progressive if defined, Interlaced if not defined
-	-vsync-active-high:
-		VSYNC polarity configuration.
-			High if defined, Low if not defined
-	-hsync-active-high:
-		HSYNC polarity configuration.
-			High if defined, Low if not defined
-	-samsung,hpd-gpio:
-		Hotplug detect GPIO.
-			Indicates which GPIO should be used for hotplug
-			detection
-	-video interfaces: Device node can contain video interface port
-			    nodes according to [1].
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+	-phys (required)
+	-phy-names (required)
+	-hpd-gpios (optional)
+	-video interfaces (optional)
 
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+Deprecated properties for DisplayPort:
+-interlaced:            deprecated prop that can parsed frm drm_display_mode.
+-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-samsung,ycbcr-coeff:   deprecated prop that can parsed frm drm_display_mode.
+-samsung,dynamic-range: deprecated prop that can parsed frm drm_display_mode.
+-samsung,color-space:   deprecated prop that can parsed from drm_display_info.
+-samsung,color-depth:   deprecated prop that can parsed from drm_display_info.
+-samsung,link-rate:     deprecated prop that can reading from monitor by dpcd method.
+-samsung,lane-count:    deprecated prop that can reading from monitor by dpcd method.
+-samsung,hpd-gpio:      deprecated name for hpd-gpios.
+
+-------------------------------------------------------------------------------
 
 Example:
 
@@ -88,13 +74,6 @@ SOC specific portion:
 
 Board Specific portion:
 	dp-controller {
-		samsung,color-space = <0>;
-		samsung,dynamic-range = <0>;
-		samsung,ycbcr-coeff = <0>;
-		samsung,color-depth = <1>;
-		samsung,link-rate = <0x0a>;
-		samsung,lane-count = <4>;
-
 		display-timings {
 			native-mode = <&lcd_timing>;
 			lcd_timing: 1366x768 {
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
  2015-09-22  7:20   ` Yakir Yang
@ 2015-09-22  7:43     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:43 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.

Beside the backward compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Correct the misspell in commit message. (Krzysztof)

Changes in v4:
- Separate all DTS changes to a separate patch. (Krzysztof)

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/exynos5250-arndale.dts   | 2 --
 arch/arm/boot/dts/exynos5250-smdk5250.dts  | 2 --
 arch/arm/boot/dts/exynos5250-snow.dts      | 4 +---
 arch/arm/boot/dts/exynos5250-spring.dts    | 4 +---
 arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
 arch/arm/boot/dts/exynos5420-smdk5420.dts  | 2 --
 arch/arm/boot/dts/exynos5800-peach-pi.dts  | 4 +---
 7 files changed, 4 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index db3f65f..4636862 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -124,8 +124,6 @@
 &dp {
 	status = "okay";
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index c625e71..cd424d6 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -80,8 +80,6 @@
 
 &dp {
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 0720caa..242b621 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -244,12 +244,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
 
 	ports {
 		port@0 {
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index c1edd6d..91881d7 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -74,12 +74,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <1>;
-	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
 };
 
 &ehci {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 8f4d76c..7433683 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -148,12 +148,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x06>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 0>;
+	hpd-gpio = <&gpx2 6 0>;
 
 	ports {
 		port@0 {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 98871f9..b3df3c1 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -92,8 +92,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7d5b386..b89bff5 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -142,12 +142,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 0>;
+	hpd-gpios = <&gpx2 6 0>;
 	panel = <&panel>;
 };
 
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
@ 2015-09-22  7:43     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:43 UTC (permalink / raw)
  To: linux-arm-kernel

After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.

Beside the backward compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Correct the misspell in commit message. (Krzysztof)

Changes in v4:
- Separate all DTS changes to a separate patch. (Krzysztof)

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/exynos5250-arndale.dts   | 2 --
 arch/arm/boot/dts/exynos5250-smdk5250.dts  | 2 --
 arch/arm/boot/dts/exynos5250-snow.dts      | 4 +---
 arch/arm/boot/dts/exynos5250-spring.dts    | 4 +---
 arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
 arch/arm/boot/dts/exynos5420-smdk5420.dts  | 2 --
 arch/arm/boot/dts/exynos5800-peach-pi.dts  | 4 +---
 7 files changed, 4 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index db3f65f..4636862 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -124,8 +124,6 @@
 &dp {
 	status = "okay";
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index c625e71..cd424d6 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -80,8 +80,6 @@
 
 &dp {
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 0720caa..242b621 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -244,12 +244,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
 
 	ports {
 		port at 0 {
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index c1edd6d..91881d7 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -74,12 +74,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <1>;
-	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
 };
 
 &ehci {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 8f4d76c..7433683 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -148,12 +148,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x06>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 0>;
+	hpd-gpio = <&gpx2 6 0>;
 
 	ports {
 		port at 0 {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 98871f9..b3df3c1 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -92,8 +92,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7d5b386..b89bff5 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -142,12 +142,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 0>;
+	hpd-gpios = <&gpx2 6 0>;
 	panel = <&panel>;
 };
 
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 08/17] drm: rockchip: dp: add rockchip platform dp driver
  2015-09-22  7:20   ` Yakir Yang
@ 2015-09-22  7:45     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:45 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
  numbers in the example DT node, and remove the regulator iomux setting
  in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
  support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)

Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.

Changes in v3:
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
  and leave "sclk_edp" to analogix dp core driver which name to "dp",
  and leave "pclk_edp" to rockchip dp platform driver which name to
  "pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
  node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.

Changes in v2:
- Get panel node with remote-endpoint method, and create devicetree binding
  for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.

 drivers/gpu/drm/rockchip/Kconfig                |   9 +
 drivers/gpu/drm/rockchip/Makefile               |   1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 442 ++++++++++++++++++++++++
 include/drm/bridge/analogix_dp.h                |   1 +
 4 files changed, 453 insertions(+)
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..c2ba945 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
 	  for the Synopsys DesignWare HDMI driver. If you want to
 	  enable HDMI on RK3288 based SoC, you should selet this
 	  option.
+
+config ROCKCHIP_ANALOGIX_DP
+        tristate "Rockchip specific extensions for Analogix DP driver"
+        depends on DRM_ROCKCHIP
+        select DRM_ANALOGIX_DP
+        help
+	  This selects support for Rockchip SoC specific extensions
+	  for the Analogix Core DP driver. If you want to enable DP
+	  on RK3288 based SoC, you should selet this option.
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..8ad01fb 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \
 		rockchip_drm_gem.o
 
 obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 
 obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
new file mode 100644
index 0000000..2c82a9a
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -0,0 +1,442 @@
+/*
+ * Rockchip SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ *         Yakir Yang <ykk@rock-chips.com>
+ *         Jeff Chen <jeff.chen@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)
+
+/* dp grf register offset */
+#define GRF_SOC_CON6                            0x025c
+#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
+#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
+#define GRF_EDP_SEL_VOP_BIG                     0
+
+struct rockchip_dp_device {
+	struct drm_device        *drm_dev;
+	struct device            *dev;
+	struct drm_encoder       encoder;
+	struct drm_connector     connector;
+	struct drm_display_mode  mode;
+
+	struct clk               *pclk;
+	struct regmap            *grf;
+	struct reset_control     *rst;
+
+	struct analogix_dp_plat_data plat_data;
+};
+
+static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+{
+	reset_control_assert(dp->rst);
+	usleep_range(10, 20);
+	reset_control_deassert(dp->rst);
+
+	return 0;
+}
+
+static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+	int ret;
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+
+	clk_disable_unprepare(dp->pclk);
+
+	return 0;
+}
+
+static int rockchip_dp_get_modes(struct drm_connector *connector)
+{
+	struct rockchip_dp_device *dp = to_dp(connector);
+
+	return analogix_dp_get_modes(dp->dev);
+}
+
+static struct drm_encoder *
+rockchip_dp_best_encoder(struct drm_connector *connector)
+{
+	struct rockchip_dp_device *dp = to_dp(connector);
+
+	return &dp->encoder;
+}
+
+static struct drm_connector_helper_funcs rockchip_dp_connector_helper_funcs = {
+	.get_modes = rockchip_dp_get_modes,
+	.best_encoder = rockchip_dp_best_encoder,
+};
+
+static enum drm_connector_status
+rockchip_dp_detect(struct drm_connector *connector, bool force)
+{
+	struct rockchip_dp_device *dp = to_dp(connector);
+
+	return analogix_dp_detect(dp->dev, force);
+}
+
+static void rockchip_dp_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static struct drm_connector_funcs rockchip_dp_connector_funcs = {
+	.dpms = drm_helper_connector_dpms,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.detect = rockchip_dp_detect,
+	.destroy = rockchip_dp_connector_destroy,
+};
+
+static int rockchip_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+				     struct drm_bridge *bridge)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+	struct drm_connector *connector = &dp->connector;
+	struct drm_encoder *encoder = &dp->encoder;
+	int ret;
+
+	connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+	ret = drm_connector_init(dp->drm_dev, connector,
+				 &rockchip_dp_connector_funcs,
+				 DRM_MODE_CONNECTOR_eDP);
+	if (ret) {
+		DRM_ERROR("Failed to initialize connector with drm\n");
+		return ret;
+	}
+
+	drm_connector_helper_add(connector,
+				 &rockchip_dp_connector_helper_funcs);
+	drm_mode_connector_attach_encoder(connector, encoder);
+
+	dp->plat_data.connector = connector;
+
+	return 0;
+}
+
+static bool
+rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
+				   const struct drm_display_mode *mode,
+				   struct drm_display_mode *adjusted_mode)
+{
+	/* do nothing */
+	return true;
+}
+
+static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
+					     struct drm_display_mode *mode,
+					     struct drm_display_mode *adjusted)
+{
+	/* do nothing */
+}
+
+static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
+{
+	struct rockchip_dp_device *dp = to_dp(encoder);
+	u32 val;
+	int ret;
+
+	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					    DRM_MODE_CONNECTOR_eDP,
+					    ROCKCHIP_OUT_MODE_AAAA);
+	if (ret < 0) {
+		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+		return;
+	}
+
+	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
+	if (ret < 0)
+		return;
+
+	if (ret)
+		val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
+	else
+		val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
+
+	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+		return;
+	}
+}
+
+static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
+{
+	/* do nothing */
+}
+
+static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
+	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
+	.mode_set = rockchip_dp_drm_encoder_mode_set,
+	.prepare = rockchip_dp_drm_encoder_prepare,
+	.commit = rockchip_dp_drm_encoder_nop,
+	.disable = rockchip_dp_drm_encoder_nop,
+};
+
+static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
+	.destroy = rockchip_dp_drm_encoder_destroy,
+};
+
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+	struct device *dev = dp->dev;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "failed to get rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	dp->pclk = devm_clk_get(dev, "pclk");
+	if (IS_ERR(dp->pclk)) {
+		dev_err(dev, "failed to get pclk property\n");
+		return PTR_ERR(dp->pclk);
+	}
+
+	dp->rst = devm_reset_control_get(dev, "dp");
+	if (IS_ERR(dp->rst)) {
+		dev_err(dev, "failed to get dp reset control\n");
+		return PTR_ERR(dp->rst);
+	}
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
+{
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct device *dev = dp->dev;
+	int ret;
+
+	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+							     dev->of_node);
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
+			       DRM_MODE_ENCODER_TMDS);
+	if (ret) {
+		DRM_ERROR("failed to initialize encoder with drm\n");
+		return ret;
+	}
+
+	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
+
+	return 0;
+}
+
+static int rockchip_dp_bind(struct device *dev, struct device *master,
+			    void *data)
+{
+	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_device *drm_dev = data;
+	int ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	ret = rockchip_dp_init(dp);
+	if (ret < 0)
+		return ret;
+
+	dp->drm_dev = drm_dev;
+
+	ret = rockchip_dp_drm_create_encoder(dp);
+	if (ret) {
+		DRM_ERROR("failed to create drm encoder\n");
+		return ret;
+	}
+
+	dp->plat_data.encoder = &dp->encoder;
+
+	dp->plat_data.dev_type = RK3288_DP;
+	dp->plat_data.power_on = rockchip_dp_poweron;
+	dp->plat_data.power_off = rockchip_dp_powerdown;
+	dp->plat_data.attach = rockchip_dp_bridge_attach;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
+}
+
+static void rockchip_dp_unbind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops rockchip_dp_component_ops = {
+	.bind = rockchip_dp_bind,
+	.unbind = rockchip_dp_unbind,
+};
+
+static int rockchip_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *port, *endpoint;
+	struct rockchip_dp_device *dp;
+	struct drm_panel *panel;
+
+	port = of_graph_get_port_by_id(dev->of_node, 1);
+	if (!port) {
+		dev_err(dev, "can't find output port\n");
+		return -EINVAL;
+	}
+
+	endpoint = of_get_child_by_name(port, "endpoint");
+	of_node_put(port);
+	if (!endpoint) {
+		dev_err(dev, "no output endpoint found\n");
+		return -EINVAL;
+	}
+
+	panel_node = of_graph_get_remote_port_parent(endpoint);
+	of_node_put(endpoint);
+	if (!panel_node) {
+		dev_err(dev, "no output node found\n");
+		return -EINVAL;
+	}
+
+	panel = of_drm_find_panel(panel_node);
+	if (!panel) {
+		DRM_ERROR("failed to find panel\n");
+		of_node_put(panel_node);
+		return -EPROBE_DEFER;
+	}
+
+	of_node_put(panel_node);
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->plat_data.panel = panel;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver could take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	return component_add(dev, &rockchip_dp_component_ops);
+}
+
+static int rockchip_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &rockchip_dp_component_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int rockchip_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops rockchip_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
+};
+
+static const struct of_device_id rockchip_dp_dt_ids[] = {
+	{.compatible = "rockchip,rk3288-dp",},
+	{}
+};
+MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
+
+static struct platform_driver rockchip_dp_driver = {
+	.probe = rockchip_dp_probe,
+	.remove = rockchip_dp_remove,
+	.driver = {
+		   .name = "rockchip-dp",
+		   .owner = THIS_MODULE,
+		   .pm = &rockchip_dp_pm_ops,
+		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
+	},
+};
+
+module_platform_driver(rockchip_dp_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index 134638af..7d9857a 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -15,6 +15,7 @@
 
 enum analogix_dp_devtype {
 	EXYNOS_DP,
+	RK3288_DP,
 };
 
 struct analogix_dp_plat_data {
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 08/17] drm: rockchip: dp: add rockchip platform dp driver
@ 2015-09-22  7:45     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:45 UTC (permalink / raw)
  To: linux-arm-kernel

Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
  numbers in the example DT node, and remove the regulator iomux setting
  in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
  support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)

Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.

Changes in v3:
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
  and leave "sclk_edp" to analogix dp core driver which name to "dp",
  and leave "pclk_edp" to rockchip dp platform driver which name to
  "pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
  node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.

Changes in v2:
- Get panel node with remote-endpoint method, and create devicetree binding
  for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.

 drivers/gpu/drm/rockchip/Kconfig                |   9 +
 drivers/gpu/drm/rockchip/Makefile               |   1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 442 ++++++++++++++++++++++++
 include/drm/bridge/analogix_dp.h                |   1 +
 4 files changed, 453 insertions(+)
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..c2ba945 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
 	  for the Synopsys DesignWare HDMI driver. If you want to
 	  enable HDMI on RK3288 based SoC, you should selet this
 	  option.
+
+config ROCKCHIP_ANALOGIX_DP
+        tristate "Rockchip specific extensions for Analogix DP driver"
+        depends on DRM_ROCKCHIP
+        select DRM_ANALOGIX_DP
+        help
+	  This selects support for Rockchip SoC specific extensions
+	  for the Analogix Core DP driver. If you want to enable DP
+	  on RK3288 based SoC, you should selet this option.
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..8ad01fb 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \
 		rockchip_drm_gem.o
 
 obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 
 obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
new file mode 100644
index 0000000..2c82a9a
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -0,0 +1,442 @@
+/*
+ * Rockchip SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ *         Yakir Yang <ykk@rock-chips.com>
+ *         Jeff Chen <jeff.chen@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)
+
+/* dp grf register offset */
+#define GRF_SOC_CON6                            0x025c
+#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
+#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
+#define GRF_EDP_SEL_VOP_BIG                     0
+
+struct rockchip_dp_device {
+	struct drm_device        *drm_dev;
+	struct device            *dev;
+	struct drm_encoder       encoder;
+	struct drm_connector     connector;
+	struct drm_display_mode  mode;
+
+	struct clk               *pclk;
+	struct regmap            *grf;
+	struct reset_control     *rst;
+
+	struct analogix_dp_plat_data plat_data;
+};
+
+static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+{
+	reset_control_assert(dp->rst);
+	usleep_range(10, 20);
+	reset_control_deassert(dp->rst);
+
+	return 0;
+}
+
+static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+	int ret;
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+
+	clk_disable_unprepare(dp->pclk);
+
+	return 0;
+}
+
+static int rockchip_dp_get_modes(struct drm_connector *connector)
+{
+	struct rockchip_dp_device *dp = to_dp(connector);
+
+	return analogix_dp_get_modes(dp->dev);
+}
+
+static struct drm_encoder *
+rockchip_dp_best_encoder(struct drm_connector *connector)
+{
+	struct rockchip_dp_device *dp = to_dp(connector);
+
+	return &dp->encoder;
+}
+
+static struct drm_connector_helper_funcs rockchip_dp_connector_helper_funcs = {
+	.get_modes = rockchip_dp_get_modes,
+	.best_encoder = rockchip_dp_best_encoder,
+};
+
+static enum drm_connector_status
+rockchip_dp_detect(struct drm_connector *connector, bool force)
+{
+	struct rockchip_dp_device *dp = to_dp(connector);
+
+	return analogix_dp_detect(dp->dev, force);
+}
+
+static void rockchip_dp_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static struct drm_connector_funcs rockchip_dp_connector_funcs = {
+	.dpms = drm_helper_connector_dpms,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.detect = rockchip_dp_detect,
+	.destroy = rockchip_dp_connector_destroy,
+};
+
+static int rockchip_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+				     struct drm_bridge *bridge)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+	struct drm_connector *connector = &dp->connector;
+	struct drm_encoder *encoder = &dp->encoder;
+	int ret;
+
+	connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+	ret = drm_connector_init(dp->drm_dev, connector,
+				 &rockchip_dp_connector_funcs,
+				 DRM_MODE_CONNECTOR_eDP);
+	if (ret) {
+		DRM_ERROR("Failed to initialize connector with drm\n");
+		return ret;
+	}
+
+	drm_connector_helper_add(connector,
+				 &rockchip_dp_connector_helper_funcs);
+	drm_mode_connector_attach_encoder(connector, encoder);
+
+	dp->plat_data.connector = connector;
+
+	return 0;
+}
+
+static bool
+rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
+				   const struct drm_display_mode *mode,
+				   struct drm_display_mode *adjusted_mode)
+{
+	/* do nothing */
+	return true;
+}
+
+static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
+					     struct drm_display_mode *mode,
+					     struct drm_display_mode *adjusted)
+{
+	/* do nothing */
+}
+
+static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
+{
+	struct rockchip_dp_device *dp = to_dp(encoder);
+	u32 val;
+	int ret;
+
+	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					    DRM_MODE_CONNECTOR_eDP,
+					    ROCKCHIP_OUT_MODE_AAAA);
+	if (ret < 0) {
+		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+		return;
+	}
+
+	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
+	if (ret < 0)
+		return;
+
+	if (ret)
+		val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
+	else
+		val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
+
+	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+		return;
+	}
+}
+
+static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
+{
+	/* do nothing */
+}
+
+static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
+	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
+	.mode_set = rockchip_dp_drm_encoder_mode_set,
+	.prepare = rockchip_dp_drm_encoder_prepare,
+	.commit = rockchip_dp_drm_encoder_nop,
+	.disable = rockchip_dp_drm_encoder_nop,
+};
+
+static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
+	.destroy = rockchip_dp_drm_encoder_destroy,
+};
+
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+	struct device *dev = dp->dev;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "failed to get rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	dp->pclk = devm_clk_get(dev, "pclk");
+	if (IS_ERR(dp->pclk)) {
+		dev_err(dev, "failed to get pclk property\n");
+		return PTR_ERR(dp->pclk);
+	}
+
+	dp->rst = devm_reset_control_get(dev, "dp");
+	if (IS_ERR(dp->rst)) {
+		dev_err(dev, "failed to get dp reset control\n");
+		return PTR_ERR(dp->rst);
+	}
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
+{
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct device *dev = dp->dev;
+	int ret;
+
+	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+							     dev->of_node);
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
+			       DRM_MODE_ENCODER_TMDS);
+	if (ret) {
+		DRM_ERROR("failed to initialize encoder with drm\n");
+		return ret;
+	}
+
+	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
+
+	return 0;
+}
+
+static int rockchip_dp_bind(struct device *dev, struct device *master,
+			    void *data)
+{
+	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_device *drm_dev = data;
+	int ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	ret = rockchip_dp_init(dp);
+	if (ret < 0)
+		return ret;
+
+	dp->drm_dev = drm_dev;
+
+	ret = rockchip_dp_drm_create_encoder(dp);
+	if (ret) {
+		DRM_ERROR("failed to create drm encoder\n");
+		return ret;
+	}
+
+	dp->plat_data.encoder = &dp->encoder;
+
+	dp->plat_data.dev_type = RK3288_DP;
+	dp->plat_data.power_on = rockchip_dp_poweron;
+	dp->plat_data.power_off = rockchip_dp_powerdown;
+	dp->plat_data.attach = rockchip_dp_bridge_attach;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
+}
+
+static void rockchip_dp_unbind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops rockchip_dp_component_ops = {
+	.bind = rockchip_dp_bind,
+	.unbind = rockchip_dp_unbind,
+};
+
+static int rockchip_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *port, *endpoint;
+	struct rockchip_dp_device *dp;
+	struct drm_panel *panel;
+
+	port = of_graph_get_port_by_id(dev->of_node, 1);
+	if (!port) {
+		dev_err(dev, "can't find output port\n");
+		return -EINVAL;
+	}
+
+	endpoint = of_get_child_by_name(port, "endpoint");
+	of_node_put(port);
+	if (!endpoint) {
+		dev_err(dev, "no output endpoint found\n");
+		return -EINVAL;
+	}
+
+	panel_node = of_graph_get_remote_port_parent(endpoint);
+	of_node_put(endpoint);
+	if (!panel_node) {
+		dev_err(dev, "no output node found\n");
+		return -EINVAL;
+	}
+
+	panel = of_drm_find_panel(panel_node);
+	if (!panel) {
+		DRM_ERROR("failed to find panel\n");
+		of_node_put(panel_node);
+		return -EPROBE_DEFER;
+	}
+
+	of_node_put(panel_node);
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->plat_data.panel = panel;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver could take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	return component_add(dev, &rockchip_dp_component_ops);
+}
+
+static int rockchip_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &rockchip_dp_component_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int rockchip_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops rockchip_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
+};
+
+static const struct of_device_id rockchip_dp_dt_ids[] = {
+	{.compatible = "rockchip,rk3288-dp",},
+	{}
+};
+MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
+
+static struct platform_driver rockchip_dp_driver = {
+	.probe = rockchip_dp_probe,
+	.remove = rockchip_dp_remove,
+	.driver = {
+		   .name = "rockchip-dp",
+		   .owner = THIS_MODULE,
+		   .pm = &rockchip_dp_pm_ops,
+		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
+	},
+};
+
+module_platform_driver(rockchip_dp_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index 134638af..7d9857a 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -15,6 +15,7 @@
 
 enum analogix_dp_devtype {
 	EXYNOS_DP,
+	RK3288_DP,
 };
 
 struct analogix_dp_plat_data {
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 09/17] Documentation: drm/bridge: add document for analogix_dp
  2015-09-22  7:20   ` Yakir Yang
@ 2015-09-22  7:48     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:48 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../bindings/video/analogix_dp-rockchip.txt        | 90 ++++++++++++++++++++++
 1 file changed, 90 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt

diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..ec93917
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -0,0 +1,90 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+	  of memory mapped region.
+
+- clock-names: from common clock binding:
+	       Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+	  See ../reset/reset.txt for details.
+
+- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
+- pinctrl-0: pin-control mode. should be <&edp_hpd>
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+	dp-controller: dp@ff970000 {
+		compatible = "rockchip,rk3288-dp";
+		reg = <0xff970000 0x4000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+		clock-names = "dp", "pclk";
+		phys = <&dp_phy>;
+		phy-names = "dp";
+
+		rockchip,grf = <&grf>;
+		resets = <&cru 111>;
+		reset-names = "dp";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_hpd>;
+
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			edp_in: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_edp>;
+				};
+				edp_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_edp>;
+				};
+			};
+
+			edp_out: port@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_out_panel: endpoint {
+					reg = <0>;
+					remote-endpoint = <&panel_in_edp>
+				};
+			};
+		};
+	};
+
+	pinctrl {
+		edp {
+			edp_hpd: edp-hpd {
+				rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+	};
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 09/17] Documentation: drm/bridge: add document for analogix_dp
@ 2015-09-22  7:48     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:48 UTC (permalink / raw)
  To: linux-arm-kernel

Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../bindings/video/analogix_dp-rockchip.txt        | 90 ++++++++++++++++++++++
 1 file changed, 90 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt

diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..ec93917
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -0,0 +1,90 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+	  of memory mapped region.
+
+- clock-names: from common clock binding:
+	       Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+	  See ../reset/reset.txt for details.
+
+- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
+- pinctrl-0: pin-control mode. should be <&edp_hpd>
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+	dp-controller: dp at ff970000 {
+		compatible = "rockchip,rk3288-dp";
+		reg = <0xff970000 0x4000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+		clock-names = "dp", "pclk";
+		phys = <&dp_phy>;
+		phy-names = "dp";
+
+		rockchip,grf = <&grf>;
+		resets = <&cru 111>;
+		reset-names = "dp";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_hpd>;
+
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			edp_in: port at 0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_in_vopb: endpoint at 0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_edp>;
+				};
+				edp_in_vopl: endpoint at 1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_edp>;
+				};
+			};
+
+			edp_out: port at 1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_out_panel: endpoint {
+					reg = <0>;
+					remote-endpoint = <&panel_in_edp>
+				};
+			};
+		};
+	};
+
+	pinctrl {
+		edp {
+			edp_hpd: edp-hpd {
+				rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+	};
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 10/17] phy: Add driver for rockchip Display Port PHY
  2015-09-22  7:20   ` Yakir Yang
@ 2015-09-22  7:48     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:48 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
  the exist "grf" syscon already. And rename the example DT node from
  "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
  struct" to "static const struct". And correct the input paramters of
  devm_phy_create() interfaces. (Heiko)

Changes in v4:
- Add commit message, and remove the redundant rockchip_dp_phy_init()
  function, move those code to probe() method. And remove driver .owner
  number. (Kishon)

Changes in v3:
- Suggest, add rockchip dp phy driver, collect the phy clocks and
  power control. (Heiko)

Changes in v2: None

 drivers/phy/Kconfig           |   7 ++
 drivers/phy/Makefile          |   1 +
 drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 159 insertions(+)
 create mode 100644 drivers/phy/phy-rockchip-dp.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573..8f2bc4f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
 	help
 	  Enable this to support the Rockchip USB 2.0 PHY.
 
+config PHY_ROCKCHIP_DP
+	tristate "Rockchip Display Port PHY Driver"
+	depends on ARCH_ROCKCHIP && OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the Rockchip Display Port PHY.
+
 config PHY_ST_SPEAR1310_MIPHY
 	tristate "ST SPEAR1310-MIPHY driver"
 	select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a5b18c1..e281f35 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
 obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 0000000..3a2ac120
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,151 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#define GRF_SOC_CON12                   0x0274
+#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
+#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
+#define GRF_EDP_PHY_SIDDQ_ON            0
+#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
+
+struct rockchip_dp_phy {
+	struct device  *dev;
+	struct regmap  *grf;
+	struct clk     *phy_24m;
+};
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+	int ret;
+
+	if (enable) {
+		ret = clk_prepare_enable(dp->phy_24m);
+		if (ret < 0) {
+			dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
+			return ret;
+		}
+
+		ret = regmap_write(dp->grf, GRF_SOC_CON12,
+				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
+				   GRF_EDP_PHY_SIDDQ_ON);
+	} else {
+		clk_disable_unprepare(dp->phy_24m);
+		ret = regmap_write(dp->grf, GRF_SOC_CON12,
+				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
+				   GRF_EDP_PHY_SIDDQ_OFF);
+	}
+
+	return ret;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, false);
+}
+
+static const struct phy_ops rockchip_dp_phy_ops = {
+	.power_on	= rockchip_dp_phy_power_on,
+	.power_off	= rockchip_dp_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct phy_provider *phy_provider;
+	struct rockchip_dp_phy *dp;
+	struct resource *res;
+	struct phy *phy;
+	int ret;
+
+	if (!np)
+		return -ENODEV;
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (IS_ERR(dp))
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->phy_24m = devm_clk_get(dev, "24m");
+	if (IS_ERR(dp->phy_24m)) {
+		dev_err(dev, "cannot get clock 24m\n");
+		return PTR_ERR(dp->phy_24m);
+	}
+
+	ret = clk_set_rate(dp->phy_24m, 24000000);
+	if (ret < 0) {
+		dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+		return ret;
+	}
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
+			   (GRF_EDP_REF_CLK_SEL_INTER << 16));
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+		return ret;
+	}
+
+	phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
+	if (IS_ERR(phy)) {
+		dev_err(dev, "failed to create phy\n");
+		return PTR_ERR(phy);
+	}
+	phy_set_drvdata(phy, dp);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+	{ .compatible = "rockchip,rk3288-dp-phy" },
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+	.probe		= rockchip_dp_phy_probe,
+	.driver		= {
+		.name	= "rockchip-dp-phy",
+		.of_match_table = rockchip_dp_phy_dt_ids,
+	},
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 10/17] phy: Add driver for rockchip Display Port PHY
@ 2015-09-22  7:48     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:48 UTC (permalink / raw)
  To: linux-arm-kernel

This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
  the exist "grf" syscon already. And rename the example DT node from
  "edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
  struct" to "static const struct". And correct the input paramters of
  devm_phy_create() interfaces. (Heiko)

Changes in v4:
- Add commit message, and remove the redundant rockchip_dp_phy_init()
  function, move those code to probe() method. And remove driver .owner
  number. (Kishon)

Changes in v3:
- Suggest, add rockchip dp phy driver, collect the phy clocks and
  power control. (Heiko)

Changes in v2: None

 drivers/phy/Kconfig           |   7 ++
 drivers/phy/Makefile          |   1 +
 drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 159 insertions(+)
 create mode 100644 drivers/phy/phy-rockchip-dp.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573..8f2bc4f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
 	help
 	  Enable this to support the Rockchip USB 2.0 PHY.
 
+config PHY_ROCKCHIP_DP
+	tristate "Rockchip Display Port PHY Driver"
+	depends on ARCH_ROCKCHIP && OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the Rockchip Display Port PHY.
+
 config PHY_ST_SPEAR1310_MIPHY
 	tristate "ST SPEAR1310-MIPHY driver"
 	select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a5b18c1..e281f35 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
 obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 0000000..3a2ac120
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,151 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#define GRF_SOC_CON12                   0x0274
+#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
+#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
+#define GRF_EDP_PHY_SIDDQ_ON            0
+#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
+
+struct rockchip_dp_phy {
+	struct device  *dev;
+	struct regmap  *grf;
+	struct clk     *phy_24m;
+};
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+	int ret;
+
+	if (enable) {
+		ret = clk_prepare_enable(dp->phy_24m);
+		if (ret < 0) {
+			dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
+			return ret;
+		}
+
+		ret = regmap_write(dp->grf, GRF_SOC_CON12,
+				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
+				   GRF_EDP_PHY_SIDDQ_ON);
+	} else {
+		clk_disable_unprepare(dp->phy_24m);
+		ret = regmap_write(dp->grf, GRF_SOC_CON12,
+				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
+				   GRF_EDP_PHY_SIDDQ_OFF);
+	}
+
+	return ret;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, false);
+}
+
+static const struct phy_ops rockchip_dp_phy_ops = {
+	.power_on	= rockchip_dp_phy_power_on,
+	.power_off	= rockchip_dp_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct phy_provider *phy_provider;
+	struct rockchip_dp_phy *dp;
+	struct resource *res;
+	struct phy *phy;
+	int ret;
+
+	if (!np)
+		return -ENODEV;
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (IS_ERR(dp))
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->phy_24m = devm_clk_get(dev, "24m");
+	if (IS_ERR(dp->phy_24m)) {
+		dev_err(dev, "cannot get clock 24m\n");
+		return PTR_ERR(dp->phy_24m);
+	}
+
+	ret = clk_set_rate(dp->phy_24m, 24000000);
+	if (ret < 0) {
+		dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+		return ret;
+	}
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
+			   (GRF_EDP_REF_CLK_SEL_INTER << 16));
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+		return ret;
+	}
+
+	phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
+	if (IS_ERR(phy)) {
+		dev_err(dev, "failed to create phy\n");
+		return PTR_ERR(phy);
+	}
+	phy_set_drvdata(phy, dp);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+	{ .compatible = "rockchip,rk3288-dp-phy" },
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+	.probe		= rockchip_dp_phy_probe,
+	.driver		= {
+		.name	= "rockchip-dp-phy",
+		.of_match_table = rockchip_dp_phy_dt_ids,
+	},
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 11/17] Documentation: phy: add document for rockchip dp phy
  2015-09-22  7:20   ` Yakir Yang
@ 2015-09-22  7:51     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:51 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

This phy driver is binded with the Rockchip DisplayPort
driver, here are the brief properties:
	edp_phy: edp-phy@ff770274 {
		compatible = "rockchip,rk3288-dp-phy";
		rockchip,grf = <&grf>;
		clocks = <&cru SCLK_EDP_24M>;
		clock-names = "24m";
		#phy-cells = <0>;
	};

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
  elemets in document. (Rob & Heiko)

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../devicetree/bindings/phy/rockchip-dp-phy.txt    | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
new file mode 100644
index 0000000..505194e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
@@ -0,0 +1,22 @@
+Rockchip Soc Seroes Display Port PHY
+------------------------------------
+
+Required properties:
+- compatible : should be one of the following supported values:
+	 - "rockchip.rk3288-dp-phy"
+- clocks: from common clock binding: handle to dp clock.
+	of memory mapped region.
+- clock-names: from common clock binding:
+	Required elements: "24m"
+- rockchip,grf: phandle to the syscon managing the "general register files"
+- #phy-cells : from the generic PHY bindings, must be 0;
+
+Example:
+
+edp_phy: edp-phy@ff770274 {
+	compatible = "rockchip,rk3288-dp-phy";
+	rockchip,grf = <&grf>;
+	clocks = <&cru SCLK_EDP_24M>;
+	clock-names = "24m";
+	#phy-cells = <0>;
+};
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 11/17] Documentation: phy: add document for rockchip dp phy
@ 2015-09-22  7:51     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:51 UTC (permalink / raw)
  To: linux-arm-kernel

This phy driver is binded with the Rockchip DisplayPort
driver, here are the brief properties:
	edp_phy: edp-phy at ff770274 {
		compatible = "rockchip,rk3288-dp-phy";
		rockchip,grf = <&grf>;
		clocks = <&cru SCLK_EDP_24M>;
		clock-names = "24m";
		#phy-cells = <0>;
	};

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
  elemets in document. (Rob & Heiko)

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../devicetree/bindings/phy/rockchip-dp-phy.txt    | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
new file mode 100644
index 0000000..505194e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
@@ -0,0 +1,22 @@
+Rockchip Soc Seroes Display Port PHY
+------------------------------------
+
+Required properties:
+- compatible : should be one of the following supported values:
+	 - "rockchip.rk3288-dp-phy"
+- clocks: from common clock binding: handle to dp clock.
+	of memory mapped region.
+- clock-names: from common clock binding:
+	Required elements: "24m"
+- rockchip,grf: phandle to the syscon managing the "general register files"
+- #phy-cells : from the generic PHY bindings, must be 0;
+
+Example:
+
+edp_phy: edp-phy at ff770274 {
+	compatible = "rockchip,rk3288-dp-phy";
+	rockchip,grf = <&grf>;
+	clocks = <&cru SCLK_EDP_24M>;
+	clock-names = "24m";
+	#phy-cells = <0>;
+};
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 12/17] drm: rockchip: vop: add bpc and color mode setting
@ 2015-09-22  7:55     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:55 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel, Mark Yao

From: Mark Yao <yzq@rock-chips.com>

Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.

Signed-off-by: Mark Yao <yzq@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Fix compiled error (Heiko)
- Using the connector display info message to configure eDP driver input
  video mode, but hard code CRTC video output mode to RGBaaa.

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 25 +++++++++++++++----
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 32 ++++++++++++++++++++++---
 4 files changed, 51 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 2c82a9a..3990951 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -180,14 +180,29 @@ static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
 static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct rockchip_dp_device *dp = to_dp(encoder);
+	struct drm_connector *cn = &dp->connector;
+	int ret = -1;
 	u32 val;
-	int ret;
 
-	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
-					    DRM_MODE_CONNECTOR_eDP,
-					    ROCKCHIP_OUT_MODE_AAAA);
+	/*
+	 * FIXME(Yakir): driver should configure the CRTC output video
+	 * mode with the display information which indicated the monitor
+	 * support colorimetry.
+	 *
+	 * But don't know why the CRTC driver seems could only output the
+	 * RGBaaa rightly. For example, if connect the "innolux,n116bge"
+	 * eDP screen, EDID would indicated that screen only accepted the
+	 * 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
+	 * screen would show a blue picture (RGB888 show a green picture).
+	 * But if I configure CTRC to RGBaaa, and eDP driver still keep
+	 * RGB666 input video mode, then screen would works prefect.
+	 */
+	if (cn->display_info.color_formats & DRM_COLOR_FORMAT_RGB444)
+		ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					DRM_MODE_CONNECTOR_eDP,
+					10, DRM_COLOR_FORMAT_RGB444);
 	if (ret < 0) {
-		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+		dev_err(dp->dev, "Could not set crtc mode config (%d)\n", ret);
 		return;
 	}
 
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 80d6fc8..428a3c1 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
 static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
 {
 	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
-				      ROCKCHIP_OUT_MODE_AAAA);
+				      10, DRM_COLOR_FORMAT_RGB444);
 }
 
 static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index dc4e5f0..ef1d7fb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe);
 int rockchip_drm_encoder_get_mux_id(struct device_node *node,
 				    struct drm_encoder *encoder);
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
-				  int out_mode);
+				  int bpc, int color);
 int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
 				   struct device *dev);
 void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e..9ef4a1f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1062,14 +1062,40 @@ static const struct drm_plane_funcs vop_plane_funcs = {
 
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
 				  int connector_type,
-				  int out_mode)
+				  int bpc, int color)
 {
 	struct vop *vop = to_vop(crtc);
 
+	/*
+	 * RK3288 vop only support RGB Color output.
+	 */
+	if (color != DRM_COLOR_FORMAT_RGB444) {
+		DRM_ERROR("Only support output RGB444, not support%d\n",
+			  color);
+		return -EINVAL;
+	}
+
 	vop->connector_type = connector_type;
-	vop->connector_out_mode = out_mode;
 
-	return 0;
+	/*
+	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
+	 * bpc, 5 or 6?
+	 */
+	if (bpc >= 10) {
+		bpc = 10;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
+	} else if (bpc >= 8) {
+		bpc = 8;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+	} else if (bpc >= 6) {
+		bpc = 6;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P666;
+	} else {
+		DRM_ERROR("unsupport bpc %d\n", bpc);
+		return -EINVAL;
+	}
+
+	return bpc;
 }
 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
 
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 12/17] drm: rockchip: vop: add bpc and color mode setting
@ 2015-09-22  7:55     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:55 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe-6d6DIl74uiNBDgjK7y7TUQ, Krzysztof Kozlowski,
	Rob Herring
  Cc: David Airlie, Russell King, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan, Yakir Yang,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Yao

From: Mark Yao <yzq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.

Signed-off-by: Mark Yao <yzq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v5:
- Fix compiled error (Heiko)
- Using the connector display info message to configure eDP driver input
  video mode, but hard code CRTC video output mode to RGBaaa.

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 25 +++++++++++++++----
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 32 ++++++++++++++++++++++---
 4 files changed, 51 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 2c82a9a..3990951 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -180,14 +180,29 @@ static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
 static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct rockchip_dp_device *dp = to_dp(encoder);
+	struct drm_connector *cn = &dp->connector;
+	int ret = -1;
 	u32 val;
-	int ret;
 
-	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
-					    DRM_MODE_CONNECTOR_eDP,
-					    ROCKCHIP_OUT_MODE_AAAA);
+	/*
+	 * FIXME(Yakir): driver should configure the CRTC output video
+	 * mode with the display information which indicated the monitor
+	 * support colorimetry.
+	 *
+	 * But don't know why the CRTC driver seems could only output the
+	 * RGBaaa rightly. For example, if connect the "innolux,n116bge"
+	 * eDP screen, EDID would indicated that screen only accepted the
+	 * 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
+	 * screen would show a blue picture (RGB888 show a green picture).
+	 * But if I configure CTRC to RGBaaa, and eDP driver still keep
+	 * RGB666 input video mode, then screen would works prefect.
+	 */
+	if (cn->display_info.color_formats & DRM_COLOR_FORMAT_RGB444)
+		ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					DRM_MODE_CONNECTOR_eDP,
+					10, DRM_COLOR_FORMAT_RGB444);
 	if (ret < 0) {
-		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+		dev_err(dp->dev, "Could not set crtc mode config (%d)\n", ret);
 		return;
 	}
 
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 80d6fc8..428a3c1 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
 static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
 {
 	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
-				      ROCKCHIP_OUT_MODE_AAAA);
+				      10, DRM_COLOR_FORMAT_RGB444);
 }
 
 static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index dc4e5f0..ef1d7fb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe);
 int rockchip_drm_encoder_get_mux_id(struct device_node *node,
 				    struct drm_encoder *encoder);
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
-				  int out_mode);
+				  int bpc, int color);
 int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
 				   struct device *dev);
 void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e..9ef4a1f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1062,14 +1062,40 @@ static const struct drm_plane_funcs vop_plane_funcs = {
 
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
 				  int connector_type,
-				  int out_mode)
+				  int bpc, int color)
 {
 	struct vop *vop = to_vop(crtc);
 
+	/*
+	 * RK3288 vop only support RGB Color output.
+	 */
+	if (color != DRM_COLOR_FORMAT_RGB444) {
+		DRM_ERROR("Only support output RGB444, not support%d\n",
+			  color);
+		return -EINVAL;
+	}
+
 	vop->connector_type = connector_type;
-	vop->connector_out_mode = out_mode;
 
-	return 0;
+	/*
+	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
+	 * bpc, 5 or 6?
+	 */
+	if (bpc >= 10) {
+		bpc = 10;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
+	} else if (bpc >= 8) {
+		bpc = 8;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+	} else if (bpc >= 6) {
+		bpc = 6;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P666;
+	} else {
+		DRM_ERROR("unsupport bpc %d\n", bpc);
+		return -EINVAL;
+	}
+
+	return bpc;
 }
 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
 
-- 
1.9.1


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^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 12/17] drm: rockchip: vop: add bpc and color mode setting
@ 2015-09-22  7:55     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:55 UTC (permalink / raw)
  To: linux-arm-kernel

From: Mark Yao <yzq@rock-chips.com>

Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.

Signed-off-by: Mark Yao <yzq@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5:
- Fix compiled error (Heiko)
- Using the connector display info message to configure eDP driver input
  video mode, but hard code CRTC video output mode to RGBaaa.

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 25 +++++++++++++++----
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 32 ++++++++++++++++++++++---
 4 files changed, 51 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 2c82a9a..3990951 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -180,14 +180,29 @@ static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
 static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct rockchip_dp_device *dp = to_dp(encoder);
+	struct drm_connector *cn = &dp->connector;
+	int ret = -1;
 	u32 val;
-	int ret;
 
-	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
-					    DRM_MODE_CONNECTOR_eDP,
-					    ROCKCHIP_OUT_MODE_AAAA);
+	/*
+	 * FIXME(Yakir): driver should configure the CRTC output video
+	 * mode with the display information which indicated the monitor
+	 * support colorimetry.
+	 *
+	 * But don't know why the CRTC driver seems could only output the
+	 * RGBaaa rightly. For example, if connect the "innolux,n116bge"
+	 * eDP screen, EDID would indicated that screen only accepted the
+	 * 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
+	 * screen would show a blue picture (RGB888 show a green picture).
+	 * But if I configure CTRC to RGBaaa, and eDP driver still keep
+	 * RGB666 input video mode, then screen would works prefect.
+	 */
+	if (cn->display_info.color_formats & DRM_COLOR_FORMAT_RGB444)
+		ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					DRM_MODE_CONNECTOR_eDP,
+					10, DRM_COLOR_FORMAT_RGB444);
 	if (ret < 0) {
-		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+		dev_err(dp->dev, "Could not set crtc mode config (%d)\n", ret);
 		return;
 	}
 
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 80d6fc8..428a3c1 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
 static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
 {
 	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
-				      ROCKCHIP_OUT_MODE_AAAA);
+				      10, DRM_COLOR_FORMAT_RGB444);
 }
 
 static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index dc4e5f0..ef1d7fb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe);
 int rockchip_drm_encoder_get_mux_id(struct device_node *node,
 				    struct drm_encoder *encoder);
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
-				  int out_mode);
+				  int bpc, int color);
 int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
 				   struct device *dev);
 void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e..9ef4a1f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1062,14 +1062,40 @@ static const struct drm_plane_funcs vop_plane_funcs = {
 
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
 				  int connector_type,
-				  int out_mode)
+				  int bpc, int color)
 {
 	struct vop *vop = to_vop(crtc);
 
+	/*
+	 * RK3288 vop only support RGB Color output.
+	 */
+	if (color != DRM_COLOR_FORMAT_RGB444) {
+		DRM_ERROR("Only support output RGB444, not support%d\n",
+			  color);
+		return -EINVAL;
+	}
+
 	vop->connector_type = connector_type;
-	vop->connector_out_mode = out_mode;
 
-	return 0;
+	/*
+	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
+	 * bpc, 5 or 6?
+	 */
+	if (bpc >= 10) {
+		bpc = 10;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
+	} else if (bpc >= 8) {
+		bpc = 8;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+	} else if (bpc >= 6) {
+		bpc = 6;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P666;
+	} else {
+		DRM_ERROR("unsupport bpc %d\n", bpc);
+		return -EINVAL;
+	}
+
+	return bpc;
 }
 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
 
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting
  2015-09-22  7:20   ` Yakir Yang
@ 2015-09-22  7:57     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:57 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++++++++++++++---------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 ++++
 2 files changed, 60 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 861097a..21a3287 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -15,6 +15,8 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
+#include <drm/bridge/analogix_dp.h>
+
 #include "analogix_dp_core.h"
 #include "analogix_dp_reg.h"
 
@@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
 	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
 
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
+		writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
+		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
+		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
+		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
+	}
+
 	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
 
@@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable)
 {
 	u32 reg;
+	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		phy_pd_addr = ANALOGIX_DP_PD;
 
 	switch (block) {
 	case AUX_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH0_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH1_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH2_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH3_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case ANALOG_TOTAL:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case POWER_ALL:
 		if (enable) {
 			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(0x00, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	default:
@@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
-	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
+		      AUX_HW_RETRY_COUNT_SEL(3) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	else
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
+		      AUX_HW_RETRY_COUNT_SEL(0) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 738db4c..337912b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -22,6 +22,14 @@
 #define ANALOGIX_DP_VIDEO_CTL_8			0x3C
 #define ANALOGIX_DP_VIDEO_CTL_10		0x44
 
+#define ANALOGIX_DP_PLL_REG_1			0xfc
+#define ANALOGIX_DP_PLL_REG_2			0x9e4
+#define ANALOGIX_DP_PLL_REG_3			0x9e8
+#define ANALOGIX_DP_PLL_REG_4			0x9ec
+#define ANALOGIX_DP_PLL_REG_5			0xa00
+
+#define ANALOGIX_DP_PD				0x12c
+
 #define ANALOGIX_DP_LANE_MAP			0x35C
 
 #define ANALOGIX_DP_ANALOG_CTL_1		0x370
@@ -154,6 +162,10 @@
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
+/* ANALOGIX_DP_PLL_REG_1 */
+#define REF_CLK_24M				(0x1 << 1)
+#define REF_CLK_27M				(0x0 << 1)
+
 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting
@ 2015-09-22  7:57     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  7:57 UTC (permalink / raw)
  To: linux-arm-kernel

RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++++++++++++++---------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 ++++
 2 files changed, 60 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 861097a..21a3287 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -15,6 +15,8 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
+#include <drm/bridge/analogix_dp.h>
+
 #include "analogix_dp_core.h"
 #include "analogix_dp_reg.h"
 
@@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
 	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
 
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
+		writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
+		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
+		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
+		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
+	}
+
 	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
 
@@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable)
 {
 	u32 reg;
+	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		phy_pd_addr = ANALOGIX_DP_PD;
 
 	switch (block) {
 	case AUX_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH0_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH1_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH2_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH3_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case ANALOG_TOTAL:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case POWER_ALL:
 		if (enable) {
 			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(0x00, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	default:
@@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
-	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
+		      AUX_HW_RETRY_COUNT_SEL(3) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	else
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
+		      AUX_HW_RETRY_COUNT_SEL(0) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 738db4c..337912b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -22,6 +22,14 @@
 #define ANALOGIX_DP_VIDEO_CTL_8			0x3C
 #define ANALOGIX_DP_VIDEO_CTL_10		0x44
 
+#define ANALOGIX_DP_PLL_REG_1			0xfc
+#define ANALOGIX_DP_PLL_REG_2			0x9e4
+#define ANALOGIX_DP_PLL_REG_3			0x9e8
+#define ANALOGIX_DP_PLL_REG_4			0x9ec
+#define ANALOGIX_DP_PLL_REG_5			0xa00
+
+#define ANALOGIX_DP_PD				0x12c
+
 #define ANALOGIX_DP_LANE_MAP			0x35C
 
 #define ANALOGIX_DP_ANALOG_CTL_1		0x370
@@ -154,6 +162,10 @@
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
+/* ANALOGIX_DP_PLL_REG_1 */
+#define REF_CLK_24M				(0x1 << 1)
+#define REF_CLK_27M				(0x0 << 1)
+
 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
  2015-09-22  7:20   ` Yakir Yang
@ 2015-09-22  8:00     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  8:00 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
  flag. (Thierry)

Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 35 ++++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  4 +--
 2 files changed, 24 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 6be139b..3efae33 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
-					 dp->video_info.link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
+					 dp->video_info.max_link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1153,18 +1153,27 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
 	struct device_node *dp_node = dp->dev->of_node;
-	struct video_info *video_info = &dp->video_info
+	struct video_info *video_info = &dp->video_info;
 
-	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &video_info->link_rate)) {
-		dev_err(dev, "failed to get link-rate\n");
-		return -EINVAL;
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &video_info->lane_count)) {
-		dev_err(dev, "failed to get lane-count\n");
-		return -EINVAL;
+	switch (dp->plat_data && dp->plat_data->dev_type) {
+	case RK3288_DP:
+		/*
+		 * Like Rk3288 DisplayPort TRM indicate that "Main link
+		 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
+		 */
+		video_info->max_link_rate = 0x0A;
+		video_info->max_lane_count = 0x04;
+		break;
+	case EXYNOS_DP:
+		/*
+		 * NOTE: those property parseing code is used for
+		 * providing backward compatibility for samsung platform.
+		 */
+		of_property_read_u32(dp_node, "samsung,link-rate",
+				     &video_info->max_link_rate);
+		of_property_read_u32(dp_node, "samsung,lane-count",
+				     &video_info->max_lane_count);
+		break;
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 730486d..f4cb799 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -129,8 +129,8 @@ struct video_info {
 	enum color_coefficient ycbcr_coeff;
 	enum color_depth color_depth;
 
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
+	enum link_rate_type max_link_rate;
+	enum link_lane_count_type max_lane_count;
 };
 
 struct link_train {
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
@ 2015-09-22  8:00     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  8:00 UTC (permalink / raw)
  To: linux-arm-kernel

There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
  flag. (Thierry)

Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 35 ++++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  4 +--
 2 files changed, 24 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 6be139b..3efae33 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
-					 dp->video_info.link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
+					 dp->video_info.max_link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1153,18 +1153,27 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
 	struct device_node *dp_node = dp->dev->of_node;
-	struct video_info *video_info = &dp->video_info
+	struct video_info *video_info = &dp->video_info;
 
-	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &video_info->link_rate)) {
-		dev_err(dev, "failed to get link-rate\n");
-		return -EINVAL;
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &video_info->lane_count)) {
-		dev_err(dev, "failed to get lane-count\n");
-		return -EINVAL;
+	switch (dp->plat_data && dp->plat_data->dev_type) {
+	case RK3288_DP:
+		/*
+		 * Like Rk3288 DisplayPort TRM indicate that "Main link
+		 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
+		 */
+		video_info->max_link_rate = 0x0A;
+		video_info->max_lane_count = 0x04;
+		break;
+	case EXYNOS_DP:
+		/*
+		 * NOTE: those property parseing code is used for
+		 * providing backward compatibility for samsung platform.
+		 */
+		of_property_read_u32(dp_node, "samsung,link-rate",
+				     &video_info->max_link_rate);
+		of_property_read_u32(dp_node, "samsung,lane-count",
+				     &video_info->max_lane_count);
+		break;
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 730486d..f4cb799 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -129,8 +129,8 @@ struct video_info {
 	enum color_coefficient ycbcr_coeff;
 	enum color_depth color_depth;
 
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
+	enum link_rate_type max_link_rate;
+	enum link_lane_count_type max_lane_count;
 };
 
 struct link_train {
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2015-09-22  7:20   ` Yakir Yang
@ 2015-09-22  8:02     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  8:02 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.

This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.

Changes in v2: None

 .../devicetree/bindings/drm/bridge/analogix_dp.txt |  4 ++-
 .../bindings/video/analogix_dp-rockchip.txt        |  1 +
 .../devicetree/bindings/video/exynos_dp.txt        |  1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
 6 files changed, 47 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
index f54dc3e..c310367 100644
--- a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -22,6 +22,9 @@ Required properties for dp-controller:
 		from general PHY binding: Should be "dp".
 
 Optional properties for dp-controller:
+	-analogix,need-force-hpd:
+		Indicate driver need force hpd when hpd detect failed, this
+		is used for some eDP screen which don't have hpd signal.
 	-hpd-gpios:
 		Hotplug detect GPIO.
 		Indicates which GPIO should be used for hotplug detection
@@ -31,7 +34,6 @@ Optional properties for dp-controller:
 		* Documentation/devicetree/bindings/video/exynos_dp.txt
 		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 
-
 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
 -------------------------------------------------------------------------------
 
diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
index ec93917..be18388 100644
--- a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -31,6 +31,7 @@ For the below properties, please refer to Analogix DP binding document:
 - phys (required)
 - phy-names (required)
 - hpd-gpios (optional)
+- analogix,need-force-hpd (optional)
 -------------------------------------------------------------------------------
 
 Example:
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index ea03b3a..4f06e80 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
 	-phys (required)
 	-phy-names (required)
 	-hpd-gpios (optional)
+	-analogix,need-force-hpd (optional)
 	-video interfaces (optional)
 
 Deprecated properties for DisplayPort:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 3efae33..7e83738 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -59,15 +59,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (analogix_dp_get_plug_in_status(dp) != 0) {
+	while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
+		if (analogix_dp_get_plug_in_status(dp) == 0)
+			return 0;
+
 		timeout_loop++;
-		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
-			dev_err(dp->dev, "failed to get hpd plug status\n");
-			return -ETIMEDOUT;
-		}
 		usleep_range(10, 11);
 	}
 
+	/*
+	 * Some edp screen do not have hpd signal, so we can't just
+	 * return failed when hpd plug in detect failed, DT property
+	 * "need-force-hpd" would indicate whether driver need this.
+	 */
+	if (!dp->need_force_hpd)
+		return -ETIMEDOUT;
+
+	/*
+	 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
+	 * will not work, so we need to give a force hpd action to
+	 * set HPD_STATUS manually.
+	 */
+	dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
+
+	analogix_dp_force_hpd(dp);
+
+	if (analogix_dp_get_plug_in_status(dp) != 0) {
+		dev_err(dp->dev, "failed to get hpd plug in status\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
+
 	return 0;
 }
 
@@ -1243,6 +1266,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
+	dp->need_force_hpd =
+		of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
+
 	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
 	if (!gpio_is_valid(dp->hpd_gpio))
 		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index f4cb799..3a136b8 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -160,6 +160,7 @@ struct analogix_dp_device {
 	struct phy		*phy;
 	int			dpms_mode;
 	int			hpd_gpio;
+	bool                    need_force_hpd;
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable);
 void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
 void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+void analogix_dp_force_hpd(struct analogix_dp_device *dp);
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
 void analogix_dp_reset_aux(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 21a3287..c7e2959 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 }
 
+void analogix_dp_force_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg = (F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
 {
 	u32 reg;
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-09-22  8:02     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  8:02 UTC (permalink / raw)
  To: linux-arm-kernel

Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.

This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.

Changes in v2: None

 .../devicetree/bindings/drm/bridge/analogix_dp.txt |  4 ++-
 .../bindings/video/analogix_dp-rockchip.txt        |  1 +
 .../devicetree/bindings/video/exynos_dp.txt        |  1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
 6 files changed, 47 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
index f54dc3e..c310367 100644
--- a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -22,6 +22,9 @@ Required properties for dp-controller:
 		from general PHY binding: Should be "dp".
 
 Optional properties for dp-controller:
+	-analogix,need-force-hpd:
+		Indicate driver need force hpd when hpd detect failed, this
+		is used for some eDP screen which don't have hpd signal.
 	-hpd-gpios:
 		Hotplug detect GPIO.
 		Indicates which GPIO should be used for hotplug detection
@@ -31,7 +34,6 @@ Optional properties for dp-controller:
 		* Documentation/devicetree/bindings/video/exynos_dp.txt
 		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 
-
 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
 -------------------------------------------------------------------------------
 
diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
index ec93917..be18388 100644
--- a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -31,6 +31,7 @@ For the below properties, please refer to Analogix DP binding document:
 - phys (required)
 - phy-names (required)
 - hpd-gpios (optional)
+- analogix,need-force-hpd (optional)
 -------------------------------------------------------------------------------
 
 Example:
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index ea03b3a..4f06e80 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
 	-phys (required)
 	-phy-names (required)
 	-hpd-gpios (optional)
+	-analogix,need-force-hpd (optional)
 	-video interfaces (optional)
 
 Deprecated properties for DisplayPort:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 3efae33..7e83738 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -59,15 +59,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (analogix_dp_get_plug_in_status(dp) != 0) {
+	while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
+		if (analogix_dp_get_plug_in_status(dp) == 0)
+			return 0;
+
 		timeout_loop++;
-		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
-			dev_err(dp->dev, "failed to get hpd plug status\n");
-			return -ETIMEDOUT;
-		}
 		usleep_range(10, 11);
 	}
 
+	/*
+	 * Some edp screen do not have hpd signal, so we can't just
+	 * return failed when hpd plug in detect failed, DT property
+	 * "need-force-hpd" would indicate whether driver need this.
+	 */
+	if (!dp->need_force_hpd)
+		return -ETIMEDOUT;
+
+	/*
+	 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
+	 * will not work, so we need to give a force hpd action to
+	 * set HPD_STATUS manually.
+	 */
+	dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
+
+	analogix_dp_force_hpd(dp);
+
+	if (analogix_dp_get_plug_in_status(dp) != 0) {
+		dev_err(dp->dev, "failed to get hpd plug in status\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
+
 	return 0;
 }
 
@@ -1243,6 +1266,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
+	dp->need_force_hpd =
+		of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
+
 	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
 	if (!gpio_is_valid(dp->hpd_gpio))
 		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index f4cb799..3a136b8 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -160,6 +160,7 @@ struct analogix_dp_device {
 	struct phy		*phy;
 	int			dpms_mode;
 	int			hpd_gpio;
+	bool                    need_force_hpd;
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable);
 void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
 void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+void analogix_dp_force_hpd(struct analogix_dp_device *dp);
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
 void analogix_dp_reset_aux(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 21a3287..c7e2959 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 }
 
+void analogix_dp_force_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg = (F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
 {
 	u32 reg;
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function
@ 2015-09-22  8:05     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  8:05 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit messages.

Changes in v3:
- move dp hpd detect to connector detect function.

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 7e83738..90c4fda 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_detect_hpd(dp);
-	if (ret) {
-		/* Cable has been disconnected, we're done */
-		return;
-	}
-
 	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
@@ -941,6 +935,11 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 
 enum drm_connector_status analogix_dp_detect(struct device *dev, bool force)
 {
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+
+	if (analogix_dp_detect_hpd(dp))
+		return connector_status_disconnected;
+
 	return connector_status_connected;
 }
 EXPORT_SYMBOL_GPL(analogix_dp_detect);
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function
@ 2015-09-22  8:05     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  8:05 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe-6d6DIl74uiNBDgjK7y7TUQ, Krzysztof Kozlowski,
	Rob Herring
  Cc: David Airlie, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Yakir Yang, Gustavo Padovan,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Russell King,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Sean Paul, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kumar Gala,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan

This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit messages.

Changes in v3:
- move dp hpd detect to connector detect function.

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 7e83738..90c4fda 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_detect_hpd(dp);
-	if (ret) {
-		/* Cable has been disconnected, we're done */
-		return;
-	}
-
 	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
@@ -941,6 +935,11 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 
 enum drm_connector_status analogix_dp_detect(struct device *dev, bool force)
 {
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+
+	if (analogix_dp_detect_hpd(dp))
+		return connector_status_disconnected;
+
 	return connector_status_connected;
 }
 EXPORT_SYMBOL_GPL(analogix_dp_detect);
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function
@ 2015-09-22  8:05     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  8:05 UTC (permalink / raw)
  To: linux-arm-kernel

This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit messages.

Changes in v3:
- move dp hpd detect to connector detect function.

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 7e83738..90c4fda 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_detect_hpd(dp);
-	if (ret) {
-		/* Cable has been disconnected, we're done */
-		return;
-	}
-
 	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
@@ -941,6 +935,11 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 
 enum drm_connector_status analogix_dp_detect(struct device *dev, bool force)
 {
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+
+	if (analogix_dp_detect_hpd(dp))
+		return connector_status_disconnected;
+
 	return connector_status_connected;
 }
 EXPORT_SYMBOL_GPL(analogix_dp_detect);
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method
@ 2015-09-22  8:07     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  8:07 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Add edid modes parse support

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 24 +++++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 46 +++++++++++-----------
 2 files changed, 40 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 90c4fda..5f8fc11 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -107,7 +107,7 @@ static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 
 static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
-	unsigned char edid[EDID_BLOCK_LENGTH * 2];
+	unsigned char *edid = dp->edid;
 	unsigned int extend_block = 0;
 	unsigned char sum;
 	unsigned char test_vector;
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_handle_edid(dp);
-	if (ret) {
-		dev_err(dp->dev, "unable to handle edid\n");
-		return;
-	}
-
 	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
 					 dp->video_info.max_link_rate);
 	if (ret) {
@@ -947,8 +941,24 @@ EXPORT_SYMBOL_GPL(analogix_dp_detect);
 int analogix_dp_get_modes(struct device *dev)
 {
 	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+	struct edid *edid = (struct edid *)dp->edid;
 	int num_modes = 0;
 
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
+			DRM_ERROR("failed to setup the panel\n");
+			return -EINVAL;
+		}
+	}
+
+	if (analogix_dp_handle_edid(dp)) {
+		dev_err(dp->dev, "unable to handle edid\n");
+		return -EINVAL;
+	}
+
+	drm_mode_connector_update_edid_property(dp->connector, edid);
+	num_modes += drm_add_edid_modes(dp->connector, edid);
+
 	if (dp->plat_data->panel)
 		num_modes += drm_panel_get_modes(dp->plat_data->panel);
 
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 3a136b8..089489d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,28 @@
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
 
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
 enum link_rate_type {
 	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
 	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
@@ -161,6 +183,7 @@ struct analogix_dp_device {
 	int			dpms_mode;
 	int			hpd_gpio;
 	bool                    need_force_hpd;
+	unsigned char           edid[EDID_BLOCK_LENGTH * 2];
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -260,27 +283,4 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
 #endif /* _ANALOGIX_DP_CORE_H */
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method
@ 2015-09-22  8:07     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  8:07 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe-6d6DIl74uiNBDgjK7y7TUQ, Krzysztof Kozlowski,
	Rob Herring
  Cc: David Airlie, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Yakir Yang, Gustavo Padovan,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Russell King,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Sean Paul, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kumar Gala,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan

Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Add edid modes parse support

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 24 +++++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 46 +++++++++++-----------
 2 files changed, 40 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 90c4fda..5f8fc11 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -107,7 +107,7 @@ static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 
 static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
-	unsigned char edid[EDID_BLOCK_LENGTH * 2];
+	unsigned char *edid = dp->edid;
 	unsigned int extend_block = 0;
 	unsigned char sum;
 	unsigned char test_vector;
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_handle_edid(dp);
-	if (ret) {
-		dev_err(dp->dev, "unable to handle edid\n");
-		return;
-	}
-
 	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
 					 dp->video_info.max_link_rate);
 	if (ret) {
@@ -947,8 +941,24 @@ EXPORT_SYMBOL_GPL(analogix_dp_detect);
 int analogix_dp_get_modes(struct device *dev)
 {
 	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+	struct edid *edid = (struct edid *)dp->edid;
 	int num_modes = 0;
 
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
+			DRM_ERROR("failed to setup the panel\n");
+			return -EINVAL;
+		}
+	}
+
+	if (analogix_dp_handle_edid(dp)) {
+		dev_err(dp->dev, "unable to handle edid\n");
+		return -EINVAL;
+	}
+
+	drm_mode_connector_update_edid_property(dp->connector, edid);
+	num_modes += drm_add_edid_modes(dp->connector, edid);
+
 	if (dp->plat_data->panel)
 		num_modes += drm_panel_get_modes(dp->plat_data->panel);
 
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 3a136b8..089489d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,28 @@
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
 
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
 enum link_rate_type {
 	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
 	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
@@ -161,6 +183,7 @@ struct analogix_dp_device {
 	int			dpms_mode;
 	int			hpd_gpio;
 	bool                    need_force_hpd;
+	unsigned char           edid[EDID_BLOCK_LENGTH * 2];
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -260,27 +283,4 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
 #endif /* _ANALOGIX_DP_CORE_H */
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method
@ 2015-09-22  8:07     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-22  8:07 UTC (permalink / raw)
  To: linux-arm-kernel

Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Add edid modes parse support

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 24 +++++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 46 +++++++++++-----------
 2 files changed, 40 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 90c4fda..5f8fc11 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -107,7 +107,7 @@ static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 
 static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
-	unsigned char edid[EDID_BLOCK_LENGTH * 2];
+	unsigned char *edid = dp->edid;
 	unsigned int extend_block = 0;
 	unsigned char sum;
 	unsigned char test_vector;
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_handle_edid(dp);
-	if (ret) {
-		dev_err(dp->dev, "unable to handle edid\n");
-		return;
-	}
-
 	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
 					 dp->video_info.max_link_rate);
 	if (ret) {
@@ -947,8 +941,24 @@ EXPORT_SYMBOL_GPL(analogix_dp_detect);
 int analogix_dp_get_modes(struct device *dev)
 {
 	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+	struct edid *edid = (struct edid *)dp->edid;
 	int num_modes = 0;
 
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
+			DRM_ERROR("failed to setup the panel\n");
+			return -EINVAL;
+		}
+	}
+
+	if (analogix_dp_handle_edid(dp)) {
+		dev_err(dp->dev, "unable to handle edid\n");
+		return -EINVAL;
+	}
+
+	drm_mode_connector_update_edid_property(dp->connector, edid);
+	num_modes += drm_add_edid_modes(dp->connector, edid);
+
 	if (dp->plat_data->panel)
 		num_modes += drm_panel_get_modes(dp->plat_data->panel);
 
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 3a136b8..089489d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,28 @@
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
 
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
 enum link_rate_type {
 	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
 	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
@@ -161,6 +183,7 @@ struct analogix_dp_device {
 	int			dpms_mode;
 	int			hpd_gpio;
 	bool                    need_force_hpd;
+	unsigned char           edid[EDID_BLOCK_LENGTH * 2];
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -260,27 +283,4 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
 #endif /* _ANALOGIX_DP_CORE_H */
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
  2015-09-22  7:29     ` Yakir Yang
@ 2015-09-30  5:17       ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  5:17 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

On 22.09.2015 16:29, Yakir Yang wrote:
> Split the dp core driver from exynos directory to bridge directory,
> and rename the core driver to analogix_dp_*, rename the platform
> code to exynos_dp.
> 
> Beside the new analogix_dp driver would export four hooks.
> "analogix_dp_bind()" and "analogix_dp_unbind()"
> "analogix_dp_detect()" and "analogix_dp_get_modes()"
> 
> The bind/unbind symbols is used for analogix platform driver to connect
> with analogix_dp core driver. And the detect/get_modes is used for analogix
> platform driver to init the connector.
> 
> They reason why connector need register in helper driver is rockchip drm
> haven't implement the atomic API, but Exynos drm have implement it, so
> there would need two different connector helper functions, that's why we
> leave the connector register in helper driver.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v5:
> - Correct the check condition of gpio_is_valid when driver try to get
>   the "hpd-gpios" DT propery. (Heiko)
> - Move the platform attach callback in the front of core driver bridge
>   attch function. Cause once platform failed at attach, core driver should
>   still failed, so no need to init connector before platform attached (Krzysztof)
> - Keep code style no changes with the previous exynos_dp_code.c in this
>   patch, and update commit message about the new export symbol (Krzysztof)
> - Gather the device type patch (v4 11/16) into this one. (Krzysztof)
> - leave out the connector registration to analogix platform driver. (Thierry)

Thanks for fixing this, looks much better.

I don't feel comfortable enough to provide a review tag but it looks
good to me.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
@ 2015-09-30  5:17       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  5:17 UTC (permalink / raw)
  To: linux-arm-kernel

On 22.09.2015 16:29, Yakir Yang wrote:
> Split the dp core driver from exynos directory to bridge directory,
> and rename the core driver to analogix_dp_*, rename the platform
> code to exynos_dp.
> 
> Beside the new analogix_dp driver would export four hooks.
> "analogix_dp_bind()" and "analogix_dp_unbind()"
> "analogix_dp_detect()" and "analogix_dp_get_modes()"
> 
> The bind/unbind symbols is used for analogix platform driver to connect
> with analogix_dp core driver. And the detect/get_modes is used for analogix
> platform driver to init the connector.
> 
> They reason why connector need register in helper driver is rockchip drm
> haven't implement the atomic API, but Exynos drm have implement it, so
> there would need two different connector helper functions, that's why we
> leave the connector register in helper driver.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v5:
> - Correct the check condition of gpio_is_valid when driver try to get
>   the "hpd-gpios" DT propery. (Heiko)
> - Move the platform attach callback in the front of core driver bridge
>   attch function. Cause once platform failed at attach, core driver should
>   still failed, so no need to init connector before platform attached (Krzysztof)
> - Keep code style no changes with the previous exynos_dp_code.c in this
>   patch, and update commit message about the new export symbol (Krzysztof)
> - Gather the device type patch (v4 11/16) into this one. (Krzysztof)
> - leave out the connector registration to analogix platform driver. (Thierry)

Thanks for fixing this, looks much better.

I don't feel comfortable enough to provide a review tag but it looks
good to me.

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 03/17] drm: bridge: analogix/dp: fix some obvious code style
  2015-09-22  7:34     ` Yakir Yang
@ 2015-09-30  5:22       ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  5:22 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

On 22.09.2015 16:34, Yakir Yang wrote:
> Fix some obvious alignment problems, like alignment and line
> over 80 characters problems, make this easy to be maintained
> later.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v5:
> - Resequence this patch after analogix_dp driver have been split
>   from exynos_dp code, and rephrase reasonable commit message, and
>   remove some controversial style (Krzysztof)
>     -		analogix_dp_write_byte_to_dpcd(
>     - 				dp, DP_TEST_RESPONSE,
>     +		analogix_dp_write_byte_to_dpcd(dp,
>     +				DP_TEST_RESPONSE,
> 				DP_TEST_EDID_CHECKSUM_WRITE);
> 
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Improved commit message more readable, and avoid using some
>   uncommon style like bellow: (Joe Preches)
>     -  retval = exynos_dp_read_bytes_from_i2c(...
>   				  ...);
>     +  retval =
>     +  exynos_dp_read_bytes_from_i2c(......);
> 
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++++++++++-----------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  72 ++++++------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 124 ++++++++++----------
>  3 files changed, 163 insertions(+), 162 deletions(-)
> 

IMHO much better than in previous attempt. The code looks good:

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

BTW my opinion is not enough, you still need an ack from Exynos DP
maintainer (or DRM guys).


Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 03/17] drm: bridge: analogix/dp: fix some obvious code style
@ 2015-09-30  5:22       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  5:22 UTC (permalink / raw)
  To: linux-arm-kernel

On 22.09.2015 16:34, Yakir Yang wrote:
> Fix some obvious alignment problems, like alignment and line
> over 80 characters problems, make this easy to be maintained
> later.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v5:
> - Resequence this patch after analogix_dp driver have been split
>   from exynos_dp code, and rephrase reasonable commit message, and
>   remove some controversial style (Krzysztof)
>     -		analogix_dp_write_byte_to_dpcd(
>     - 				dp, DP_TEST_RESPONSE,
>     +		analogix_dp_write_byte_to_dpcd(dp,
>     +				DP_TEST_RESPONSE,
> 				DP_TEST_EDID_CHECKSUM_WRITE);
> 
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Improved commit message more readable, and avoid using some
>   uncommon style like bellow: (Joe Preches)
>     -  retval = exynos_dp_read_bytes_from_i2c(...
>   				  ...);
>     +  retval =
>     +  exynos_dp_read_bytes_from_i2c(......);
> 
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++++++++++-----------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  72 ++++++------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 124 ++++++++++----------
>  3 files changed, 163 insertions(+), 162 deletions(-)
> 

IMHO much better than in previous attempt. The code looks good:

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

BTW my opinion is not enough, you still need an ack from Exynos DP
maintainer (or DRM guys).


Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-09-30  5:32       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  5:32 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

On 22.09.2015 16:37, Yakir Yang wrote:
> Both hsync/vsync polarity and interlace mode can be parsed from
> drm display mode, and dynamic_range and ycbcr_coeff can be judge
> by the video code.
> 
> But presumably Exynos still relies on the DT properties, so take
> good use of mode_fixup() in to achieve the compatibility hacks.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v5:
> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>   to get the backword timing values. 

Okay

> Krzysztof suggest me that driver could use
>   the "of_property_read_bool" to get backword timing values, but that interfacs
>   would modify the original drm_display_mode timing directly (whether those
>   properties exists or not).

Hmm, I don't understand. You have a:
	struct video_info {
		bool h_sync_polarity;
		bool v_sync_polarity;
		bool interlaced;
	};

so what is wrong with:
	dp_video_config->h_sync_polarity =
		of_property_read_bool(dp_node, "hsync-active-high");

Is it exactly the same binding as previously?

Best regards,
Krzysztof

> 
> Changes in v4:
> - Provide backword compatibility with samsung. (Krzysztof)
> 
> Changes in v3:
> - Dynamic parse video timing info from struct drm_display_mode and
>   struct drm_display_info. (Thierry)
> 
> Changes in v2: None
> 
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 144 +++++++++++++--------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   8 +-
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>  3 files changed, 104 insertions(+), 62 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index 1e3c8d3..6be139b 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
>  		return;
>  	}
>  
> -	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
> -					 dp->video_info->link_rate);
> +	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
> +					 dp->video_info.link_rate);
>  	if (ret) {
>  		dev_err(dp->dev, "unable to do link train\n");
>  		return;
> @@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
>  	dp->dpms_mode = DRM_MODE_DPMS_OFF;
>  }
>  
> +static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
> +					struct drm_display_mode *orig_mode,
> +					struct drm_display_mode *mode)
> +{
> +	struct analogix_dp_device *dp = bridge->driver_private;
> +	struct drm_display_info *display_info = &dp->connector->display_info;
> +	struct video_info *video = &dp->video_info;
> +	struct device_node *dp_node = dp->dev->of_node;
> +	int vic;
> +
> +	/* Input video interlaces & hsync pol & vsync pol */
> +	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
> +	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
> +	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
> +
> +	/* Input video dynamic_range & colorimetry */
> +	vic = drm_match_cea_mode(mode);
> +	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
> +	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
> +		video->dynamic_range = CEA;
> +		video->ycbcr_coeff = COLOR_YCBCR601;
> +	} else if (vic) {
> +		video->dynamic_range = CEA;
> +		video->ycbcr_coeff = COLOR_YCBCR709;
> +	} else {
> +		video->dynamic_range = VESA;
> +		video->ycbcr_coeff = COLOR_YCBCR709;
> +	}
> +
> +	/* Input vide bpc and color_formats */
> +	switch (display_info->bpc) {
> +	case 12:
> +		video->color_depth = COLOR_12;
> +		break;
> +	case 10:
> +		video->color_depth = COLOR_10;
> +		break;
> +	case 8:
> +		video->color_depth = COLOR_8;
> +		break;
> +	case 6:
> +		video->color_depth = COLOR_6;
> +		break;
> +	default:
> +		video->color_depth = COLOR_8;
> +		break;
> +	}
> +	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
> +		video->color_space = COLOR_YCBCR444;
> +	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
> +		video->color_space = COLOR_YCBCR422;
> +	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
> +		video->color_space = COLOR_RGB;
> +	else
> +		video->color_space = COLOR_RGB;
> +
> +	/*
> +	 * NOTE: those property parsing code is used for providing backward
> +	 * compatibility for samsung platform.
> +	 * Due to we used the "of_property_read_u32" interfaces, when this
> +	 * property isn't present, the "video_info" can keep the original
> +	 * values and wouldn't be modified.
> +	 */
> +	of_property_read_u32(dp_node, "samsung,color-space",
> +			     &video->color_space);
> +	of_property_read_u32(dp_node, "samsung,dynamic-range",
> +			     &video->dynamic_range);
> +	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> +			     &video->ycbcr_coeff);
> +	of_property_read_u32(dp_node, "samsung,color-depth",
> +			     &video->color_depth);
> +	of_property_read_u32(dp_node, "hsync-active-high",
> +			     &video->h_sync_polarity);
> +	of_property_read_u32(dp_node, "vsync-active-high",
> +			     &video->v_sync_polarity);
> +	of_property_read_u32(dp_node, "interlaced",
> +			     &video->interlaced);
> +}
> +
>  static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
>  {
>  	/* do nothing */
> @@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
>  	.disable = analogix_dp_bridge_disable,
>  	.pre_enable = analogix_dp_bridge_nop,
>  	.post_disable = analogix_dp_bridge_nop,
> +	.mode_set = analogix_dp_bridge_mode_set,
>  	.attach = analogix_dp_bridge_attach,
>  };
>  
> @@ -1070,62 +1150,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>  	return 0;
>  }
>  
> -static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
> +static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
>  {
> -	struct device_node *dp_node = dev->of_node;
> -	struct video_info *dp_video_config;
> -
> -	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
> -				       GFP_KERNEL);
> -	if (!dp_video_config)
> -		return ERR_PTR(-ENOMEM);
> -
> -	dp_video_config->h_sync_polarity =
> -		of_property_read_bool(dp_node, "hsync-active-high");
> -
> -	dp_video_config->v_sync_polarity =
> -		of_property_read_bool(dp_node, "vsync-active-high");
> -
> -	dp_video_config->interlaced =
> -		of_property_read_bool(dp_node, "interlaced");
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-space",
> -				 &dp_video_config->color_space)) {
> -		dev_err(dev, "failed to get color-space\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
> -				 &dp_video_config->dynamic_range)) {
> -		dev_err(dev, "failed to get dynamic-range\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> -				 &dp_video_config->ycbcr_coeff)) {
> -		dev_err(dev, "failed to get ycbcr-coeff\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-depth",
> -				 &dp_video_config->color_depth)) {
> -		dev_err(dev, "failed to get color-depth\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> +	struct device_node *dp_node = dp->dev->of_node;
> +	struct video_info *video_info = &dp->video_info
>  
>  	if (of_property_read_u32(dp_node, "samsung,link-rate",
> -				 &dp_video_config->link_rate)) {
> +				 &video_info->link_rate)) {
>  		dev_err(dev, "failed to get link-rate\n");
> -		return ERR_PTR(-EINVAL);
> +		return -EINVAL;
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,lane-count",
> -				 &dp_video_config->lane_count)) {
> +				 &video_info->lane_count)) {
>  		dev_err(dev, "failed to get lane-count\n");
> -		return ERR_PTR(-EINVAL);
> +		return -EINVAL;
>  	}
>  
> -	return dp_video_config;
> +	return 0;
>  }
>  
>  int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
> @@ -1158,9 +1200,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>  	 */
>  	dp->plat_data = plat_data;
>  
> -	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
> -	if (IS_ERR(dp->video_info))
> -		return PTR_ERR(dp->video_info);
> +	ret = analogix_dp_dt_parse_pdata(dp);
> +	if (ret)
> +		return ret;
>  
>  	dp->phy = devm_phy_get(dp->dev, "dp");
>  	if (IS_ERR(dp->phy)) {
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> index 9a90a18..730486d 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> @@ -120,9 +120,9 @@ enum dp_irq_type {
>  struct video_info {
>  	char *name;
>  
> -	bool h_sync_polarity;
> -	bool v_sync_polarity;
> -	bool interlaced;
> +	u32 h_sync_polarity;
> +	u32 v_sync_polarity;
> +	u32 interlaced;
>  
>  	enum color_space color_space;
>  	enum dynamic_range dynamic_range;
> @@ -154,7 +154,7 @@ struct analogix_dp_device {
>  	unsigned int		irq;
>  	void __iomem		*reg_base;
>  
> -	struct video_info	*video_info;
> +	struct video_info	video_info;
>  	struct link_train	link_train;
>  	struct work_struct	hotplug_work;
>  	struct phy		*phy;
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index a388c0a..861097a 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
>  	u32 reg;
>  
>  	/* Configure the input color depth, color space, dynamic range */
> -	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
> -		(dp->video_info->color_depth << IN_BPC_SHIFT) |
> -		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
> +	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
> +		(dp->video_info.color_depth << IN_BPC_SHIFT) |
> +		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
>  
>  	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>  	reg &= ~IN_YC_COEFFI_MASK;
> -	if (dp->video_info->ycbcr_coeff)
> +	if (dp->video_info.ycbcr_coeff)
>  		reg |= IN_YC_COEFFI_ITU709;
>  	else
>  		reg |= IN_YC_COEFFI_ITU601;
> @@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~INTERACE_SCAN_CFG;
> -	reg |= (dp->video_info->interlaced << 2);
> +	reg |= (dp->video_info.interlaced << 2);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~VSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->v_sync_polarity << 1);
> +	reg |= (dp->video_info.v_sync_polarity << 1);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~HSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->h_sync_polarity << 0);
> +	reg |= (dp->video_info.h_sync_polarity << 0);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
> 


^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-09-30  5:32       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  5:32 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Rob Herring
  Cc: David Airlie, Russell King, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

On 22.09.2015 16:37, Yakir Yang wrote:
> Both hsync/vsync polarity and interlace mode can be parsed from
> drm display mode, and dynamic_range and ycbcr_coeff can be judge
> by the video code.
> 
> But presumably Exynos still relies on the DT properties, so take
> good use of mode_fixup() in to achieve the compatibility hacks.
> 
> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> Changes in v5:
> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>   to get the backword timing values. 

Okay

> Krzysztof suggest me that driver could use
>   the "of_property_read_bool" to get backword timing values, but that interfacs
>   would modify the original drm_display_mode timing directly (whether those
>   properties exists or not).

Hmm, I don't understand. You have a:
	struct video_info {
		bool h_sync_polarity;
		bool v_sync_polarity;
		bool interlaced;
	};

so what is wrong with:
	dp_video_config->h_sync_polarity =
		of_property_read_bool(dp_node, "hsync-active-high");

Is it exactly the same binding as previously?

Best regards,
Krzysztof

> 
> Changes in v4:
> - Provide backword compatibility with samsung. (Krzysztof)
> 
> Changes in v3:
> - Dynamic parse video timing info from struct drm_display_mode and
>   struct drm_display_info. (Thierry)
> 
> Changes in v2: None
> 
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 144 +++++++++++++--------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   8 +-
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>  3 files changed, 104 insertions(+), 62 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index 1e3c8d3..6be139b 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
>  		return;
>  	}
>  
> -	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
> -					 dp->video_info->link_rate);
> +	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
> +					 dp->video_info.link_rate);
>  	if (ret) {
>  		dev_err(dp->dev, "unable to do link train\n");
>  		return;
> @@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
>  	dp->dpms_mode = DRM_MODE_DPMS_OFF;
>  }
>  
> +static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
> +					struct drm_display_mode *orig_mode,
> +					struct drm_display_mode *mode)
> +{
> +	struct analogix_dp_device *dp = bridge->driver_private;
> +	struct drm_display_info *display_info = &dp->connector->display_info;
> +	struct video_info *video = &dp->video_info;
> +	struct device_node *dp_node = dp->dev->of_node;
> +	int vic;
> +
> +	/* Input video interlaces & hsync pol & vsync pol */
> +	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
> +	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
> +	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
> +
> +	/* Input video dynamic_range & colorimetry */
> +	vic = drm_match_cea_mode(mode);
> +	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
> +	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
> +		video->dynamic_range = CEA;
> +		video->ycbcr_coeff = COLOR_YCBCR601;
> +	} else if (vic) {
> +		video->dynamic_range = CEA;
> +		video->ycbcr_coeff = COLOR_YCBCR709;
> +	} else {
> +		video->dynamic_range = VESA;
> +		video->ycbcr_coeff = COLOR_YCBCR709;
> +	}
> +
> +	/* Input vide bpc and color_formats */
> +	switch (display_info->bpc) {
> +	case 12:
> +		video->color_depth = COLOR_12;
> +		break;
> +	case 10:
> +		video->color_depth = COLOR_10;
> +		break;
> +	case 8:
> +		video->color_depth = COLOR_8;
> +		break;
> +	case 6:
> +		video->color_depth = COLOR_6;
> +		break;
> +	default:
> +		video->color_depth = COLOR_8;
> +		break;
> +	}
> +	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
> +		video->color_space = COLOR_YCBCR444;
> +	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
> +		video->color_space = COLOR_YCBCR422;
> +	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
> +		video->color_space = COLOR_RGB;
> +	else
> +		video->color_space = COLOR_RGB;
> +
> +	/*
> +	 * NOTE: those property parsing code is used for providing backward
> +	 * compatibility for samsung platform.
> +	 * Due to we used the "of_property_read_u32" interfaces, when this
> +	 * property isn't present, the "video_info" can keep the original
> +	 * values and wouldn't be modified.
> +	 */
> +	of_property_read_u32(dp_node, "samsung,color-space",
> +			     &video->color_space);
> +	of_property_read_u32(dp_node, "samsung,dynamic-range",
> +			     &video->dynamic_range);
> +	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> +			     &video->ycbcr_coeff);
> +	of_property_read_u32(dp_node, "samsung,color-depth",
> +			     &video->color_depth);
> +	of_property_read_u32(dp_node, "hsync-active-high",
> +			     &video->h_sync_polarity);
> +	of_property_read_u32(dp_node, "vsync-active-high",
> +			     &video->v_sync_polarity);
> +	of_property_read_u32(dp_node, "interlaced",
> +			     &video->interlaced);
> +}
> +
>  static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
>  {
>  	/* do nothing */
> @@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
>  	.disable = analogix_dp_bridge_disable,
>  	.pre_enable = analogix_dp_bridge_nop,
>  	.post_disable = analogix_dp_bridge_nop,
> +	.mode_set = analogix_dp_bridge_mode_set,
>  	.attach = analogix_dp_bridge_attach,
>  };
>  
> @@ -1070,62 +1150,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>  	return 0;
>  }
>  
> -static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
> +static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
>  {
> -	struct device_node *dp_node = dev->of_node;
> -	struct video_info *dp_video_config;
> -
> -	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
> -				       GFP_KERNEL);
> -	if (!dp_video_config)
> -		return ERR_PTR(-ENOMEM);
> -
> -	dp_video_config->h_sync_polarity =
> -		of_property_read_bool(dp_node, "hsync-active-high");
> -
> -	dp_video_config->v_sync_polarity =
> -		of_property_read_bool(dp_node, "vsync-active-high");
> -
> -	dp_video_config->interlaced =
> -		of_property_read_bool(dp_node, "interlaced");
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-space",
> -				 &dp_video_config->color_space)) {
> -		dev_err(dev, "failed to get color-space\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
> -				 &dp_video_config->dynamic_range)) {
> -		dev_err(dev, "failed to get dynamic-range\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> -				 &dp_video_config->ycbcr_coeff)) {
> -		dev_err(dev, "failed to get ycbcr-coeff\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-depth",
> -				 &dp_video_config->color_depth)) {
> -		dev_err(dev, "failed to get color-depth\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> +	struct device_node *dp_node = dp->dev->of_node;
> +	struct video_info *video_info = &dp->video_info
>  
>  	if (of_property_read_u32(dp_node, "samsung,link-rate",
> -				 &dp_video_config->link_rate)) {
> +				 &video_info->link_rate)) {
>  		dev_err(dev, "failed to get link-rate\n");
> -		return ERR_PTR(-EINVAL);
> +		return -EINVAL;
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,lane-count",
> -				 &dp_video_config->lane_count)) {
> +				 &video_info->lane_count)) {
>  		dev_err(dev, "failed to get lane-count\n");
> -		return ERR_PTR(-EINVAL);
> +		return -EINVAL;
>  	}
>  
> -	return dp_video_config;
> +	return 0;
>  }
>  
>  int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
> @@ -1158,9 +1200,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>  	 */
>  	dp->plat_data = plat_data;
>  
> -	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
> -	if (IS_ERR(dp->video_info))
> -		return PTR_ERR(dp->video_info);
> +	ret = analogix_dp_dt_parse_pdata(dp);
> +	if (ret)
> +		return ret;
>  
>  	dp->phy = devm_phy_get(dp->dev, "dp");
>  	if (IS_ERR(dp->phy)) {
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> index 9a90a18..730486d 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> @@ -120,9 +120,9 @@ enum dp_irq_type {
>  struct video_info {
>  	char *name;
>  
> -	bool h_sync_polarity;
> -	bool v_sync_polarity;
> -	bool interlaced;
> +	u32 h_sync_polarity;
> +	u32 v_sync_polarity;
> +	u32 interlaced;
>  
>  	enum color_space color_space;
>  	enum dynamic_range dynamic_range;
> @@ -154,7 +154,7 @@ struct analogix_dp_device {
>  	unsigned int		irq;
>  	void __iomem		*reg_base;
>  
> -	struct video_info	*video_info;
> +	struct video_info	video_info;
>  	struct link_train	link_train;
>  	struct work_struct	hotplug_work;
>  	struct phy		*phy;
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index a388c0a..861097a 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
>  	u32 reg;
>  
>  	/* Configure the input color depth, color space, dynamic range */
> -	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
> -		(dp->video_info->color_depth << IN_BPC_SHIFT) |
> -		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
> +	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
> +		(dp->video_info.color_depth << IN_BPC_SHIFT) |
> +		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
>  
>  	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>  	reg &= ~IN_YC_COEFFI_MASK;
> -	if (dp->video_info->ycbcr_coeff)
> +	if (dp->video_info.ycbcr_coeff)
>  		reg |= IN_YC_COEFFI_ITU709;
>  	else
>  		reg |= IN_YC_COEFFI_ITU601;
> @@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~INTERACE_SCAN_CFG;
> -	reg |= (dp->video_info->interlaced << 2);
> +	reg |= (dp->video_info.interlaced << 2);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~VSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->v_sync_polarity << 1);
> +	reg |= (dp->video_info.v_sync_polarity << 1);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~HSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->h_sync_polarity << 0);
> +	reg |= (dp->video_info.h_sync_polarity << 0);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
> 

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-09-30  5:32       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  5:32 UTC (permalink / raw)
  To: linux-arm-kernel

On 22.09.2015 16:37, Yakir Yang wrote:
> Both hsync/vsync polarity and interlace mode can be parsed from
> drm display mode, and dynamic_range and ycbcr_coeff can be judge
> by the video code.
> 
> But presumably Exynos still relies on the DT properties, so take
> good use of mode_fixup() in to achieve the compatibility hacks.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v5:
> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>   to get the backword timing values. 

Okay

> Krzysztof suggest me that driver could use
>   the "of_property_read_bool" to get backword timing values, but that interfacs
>   would modify the original drm_display_mode timing directly (whether those
>   properties exists or not).

Hmm, I don't understand. You have a:
	struct video_info {
		bool h_sync_polarity;
		bool v_sync_polarity;
		bool interlaced;
	};

so what is wrong with:
	dp_video_config->h_sync_polarity =
		of_property_read_bool(dp_node, "hsync-active-high");

Is it exactly the same binding as previously?

Best regards,
Krzysztof

> 
> Changes in v4:
> - Provide backword compatibility with samsung. (Krzysztof)
> 
> Changes in v3:
> - Dynamic parse video timing info from struct drm_display_mode and
>   struct drm_display_info. (Thierry)
> 
> Changes in v2: None
> 
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 144 +++++++++++++--------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   8 +-
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>  3 files changed, 104 insertions(+), 62 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index 1e3c8d3..6be139b 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
>  		return;
>  	}
>  
> -	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
> -					 dp->video_info->link_rate);
> +	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
> +					 dp->video_info.link_rate);
>  	if (ret) {
>  		dev_err(dp->dev, "unable to do link train\n");
>  		return;
> @@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
>  	dp->dpms_mode = DRM_MODE_DPMS_OFF;
>  }
>  
> +static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
> +					struct drm_display_mode *orig_mode,
> +					struct drm_display_mode *mode)
> +{
> +	struct analogix_dp_device *dp = bridge->driver_private;
> +	struct drm_display_info *display_info = &dp->connector->display_info;
> +	struct video_info *video = &dp->video_info;
> +	struct device_node *dp_node = dp->dev->of_node;
> +	int vic;
> +
> +	/* Input video interlaces & hsync pol & vsync pol */
> +	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
> +	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
> +	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
> +
> +	/* Input video dynamic_range & colorimetry */
> +	vic = drm_match_cea_mode(mode);
> +	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
> +	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
> +		video->dynamic_range = CEA;
> +		video->ycbcr_coeff = COLOR_YCBCR601;
> +	} else if (vic) {
> +		video->dynamic_range = CEA;
> +		video->ycbcr_coeff = COLOR_YCBCR709;
> +	} else {
> +		video->dynamic_range = VESA;
> +		video->ycbcr_coeff = COLOR_YCBCR709;
> +	}
> +
> +	/* Input vide bpc and color_formats */
> +	switch (display_info->bpc) {
> +	case 12:
> +		video->color_depth = COLOR_12;
> +		break;
> +	case 10:
> +		video->color_depth = COLOR_10;
> +		break;
> +	case 8:
> +		video->color_depth = COLOR_8;
> +		break;
> +	case 6:
> +		video->color_depth = COLOR_6;
> +		break;
> +	default:
> +		video->color_depth = COLOR_8;
> +		break;
> +	}
> +	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
> +		video->color_space = COLOR_YCBCR444;
> +	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
> +		video->color_space = COLOR_YCBCR422;
> +	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
> +		video->color_space = COLOR_RGB;
> +	else
> +		video->color_space = COLOR_RGB;
> +
> +	/*
> +	 * NOTE: those property parsing code is used for providing backward
> +	 * compatibility for samsung platform.
> +	 * Due to we used the "of_property_read_u32" interfaces, when this
> +	 * property isn't present, the "video_info" can keep the original
> +	 * values and wouldn't be modified.
> +	 */
> +	of_property_read_u32(dp_node, "samsung,color-space",
> +			     &video->color_space);
> +	of_property_read_u32(dp_node, "samsung,dynamic-range",
> +			     &video->dynamic_range);
> +	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> +			     &video->ycbcr_coeff);
> +	of_property_read_u32(dp_node, "samsung,color-depth",
> +			     &video->color_depth);
> +	of_property_read_u32(dp_node, "hsync-active-high",
> +			     &video->h_sync_polarity);
> +	of_property_read_u32(dp_node, "vsync-active-high",
> +			     &video->v_sync_polarity);
> +	of_property_read_u32(dp_node, "interlaced",
> +			     &video->interlaced);
> +}
> +
>  static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
>  {
>  	/* do nothing */
> @@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
>  	.disable = analogix_dp_bridge_disable,
>  	.pre_enable = analogix_dp_bridge_nop,
>  	.post_disable = analogix_dp_bridge_nop,
> +	.mode_set = analogix_dp_bridge_mode_set,
>  	.attach = analogix_dp_bridge_attach,
>  };
>  
> @@ -1070,62 +1150,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>  	return 0;
>  }
>  
> -static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
> +static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
>  {
> -	struct device_node *dp_node = dev->of_node;
> -	struct video_info *dp_video_config;
> -
> -	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
> -				       GFP_KERNEL);
> -	if (!dp_video_config)
> -		return ERR_PTR(-ENOMEM);
> -
> -	dp_video_config->h_sync_polarity =
> -		of_property_read_bool(dp_node, "hsync-active-high");
> -
> -	dp_video_config->v_sync_polarity =
> -		of_property_read_bool(dp_node, "vsync-active-high");
> -
> -	dp_video_config->interlaced =
> -		of_property_read_bool(dp_node, "interlaced");
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-space",
> -				 &dp_video_config->color_space)) {
> -		dev_err(dev, "failed to get color-space\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
> -				 &dp_video_config->dynamic_range)) {
> -		dev_err(dev, "failed to get dynamic-range\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> -				 &dp_video_config->ycbcr_coeff)) {
> -		dev_err(dev, "failed to get ycbcr-coeff\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-depth",
> -				 &dp_video_config->color_depth)) {
> -		dev_err(dev, "failed to get color-depth\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> +	struct device_node *dp_node = dp->dev->of_node;
> +	struct video_info *video_info = &dp->video_info
>  
>  	if (of_property_read_u32(dp_node, "samsung,link-rate",
> -				 &dp_video_config->link_rate)) {
> +				 &video_info->link_rate)) {
>  		dev_err(dev, "failed to get link-rate\n");
> -		return ERR_PTR(-EINVAL);
> +		return -EINVAL;
>  	}
>  
>  	if (of_property_read_u32(dp_node, "samsung,lane-count",
> -				 &dp_video_config->lane_count)) {
> +				 &video_info->lane_count)) {
>  		dev_err(dev, "failed to get lane-count\n");
> -		return ERR_PTR(-EINVAL);
> +		return -EINVAL;
>  	}
>  
> -	return dp_video_config;
> +	return 0;
>  }
>  
>  int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
> @@ -1158,9 +1200,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>  	 */
>  	dp->plat_data = plat_data;
>  
> -	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
> -	if (IS_ERR(dp->video_info))
> -		return PTR_ERR(dp->video_info);
> +	ret = analogix_dp_dt_parse_pdata(dp);
> +	if (ret)
> +		return ret;
>  
>  	dp->phy = devm_phy_get(dp->dev, "dp");
>  	if (IS_ERR(dp->phy)) {
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> index 9a90a18..730486d 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> @@ -120,9 +120,9 @@ enum dp_irq_type {
>  struct video_info {
>  	char *name;
>  
> -	bool h_sync_polarity;
> -	bool v_sync_polarity;
> -	bool interlaced;
> +	u32 h_sync_polarity;
> +	u32 v_sync_polarity;
> +	u32 interlaced;
>  
>  	enum color_space color_space;
>  	enum dynamic_range dynamic_range;
> @@ -154,7 +154,7 @@ struct analogix_dp_device {
>  	unsigned int		irq;
>  	void __iomem		*reg_base;
>  
> -	struct video_info	*video_info;
> +	struct video_info	video_info;
>  	struct link_train	link_train;
>  	struct work_struct	hotplug_work;
>  	struct phy		*phy;
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index a388c0a..861097a 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
>  	u32 reg;
>  
>  	/* Configure the input color depth, color space, dynamic range */
> -	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
> -		(dp->video_info->color_depth << IN_BPC_SHIFT) |
> -		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
> +	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
> +		(dp->video_info.color_depth << IN_BPC_SHIFT) |
> +		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
>  
>  	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>  	reg &= ~IN_YC_COEFFI_MASK;
> -	if (dp->video_info->ycbcr_coeff)
> +	if (dp->video_info.ycbcr_coeff)
>  		reg |= IN_YC_COEFFI_ITU709;
>  	else
>  		reg |= IN_YC_COEFFI_ITU601;
> @@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~INTERACE_SCAN_CFG;
> -	reg |= (dp->video_info->interlaced << 2);
> +	reg |= (dp->video_info.interlaced << 2);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~VSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->v_sync_polarity << 1);
> +	reg |= (dp->video_info.v_sync_polarity << 1);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  	reg &= ~HSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->h_sync_polarity << 0);
> +	reg |= (dp->video_info.h_sync_polarity << 0);
>  	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>  
>  	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
> 

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
  2015-09-22  7:43     ` Yakir Yang
@ 2015-09-30  5:39       ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  5:39 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

On 22.09.2015 16:43, Yakir Yang wrote:
> After exynos_dp have been split the common IP code into analogix_dp driver,
> the analogix_dp driver have deprecated some Samsung platform properties which
> could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
> for Exynos DTS file for dp-controller.
> 
> Beside the backward compatibility is fully preserved, so there are no
> bisectability break that make this change in a separate patch.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v5:
> - Correct the misspell in commit message. (Krzysztof)
> 
> Changes in v4:
> - Separate all DTS changes to a separate patch. (Krzysztof)
> 
> Changes in v3: None
> Changes in v2: None
> 
>  arch/arm/boot/dts/exynos5250-arndale.dts   | 2 --
>  arch/arm/boot/dts/exynos5250-smdk5250.dts  | 2 --
>  arch/arm/boot/dts/exynos5250-snow.dts      | 4 +---
>  arch/arm/boot/dts/exynos5250-spring.dts    | 4 +---
>  arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
>  arch/arm/boot/dts/exynos5420-smdk5420.dts  | 2 --
>  arch/arm/boot/dts/exynos5800-peach-pi.dts  | 4 +---
>  7 files changed, 4 insertions(+), 18 deletions(-)
> 

Assuming this will be merged as part of this set (dependency on previous
patches):

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
@ 2015-09-30  5:39       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  5:39 UTC (permalink / raw)
  To: linux-arm-kernel

On 22.09.2015 16:43, Yakir Yang wrote:
> After exynos_dp have been split the common IP code into analogix_dp driver,
> the analogix_dp driver have deprecated some Samsung platform properties which
> could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
> for Exynos DTS file for dp-controller.
> 
> Beside the backward compatibility is fully preserved, so there are no
> bisectability break that make this change in a separate patch.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v5:
> - Correct the misspell in commit message. (Krzysztof)
> 
> Changes in v4:
> - Separate all DTS changes to a separate patch. (Krzysztof)
> 
> Changes in v3: None
> Changes in v2: None
> 
>  arch/arm/boot/dts/exynos5250-arndale.dts   | 2 --
>  arch/arm/boot/dts/exynos5250-smdk5250.dts  | 2 --
>  arch/arm/boot/dts/exynos5250-snow.dts      | 4 +---
>  arch/arm/boot/dts/exynos5250-spring.dts    | 4 +---
>  arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
>  arch/arm/boot/dts/exynos5420-smdk5420.dts  | 2 --
>  arch/arm/boot/dts/exynos5800-peach-pi.dts  | 4 +---
>  7 files changed, 4 insertions(+), 18 deletions(-)
> 

Assuming this will be merged as part of this set (dependency on previous
patches):

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
@ 2015-09-30  6:48         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-30  6:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hi Krzysztof,

On 09/30/2015 01:17 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:29, Yakir Yang wrote:
>> Split the dp core driver from exynos directory to bridge directory,
>> and rename the core driver to analogix_dp_*, rename the platform
>> code to exynos_dp.
>>
>> Beside the new analogix_dp driver would export four hooks.
>> "analogix_dp_bind()" and "analogix_dp_unbind()"
>> "analogix_dp_detect()" and "analogix_dp_get_modes()"
>>
>> The bind/unbind symbols is used for analogix platform driver to connect
>> with analogix_dp core driver. And the detect/get_modes is used for analogix
>> platform driver to init the connector.
>>
>> They reason why connector need register in helper driver is rockchip drm
>> haven't implement the atomic API, but Exynos drm have implement it, so
>> there would need two different connector helper functions, that's why we
>> leave the connector register in helper driver.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v5:
>> - Correct the check condition of gpio_is_valid when driver try to get
>>    the "hpd-gpios" DT propery. (Heiko)
>> - Move the platform attach callback in the front of core driver bridge
>>    attch function. Cause once platform failed at attach, core driver should
>>    still failed, so no need to init connector before platform attached (Krzysztof)
>> - Keep code style no changes with the previous exynos_dp_code.c in this
>>    patch, and update commit message about the new export symbol (Krzysztof)
>> - Gather the device type patch (v4 11/16) into this one. (Krzysztof)
>> - leave out the connector registration to analogix platform driver. (Thierry)
> Thanks for fixing this, looks much better.
>
> I don't feel comfortable enough to provide a review tag but it looks
> good to me.

Thanks  ;)

- Yakir

> Best regards,
> Krzysztof
>
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
@ 2015-09-30  6:48         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-30  6:48 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Rob Herring
  Cc: David Airlie, Russell King, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Hi Krzysztof,

On 09/30/2015 01:17 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:29, Yakir Yang wrote:
>> Split the dp core driver from exynos directory to bridge directory,
>> and rename the core driver to analogix_dp_*, rename the platform
>> code to exynos_dp.
>>
>> Beside the new analogix_dp driver would export four hooks.
>> "analogix_dp_bind()" and "analogix_dp_unbind()"
>> "analogix_dp_detect()" and "analogix_dp_get_modes()"
>>
>> The bind/unbind symbols is used for analogix platform driver to connect
>> with analogix_dp core driver. And the detect/get_modes is used for analogix
>> platform driver to init the connector.
>>
>> They reason why connector need register in helper driver is rockchip drm
>> haven't implement the atomic API, but Exynos drm have implement it, so
>> there would need two different connector helper functions, that's why we
>> leave the connector register in helper driver.
>>
>> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>> Changes in v5:
>> - Correct the check condition of gpio_is_valid when driver try to get
>>    the "hpd-gpios" DT propery. (Heiko)
>> - Move the platform attach callback in the front of core driver bridge
>>    attch function. Cause once platform failed at attach, core driver should
>>    still failed, so no need to init connector before platform attached (Krzysztof)
>> - Keep code style no changes with the previous exynos_dp_code.c in this
>>    patch, and update commit message about the new export symbol (Krzysztof)
>> - Gather the device type patch (v4 11/16) into this one. (Krzysztof)
>> - leave out the connector registration to analogix platform driver. (Thierry)
> Thanks for fixing this, looks much better.
>
> I don't feel comfortable enough to provide a review tag but it looks
> good to me.

Thanks  ;)

- Yakir

> Best regards,
> Krzysztof
>
>
>
>


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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
@ 2015-09-30  6:48         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-30  6:48 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Krzysztof,

On 09/30/2015 01:17 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:29, Yakir Yang wrote:
>> Split the dp core driver from exynos directory to bridge directory,
>> and rename the core driver to analogix_dp_*, rename the platform
>> code to exynos_dp.
>>
>> Beside the new analogix_dp driver would export four hooks.
>> "analogix_dp_bind()" and "analogix_dp_unbind()"
>> "analogix_dp_detect()" and "analogix_dp_get_modes()"
>>
>> The bind/unbind symbols is used for analogix platform driver to connect
>> with analogix_dp core driver. And the detect/get_modes is used for analogix
>> platform driver to init the connector.
>>
>> They reason why connector need register in helper driver is rockchip drm
>> haven't implement the atomic API, but Exynos drm have implement it, so
>> there would need two different connector helper functions, that's why we
>> leave the connector register in helper driver.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v5:
>> - Correct the check condition of gpio_is_valid when driver try to get
>>    the "hpd-gpios" DT propery. (Heiko)
>> - Move the platform attach callback in the front of core driver bridge
>>    attch function. Cause once platform failed at attach, core driver should
>>    still failed, so no need to init connector before platform attached (Krzysztof)
>> - Keep code style no changes with the previous exynos_dp_code.c in this
>>    patch, and update commit message about the new export symbol (Krzysztof)
>> - Gather the device type patch (v4 11/16) into this one. (Krzysztof)
>> - leave out the connector registration to analogix platform driver. (Thierry)
> Thanks for fixing this, looks much better.
>
> I don't feel comfortable enough to provide a review tag but it looks
> good to me.

Thanks  ;)

- Yakir

> Best regards,
> Krzysztof
>
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 03/17] drm: bridge: analogix/dp: fix some obvious code style
  2015-09-30  5:22       ` Krzysztof Kozlowski
@ 2015-09-30  6:52         ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-30  6:52 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hi Krzysztof,

On 09/30/2015 01:22 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:34, Yakir Yang wrote:
>> Fix some obvious alignment problems, like alignment and line
>> over 80 characters problems, make this easy to be maintained
>> later.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v5:
>> - Resequence this patch after analogix_dp driver have been split
>>    from exynos_dp code, and rephrase reasonable commit message, and
>>    remove some controversial style (Krzysztof)
>>      -		analogix_dp_write_byte_to_dpcd(
>>      - 				dp, DP_TEST_RESPONSE,
>>      +		analogix_dp_write_byte_to_dpcd(dp,
>>      +				DP_TEST_RESPONSE,
>> 				DP_TEST_EDID_CHECKSUM_WRITE);
>>
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2:
>> - Improved commit message more readable, and avoid using some
>>    uncommon style like bellow: (Joe Preches)
>>      -  retval = exynos_dp_read_bytes_from_i2c(...
>>    				  ...);
>>      +  retval =
>>      +  exynos_dp_read_bytes_from_i2c(......);
>>
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++++++++++-----------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  72 ++++++------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 124 ++++++++++----------
>>   3 files changed, 163 insertions(+), 162 deletions(-)
>>
> IMHO much better than in previous attempt. The code looks good:
>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>
> BTW my opinion is not enough, you still need an ack from Exynos DP
> maintainer (or DRM guys).

Aha, thanks.

- Yakir

> Best regards,
> Krzysztof
>
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 03/17] drm: bridge: analogix/dp: fix some obvious code style
@ 2015-09-30  6:52         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-30  6:52 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Krzysztof,

On 09/30/2015 01:22 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:34, Yakir Yang wrote:
>> Fix some obvious alignment problems, like alignment and line
>> over 80 characters problems, make this easy to be maintained
>> later.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v5:
>> - Resequence this patch after analogix_dp driver have been split
>>    from exynos_dp code, and rephrase reasonable commit message, and
>>    remove some controversial style (Krzysztof)
>>      -		analogix_dp_write_byte_to_dpcd(
>>      - 				dp, DP_TEST_RESPONSE,
>>      +		analogix_dp_write_byte_to_dpcd(dp,
>>      +				DP_TEST_RESPONSE,
>> 				DP_TEST_EDID_CHECKSUM_WRITE);
>>
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2:
>> - Improved commit message more readable, and avoid using some
>>    uncommon style like bellow: (Joe Preches)
>>      -  retval = exynos_dp_read_bytes_from_i2c(...
>>    				  ...);
>>      +  retval =
>>      +  exynos_dp_read_bytes_from_i2c(......);
>>
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++++++++++-----------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  72 ++++++------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 124 ++++++++++----------
>>   3 files changed, 163 insertions(+), 162 deletions(-)
>>
> IMHO much better than in previous attempt. The code looks good:
>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>
> BTW my opinion is not enough, you still need an ack from Exynos DP
> maintainer (or DRM guys).

Aha, thanks.

- Yakir

> Best regards,
> Krzysztof
>
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  2015-09-30  5:32       ` Krzysztof Kozlowski
  (?)
  (?)
@ 2015-09-30  7:19       ` Yakir Yang
  2015-09-30  7:34           ` Krzysztof Kozlowski
  -1 siblings, 1 reply; 370+ messages in thread
From: Yakir Yang @ 2015-09-30  7:19 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Rob Herring
  Cc: devicetree, linux-samsung-soc, Russell King, Pawel Moll,
	Ian Campbell, linux-kernel, emil.l.velikov, dianders,
	Kishon Vijay Abraham I, linux-rockchip, Kukjin Kim, dri-devel,
	Kumar Gala, ajaynumb, robherring2, Andy Yan, Gustavo Padovan,
	linux-arm-kernel


[-- Attachment #1.1: Type: text/plain, Size: 13807 bytes --]

Hi Krzysztof,

On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:37, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code.
>>
>> But presumably Exynos still relies on the DT properties, so take
>> good use of mode_fixup() in to achieve the compatibility hacks.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v5:
>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>>    to get the backword timing values.
> Okay
>
>> Krzysztof suggest me that driver could use
>>    the "of_property_read_bool" to get backword timing values, but that interfacs
>>    would modify the original drm_display_mode timing directly (whether those
>>    properties exists or not).
> Hmm, I don't understand. You have a:
> 	struct video_info {
> 		bool h_sync_polarity;
> 		bool v_sync_polarity;
> 		bool interlaced;
> 	};
>
> so what is wrong with:
> 	dp_video_config->h_sync_polarity =
> 		of_property_read_bool(dp_node, "hsync-active-high");
>
> Is it exactly the same binding as previously?

Yes, it is the same binding as previously. But just a note that we already
mark those DT binding as deprecated.

+-interlaced:            deprecated prop that can parsed frm drm_display_mode.
+-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.


For now those values should come from "struct drm_display_mode",
and we already parsed them out from "drm_display_mode" before
driver provide the backward compatibility.

Let's used the "hsync-active-high" example:
     As for now the code would like:
     static void analogix_dp_bridge_mode_set(...)
     {
         // Parsed timing value from "drm_display_mode"
         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);

         // Try to detect the deprecated property, providing
         // the backward compatibility
         of_property_read_u32(dp_node, "hsync-active-high",
                                  &video->h_sync_polarity);

         /*
          * In this case, if "hsync-active-high" property haven't been
          * found, then the video timing "h_sync_polarity" would keep
          * no change, keeping the parsed value from "drm_display_mode"
          */
     }

     But if keep the "of_property_read_bool", then code would like:
     static void analogix_dp_bridge_mode_set(...)
     {
         // Parsed timing value from "drm_display_mode"
         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);

         // Try to detect the deprecated property, providing
         // the backward compatibility
video->h_sync_polarity =
of_property_read_bool(dp_node, "hsync-active-high");

         /*
          * In this case, if "hsync-active-high" property haven't been
          * found, then the video timing "h_sync_polarity" would just
          * modify to "false". That is the place we don't want, cause
          * it would always modify the timing value parsed from
          * "drm_display_mode"
          */
     }


Thanks,
- Yakir

> Best regards,
> Krzysztof
>
>> Changes in v4:
>> - Provide backword compatibility with samsung. (Krzysztof)
>>
>> Changes in v3:
>> - Dynamic parse video timing info from struct drm_display_mode and
>>    struct drm_display_info. (Thierry)
>>
>> Changes in v2: None
>>
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 144 +++++++++++++--------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   8 +-
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>>   3 files changed, 104 insertions(+), 62 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index 1e3c8d3..6be139b 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
>>   		return;
>>   	}
>>   
>> -	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
>> -					 dp->video_info->link_rate);
>> +	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
>> +					 dp->video_info.link_rate);
>>   	if (ret) {
>>   		dev_err(dp->dev, "unable to do link train\n");
>>   		return;
>> @@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
>>   	dp->dpms_mode = DRM_MODE_DPMS_OFF;
>>   }
>>   
>> +static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
>> +					struct drm_display_mode *orig_mode,
>> +					struct drm_display_mode *mode)
>> +{
>> +	struct analogix_dp_device *dp = bridge->driver_private;
>> +	struct drm_display_info *display_info = &dp->connector->display_info;
>> +	struct video_info *video = &dp->video_info;
>> +	struct device_node *dp_node = dp->dev->of_node;
>> +	int vic;
>> +
>> +	/* Input video interlaces & hsync pol & vsync pol */
>> +	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
>> +	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
>> +	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>> +
>> +	/* Input video dynamic_range & colorimetry */
>> +	vic = drm_match_cea_mode(mode);
>> +	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
>> +	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
>> +		video->dynamic_range = CEA;
>> +		video->ycbcr_coeff = COLOR_YCBCR601;
>> +	} else if (vic) {
>> +		video->dynamic_range = CEA;
>> +		video->ycbcr_coeff = COLOR_YCBCR709;
>> +	} else {
>> +		video->dynamic_range = VESA;
>> +		video->ycbcr_coeff = COLOR_YCBCR709;
>> +	}
>> +
>> +	/* Input vide bpc and color_formats */
>> +	switch (display_info->bpc) {
>> +	case 12:
>> +		video->color_depth = COLOR_12;
>> +		break;
>> +	case 10:
>> +		video->color_depth = COLOR_10;
>> +		break;
>> +	case 8:
>> +		video->color_depth = COLOR_8;
>> +		break;
>> +	case 6:
>> +		video->color_depth = COLOR_6;
>> +		break;
>> +	default:
>> +		video->color_depth = COLOR_8;
>> +		break;
>> +	}
>> +	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
>> +		video->color_space = COLOR_YCBCR444;
>> +	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
>> +		video->color_space = COLOR_YCBCR422;
>> +	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
>> +		video->color_space = COLOR_RGB;
>> +	else
>> +		video->color_space = COLOR_RGB;
>> +
>> +	/*
>> +	 * NOTE: those property parsing code is used for providing backward
>> +	 * compatibility for samsung platform.
>> +	 * Due to we used the "of_property_read_u32" interfaces, when this
>> +	 * property isn't present, the "video_info" can keep the original
>> +	 * values and wouldn't be modified.
>> +	 */
>> +	of_property_read_u32(dp_node, "samsung,color-space",
>> +			     &video->color_space);
>> +	of_property_read_u32(dp_node, "samsung,dynamic-range",
>> +			     &video->dynamic_range);
>> +	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
>> +			     &video->ycbcr_coeff);
>> +	of_property_read_u32(dp_node, "samsung,color-depth",
>> +			     &video->color_depth);
>> +	of_property_read_u32(dp_node, "hsync-active-high",
>> +			     &video->h_sync_polarity);
>> +	of_property_read_u32(dp_node, "vsync-active-high",
>> +			     &video->v_sync_polarity);
>> +	of_property_read_u32(dp_node, "interlaced",
>> +			     &video->interlaced);
>> +}
>> +
>>   static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
>>   {
>>   	/* do nothing */
>> @@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
>>   	.disable = analogix_dp_bridge_disable,
>>   	.pre_enable = analogix_dp_bridge_nop,
>>   	.post_disable = analogix_dp_bridge_nop,
>> +	.mode_set = analogix_dp_bridge_mode_set,
>>   	.attach = analogix_dp_bridge_attach,
>>   };
>>   
>> @@ -1070,62 +1150,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>>   	return 0;
>>   }
>>   
>> -static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
>> +static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
>>   {
>> -	struct device_node *dp_node = dev->of_node;
>> -	struct video_info *dp_video_config;
>> -
>> -	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
>> -				       GFP_KERNEL);
>> -	if (!dp_video_config)
>> -		return ERR_PTR(-ENOMEM);
>> -
>> -	dp_video_config->h_sync_polarity =
>> -		of_property_read_bool(dp_node, "hsync-active-high");
>> -
>> -	dp_video_config->v_sync_polarity =
>> -		of_property_read_bool(dp_node, "vsync-active-high");
>> -
>> -	dp_video_config->interlaced =
>> -		of_property_read_bool(dp_node, "interlaced");
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,color-space",
>> -				 &dp_video_config->color_space)) {
>> -		dev_err(dev, "failed to get color-space\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
>> -				 &dp_video_config->dynamic_range)) {
>> -		dev_err(dev, "failed to get dynamic-range\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
>> -				 &dp_video_config->ycbcr_coeff)) {
>> -		dev_err(dev, "failed to get ycbcr-coeff\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> -
>> -	if (of_property_read_u32(dp_node, "samsung,color-depth",
>> -				 &dp_video_config->color_depth)) {
>> -		dev_err(dev, "failed to get color-depth\n");
>> -		return ERR_PTR(-EINVAL);
>> -	}
>> +	struct device_node *dp_node = dp->dev->of_node;
>> +	struct video_info *video_info = &dp->video_info
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,link-rate",
>> -				 &dp_video_config->link_rate)) {
>> +				 &video_info->link_rate)) {
>>   		dev_err(dev, "failed to get link-rate\n");
>> -		return ERR_PTR(-EINVAL);
>> +		return -EINVAL;
>>   	}
>>   
>>   	if (of_property_read_u32(dp_node, "samsung,lane-count",
>> -				 &dp_video_config->lane_count)) {
>> +				 &video_info->lane_count)) {
>>   		dev_err(dev, "failed to get lane-count\n");
>> -		return ERR_PTR(-EINVAL);
>> +		return -EINVAL;
>>   	}
>>   
>> -	return dp_video_config;
>> +	return 0;
>>   }
>>   
>>   int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>> @@ -1158,9 +1200,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>>   	 */
>>   	dp->plat_data = plat_data;
>>   
>> -	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
>> -	if (IS_ERR(dp->video_info))
>> -		return PTR_ERR(dp->video_info);
>> +	ret = analogix_dp_dt_parse_pdata(dp);
>> +	if (ret)
>> +		return ret;
>>   
>>   	dp->phy = devm_phy_get(dp->dev, "dp");
>>   	if (IS_ERR(dp->phy)) {
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> index 9a90a18..730486d 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>> @@ -120,9 +120,9 @@ enum dp_irq_type {
>>   struct video_info {
>>   	char *name;
>>   
>> -	bool h_sync_polarity;
>> -	bool v_sync_polarity;
>> -	bool interlaced;
>> +	u32 h_sync_polarity;
>> +	u32 v_sync_polarity;
>> +	u32 interlaced;
>>   
>>   	enum color_space color_space;
>>   	enum dynamic_range dynamic_range;
>> @@ -154,7 +154,7 @@ struct analogix_dp_device {
>>   	unsigned int		irq;
>>   	void __iomem		*reg_base;
>>   
>> -	struct video_info	*video_info;
>> +	struct video_info	video_info;
>>   	struct link_train	link_train;
>>   	struct work_struct	hotplug_work;
>>   	struct phy		*phy;
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> index a388c0a..861097a 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> @@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
>>   	u32 reg;
>>   
>>   	/* Configure the input color depth, color space, dynamic range */
>> -	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
>> -		(dp->video_info->color_depth << IN_BPC_SHIFT) |
>> -		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
>> +	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
>> +		(dp->video_info.color_depth << IN_BPC_SHIFT) |
>> +		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
>>   
>>   	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>>   	reg &= ~IN_YC_COEFFI_MASK;
>> -	if (dp->video_info->ycbcr_coeff)
>> +	if (dp->video_info.ycbcr_coeff)
>>   		reg |= IN_YC_COEFFI_ITU709;
>>   	else
>>   		reg |= IN_YC_COEFFI_ITU601;
>> @@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
>>   
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   	reg &= ~INTERACE_SCAN_CFG;
>> -	reg |= (dp->video_info->interlaced << 2);
>> +	reg |= (dp->video_info.interlaced << 2);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   	reg &= ~VSYNC_POLARITY_CFG;
>> -	reg |= (dp->video_info->v_sync_polarity << 1);
>> +	reg |= (dp->video_info.v_sync_polarity << 1);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   
>>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   	reg &= ~HSYNC_POLARITY_CFG;
>> -	reg |= (dp->video_info->h_sync_polarity << 0);
>> +	reg |= (dp->video_info.h_sync_polarity << 0);
>>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>>   
>>   	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
>>
>
>
>


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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
@ 2015-09-30  7:20         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-30  7:20 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hi Krzysztof,

On 09/30/2015 01:39 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:43, Yakir Yang wrote:
>> After exynos_dp have been split the common IP code into analogix_dp driver,
>> the analogix_dp driver have deprecated some Samsung platform properties which
>> could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
>> for Exynos DTS file for dp-controller.
>>
>> Beside the backward compatibility is fully preserved, so there are no
>> bisectability break that make this change in a separate patch.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v5:
>> - Correct the misspell in commit message. (Krzysztof)
>>
>> Changes in v4:
>> - Separate all DTS changes to a separate patch. (Krzysztof)
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>   arch/arm/boot/dts/exynos5250-arndale.dts   | 2 --
>>   arch/arm/boot/dts/exynos5250-smdk5250.dts  | 2 --
>>   arch/arm/boot/dts/exynos5250-snow.dts      | 4 +---
>>   arch/arm/boot/dts/exynos5250-spring.dts    | 4 +---
>>   arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
>>   arch/arm/boot/dts/exynos5420-smdk5420.dts  | 2 --
>>   arch/arm/boot/dts/exynos5800-peach-pi.dts  | 4 +---
>>   7 files changed, 4 insertions(+), 18 deletions(-)
>>
> Assuming this will be merged as part of this set (dependency on previous
> patches):
>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Thanks a lot ;)

- Yakir

> Best regards,
> Krzysztof
>
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
@ 2015-09-30  7:20         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-30  7:20 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Russell King,
	Pawel Moll, Ian Campbell, David Airlie,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w,
	dianders-F7+t8E8rja9g9hUCZPvPmw, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	Sean Paul, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	Kumar Gala, ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan, Gustavo Padovan,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Hi Krzysztof,

On 09/30/2015 01:39 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:43, Yakir Yang wrote:
>> After exynos_dp have been split the common IP code into analogix_dp driver,
>> the analogix_dp driver have deprecated some Samsung platform properties which
>> could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
>> for Exynos DTS file for dp-controller.
>>
>> Beside the backward compatibility is fully preserved, so there are no
>> bisectability break that make this change in a separate patch.
>>
>> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>> Changes in v5:
>> - Correct the misspell in commit message. (Krzysztof)
>>
>> Changes in v4:
>> - Separate all DTS changes to a separate patch. (Krzysztof)
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>   arch/arm/boot/dts/exynos5250-arndale.dts   | 2 --
>>   arch/arm/boot/dts/exynos5250-smdk5250.dts  | 2 --
>>   arch/arm/boot/dts/exynos5250-snow.dts      | 4 +---
>>   arch/arm/boot/dts/exynos5250-spring.dts    | 4 +---
>>   arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
>>   arch/arm/boot/dts/exynos5420-smdk5420.dts  | 2 --
>>   arch/arm/boot/dts/exynos5800-peach-pi.dts  | 4 +---
>>   7 files changed, 4 insertions(+), 18 deletions(-)
>>
> Assuming this will be merged as part of this set (dependency on previous
> patches):
>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>

Thanks a lot ;)

- Yakir

> Best regards,
> Krzysztof
>
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
@ 2015-09-30  7:20         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-30  7:20 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Krzysztof,

On 09/30/2015 01:39 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:43, Yakir Yang wrote:
>> After exynos_dp have been split the common IP code into analogix_dp driver,
>> the analogix_dp driver have deprecated some Samsung platform properties which
>> could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
>> for Exynos DTS file for dp-controller.
>>
>> Beside the backward compatibility is fully preserved, so there are no
>> bisectability break that make this change in a separate patch.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v5:
>> - Correct the misspell in commit message. (Krzysztof)
>>
>> Changes in v4:
>> - Separate all DTS changes to a separate patch. (Krzysztof)
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>   arch/arm/boot/dts/exynos5250-arndale.dts   | 2 --
>>   arch/arm/boot/dts/exynos5250-smdk5250.dts  | 2 --
>>   arch/arm/boot/dts/exynos5250-snow.dts      | 4 +---
>>   arch/arm/boot/dts/exynos5250-spring.dts    | 4 +---
>>   arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
>>   arch/arm/boot/dts/exynos5420-smdk5420.dts  | 2 --
>>   arch/arm/boot/dts/exynos5800-peach-pi.dts  | 4 +---
>>   7 files changed, 4 insertions(+), 18 deletions(-)
>>
> Assuming this will be merged as part of this set (dependency on previous
> patches):
>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Thanks a lot ;)

- Yakir

> Best regards,
> Krzysztof
>
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  2015-09-30  7:19       ` Yakir Yang
@ 2015-09-30  7:34           ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  7:34 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

On 30.09.2015 16:19, Yakir Yang wrote:
> Hi Krzysztof,
> 
> On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
>> On 22.09.2015 16:37, Yakir Yang wrote:
>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>> by the video code.
>>>
>>> But presumably Exynos still relies on the DT properties, so take
>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>
>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>> ---
>>> Changes in v5:
>>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>>>   to get the backword timing values. 
>> Okay
>>
>>> Krzysztof suggest me that driver could use
>>>   the "of_property_read_bool" to get backword timing values, but that interfacs
>>>   would modify the original drm_display_mode timing directly (whether those
>>>   properties exists or not).
>> Hmm, I don't understand. You have a:
>> 	struct video_info {
>> 		bool h_sync_polarity;
>> 		bool v_sync_polarity;
>> 		bool interlaced;
>> 	};
>>
>> so what is wrong with:
>> 	dp_video_config->h_sync_polarity =
>> 		of_property_read_bool(dp_node, "hsync-active-high");
>>
>> Is it exactly the same binding as previously?
> 
> Yes, it is the same binding as previously. But just a note that we already
> mark those DT binding as deprecated.
> 
> +-interlaced:            deprecated prop that can parsed frm drm_display_mode.
> +-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
> +-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
> 
> 
> For now those values should come from "struct drm_display_mode",
> and we already parsed them out from "drm_display_mode" before
> driver provide the backward compatibility.
> 
> Let's used the "hsync-active-high" example:
>     As for now the code would like:
>     static void analogix_dp_bridge_mode_set(...)
>     {
>         // Parsed timing value from "drm_display_mode"
>         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
> 
>         // Try to detect the deprecated property, providing
>         // the backward compatibility
>         of_property_read_u32(dp_node, "hsync-active-high",
>                                  &video->h_sync_polarity);    
> 
>         /*
>          * In this case, if "hsync-active-high" property haven't been
>          * found, then the video timing "h_sync_polarity" would  keep
>          * no change, keeping the parsed value from "drm_display_mode"
>          */     
>     }   
> 
>     But if keep the "of_property_read_bool", then code would like:
>     static void analogix_dp_bridge_mode_set(...)
>     {
>         // Parsed timing value from "drm_display_mode"
>         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
> 
>         // Try to detect the deprecated property, providing
>         // the backward compatibility
>         video->h_sync_polarity =
>                     of_property_read_bool(dp_node, "hsync-active-high");
>    
> 
>         /*
>          * In this case, if "hsync-active-high" property haven't been
>          * found, then the video timing "h_sync_polarity" would just
>          * modify to "false". That is the place we don't want, cause
>          * it would always modify the timing value parsed from
>          * "drm_display_mode"
>          */  
>     }   
> 

OK, I see the point of overwriting values from drm_display_mode. However
I think you changed the binding. I believe the of_property_read_u32()
will behave differently for such DTS:

exynos_dp {
	...
	hsync-active-high;
}

It will return -EOVERFLOW which means it would be broken now...

Best regards,
Krzysztof



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-09-30  7:34           ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  7:34 UTC (permalink / raw)
  To: linux-arm-kernel

On 30.09.2015 16:19, Yakir Yang wrote:
> Hi Krzysztof,
> 
> On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
>> On 22.09.2015 16:37, Yakir Yang wrote:
>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>> by the video code.
>>>
>>> But presumably Exynos still relies on the DT properties, so take
>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>
>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>> ---
>>> Changes in v5:
>>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>>>   to get the backword timing values. 
>> Okay
>>
>>> Krzysztof suggest me that driver could use
>>>   the "of_property_read_bool" to get backword timing values, but that interfacs
>>>   would modify the original drm_display_mode timing directly (whether those
>>>   properties exists or not).
>> Hmm, I don't understand. You have a:
>> 	struct video_info {
>> 		bool h_sync_polarity;
>> 		bool v_sync_polarity;
>> 		bool interlaced;
>> 	};
>>
>> so what is wrong with:
>> 	dp_video_config->h_sync_polarity =
>> 		of_property_read_bool(dp_node, "hsync-active-high");
>>
>> Is it exactly the same binding as previously?
> 
> Yes, it is the same binding as previously. But just a note that we already
> mark those DT binding as deprecated.
> 
> +-interlaced:            deprecated prop that can parsed frm drm_display_mode.
> +-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
> +-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
> 
> 
> For now those values should come from "struct drm_display_mode",
> and we already parsed them out from "drm_display_mode" before
> driver provide the backward compatibility.
> 
> Let's used the "hsync-active-high" example:
>     As for now the code would like:
>     static void analogix_dp_bridge_mode_set(...)
>     {
>         // Parsed timing value from "drm_display_mode"
>         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
> 
>         // Try to detect the deprecated property, providing
>         // the backward compatibility
>         of_property_read_u32(dp_node, "hsync-active-high",
>                                  &video->h_sync_polarity);    
> 
>         /*
>          * In this case, if "hsync-active-high" property haven't been
>          * found, then the video timing "h_sync_polarity" would  keep
>          * no change, keeping the parsed value from "drm_display_mode"
>          */     
>     }   
> 
>     But if keep the "of_property_read_bool", then code would like:
>     static void analogix_dp_bridge_mode_set(...)
>     {
>         // Parsed timing value from "drm_display_mode"
>         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
> 
>         // Try to detect the deprecated property, providing
>         // the backward compatibility
>         video->h_sync_polarity =
>                     of_property_read_bool(dp_node, "hsync-active-high");
>    
> 
>         /*
>          * In this case, if "hsync-active-high" property haven't been
>          * found, then the video timing "h_sync_polarity" would just
>          * modify to "false". That is the place we don't want, cause
>          * it would always modify the timing value parsed from
>          * "drm_display_mode"
>          */  
>     }   
> 

OK, I see the point of overwriting values from drm_display_mode. However
I think you changed the binding. I believe the of_property_read_u32()
will behave differently for such DTS:

exynos_dp {
	...
	hsync-active-high;
}

It will return -EOVERFLOW which means it would be broken now...

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  2015-09-30  7:34           ` Krzysztof Kozlowski
  (?)
@ 2015-09-30  8:20           ` Yakir Yang
  2015-09-30  8:26               ` Krzysztof Kozlowski
  -1 siblings, 1 reply; 370+ messages in thread
From: Yakir Yang @ 2015-09-30  8:20 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Rob Herring
  Cc: devicetree, linux-samsung-soc, Russell King, Pawel Moll,
	Ian Campbell, linux-kernel, emil.l.velikov, dianders,
	Kishon Vijay Abraham I, linux-rockchip, Kukjin Kim, dri-devel,
	Kumar Gala, ajaynumb, robherring2, Andy Yan, Gustavo Padovan,
	linux-arm-kernel


[-- Attachment #1.1: Type: text/plain, Size: 4646 bytes --]

Hi Krzysztof,

On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
> On 30.09.2015 16:19, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
>>> On 22.09.2015 16:37, Yakir Yang wrote:
>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>> by the video code.
>>>>
>>>> But presumably Exynos still relies on the DT properties, so take
>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>
>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>> ---
>>>> Changes in v5:
>>>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>>>>    to get the backword timing values.
>>> Okay
>>>
>>>> Krzysztof suggest me that driver could use
>>>>    the "of_property_read_bool" to get backword timing values, but that interfacs
>>>>    would modify the original drm_display_mode timing directly (whether those
>>>>    properties exists or not).
>>> Hmm, I don't understand. You have a:
>>> 	struct video_info {
>>> 		bool h_sync_polarity;
>>> 		bool v_sync_polarity;
>>> 		bool interlaced;
>>> 	};
>>>
>>> so what is wrong with:
>>> 	dp_video_config->h_sync_polarity =
>>> 		of_property_read_bool(dp_node, "hsync-active-high");
>>>
>>> Is it exactly the same binding as previously?
>> Yes, it is the same binding as previously. But just a note that we already
>> mark those DT binding as deprecated.
>>
>> +-interlaced:            deprecated prop that can parsed frm drm_display_mode.
>> +-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
>> +-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
>>
>>
>> For now those values should come from "struct drm_display_mode",
>> and we already parsed them out from "drm_display_mode" before
>> driver provide the backward compatibility.
>>
>> Let's used the "hsync-active-high" example:
>>      As for now the code would like:
>>      static void analogix_dp_bridge_mode_set(...)
>>      {
>>          // Parsed timing value from "drm_display_mode"
>>          video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>>
>>          // Try to detect the deprecated property, providing
>>          // the backward compatibility
>>          of_property_read_u32(dp_node, "hsync-active-high",
>>                                   &video->h_sync_polarity);
>>
>>          /*
>>           * In this case, if "hsync-active-high" property haven't been
>>           * found, then the video timing "h_sync_polarity" would  keep
>>           * no change, keeping the parsed value from "drm_display_mode"
>>           */
>>      }
>>
>>      But if keep the "of_property_read_bool", then code would like:
>>      static void analogix_dp_bridge_mode_set(...)
>>      {
>>          // Parsed timing value from "drm_display_mode"
>>          video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>>
>>          // Try to detect the deprecated property, providing
>>          // the backward compatibility
>>          video->h_sync_polarity =
>>                      of_property_read_bool(dp_node, "hsync-active-high");
>>     
>>
>>          /*
>>           * In this case, if "hsync-active-high" property haven't been
>>           * found, then the video timing "h_sync_polarity" would just
>>           * modify to "false". That is the place we don't want, cause
>>           * it would always modify the timing value parsed from
>>           * "drm_display_mode"
>>           */
>>      }
>>
> OK, I see the point of overwriting values from drm_display_mode. However
> I think you changed the binding. I believe the of_property_read_u32()
> will behave differently for such DTS:
>
> exynos_dp {
> 	...
> 	hsync-active-high;
> }
>
> It will return -EOVERFLOW which means it would be broken now...

Whoops, thanks for your remind, after try that, I do see over flow error.
static void *of_find_property_value_of_size(const struct device_node *np,
                         const char *propname, u32 len)
{
         ....
         if (len > prop->length)
                 return ERR_PTR(-EOVERFLOW);
         ...
}

So I though code should be:
     if (of_property_read_bool(dp_node, "hsync-active-high"))
         video->h_sync_polarity = true;

And we can't provide full backward compatibility for this property, cause
the previous exynos_dp driver would set this timing value to "false" when
property not defined, but analogix_dp driver keep this timing value
corresponding to "drm_display_mode" when property not found.


Thanks,
- Yakir

> Best regards,
> Krzysztof
>
>
>
>
>


[-- Attachment #1.2: Type: text/html, Size: 5769 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-09-30  8:26               ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  8:26 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

On 30.09.2015 17:20, Yakir Yang wrote:
> Hi Krzysztof,
> 
> On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
>> On 30.09.2015 16:19, Yakir Yang wrote:
>>> Hi Krzysztof,
>>>
>>> On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
>>>> On 22.09.2015 16:37, Yakir Yang wrote:
>>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>>> by the video code.
>>>>>
>>>>> But presumably Exynos still relies on the DT properties, so take
>>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>>
>>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>>> ---
>>>>> Changes in v5:
>>>>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>>>>>   to get the backword timing values. 
>>>> Okay
>>>>
>>>>> Krzysztof suggest me that driver could use
>>>>>   the "of_property_read_bool" to get backword timing values, but that interfacs
>>>>>   would modify the original drm_display_mode timing directly (whether those
>>>>>   properties exists or not).
>>>> Hmm, I don't understand. You have a:
>>>> 	struct video_info {
>>>> 		bool h_sync_polarity;
>>>> 		bool v_sync_polarity;
>>>> 		bool interlaced;
>>>> 	};
>>>>
>>>> so what is wrong with:
>>>> 	dp_video_config->h_sync_polarity =
>>>> 		of_property_read_bool(dp_node, "hsync-active-high");
>>>>
>>>> Is it exactly the same binding as previously?
>>> Yes, it is the same binding as previously. But just a note that we already
>>> mark those DT binding as deprecated.
>>>
>>> +-interlaced:            deprecated prop that can parsed frm drm_display_mode.
>>> +-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
>>> +-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
>>>
>>>
>>> For now those values should come from "struct drm_display_mode",
>>> and we already parsed them out from "drm_display_mode" before
>>> driver provide the backward compatibility.
>>>
>>> Let's used the "hsync-active-high" example:
>>>     As for now the code would like:
>>>     static void analogix_dp_bridge_mode_set(...)
>>>     {
>>>         // Parsed timing value from "drm_display_mode"
>>>         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>>>
>>>         // Try to detect the deprecated property, providing
>>>         // the backward compatibility
>>>         of_property_read_u32(dp_node, "hsync-active-high",
>>>                                  &video->h_sync_polarity);    
>>>
>>>         /*
>>>          * In this case, if "hsync-active-high" property haven't been
>>>          * found, then the video timing "h_sync_polarity" would  keep
>>>          * no change, keeping the parsed value from "drm_display_mode"
>>>          */     
>>>     }   
>>>
>>>     But if keep the "of_property_read_bool", then code would like:
>>>     static void analogix_dp_bridge_mode_set(...)
>>>     {
>>>         // Parsed timing value from "drm_display_mode"
>>>         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>>>
>>>         // Try to detect the deprecated property, providing
>>>         // the backward compatibility
>>>         video->h_sync_polarity =
>>>                     of_property_read_bool(dp_node, "hsync-active-high");
>>>    
>>>
>>>         /*
>>>          * In this case, if "hsync-active-high" property haven't been
>>>          * found, then the video timing "h_sync_polarity" would just
>>>          * modify to "false". That is the place we don't want, cause
>>>          * it would always modify the timing value parsed from
>>>          * "drm_display_mode"
>>>          */  
>>>     }   
>>>
>> OK, I see the point of overwriting values from drm_display_mode. However
>> I think you changed the binding. I believe the of_property_read_u32()
>> will behave differently for such DTS:
>>
>> exynos_dp {
>> 	...
>> 	hsync-active-high;
>> }
>>
>> It will return -EOVERFLOW which means it would be broken now...
> 
> Whoops, thanks for your remind, after try that, I do see over flow error.
> static void *of_find_property_value_of_size(const struct device_node *np,
>                         const char *propname, u32 len)
> {
>         ....
>         if (len > prop->length)
>                 return ERR_PTR(-EOVERFLOW);
>         ...
> }
> 
> So I though code should be:
>     if (of_property_read_bool(dp_node, "hsync-active-high"))
>         video->h_sync_polarity = true;

Looks good.

> 
> And we can't provide full backward compatibility for this property, cause
> the previous exynos_dp driver would set this timing value to "false" when
> property not defined, but analogix_dp driver keep this timing value
> corresponding to "drm_display_mode" when property not found.

Indeed, the behaviour changes. I don't know if this is important issue...

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-09-30  8:26               ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  8:26 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Rob Herring
  Cc: David Airlie, Russell King, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

On 30.09.2015 17:20, Yakir Yang wrote:
> Hi Krzysztof,
> 
> On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
>> On 30.09.2015 16:19, Yakir Yang wrote:
>>> Hi Krzysztof,
>>>
>>> On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
>>>> On 22.09.2015 16:37, Yakir Yang wrote:
>>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>>> by the video code.
>>>>>
>>>>> But presumably Exynos still relies on the DT properties, so take
>>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>>
>>>>> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>>>>> ---
>>>>> Changes in v5:
>>>>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>>>>>   to get the backword timing values. 
>>>> Okay
>>>>
>>>>> Krzysztof suggest me that driver could use
>>>>>   the "of_property_read_bool" to get backword timing values, but that interfacs
>>>>>   would modify the original drm_display_mode timing directly (whether those
>>>>>   properties exists or not).
>>>> Hmm, I don't understand. You have a:
>>>> 	struct video_info {
>>>> 		bool h_sync_polarity;
>>>> 		bool v_sync_polarity;
>>>> 		bool interlaced;
>>>> 	};
>>>>
>>>> so what is wrong with:
>>>> 	dp_video_config->h_sync_polarity =
>>>> 		of_property_read_bool(dp_node, "hsync-active-high");
>>>>
>>>> Is it exactly the same binding as previously?
>>> Yes, it is the same binding as previously. But just a note that we already
>>> mark those DT binding as deprecated.
>>>
>>> +-interlaced:            deprecated prop that can parsed frm drm_display_mode.
>>> +-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
>>> +-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
>>>
>>>
>>> For now those values should come from "struct drm_display_mode",
>>> and we already parsed them out from "drm_display_mode" before
>>> driver provide the backward compatibility.
>>>
>>> Let's used the "hsync-active-high" example:
>>>     As for now the code would like:
>>>     static void analogix_dp_bridge_mode_set(...)
>>>     {
>>>         // Parsed timing value from "drm_display_mode"
>>>         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>>>
>>>         // Try to detect the deprecated property, providing
>>>         // the backward compatibility
>>>         of_property_read_u32(dp_node, "hsync-active-high",
>>>                                  &video->h_sync_polarity);    
>>>
>>>         /*
>>>          * In this case, if "hsync-active-high" property haven't been
>>>          * found, then the video timing "h_sync_polarity" would  keep
>>>          * no change, keeping the parsed value from "drm_display_mode"
>>>          */     
>>>     }   
>>>
>>>     But if keep the "of_property_read_bool", then code would like:
>>>     static void analogix_dp_bridge_mode_set(...)
>>>     {
>>>         // Parsed timing value from "drm_display_mode"
>>>         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>>>
>>>         // Try to detect the deprecated property, providing
>>>         // the backward compatibility
>>>         video->h_sync_polarity =
>>>                     of_property_read_bool(dp_node, "hsync-active-high");
>>>    
>>>
>>>         /*
>>>          * In this case, if "hsync-active-high" property haven't been
>>>          * found, then the video timing "h_sync_polarity" would just
>>>          * modify to "false". That is the place we don't want, cause
>>>          * it would always modify the timing value parsed from
>>>          * "drm_display_mode"
>>>          */  
>>>     }   
>>>
>> OK, I see the point of overwriting values from drm_display_mode. However
>> I think you changed the binding. I believe the of_property_read_u32()
>> will behave differently for such DTS:
>>
>> exynos_dp {
>> 	...
>> 	hsync-active-high;
>> }
>>
>> It will return -EOVERFLOW which means it would be broken now...
> 
> Whoops, thanks for your remind, after try that, I do see over flow error.
> static void *of_find_property_value_of_size(const struct device_node *np,
>                         const char *propname, u32 len)
> {
>         ....
>         if (len > prop->length)
>                 return ERR_PTR(-EOVERFLOW);
>         ...
> }
> 
> So I though code should be:
>     if (of_property_read_bool(dp_node, "hsync-active-high"))
>         video->h_sync_polarity = true;

Looks good.

> 
> And we can't provide full backward compatibility for this property, cause
> the previous exynos_dp driver would set this timing value to "false" when
> property not defined, but analogix_dp driver keep this timing value
> corresponding to "drm_display_mode" when property not found.

Indeed, the behaviour changes. I don't know if this is important issue...

Best regards,
Krzysztof

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-09-30  8:26               ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-09-30  8:26 UTC (permalink / raw)
  To: linux-arm-kernel

On 30.09.2015 17:20, Yakir Yang wrote:
> Hi Krzysztof,
> 
> On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
>> On 30.09.2015 16:19, Yakir Yang wrote:
>>> Hi Krzysztof,
>>>
>>> On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
>>>> On 22.09.2015 16:37, Yakir Yang wrote:
>>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>>> by the video code.
>>>>>
>>>>> But presumably Exynos still relies on the DT properties, so take
>>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>>
>>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>>> ---
>>>>> Changes in v5:
>>>>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>>>>>   to get the backword timing values. 
>>>> Okay
>>>>
>>>>> Krzysztof suggest me that driver could use
>>>>>   the "of_property_read_bool" to get backword timing values, but that interfacs
>>>>>   would modify the original drm_display_mode timing directly (whether those
>>>>>   properties exists or not).
>>>> Hmm, I don't understand. You have a:
>>>> 	struct video_info {
>>>> 		bool h_sync_polarity;
>>>> 		bool v_sync_polarity;
>>>> 		bool interlaced;
>>>> 	};
>>>>
>>>> so what is wrong with:
>>>> 	dp_video_config->h_sync_polarity =
>>>> 		of_property_read_bool(dp_node, "hsync-active-high");
>>>>
>>>> Is it exactly the same binding as previously?
>>> Yes, it is the same binding as previously. But just a note that we already
>>> mark those DT binding as deprecated.
>>>
>>> +-interlaced:            deprecated prop that can parsed frm drm_display_mode.
>>> +-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
>>> +-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
>>>
>>>
>>> For now those values should come from "struct drm_display_mode",
>>> and we already parsed them out from "drm_display_mode" before
>>> driver provide the backward compatibility.
>>>
>>> Let's used the "hsync-active-high" example:
>>>     As for now the code would like:
>>>     static void analogix_dp_bridge_mode_set(...)
>>>     {
>>>         // Parsed timing value from "drm_display_mode"
>>>         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>>>
>>>         // Try to detect the deprecated property, providing
>>>         // the backward compatibility
>>>         of_property_read_u32(dp_node, "hsync-active-high",
>>>                                  &video->h_sync_polarity);    
>>>
>>>         /*
>>>          * In this case, if "hsync-active-high" property haven't been
>>>          * found, then the video timing "h_sync_polarity" would  keep
>>>          * no change, keeping the parsed value from "drm_display_mode"
>>>          */     
>>>     }   
>>>
>>>     But if keep the "of_property_read_bool", then code would like:
>>>     static void analogix_dp_bridge_mode_set(...)
>>>     {
>>>         // Parsed timing value from "drm_display_mode"
>>>         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>>>
>>>         // Try to detect the deprecated property, providing
>>>         // the backward compatibility
>>>         video->h_sync_polarity =
>>>                     of_property_read_bool(dp_node, "hsync-active-high");
>>>    
>>>
>>>         /*
>>>          * In this case, if "hsync-active-high" property haven't been
>>>          * found, then the video timing "h_sync_polarity" would just
>>>          * modify to "false". That is the place we don't want, cause
>>>          * it would always modify the timing value parsed from
>>>          * "drm_display_mode"
>>>          */  
>>>     }   
>>>
>> OK, I see the point of overwriting values from drm_display_mode. However
>> I think you changed the binding. I believe the of_property_read_u32()
>> will behave differently for such DTS:
>>
>> exynos_dp {
>> 	...
>> 	hsync-active-high;
>> }
>>
>> It will return -EOVERFLOW which means it would be broken now...
> 
> Whoops, thanks for your remind, after try that, I do see over flow error.
> static void *of_find_property_value_of_size(const struct device_node *np,
>                         const char *propname, u32 len)
> {
>         ....
>         if (len > prop->length)
>                 return ERR_PTR(-EOVERFLOW);
>         ...
> }
> 
> So I though code should be:
>     if (of_property_read_bool(dp_node, "hsync-active-high"))
>         video->h_sync_polarity = true;

Looks good.

> 
> And we can't provide full backward compatibility for this property, cause
> the previous exynos_dp driver would set this timing value to "false" when
> property not defined, but analogix_dp driver keep this timing value
> corresponding to "drm_display_mode" when property not found.

Indeed, the behaviour changes. I don't know if this is important issue...

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  2015-09-30  8:26               ` Krzysztof Kozlowski
@ 2015-09-30  9:39                 ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-30  9:39 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hi Krzysztof,

On 09/30/2015 04:26 PM, Krzysztof Kozlowski wrote:
> On 30.09.2015 17:20, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
>>> On 30.09.2015 16:19, Yakir Yang wrote:
>>>> Hi Krzysztof,
>>>>
>>>> On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
>>>>> On 22.09.2015 16:37, Yakir Yang wrote:
>>>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>>>> by the video code.
>>>>>>
>>>>>> But presumably Exynos still relies on the DT properties, so take
>>>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>>>
>>>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>>>> ---
>>>>>> Changes in v5:
>>>>>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>>>>>>    to get the backword timing values.
>>>>> Okay
>>>>>
>>>>>> Krzysztof suggest me that driver could use
>>>>>>    the "of_property_read_bool" to get backword timing values, but that interfacs
>>>>>>    would modify the original drm_display_mode timing directly (whether those
>>>>>>    properties exists or not).
>>>>> Hmm, I don't understand. You have a:
>>>>> 	struct video_info {
>>>>> 		bool h_sync_polarity;
>>>>> 		bool v_sync_polarity;
>>>>> 		bool interlaced;
>>>>> 	};
>>>>>
>>>>> so what is wrong with:
>>>>> 	dp_video_config->h_sync_polarity =
>>>>> 		of_property_read_bool(dp_node, "hsync-active-high");
>>>>>
>>>>> Is it exactly the same binding as previously?
>>>> Yes, it is the same binding as previously. But just a note that we already
>>>> mark those DT binding as deprecated.
>>>>
>>>> +-interlaced:            deprecated prop that can parsed frm drm_display_mode.
>>>> +-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
>>>> +-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
>>>>
>>>>
>>>> For now those values should come from "struct drm_display_mode",
>>>> and we already parsed them out from "drm_display_mode" before
>>>> driver provide the backward compatibility.
>>>>
>>>> Let's used the "hsync-active-high" example:
>>>>      As for now the code would like:
>>>>      static void analogix_dp_bridge_mode_set(...)
>>>>      {
>>>>          // Parsed timing value from "drm_display_mode"
>>>>          video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>>>>
>>>>          // Try to detect the deprecated property, providing
>>>>          // the backward compatibility
>>>>          of_property_read_u32(dp_node, "hsync-active-high",
>>>>                                   &video->h_sync_polarity);
>>>>
>>>>          /*
>>>>           * In this case, if "hsync-active-high" property haven't been
>>>>           * found, then the video timing "h_sync_polarity" would  keep
>>>>           * no change, keeping the parsed value from "drm_display_mode"
>>>>           */
>>>>      }
>>>>
>>>>      But if keep the "of_property_read_bool", then code would like:
>>>>      static void analogix_dp_bridge_mode_set(...)
>>>>      {
>>>>          // Parsed timing value from "drm_display_mode"
>>>>          video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>>>>
>>>>          // Try to detect the deprecated property, providing
>>>>          // the backward compatibility
>>>>          video->h_sync_polarity =
>>>>                      of_property_read_bool(dp_node, "hsync-active-high");
>>>>     
>>>>
>>>>          /*
>>>>           * In this case, if "hsync-active-high" property haven't been
>>>>           * found, then the video timing "h_sync_polarity" would just
>>>>           * modify to "false". That is the place we don't want, cause
>>>>           * it would always modify the timing value parsed from
>>>>           * "drm_display_mode"
>>>>           */
>>>>      }
>>>>
>>> OK, I see the point of overwriting values from drm_display_mode. However
>>> I think you changed the binding. I believe the of_property_read_u32()
>>> will behave differently for such DTS:
>>>
>>> exynos_dp {
>>> 	...
>>> 	hsync-active-high;
>>> }
>>>
>>> It will return -EOVERFLOW which means it would be broken now...
>> Whoops, thanks for your remind, after try that, I do see over flow error.
>> static void *of_find_property_value_of_size(const struct device_node *np,
>>                          const char *propname, u32 len)
>> {
>>          ....
>>          if (len > prop->length)
>>                  return ERR_PTR(-EOVERFLOW);
>>          ...
>> }
>>
>> So I though code should be:
>>      if (of_property_read_bool(dp_node, "hsync-active-high"))
>>          video->h_sync_polarity = true;
> Looks good.
>
>> And we can't provide full backward compatibility for this property, cause
>> the previous exynos_dp driver would set this timing value to "false" when
>> property not defined, but analogix_dp driver keep this timing value
>> corresponding to "drm_display_mode" when property not found.
> Indeed, the behaviour changes. I don't know if this is important issue...

Hmm... as I know the timing polarity would influence something like:
     - CTS test
     - HDCP function

But I though it's more likely that driver would made those functions 
failed if
hard code the timing polarity.

And I think it would be better to get timing polarity from 
"drm_display_mode".
Caused the analogix_dp driver have called the drm_add_edid_modes() that
function would parse the EDID "detailed timing" block which contained the
correct timing message that panel request.

Besides I see the exynos_fmid driver already setup the timing polarity from
"drm_display_mode", and there is no doubt that exynos dp should set the
same polarity with fmid driver (I guess, just notice that fmid is a kind 
of CTRC
driver).

That's to say parsing timing polarity dynamically would give more chances to
make those functions works.

Thanks,
- Yakir

> Best regards,
> Krzysztof
>
>
>
>
"


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-09-30  9:39                 ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-09-30  9:39 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Krzysztof,

On 09/30/2015 04:26 PM, Krzysztof Kozlowski wrote:
> On 30.09.2015 17:20, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
>>> On 30.09.2015 16:19, Yakir Yang wrote:
>>>> Hi Krzysztof,
>>>>
>>>> On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
>>>>> On 22.09.2015 16:37, Yakir Yang wrote:
>>>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>>>> by the video code.
>>>>>>
>>>>>> But presumably Exynos still relies on the DT properties, so take
>>>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>>>
>>>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>>>> ---
>>>>>> Changes in v5:
>>>>>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>>>>>>    to get the backword timing values.
>>>>> Okay
>>>>>
>>>>>> Krzysztof suggest me that driver could use
>>>>>>    the "of_property_read_bool" to get backword timing values, but that interfacs
>>>>>>    would modify the original drm_display_mode timing directly (whether those
>>>>>>    properties exists or not).
>>>>> Hmm, I don't understand. You have a:
>>>>> 	struct video_info {
>>>>> 		bool h_sync_polarity;
>>>>> 		bool v_sync_polarity;
>>>>> 		bool interlaced;
>>>>> 	};
>>>>>
>>>>> so what is wrong with:
>>>>> 	dp_video_config->h_sync_polarity =
>>>>> 		of_property_read_bool(dp_node, "hsync-active-high");
>>>>>
>>>>> Is it exactly the same binding as previously?
>>>> Yes, it is the same binding as previously. But just a note that we already
>>>> mark those DT binding as deprecated.
>>>>
>>>> +-interlaced:            deprecated prop that can parsed frm drm_display_mode.
>>>> +-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
>>>> +-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
>>>>
>>>>
>>>> For now those values should come from "struct drm_display_mode",
>>>> and we already parsed them out from "drm_display_mode" before
>>>> driver provide the backward compatibility.
>>>>
>>>> Let's used the "hsync-active-high" example:
>>>>      As for now the code would like:
>>>>      static void analogix_dp_bridge_mode_set(...)
>>>>      {
>>>>          // Parsed timing value from "drm_display_mode"
>>>>          video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>>>>
>>>>          // Try to detect the deprecated property, providing
>>>>          // the backward compatibility
>>>>          of_property_read_u32(dp_node, "hsync-active-high",
>>>>                                   &video->h_sync_polarity);
>>>>
>>>>          /*
>>>>           * In this case, if "hsync-active-high" property haven't been
>>>>           * found, then the video timing "h_sync_polarity" would  keep
>>>>           * no change, keeping the parsed value from "drm_display_mode"
>>>>           */
>>>>      }
>>>>
>>>>      But if keep the "of_property_read_bool", then code would like:
>>>>      static void analogix_dp_bridge_mode_set(...)
>>>>      {
>>>>          // Parsed timing value from "drm_display_mode"
>>>>          video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
>>>>
>>>>          // Try to detect the deprecated property, providing
>>>>          // the backward compatibility
>>>>          video->h_sync_polarity =
>>>>                      of_property_read_bool(dp_node, "hsync-active-high");
>>>>     
>>>>
>>>>          /*
>>>>           * In this case, if "hsync-active-high" property haven't been
>>>>           * found, then the video timing "h_sync_polarity" would just
>>>>           * modify to "false". That is the place we don't want, cause
>>>>           * it would always modify the timing value parsed from
>>>>           * "drm_display_mode"
>>>>           */
>>>>      }
>>>>
>>> OK, I see the point of overwriting values from drm_display_mode. However
>>> I think you changed the binding. I believe the of_property_read_u32()
>>> will behave differently for such DTS:
>>>
>>> exynos_dp {
>>> 	...
>>> 	hsync-active-high;
>>> }
>>>
>>> It will return -EOVERFLOW which means it would be broken now...
>> Whoops, thanks for your remind, after try that, I do see over flow error.
>> static void *of_find_property_value_of_size(const struct device_node *np,
>>                          const char *propname, u32 len)
>> {
>>          ....
>>          if (len > prop->length)
>>                  return ERR_PTR(-EOVERFLOW);
>>          ...
>> }
>>
>> So I though code should be:
>>      if (of_property_read_bool(dp_node, "hsync-active-high"))
>>          video->h_sync_polarity = true;
> Looks good.
>
>> And we can't provide full backward compatibility for this property, cause
>> the previous exynos_dp driver would set this timing value to "false" when
>> property not defined, but analogix_dp driver keep this timing value
>> corresponding to "drm_display_mode" when property not found.
> Indeed, the behaviour changes. I don't know if this is important issue...

Hmm... as I know the timing polarity would influence something like:
     - CTS test
     - HDCP function

But I though it's more likely that driver would made those functions 
failed if
hard code the timing polarity.

And I think it would be better to get timing polarity from 
"drm_display_mode".
Caused the analogix_dp driver have called the drm_add_edid_modes() that
function would parse the EDID "detailed timing" block which contained the
correct timing message that panel request.

Besides I see the exynos_fmid driver already setup the timing polarity from
"drm_display_mode", and there is no doubt that exynos dp should set the
same polarity with fmid driver (I guess, just notice that fmid is a kind 
of CTRC
driver).

That's to say parsing timing polarity dynamically would give more chances to
make those functions works.

Thanks,
- Yakir

> Best regards,
> Krzysztof
>
>
>
>
"

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
  2015-09-22  7:20   ` Yakir Yang
@ 2015-10-07  6:25     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-07  6:25 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Heiko Stuebner, Mark Yao,
	Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hi all,

Friendly ping.....   :)


Best regards,
- Yakir


On 09/22/2015 03:20 PM, Yakir Yang wrote:
> Hi all,
>
>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM :)
>
> This time I create this version on linux-next branch (tag is next-20150918),
> and also applied this version to Heiko github eDP branch to verify the function.
> (https://github.com/mmind/linux-rockchip/tree/tmp/edp-with-veyron)
> Glad to say my chromebook "cnm,n116bgeea2" eDP panel just lighted rightly on
> Heiko branch. And after back port this series to chromeos-3.14 tree, my rk3288
> SDK board still can light my 2K DisplayPort monitor. So this time would be okay
> on mainline kernel and chromeos-3.14 tree. ;)
>
> Due to no Exynos board in my side, so I haven't verified the eDP function on
> samsung platform, I only ensure that there are no obvious compiled error. Any
> help would be greatly appreciated. :)
>
> Thanks,
> - Yakir
>
> Changes in v5:
> - Correct the check condition of gpio_is_valid when driver try to get
>    the "hpd-gpios" DT propery. (Heiko)
> - Move the platform attach callback in the front of core driver bridge
>    attch function. Cause once platform failed at attach, core driver should
>    still failed, so no need to init connector before platform attached (Krzysztof)
> - Keep code style no changes with the previous exynos_dp_code.c in this
>    patch, and update commit message about the new export symbol (Krzysztof)
> - Gather the device type patch (v4 11/16) into this one. (Krzysztof)
> - leave out the connector registration to analogix platform driver. (Thierry)
> - Resequence this patch after analogix_dp driver have been split
>    from exynos_dp code, and rephrase reasonable commit message, and
>    remove some controversial style (Krzysztof)
>      -		analogix_dp_write_byte_to_dpcd(
>      - 				dp, DP_TEST_RESPONSE,
>      +		analogix_dp_write_byte_to_dpcd(dp,
>      +				DP_TEST_RESPONSE,
> 				DP_TEST_EDID_CHECKSUM_WRITE);
> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>    to get the backword timing values. Krzysztof suggest me that driver could use
>    the "of_property_read_bool" to get backword timing values, but that interfacs
>    would modify the original drm_display_mode timing directly (whether those
>    properties exists or not).
> - Correct the misspell in commit message. (Krzysztof)
> - Remove the empty line at the end of document, and correct the endpoint
>    numbers in the example DT node, and remove the regulator iomux setting
>    in driver code while using the pinctl in devicetree instead. (Heiko)
> - Add device type declared, cause the previous "platform device type
>    support (v4 11/16)" already merge into (v5 02/14).
> - Implement connector registration code. (Thierry)
> - Split binding doc's from driver changes. (Rob)
> - Add eDP hotplug pinctrl property. (Heiko)
> - Remove "reg" DT property, cause driver could poweron/poweroff phy via
>    the exist "grf" syscon already. And rename the example DT node from
>    "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
> - Add deivce_node at the front of driver, update phy_ops type from "static
>    struct" to "static const struct". And correct the input paramters of
>    devm_phy_create() interfaces. (Heiko)
> - Split binding doc's from driver changes. (Rob)
> - Update the rockchip,grf explain in document, and correct the clock required
>    elemets in document. (Rob & Heiko)
> - Fix compiled error (Heiko)
> - Using the connector display info message to configure eDP driver input
>    video mode, but hard code CRTC video output mode to RGBaaa.
>
> Changes in v4:
> - Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
> - Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
> - Create a separate folder for analogix code in bridge/ (Archit)
> - Update commit message more readable. (Jingoo)
> - Adjust the order from 05 to 04
> - Provide backword compatibility with samsung. (Krzysztof)
> - Split all DTS changes, and provide backward compatibility. Mark old
>    properties as deprecated but still support them. (Krzysztof)
> - Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
> - Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
>      "analogix,color-space" & "analogix,color-depth"   &
>      "analogix,link-rate"   & "analogix,lane-count"    &
>      "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
>      "vsync-active-high"    & "hsync-active-high"      & "interlaces"
> - Separate all DTS changes to a separate patch. (Krzysztof)
> - Remove some deprecated DT properties in rockchip dp document.
> - Add commit message, and remove the redundant rockchip_dp_phy_init()
>    function, move those code to probe() method. And remove driver .owner
>    number. (Kishon)
> - Seprate the link-rate and lane-count limit out with the device_type
>    flag. (Thierry)
> - Take Jingoo suggest, add commit messages.
> - Call drm_panel_prepare() in .get_modes function, ensure panel should
>    power on before driver try to read edid message.
>
> Changes in v3:
> - Move exynos's video_timing code to analogix_dp-exynos platform driver,
>    add get_modes method to struct analogix_dp_plat_data. (Thierry)
> - Rename some "samsung*" dts propery to "analogix*". (Heiko)
> - The link_rate and lane_count shouldn't config to the DT property value
>    directly, but we can take those as hardware limite. For example, RK3288
>    only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
>    like "link-rate = 0x0a" "lane-count = 4". (Thierry)
> - Dynamic parse video timing info from struct drm_display_mode and
>    struct drm_display_info. (Thierry)
> - Add devicetree binding documents. (Heiko)
> - Remove sync pol & colorimetry properies from the new analogix dp driver
>    devicetree binding. (Thierry)
> - Update the exist exynos dtsi file with the latest DP DT properies.
> - Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
>    and leave "sclk_edp" to analogix dp core driver which name to "dp",
>    and leave "pclk_edp" to rockchip dp platform driver which name to
>    "pclk". (Thierry & Heiko)
> - Add devicetree binding document. (Heiko)
> - Remove "rockchip,panel" DT property, take use of remote point to get panel
>    node. (Heiko)
> - Add the new function point dp_platdata->get_modes() init.
> - Suggest, add rockchip dp phy driver, collect the phy clocks and
>    power control. (Heiko)
> - Add "analogix,need-force-hpd" to indicate whether driver need foce
>    hpd when hpd detect failed.
> - move dp hpd detect to connector detect function.
> - Add edid modes parse support
>
> Changes in v2:
> - Keep author name list no changed (Jingoo)
> - Remove new copyright (Jingoo)
> - Fix compiled failed due to analogix_dp_device misspell
> - Improved commit message more readable, and avoid using some
>    uncommon style like bellow: (Joe Preches)
>      -  retval = exynos_dp_read_bytes_from_i2c(...
>    				  ...);
>      +  retval =
>      +  exynos_dp_read_bytes_from_i2c(......);
> - Get panel node with remote-endpoint method, and create devicetree binding
>    for driver. (Heiko)
> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>    leave those clock to rockchip dp phy driver.
> - Fix compile failed dut to phy_pd_addr variable misspell error
>
> Mark Yao (1):
>    drm: rockchip: vop: add bpc and color mode setting
>
> Yakir Yang (16):
>    drm: exynos: dp: convert to drm bridge mode
>    drm: bridge: analogix/dp: split exynos dp driver to bridge directory
>    drm: bridge: analogix/dp: fix some obvious code style
>    drm: bridge: analogix/dp: remove duplicate configuration of link rate
>      and link count
>    drm: bridge: analogix/dp: dynamic parse sync_pol & interlace &
>      dynamic_range
>    Documentation: drm/bridge: add document for analogix_dp
>    ARM: dts: exynos/dp: remove some properties that deprecated by
>      analogix_dp driver
>    drm: rockchip: dp: add rockchip platform dp driver
>    Documentation: drm/bridge: add document for analogix_dp
>    phy: Add driver for rockchip Display Port PHY
>    Documentation: phy: add document for rockchip dp phy
>    drm: bridge: analogix/dp: add some rk3288 special registers setting
>    drm: bridge: analogix/dp: add max link rate and lane count limit for
>      RK3288
>    drm: bridge: analogix/dp: try force hpd after plug in lookup failed
>    drm: bridge: analogix/dp: move hpd detect to connector detect function
>    drm: bridge: analogix/dp: add edid modes parse in get_modes method
>
>   .../devicetree/bindings/drm/bridge/analogix_dp.txt |   52 +
>   .../devicetree/bindings/phy/rockchip-dp-phy.txt    |   22 +
>   .../bindings/video/analogix_dp-rockchip.txt        |   91 ++
>   .../devicetree/bindings/video/exynos_dp.txt        |   64 +-
>   arch/arm/boot/dts/exynos5250-arndale.dts           |    2 -
>   arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 -
>   arch/arm/boot/dts/exynos5250-snow.dts              |    4 +-
>   arch/arm/boot/dts/exynos5250-spring.dts            |    4 +-
>   arch/arm/boot/dts/exynos5420-peach-pit.dts         |    4 +-
>   arch/arm/boot/dts/exynos5420-smdk5420.dts          |    2 -
>   arch/arm/boot/dts/exynos5800-peach-pi.dts          |    4 +-
>   drivers/gpu/drm/bridge/Kconfig                     |    2 +
>   drivers/gpu/drm/bridge/Makefile                    |    1 +
>   drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
>   drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1372 +++++++++++++++++++
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  286 ++++
>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1294 ++++++++++++++++++
>   .../analogix/analogix_dp_reg.h}                    |  270 ++--
>   drivers/gpu/drm/exynos/Kconfig                     |    3 +-
>   drivers/gpu/drm/exynos/Makefile                    |    2 +-
>   drivers/gpu/drm/exynos/exynos_dp.c                 |  366 +++++
>   drivers/gpu/drm/exynos/exynos_dp_core.c            | 1427 --------------------
>   drivers/gpu/drm/exynos/exynos_dp_core.h            |  281 ----
>   drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 -----------------
>   drivers/gpu/drm/rockchip/Kconfig                   |    9 +
>   drivers/gpu/drm/rockchip/Makefile                  |    1 +
>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    |  457 +++++++
>   drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c        |    2 +-
>   drivers/gpu/drm/rockchip/rockchip_drm_drv.h        |    2 +-
>   drivers/gpu/drm/rockchip/rockchip_drm_vop.c        |   32 +-
>   drivers/phy/Kconfig                                |    7 +
>   drivers/phy/Makefile                               |    1 +
>   drivers/phy/phy-rockchip-dp.c                      |  151 +++
>   include/drm/bridge/analogix_dp.h                   |   42 +
>   35 files changed, 4360 insertions(+), 3167 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>   create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>   create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>   create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
>   create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>   rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (62%)
>   create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.c
>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
>   create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>   create mode 100644 drivers/phy/phy-rockchip-dp.c
>   create mode 100644 include/drm/bridge/analogix_dp.h
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-07  6:25     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-07  6:25 UTC (permalink / raw)
  To: linux-arm-kernel

Hi all,

Friendly ping.....   :)


Best regards,
- Yakir


On 09/22/2015 03:20 PM, Yakir Yang wrote:
> Hi all,
>
>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM :)
>
> This time I create this version on linux-next branch (tag is next-20150918),
> and also applied this version to Heiko github eDP branch to verify the function.
> (https://github.com/mmind/linux-rockchip/tree/tmp/edp-with-veyron)
> Glad to say my chromebook "cnm,n116bgeea2" eDP panel just lighted rightly on
> Heiko branch. And after back port this series to chromeos-3.14 tree, my rk3288
> SDK board still can light my 2K DisplayPort monitor. So this time would be okay
> on mainline kernel and chromeos-3.14 tree. ;)
>
> Due to no Exynos board in my side, so I haven't verified the eDP function on
> samsung platform, I only ensure that there are no obvious compiled error. Any
> help would be greatly appreciated. :)
>
> Thanks,
> - Yakir
>
> Changes in v5:
> - Correct the check condition of gpio_is_valid when driver try to get
>    the "hpd-gpios" DT propery. (Heiko)
> - Move the platform attach callback in the front of core driver bridge
>    attch function. Cause once platform failed at attach, core driver should
>    still failed, so no need to init connector before platform attached (Krzysztof)
> - Keep code style no changes with the previous exynos_dp_code.c in this
>    patch, and update commit message about the new export symbol (Krzysztof)
> - Gather the device type patch (v4 11/16) into this one. (Krzysztof)
> - leave out the connector registration to analogix platform driver. (Thierry)
> - Resequence this patch after analogix_dp driver have been split
>    from exynos_dp code, and rephrase reasonable commit message, and
>    remove some controversial style (Krzysztof)
>      -		analogix_dp_write_byte_to_dpcd(
>      - 				dp, DP_TEST_RESPONSE,
>      +		analogix_dp_write_byte_to_dpcd(dp,
>      +				DP_TEST_RESPONSE,
> 				DP_TEST_EDID_CHECKSUM_WRITE);
> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>    to get the backword timing values. Krzysztof suggest me that driver could use
>    the "of_property_read_bool" to get backword timing values, but that interfacs
>    would modify the original drm_display_mode timing directly (whether those
>    properties exists or not).
> - Correct the misspell in commit message. (Krzysztof)
> - Remove the empty line at the end of document, and correct the endpoint
>    numbers in the example DT node, and remove the regulator iomux setting
>    in driver code while using the pinctl in devicetree instead. (Heiko)
> - Add device type declared, cause the previous "platform device type
>    support (v4 11/16)" already merge into (v5 02/14).
> - Implement connector registration code. (Thierry)
> - Split binding doc's from driver changes. (Rob)
> - Add eDP hotplug pinctrl property. (Heiko)
> - Remove "reg" DT property, cause driver could poweron/poweroff phy via
>    the exist "grf" syscon already. And rename the example DT node from
>    "edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
> - Add deivce_node at the front of driver, update phy_ops type from "static
>    struct" to "static const struct". And correct the input paramters of
>    devm_phy_create() interfaces. (Heiko)
> - Split binding doc's from driver changes. (Rob)
> - Update the rockchip,grf explain in document, and correct the clock required
>    elemets in document. (Rob & Heiko)
> - Fix compiled error (Heiko)
> - Using the connector display info message to configure eDP driver input
>    video mode, but hard code CRTC video output mode to RGBaaa.
>
> Changes in v4:
> - Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
> - Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
> - Create a separate folder for analogix code in bridge/ (Archit)
> - Update commit message more readable. (Jingoo)
> - Adjust the order from 05 to 04
> - Provide backword compatibility with samsung. (Krzysztof)
> - Split all DTS changes, and provide backward compatibility. Mark old
>    properties as deprecated but still support them. (Krzysztof)
> - Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
> - Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
>      "analogix,color-space" & "analogix,color-depth"   &
>      "analogix,link-rate"   & "analogix,lane-count"    &
>      "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
>      "vsync-active-high"    & "hsync-active-high"      & "interlaces"
> - Separate all DTS changes to a separate patch. (Krzysztof)
> - Remove some deprecated DT properties in rockchip dp document.
> - Add commit message, and remove the redundant rockchip_dp_phy_init()
>    function, move those code to probe() method. And remove driver .owner
>    number. (Kishon)
> - Seprate the link-rate and lane-count limit out with the device_type
>    flag. (Thierry)
> - Take Jingoo suggest, add commit messages.
> - Call drm_panel_prepare() in .get_modes function, ensure panel should
>    power on before driver try to read edid message.
>
> Changes in v3:
> - Move exynos's video_timing code to analogix_dp-exynos platform driver,
>    add get_modes method to struct analogix_dp_plat_data. (Thierry)
> - Rename some "samsung*" dts propery to "analogix*". (Heiko)
> - The link_rate and lane_count shouldn't config to the DT property value
>    directly, but we can take those as hardware limite. For example, RK3288
>    only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
>    like "link-rate = 0x0a" "lane-count = 4". (Thierry)
> - Dynamic parse video timing info from struct drm_display_mode and
>    struct drm_display_info. (Thierry)
> - Add devicetree binding documents. (Heiko)
> - Remove sync pol & colorimetry properies from the new analogix dp driver
>    devicetree binding. (Thierry)
> - Update the exist exynos dtsi file with the latest DP DT properies.
> - Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
>    and leave "sclk_edp" to analogix dp core driver which name to "dp",
>    and leave "pclk_edp" to rockchip dp platform driver which name to
>    "pclk". (Thierry & Heiko)
> - Add devicetree binding document. (Heiko)
> - Remove "rockchip,panel" DT property, take use of remote point to get panel
>    node. (Heiko)
> - Add the new function point dp_platdata->get_modes() init.
> - Suggest, add rockchip dp phy driver, collect the phy clocks and
>    power control. (Heiko)
> - Add "analogix,need-force-hpd" to indicate whether driver need foce
>    hpd when hpd detect failed.
> - move dp hpd detect to connector detect function.
> - Add edid modes parse support
>
> Changes in v2:
> - Keep author name list no changed (Jingoo)
> - Remove new copyright (Jingoo)
> - Fix compiled failed due to analogix_dp_device misspell
> - Improved commit message more readable, and avoid using some
>    uncommon style like bellow: (Joe Preches)
>      -  retval = exynos_dp_read_bytes_from_i2c(...
>    				  ...);
>      +  retval =
>      +  exynos_dp_read_bytes_from_i2c(......);
> - Get panel node with remote-endpoint method, and create devicetree binding
>    for driver. (Heiko)
> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>    leave those clock to rockchip dp phy driver.
> - Fix compile failed dut to phy_pd_addr variable misspell error
>
> Mark Yao (1):
>    drm: rockchip: vop: add bpc and color mode setting
>
> Yakir Yang (16):
>    drm: exynos: dp: convert to drm bridge mode
>    drm: bridge: analogix/dp: split exynos dp driver to bridge directory
>    drm: bridge: analogix/dp: fix some obvious code style
>    drm: bridge: analogix/dp: remove duplicate configuration of link rate
>      and link count
>    drm: bridge: analogix/dp: dynamic parse sync_pol & interlace &
>      dynamic_range
>    Documentation: drm/bridge: add document for analogix_dp
>    ARM: dts: exynos/dp: remove some properties that deprecated by
>      analogix_dp driver
>    drm: rockchip: dp: add rockchip platform dp driver
>    Documentation: drm/bridge: add document for analogix_dp
>    phy: Add driver for rockchip Display Port PHY
>    Documentation: phy: add document for rockchip dp phy
>    drm: bridge: analogix/dp: add some rk3288 special registers setting
>    drm: bridge: analogix/dp: add max link rate and lane count limit for
>      RK3288
>    drm: bridge: analogix/dp: try force hpd after plug in lookup failed
>    drm: bridge: analogix/dp: move hpd detect to connector detect function
>    drm: bridge: analogix/dp: add edid modes parse in get_modes method
>
>   .../devicetree/bindings/drm/bridge/analogix_dp.txt |   52 +
>   .../devicetree/bindings/phy/rockchip-dp-phy.txt    |   22 +
>   .../bindings/video/analogix_dp-rockchip.txt        |   91 ++
>   .../devicetree/bindings/video/exynos_dp.txt        |   64 +-
>   arch/arm/boot/dts/exynos5250-arndale.dts           |    2 -
>   arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 -
>   arch/arm/boot/dts/exynos5250-snow.dts              |    4 +-
>   arch/arm/boot/dts/exynos5250-spring.dts            |    4 +-
>   arch/arm/boot/dts/exynos5420-peach-pit.dts         |    4 +-
>   arch/arm/boot/dts/exynos5420-smdk5420.dts          |    2 -
>   arch/arm/boot/dts/exynos5800-peach-pi.dts          |    4 +-
>   drivers/gpu/drm/bridge/Kconfig                     |    2 +
>   drivers/gpu/drm/bridge/Makefile                    |    1 +
>   drivers/gpu/drm/bridge/analogix/Kconfig            |    4 +
>   drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1372 +++++++++++++++++++
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  286 ++++
>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1294 ++++++++++++++++++
>   .../analogix/analogix_dp_reg.h}                    |  270 ++--
>   drivers/gpu/drm/exynos/Kconfig                     |    3 +-
>   drivers/gpu/drm/exynos/Makefile                    |    2 +-
>   drivers/gpu/drm/exynos/exynos_dp.c                 |  366 +++++
>   drivers/gpu/drm/exynos/exynos_dp_core.c            | 1427 --------------------
>   drivers/gpu/drm/exynos/exynos_dp_core.h            |  281 ----
>   drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 -----------------
>   drivers/gpu/drm/rockchip/Kconfig                   |    9 +
>   drivers/gpu/drm/rockchip/Makefile                  |    1 +
>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    |  457 +++++++
>   drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c        |    2 +-
>   drivers/gpu/drm/rockchip/rockchip_drm_drv.h        |    2 +-
>   drivers/gpu/drm/rockchip/rockchip_drm_vop.c        |   32 +-
>   drivers/phy/Kconfig                                |    7 +
>   drivers/phy/Makefile                               |    1 +
>   drivers/phy/phy-rockchip-dp.c                      |  151 +++
>   include/drm/bridge/analogix_dp.h                   |   42 +
>   35 files changed, 4360 insertions(+), 3167 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>   create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>   create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
>   create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
>   create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>   rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (62%)
>   create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.c
>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
>   create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>   create mode 100644 drivers/phy/phy-rockchip-dp.c
>   create mode 100644 include/drm/bridge/analogix_dp.h
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
  2015-10-07  6:25     ` Yakir Yang
@ 2015-10-07  8:46       ` Javier Martinez Canillas
  -1 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-07  8:46 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hello Yakir,

On 10/07/2015 08:25 AM, Yakir Yang wrote:
> Hi all,
> 
> Friendly ping.....   :)
> 
> 
> Best regards,
> - Yakir
> 
> 

Do you have a tree that I can use to test these patches?

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-07  8:46       ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-07  8:46 UTC (permalink / raw)
  To: linux-arm-kernel

Hello Yakir,

On 10/07/2015 08:25 AM, Yakir Yang wrote:
> Hi all,
> 
> Friendly ping.....   :)
> 
> 
> Best regards,
> - Yakir
> 
> 

Do you have a tree that I can use to test these patches?

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
  2015-10-07  8:46       ` Javier Martinez Canillas
@ 2015-10-07  9:02         ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-07  9:02 UTC (permalink / raw)
  To: Javier Martinez Canillas, Inki Dae, Andrzej Hajda,
	Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, Jingoo Han,
	Heiko Stuebner, Mark Yao, Thierry Reding, joe,
	Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hi Javier,

On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>> Hi all,
>>
>> Friendly ping.....   :)
>>
>>
>> Best regards,
>> - Yakir
>>
>>
> Do you have a tree that I can use to test these patches?

Wow, thanks a lot, I do have a tree on github 
[https://github.com/yakir-Yang/linux/tree/analogix_dp],
crossing my finger, wish things works......    ;)

Thanks,
- Yakir

>
> Best regards,



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-07  9:02         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-07  9:02 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Javier,

On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>> Hi all,
>>
>> Friendly ping.....   :)
>>
>>
>> Best regards,
>> - Yakir
>>
>>
> Do you have a tree that I can use to test these patches?

Wow, thanks a lot, I do have a tree on github 
[https://github.com/yakir-Yang/linux/tree/analogix_dp],
crossing my finger, wish things works......    ;)

Thanks,
- Yakir

>
> Best regards,

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
  2015-10-07  9:02         ` Yakir Yang
@ 2015-10-07  9:26           ` Javier Martinez Canillas
  -1 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-07  9:26 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hello Yakir,

On 10/07/2015 11:02 AM, Yakir Yang wrote:
> Hi Javier,
> 
> On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
>> Hello Yakir,
>>
>> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>>> Hi all,
>>>
>>> Friendly ping.....   :)
>>>
>>>
>>> Best regards,
>>> - Yakir
>>>
>>>
>> Do you have a tree that I can use to test these patches?
> 
> Wow, thanks a lot, I do have a tree on github [https://github.com/yakir-Yang/linux/tree/analogix_dp],
> crossing my finger, wish things works......    ;)
>

I tried your analogix_dp branch on an Exynos5800 Peach Pi Chromebook
but the machine didn't boot. Unfortunately I need to do some soldering
to have a serial console on this board so don't have a kernel boot log.

I'll let you know if I can get more info about this issue.

Also, there is Kconfig recursive dependency that you may want to fix:

$ make exynos_defconfig
drivers/video/fbdev/Kconfig:5:error: recursive dependency detected!
drivers/video/fbdev/Kconfig:5: symbol FB is selected by DRM_KMS_FB_HELPER
drivers/gpu/drm/Kconfig:34: symbol DRM_KMS_FB_HELPER depends on DRM_KMS_HELPER
drivers/gpu/drm/Kconfig:28: symbol DRM_KMS_HELPER is selected by DRM_ANALOGIX_DP
drivers/gpu/drm/bridge/analogix/Kconfig:1: symbol DRM_ANALOGIX_DP is selected by DRM_EXYNOS_DP
drivers/gpu/drm/exynos/Kconfig:57: symbol DRM_EXYNOS_DP depends on DRM_EXYNOS_FIMD
drivers/gpu/drm/exynos/Kconfig:19: symbol DRM_EXYNOS_FIMD depends on FB_S3C
drivers/video/fbdev/Kconfig:2023: symbol FB_S3C depends on FB
 
> Thanks,
> - Yakir
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-07  9:26           ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-07  9:26 UTC (permalink / raw)
  To: linux-arm-kernel

Hello Yakir,

On 10/07/2015 11:02 AM, Yakir Yang wrote:
> Hi Javier,
> 
> On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
>> Hello Yakir,
>>
>> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>>> Hi all,
>>>
>>> Friendly ping.....   :)
>>>
>>>
>>> Best regards,
>>> - Yakir
>>>
>>>
>> Do you have a tree that I can use to test these patches?
> 
> Wow, thanks a lot, I do have a tree on github [https://github.com/yakir-Yang/linux/tree/analogix_dp],
> crossing my finger, wish things works......    ;)
>

I tried your analogix_dp branch on an Exynos5800 Peach Pi Chromebook
but the machine didn't boot. Unfortunately I need to do some soldering
to have a serial console on this board so don't have a kernel boot log.

I'll let you know if I can get more info about this issue.

Also, there is Kconfig recursive dependency that you may want to fix:

$ make exynos_defconfig
drivers/video/fbdev/Kconfig:5:error: recursive dependency detected!
drivers/video/fbdev/Kconfig:5: symbol FB is selected by DRM_KMS_FB_HELPER
drivers/gpu/drm/Kconfig:34: symbol DRM_KMS_FB_HELPER depends on DRM_KMS_HELPER
drivers/gpu/drm/Kconfig:28: symbol DRM_KMS_HELPER is selected by DRM_ANALOGIX_DP
drivers/gpu/drm/bridge/analogix/Kconfig:1: symbol DRM_ANALOGIX_DP is selected by DRM_EXYNOS_DP
drivers/gpu/drm/exynos/Kconfig:57: symbol DRM_EXYNOS_DP depends on DRM_EXYNOS_FIMD
drivers/gpu/drm/exynos/Kconfig:19: symbol DRM_EXYNOS_FIMD depends on FB_S3C
drivers/video/fbdev/Kconfig:2023: symbol FB_S3C depends on FB
 
> Thanks,
> - Yakir
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
  2015-10-07  9:26           ` Javier Martinez Canillas
  (?)
@ 2015-10-07 11:05           ` Yakir Yang
  2015-10-07 11:25               ` Javier Martinez Canillas
  -1 siblings, 1 reply; 370+ messages in thread
From: Yakir Yang @ 2015-10-07 11:05 UTC (permalink / raw)
  To: Javier Martinez Canillas, Inki Dae, Andrzej Hajda,
	Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, Jingoo Han,
	Heiko Stuebner, Mark Yao, Thierry Reding, joe,
	Krzysztof Kozlowski, Rob Herring
  Cc: devicetree, linux-samsung-soc, Russell King, Pawel Moll,
	Ian Campbell, linux-kernel, emil.l.velikov, dianders,
	Kishon Vijay Abraham I, linux-rockchip, Kukjin Kim, dri-devel,
	Kumar Gala, ajaynumb, robherring2, Andy Yan, Gustavo Padovan,
	linux-arm-kernel


[-- Attachment #1.1: Type: text/plain, Size: 2441 bytes --]

Hi Javier,

On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/07/2015 11:02 AM, Yakir Yang wrote:
>> Hi Javier,
>>
>> On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
>>> Hello Yakir,
>>>
>>> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>>>> Hi all,
>>>>
>>>> Friendly ping.....   :)
>>>>
>>>>
>>>> Best regards,
>>>> - Yakir
>>>>
>>>>
>>> Do you have a tree that I can use to test these patches?
>> Wow, thanks a lot, I do have a tree on github [https://github.com/yakir-Yang/linux/tree/analogix_dp],
>> crossing my finger, wish things works......    ;)
>>
> I tried your analogix_dp branch on an Exynos5800 Peach Pi Chromebook
> but the machine didn't boot. Unfortunately I need to do some soldering
> to have a serial console on this board so don't have a kernel boot log.
>
> I'll let you know if I can get more info about this issue.

Whoops, sorry for the failed, much appreciated for your works.

Besides, I thought maybe I can find a Peach Pit Chromebook in my side,
I remember that some of our guys have brought one, but previously I
thought that mainline kernel wouldn't run on Peach Pit directly.

Maybe you can email me the method the run mainline kernel on Peach
Pit, so I can debug the analogix_dp driver at the same time, that would
be great.
> Also, there is Kconfig recursive dependency that you may want to fix:
>
> $ make exynos_defconfig
> drivers/video/fbdev/Kconfig:5:error: recursive dependency detected!
> drivers/video/fbdev/Kconfig:5: symbol FB is selected by DRM_KMS_FB_HELPER
> drivers/gpu/drm/Kconfig:34: symbol DRM_KMS_FB_HELPER depends on DRM_KMS_HELPER
> drivers/gpu/drm/Kconfig:28: symbol DRM_KMS_HELPER is selected by DRM_ANALOGIX_DP
> drivers/gpu/drm/bridge/analogix/Kconfig:1: symbol DRM_ANALOGIX_DP is selected by DRM_EXYNOS_DP
> drivers/gpu/drm/exynos/Kconfig:57: symbol DRM_EXYNOS_DP depends on DRM_EXYNOS_FIMD
> drivers/gpu/drm/exynos/Kconfig:19: symbol DRM_EXYNOS_FIMD depends on FB_S3C
> drivers/video/fbdev/Kconfig:2023: symbol FB_S3C depends on FB
>   

Yeah, recursive dependency detected, guess I should remove the
"DRM_KMS_HELPER" from bridge analogix_dp Kconfig file, thanks
for your remind.

--- a/drivers/gpu/drm/bridge/analogix/Kconfig
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -1,4 +1,3 @@
  config DRM_ANALOGIX_DP
         tristate
         depends on DRM
-       select DRM_KMS_HELPER


Thanks,
- Yakir
>> Thanks,
>> - Yakir
>>
> Best regards,


[-- Attachment #1.2: Type: text/html, Size: 3886 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

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^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
  2015-10-07 11:05           ` Yakir Yang
@ 2015-10-07 11:25               ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-07 11:25 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hello Yakir,

On 10/07/2015 01:05 PM, Yakir Yang wrote:
> Hi Javier,
> 
> On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
>> Hello Yakir,
>>
>> On 10/07/2015 11:02 AM, Yakir Yang wrote:
>>> Hi Javier,
>>>
>>> On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
>>>> Hello Yakir,
>>>>
>>>> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>>>>> Hi all,
>>>>>
>>>>> Friendly ping.....   :)
>>>>>
>>>>>
>>>>> Best regards,
>>>>> - Yakir
>>>>>
>>>>>
>>>> Do you have a tree that I can use to test these patches?
>>> Wow, thanks a lot, I do have a tree on github [https://github.com/yakir-Yang/linux/tree/analogix_dp],
>>> crossing my finger, wish things works......    ;)
>>>
>> I tried your analogix_dp branch on an Exynos5800 Peach Pi Chromebook
>> but the machine didn't boot. Unfortunately I need to do some soldering
>> to have a serial console on this board so don't have a kernel boot log.
>>
>> I'll let you know if I can get more info about this issue.
> 
> Whoops, sorry for the failed, much appreciated for your works.
> 
> Besides, I thought maybe I can find a Peach Pit Chromebook in my side,
> I remember that some of our guys have brought one, but previously I
> thought that mainline kernel wouldn't run on Peach Pit directly.
> 

Great, mainline works correctly on all Exynos based Chromebooks.

> Maybe you can email me the method the run mainline kernel on Peach
> Pit, so I can debug the analogix_dp driver at the same time, that would
> be great.

I wrote a little blog post explaining how to run mainline on these boards:

http://blogs.s-osg.org/install-linux-mainline-kernel-distro-exynos-chromebooks/

That explains the simplest setup though so if you need a different one
(i.e: chain loading a non verified u-boot) or if you have any questions,
feel free to contact me in private and I can help you with the setup.

>> Also, there is Kconfig recursive dependency that you may want to fix:
>>
>> $ make exynos_defconfig
>> drivers/video/fbdev/Kconfig:5:error: recursive dependency detected!
>> drivers/video/fbdev/Kconfig:5: symbol FB is selected by DRM_KMS_FB_HELPER
>> drivers/gpu/drm/Kconfig:34: symbol DRM_KMS_FB_HELPER depends on DRM_KMS_HELPER
>> drivers/gpu/drm/Kconfig:28: symbol DRM_KMS_HELPER is selected by DRM_ANALOGIX_DP
>> drivers/gpu/drm/bridge/analogix/Kconfig:1: symbol DRM_ANALOGIX_DP is selected by DRM_EXYNOS_DP
>> drivers/gpu/drm/exynos/Kconfig:57: symbol DRM_EXYNOS_DP depends on DRM_EXYNOS_FIMD
>> drivers/gpu/drm/exynos/Kconfig:19: symbol DRM_EXYNOS_FIMD depends on FB_S3C
>> drivers/video/fbdev/Kconfig:2023: symbol FB_S3C depends on FB
>>   
> 
> Yeah, recursive dependency detected, guess I should remove the
> "DRM_KMS_HELPER" from bridge analogix_dp Kconfig file, thanks
> for your remind.
> 
> --- a/drivers/gpu/drm/bridge/analogix/Kconfig
> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
> @@ -1,4 +1,3 @@
>  config DRM_ANALOGIX_DP
>         tristate
>         depends on DRM
> -       select DRM_KMS_HELPER
> 
> 

That fixes the recursive dependency issue indeed. Thanks.

> Thanks,
> - Yakir

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-07 11:25               ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-07 11:25 UTC (permalink / raw)
  To: linux-arm-kernel

Hello Yakir,

On 10/07/2015 01:05 PM, Yakir Yang wrote:
> Hi Javier,
> 
> On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
>> Hello Yakir,
>>
>> On 10/07/2015 11:02 AM, Yakir Yang wrote:
>>> Hi Javier,
>>>
>>> On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
>>>> Hello Yakir,
>>>>
>>>> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>>>>> Hi all,
>>>>>
>>>>> Friendly ping.....   :)
>>>>>
>>>>>
>>>>> Best regards,
>>>>> - Yakir
>>>>>
>>>>>
>>>> Do you have a tree that I can use to test these patches?
>>> Wow, thanks a lot, I do have a tree on github [https://github.com/yakir-Yang/linux/tree/analogix_dp],
>>> crossing my finger, wish things works......    ;)
>>>
>> I tried your analogix_dp branch on an Exynos5800 Peach Pi Chromebook
>> but the machine didn't boot. Unfortunately I need to do some soldering
>> to have a serial console on this board so don't have a kernel boot log.
>>
>> I'll let you know if I can get more info about this issue.
> 
> Whoops, sorry for the failed, much appreciated for your works.
> 
> Besides, I thought maybe I can find a Peach Pit Chromebook in my side,
> I remember that some of our guys have brought one, but previously I
> thought that mainline kernel wouldn't run on Peach Pit directly.
> 

Great, mainline works correctly on all Exynos based Chromebooks.

> Maybe you can email me the method the run mainline kernel on Peach
> Pit, so I can debug the analogix_dp driver at the same time, that would
> be great.

I wrote a little blog post explaining how to run mainline on these boards:

http://blogs.s-osg.org/install-linux-mainline-kernel-distro-exynos-chromebooks/

That explains the simplest setup though so if you need a different one
(i.e: chain loading a non verified u-boot) or if you have any questions,
feel free to contact me in private and I can help you with the setup.

>> Also, there is Kconfig recursive dependency that you may want to fix:
>>
>> $ make exynos_defconfig
>> drivers/video/fbdev/Kconfig:5:error: recursive dependency detected!
>> drivers/video/fbdev/Kconfig:5: symbol FB is selected by DRM_KMS_FB_HELPER
>> drivers/gpu/drm/Kconfig:34: symbol DRM_KMS_FB_HELPER depends on DRM_KMS_HELPER
>> drivers/gpu/drm/Kconfig:28: symbol DRM_KMS_HELPER is selected by DRM_ANALOGIX_DP
>> drivers/gpu/drm/bridge/analogix/Kconfig:1: symbol DRM_ANALOGIX_DP is selected by DRM_EXYNOS_DP
>> drivers/gpu/drm/exynos/Kconfig:57: symbol DRM_EXYNOS_DP depends on DRM_EXYNOS_FIMD
>> drivers/gpu/drm/exynos/Kconfig:19: symbol DRM_EXYNOS_FIMD depends on FB_S3C
>> drivers/video/fbdev/Kconfig:2023: symbol FB_S3C depends on FB
>>   
> 
> Yeah, recursive dependency detected, guess I should remove the
> "DRM_KMS_HELPER" from bridge analogix_dp Kconfig file, thanks
> for your remind.
> 
> --- a/drivers/gpu/drm/bridge/analogix/Kconfig
> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
> @@ -1,4 +1,3 @@
>  config DRM_ANALOGIX_DP
>         tristate
>         depends on DRM
> -       select DRM_KMS_HELPER
> 
> 

That fixes the recursive dependency issue indeed. Thanks.

> Thanks,
> - Yakir

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
  2015-10-07 11:25               ` Javier Martinez Canillas
@ 2015-10-08  0:40                 ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-08  0:40 UTC (permalink / raw)
  To: Javier Martinez Canillas, Inki Dae, Andrzej Hajda,
	Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, Jingoo Han,
	Heiko Stuebner, Mark Yao, Thierry Reding, joe,
	Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hi Javier,

On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/07/2015 01:05 PM, Yakir Yang wrote:
>> Hi Javier,
>>
>> On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
>>> Hello Yakir,
>>>
>>> On 10/07/2015 11:02 AM, Yakir Yang wrote:
>>>> Hi Javier,
>>>>
>>>> On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
>>>>> Hello Yakir,
>>>>>
>>>>> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>>>>>> Hi all,
>>>>>>
>>>>>> Friendly ping.....   :)
>>>>>>
>>>>>>
>>>>>> Best regards,
>>>>>> - Yakir
>>>>>>
>>>>>>
>>>>> Do you have a tree that I can use to test these patches?
>>>> Wow, thanks a lot, I do have a tree on github [https://github.com/yakir-Yang/linux/tree/analogix_dp],
>>>> crossing my finger, wish things works......    ;)
>>>>
>>> I tried your analogix_dp branch on an Exynos5800 Peach Pi Chromebook
>>> but the machine didn't boot. Unfortunately I need to do some soldering
>>> to have a serial console on this board so don't have a kernel boot log.
>>>
>>> I'll let you know if I can get more info about this issue.
>> Whoops, sorry for the failed, much appreciated for your works.
>>
>> Besides, I thought maybe I can find a Peach Pit Chromebook in my side,
>> I remember that some of our guys have brought one, but previously I
>> thought that mainline kernel wouldn't run on Peach Pit directly.
>>
> Great, mainline works correctly on all Exynos based Chromebooks.
>
>> Maybe you can email me the method the run mainline kernel on Peach
>> Pit, so I can debug the analogix_dp driver at the same time, that would
>> be great.
> I wrote a little blog post explaining how to run mainline on these boards:
>
> http://blogs.s-osg.org/install-linux-mainline-kernel-distro-exynos-chromebooks/
>
> That explains the simplest setup though so if you need a different one
> (i.e: chain loading a non verified u-boot) or if you have any questions,
> feel free to contact me in private and I can help you with the setup.
>

Ah, thanks, gonna to step-by-step.

- Yakir

>>> Also, there is Kconfig recursive dependency that you may want to fix:
>>>
>>> $ make exynos_defconfig
>>> drivers/video/fbdev/Kconfig:5:error: recursive dependency detected!
>>> drivers/video/fbdev/Kconfig:5: symbol FB is selected by DRM_KMS_FB_HELPER
>>> drivers/gpu/drm/Kconfig:34: symbol DRM_KMS_FB_HELPER depends on DRM_KMS_HELPER
>>> drivers/gpu/drm/Kconfig:28: symbol DRM_KMS_HELPER is selected by DRM_ANALOGIX_DP
>>> drivers/gpu/drm/bridge/analogix/Kconfig:1: symbol DRM_ANALOGIX_DP is selected by DRM_EXYNOS_DP
>>> drivers/gpu/drm/exynos/Kconfig:57: symbol DRM_EXYNOS_DP depends on DRM_EXYNOS_FIMD
>>> drivers/gpu/drm/exynos/Kconfig:19: symbol DRM_EXYNOS_FIMD depends on FB_S3C
>>> drivers/video/fbdev/Kconfig:2023: symbol FB_S3C depends on FB
>>>    
>> Yeah, recursive dependency detected, guess I should remove the
>> "DRM_KMS_HELPER" from bridge analogix_dp Kconfig file, thanks
>> for your remind.
>>
>> --- a/drivers/gpu/drm/bridge/analogix/Kconfig
>> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
>> @@ -1,4 +1,3 @@
>>   config DRM_ANALOGIX_DP
>>          tristate
>>          depends on DRM
>> -       select DRM_KMS_HELPER
>>
>>
> That fixes the recursive dependency issue indeed. Thanks.
>
>> Thanks,
>> - Yakir
> Best regards,



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-08  0:40                 ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-08  0:40 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Javier,

On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/07/2015 01:05 PM, Yakir Yang wrote:
>> Hi Javier,
>>
>> On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
>>> Hello Yakir,
>>>
>>> On 10/07/2015 11:02 AM, Yakir Yang wrote:
>>>> Hi Javier,
>>>>
>>>> On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
>>>>> Hello Yakir,
>>>>>
>>>>> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>>>>>> Hi all,
>>>>>>
>>>>>> Friendly ping.....   :)
>>>>>>
>>>>>>
>>>>>> Best regards,
>>>>>> - Yakir
>>>>>>
>>>>>>
>>>>> Do you have a tree that I can use to test these patches?
>>>> Wow, thanks a lot, I do have a tree on github [https://github.com/yakir-Yang/linux/tree/analogix_dp],
>>>> crossing my finger, wish things works......    ;)
>>>>
>>> I tried your analogix_dp branch on an Exynos5800 Peach Pi Chromebook
>>> but the machine didn't boot. Unfortunately I need to do some soldering
>>> to have a serial console on this board so don't have a kernel boot log.
>>>
>>> I'll let you know if I can get more info about this issue.
>> Whoops, sorry for the failed, much appreciated for your works.
>>
>> Besides, I thought maybe I can find a Peach Pit Chromebook in my side,
>> I remember that some of our guys have brought one, but previously I
>> thought that mainline kernel wouldn't run on Peach Pit directly.
>>
> Great, mainline works correctly on all Exynos based Chromebooks.
>
>> Maybe you can email me the method the run mainline kernel on Peach
>> Pit, so I can debug the analogix_dp driver at the same time, that would
>> be great.
> I wrote a little blog post explaining how to run mainline on these boards:
>
> http://blogs.s-osg.org/install-linux-mainline-kernel-distro-exynos-chromebooks/
>
> That explains the simplest setup though so if you need a different one
> (i.e: chain loading a non verified u-boot) or if you have any questions,
> feel free to contact me in private and I can help you with the setup.
>

Ah, thanks, gonna to step-by-step.

- Yakir

>>> Also, there is Kconfig recursive dependency that you may want to fix:
>>>
>>> $ make exynos_defconfig
>>> drivers/video/fbdev/Kconfig:5:error: recursive dependency detected!
>>> drivers/video/fbdev/Kconfig:5: symbol FB is selected by DRM_KMS_FB_HELPER
>>> drivers/gpu/drm/Kconfig:34: symbol DRM_KMS_FB_HELPER depends on DRM_KMS_HELPER
>>> drivers/gpu/drm/Kconfig:28: symbol DRM_KMS_HELPER is selected by DRM_ANALOGIX_DP
>>> drivers/gpu/drm/bridge/analogix/Kconfig:1: symbol DRM_ANALOGIX_DP is selected by DRM_EXYNOS_DP
>>> drivers/gpu/drm/exynos/Kconfig:57: symbol DRM_EXYNOS_DP depends on DRM_EXYNOS_FIMD
>>> drivers/gpu/drm/exynos/Kconfig:19: symbol DRM_EXYNOS_FIMD depends on FB_S3C
>>> drivers/video/fbdev/Kconfig:2023: symbol FB_S3C depends on FB
>>>    
>> Yeah, recursive dependency detected, guess I should remove the
>> "DRM_KMS_HELPER" from bridge analogix_dp Kconfig file, thanks
>> for your remind.
>>
>> --- a/drivers/gpu/drm/bridge/analogix/Kconfig
>> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
>> @@ -1,4 +1,3 @@
>>   config DRM_ANALOGIX_DP
>>          tristate
>>          depends on DRM
>> -       select DRM_KMS_HELPER
>>
>>
> That fixes the recursive dependency issue indeed. Thanks.
>
>> Thanks,
>> - Yakir
> Best regards,

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-10 14:31                   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 14:31 UTC (permalink / raw)
  To: Javier Martinez Canillas, Inki Dae, Andrzej Hajda,
	Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, Jingoo Han,
	Heiko Stuebner, Mark Yao, Thierry Reding, joe,
	Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hi Javier,

On 10/08/2015 08:40 AM, Yakir Yang wrote:
> On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
>> On 10/07/2015 01:05 PM, Yakir Yang wrote:
>>> On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
>>>> On 10/07/2015 11:02 AM, Yakir Yang wrote:
>>>>> On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
>>>>>> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>>>>>>> Hi all,
>>>>>>>
>>>>>>> Friendly ping.....   :)
>>>>>>>
>>>>>>>
>>>>>>> Best regards,
>>>>>>> - Yakir
>>>>>>>
>>>>>>>
>>>>>> Do you have a tree that I can use to test these patches?
>>>>> Wow, thanks a lot, I do have a tree on github 
>>>>> [https://github.com/yakir-Yang/linux/tree/analogix_dp],
>>>>> crossing my finger, wish things works......    ;)
>>>>>
>>>> I tried your analogix_dp branch on an Exynos5800 Peach Pi Chromebook
>>>> but the machine didn't boot. Unfortunately I need to do some soldering
>>>> to have a serial console on this board so don't have a kernel boot 
>>>> log.
>>>>
>>>> I'll let you know if I can get more info about this issue.
>>> Whoops, sorry for the failed, much appreciated for your works.
>>>
>>> Besides, I thought maybe I can find a Peach Pit Chromebook in my side,
>>> I remember that some of our guys have brought one, but previously I
>>> thought that mainline kernel wouldn't run on Peach Pit directly.
>>>
>> Great, mainline works correctly on all Exynos based Chromebooks.
>>
>>> Maybe you can email me the method the run mainline kernel on Peach
>>> Pit, so I can debug the analogix_dp driver at the same time, that would
>>> be great.
>> I wrote a little blog post explaining how to run mainline on these 
>> boards:
>>
>> http://blogs.s-osg.org/install-linux-mainline-kernel-distro-exynos-chromebooks/ 
>>
>>
>> That explains the simplest setup though so if you need a different one
>> (i.e: chain loading a non verified u-boot) or if you have any questions,
>> feel free to contact me in private and I can help you with the setup.
>>
>
> Ah, thanks, gonna to step-by-step.

Thanks for your great material, although I meet some problems in the 
step-by-step
process, and failed at this way to setup mainline kernel environment on 
Exynos chromebooks.

But i do find another way to install mainline kernel to Exynos Chromebook:
1. Install any ChromeOS image into a USB media device (like dd tools)
2. "enable_dev_usb_boot" on Exynos chromebooks which would allowed boot 
from USB.
3. Flash the mainline kernel into the KERNEL-A and KERNEL-B partitions 
on host PC.
4. Insert USB device into Exynos chromebooks, and press CTRL+U, boot 
into USB OS.

And it's better to enable pstore function on mainline kernel, so we can 
analysis the last log when
the mainline kernel crashed. After enable PSTORE_RAM in .config, we 
still need add ramoops node
into file, like:
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -750,6 +750,15 @@
                 iommu = <&sysmmu_gsc3>;
         };

+       ramoops: ramoops {
+               compatible = "ramoops";
+               name = "ramoops";
+               reg = <0x41f00000 0x100000>;
+               record-size = <0x20000>;
+               dump-oops;
+               status = "okay";
+       };
+
         hdmi: hdmi {
                 compatible = "samsung,exynos4212-hdmi";
                 reg = <0x14530000 0x70000>;


Aha, I have tested this series on two Exynos Chromebooks that I 
borrowed(Snow and Peach Pit)
with previously method (actually I believed it's a common method without 
broken the original
ChromeOS image).

And I do find the crash place that make you failed at this series, here 
is the diff changes:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 5f8fc11..bcbc009 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1169,6 +1169,7 @@ static int analogix_dp_create_bridge(struct 
drm_device *drm_dev,

         dp->bridge = bridge;

+       dp->encoder->bridge = bridge;
         bridge->driver_private = dp;
         bridge->encoder = dp->encoder;
         bridge->funcs = &analogix_dp_bridge_funcs;
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -151,7 +151,7 @@
         samsung,color-depth = <1>;
         samsung,link-rate = <0x06>;
         samsung,lane-count = <2>;
-       hpd-gpio = <&gpx2 6 0>;
+       hpd-gpios = <&gpx2 6 0>;

         ports {
                 port@0 {


Anyway I'm going to send the v6 series, thanks for your good idea.

- Yakir

>
> - Yakir
>
>>>> Also, there is Kconfig recursive dependency that you may want to fix:
>>>>
>>>> $ make exynos_defconfig
>>>> drivers/video/fbdev/Kconfig:5:error: recursive dependency detected!
>>>> drivers/video/fbdev/Kconfig:5: symbol FB is selected by 
>>>> DRM_KMS_FB_HELPER
>>>> drivers/gpu/drm/Kconfig:34: symbol DRM_KMS_FB_HELPER depends on 
>>>> DRM_KMS_HELPER
>>>> drivers/gpu/drm/Kconfig:28: symbol DRM_KMS_HELPER is selected by 
>>>> DRM_ANALOGIX_DP
>>>> drivers/gpu/drm/bridge/analogix/Kconfig:1: symbol DRM_ANALOGIX_DP 
>>>> is selected by DRM_EXYNOS_DP
>>>> drivers/gpu/drm/exynos/Kconfig:57: symbol DRM_EXYNOS_DP depends on 
>>>> DRM_EXYNOS_FIMD
>>>> drivers/gpu/drm/exynos/Kconfig:19: symbol DRM_EXYNOS_FIMD depends 
>>>> on FB_S3C
>>>> drivers/video/fbdev/Kconfig:2023: symbol FB_S3C depends on FB
>>> Yeah, recursive dependency detected, guess I should remove the
>>> "DRM_KMS_HELPER" from bridge analogix_dp Kconfig file, thanks
>>> for your remind.
>>>
>>> --- a/drivers/gpu/drm/bridge/analogix/Kconfig
>>> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
>>> @@ -1,4 +1,3 @@
>>>   config DRM_ANALOGIX_DP
>>>          tristate
>>>          depends on DRM
>>> -       select DRM_KMS_HELPER
>>>
>>>
>> That fixes the recursive dependency issue indeed. Thanks.
>>
>>> Thanks,
>>> - Yakir
>> Best regards,
>



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-10 14:31                   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 14:31 UTC (permalink / raw)
  To: Javier Martinez Canillas, Inki Dae, Andrzej Hajda,
	Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, Jingoo Han,
	Heiko Stuebner, Mark Yao, Thierry Reding,
	joe-6d6DIl74uiNBDgjK7y7TUQ, Krzysztof Kozlowski, Rob Herring
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Russell King,
	Pawel Moll, Ian Campbell, David Airlie,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w,
	dianders-F7+t8E8rja9g9hUCZPvPmw, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	Sean Paul, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	Kumar Gala, ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan, Gustavo Padovan,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Hi Javier,

On 10/08/2015 08:40 AM, Yakir Yang wrote:
> On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
>> On 10/07/2015 01:05 PM, Yakir Yang wrote:
>>> On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
>>>> On 10/07/2015 11:02 AM, Yakir Yang wrote:
>>>>> On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
>>>>>> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>>>>>>> Hi all,
>>>>>>>
>>>>>>> Friendly ping.....   :)
>>>>>>>
>>>>>>>
>>>>>>> Best regards,
>>>>>>> - Yakir
>>>>>>>
>>>>>>>
>>>>>> Do you have a tree that I can use to test these patches?
>>>>> Wow, thanks a lot, I do have a tree on github 
>>>>> [https://github.com/yakir-Yang/linux/tree/analogix_dp],
>>>>> crossing my finger, wish things works......    ;)
>>>>>
>>>> I tried your analogix_dp branch on an Exynos5800 Peach Pi Chromebook
>>>> but the machine didn't boot. Unfortunately I need to do some soldering
>>>> to have a serial console on this board so don't have a kernel boot 
>>>> log.
>>>>
>>>> I'll let you know if I can get more info about this issue.
>>> Whoops, sorry for the failed, much appreciated for your works.
>>>
>>> Besides, I thought maybe I can find a Peach Pit Chromebook in my side,
>>> I remember that some of our guys have brought one, but previously I
>>> thought that mainline kernel wouldn't run on Peach Pit directly.
>>>
>> Great, mainline works correctly on all Exynos based Chromebooks.
>>
>>> Maybe you can email me the method the run mainline kernel on Peach
>>> Pit, so I can debug the analogix_dp driver at the same time, that would
>>> be great.
>> I wrote a little blog post explaining how to run mainline on these 
>> boards:
>>
>> http://blogs.s-osg.org/install-linux-mainline-kernel-distro-exynos-chromebooks/ 
>>
>>
>> That explains the simplest setup though so if you need a different one
>> (i.e: chain loading a non verified u-boot) or if you have any questions,
>> feel free to contact me in private and I can help you with the setup.
>>
>
> Ah, thanks, gonna to step-by-step.

Thanks for your great material, although I meet some problems in the 
step-by-step
process, and failed at this way to setup mainline kernel environment on 
Exynos chromebooks.

But i do find another way to install mainline kernel to Exynos Chromebook:
1. Install any ChromeOS image into a USB media device (like dd tools)
2. "enable_dev_usb_boot" on Exynos chromebooks which would allowed boot 
from USB.
3. Flash the mainline kernel into the KERNEL-A and KERNEL-B partitions 
on host PC.
4. Insert USB device into Exynos chromebooks, and press CTRL+U, boot 
into USB OS.

And it's better to enable pstore function on mainline kernel, so we can 
analysis the last log when
the mainline kernel crashed. After enable PSTORE_RAM in .config, we 
still need add ramoops node
into file, like:
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -750,6 +750,15 @@
                 iommu = <&sysmmu_gsc3>;
         };

+       ramoops: ramoops {
+               compatible = "ramoops";
+               name = "ramoops";
+               reg = <0x41f00000 0x100000>;
+               record-size = <0x20000>;
+               dump-oops;
+               status = "okay";
+       };
+
         hdmi: hdmi {
                 compatible = "samsung,exynos4212-hdmi";
                 reg = <0x14530000 0x70000>;


Aha, I have tested this series on two Exynos Chromebooks that I 
borrowed(Snow and Peach Pit)
with previously method (actually I believed it's a common method without 
broken the original
ChromeOS image).

And I do find the crash place that make you failed at this series, here 
is the diff changes:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 5f8fc11..bcbc009 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1169,6 +1169,7 @@ static int analogix_dp_create_bridge(struct 
drm_device *drm_dev,

         dp->bridge = bridge;

+       dp->encoder->bridge = bridge;
         bridge->driver_private = dp;
         bridge->encoder = dp->encoder;
         bridge->funcs = &analogix_dp_bridge_funcs;
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -151,7 +151,7 @@
         samsung,color-depth = <1>;
         samsung,link-rate = <0x06>;
         samsung,lane-count = <2>;
-       hpd-gpio = <&gpx2 6 0>;
+       hpd-gpios = <&gpx2 6 0>;

         ports {
                 port@0 {


Anyway I'm going to send the v6 series, thanks for your good idea.

- Yakir

>
> - Yakir
>
>>>> Also, there is Kconfig recursive dependency that you may want to fix:
>>>>
>>>> $ make exynos_defconfig
>>>> drivers/video/fbdev/Kconfig:5:error: recursive dependency detected!
>>>> drivers/video/fbdev/Kconfig:5: symbol FB is selected by 
>>>> DRM_KMS_FB_HELPER
>>>> drivers/gpu/drm/Kconfig:34: symbol DRM_KMS_FB_HELPER depends on 
>>>> DRM_KMS_HELPER
>>>> drivers/gpu/drm/Kconfig:28: symbol DRM_KMS_HELPER is selected by 
>>>> DRM_ANALOGIX_DP
>>>> drivers/gpu/drm/bridge/analogix/Kconfig:1: symbol DRM_ANALOGIX_DP 
>>>> is selected by DRM_EXYNOS_DP
>>>> drivers/gpu/drm/exynos/Kconfig:57: symbol DRM_EXYNOS_DP depends on 
>>>> DRM_EXYNOS_FIMD
>>>> drivers/gpu/drm/exynos/Kconfig:19: symbol DRM_EXYNOS_FIMD depends 
>>>> on FB_S3C
>>>> drivers/video/fbdev/Kconfig:2023: symbol FB_S3C depends on FB
>>> Yeah, recursive dependency detected, guess I should remove the
>>> "DRM_KMS_HELPER" from bridge analogix_dp Kconfig file, thanks
>>> for your remind.
>>>
>>> --- a/drivers/gpu/drm/bridge/analogix/Kconfig
>>> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
>>> @@ -1,4 +1,3 @@
>>>   config DRM_ANALOGIX_DP
>>>          tristate
>>>          depends on DRM
>>> -       select DRM_KMS_HELPER
>>>
>>>
>> That fixes the recursive dependency issue indeed. Thanks.
>>
>>> Thanks,
>>> - Yakir
>> Best regards,
>

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-10 14:31                   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 14:31 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Javier,

On 10/08/2015 08:40 AM, Yakir Yang wrote:
> On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
>> On 10/07/2015 01:05 PM, Yakir Yang wrote:
>>> On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
>>>> On 10/07/2015 11:02 AM, Yakir Yang wrote:
>>>>> On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
>>>>>> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>>>>>>> Hi all,
>>>>>>>
>>>>>>> Friendly ping.....   :)
>>>>>>>
>>>>>>>
>>>>>>> Best regards,
>>>>>>> - Yakir
>>>>>>>
>>>>>>>
>>>>>> Do you have a tree that I can use to test these patches?
>>>>> Wow, thanks a lot, I do have a tree on github 
>>>>> [https://github.com/yakir-Yang/linux/tree/analogix_dp],
>>>>> crossing my finger, wish things works......    ;)
>>>>>
>>>> I tried your analogix_dp branch on an Exynos5800 Peach Pi Chromebook
>>>> but the machine didn't boot. Unfortunately I need to do some soldering
>>>> to have a serial console on this board so don't have a kernel boot 
>>>> log.
>>>>
>>>> I'll let you know if I can get more info about this issue.
>>> Whoops, sorry for the failed, much appreciated for your works.
>>>
>>> Besides, I thought maybe I can find a Peach Pit Chromebook in my side,
>>> I remember that some of our guys have brought one, but previously I
>>> thought that mainline kernel wouldn't run on Peach Pit directly.
>>>
>> Great, mainline works correctly on all Exynos based Chromebooks.
>>
>>> Maybe you can email me the method the run mainline kernel on Peach
>>> Pit, so I can debug the analogix_dp driver at the same time, that would
>>> be great.
>> I wrote a little blog post explaining how to run mainline on these 
>> boards:
>>
>> http://blogs.s-osg.org/install-linux-mainline-kernel-distro-exynos-chromebooks/ 
>>
>>
>> That explains the simplest setup though so if you need a different one
>> (i.e: chain loading a non verified u-boot) or if you have any questions,
>> feel free to contact me in private and I can help you with the setup.
>>
>
> Ah, thanks, gonna to step-by-step.

Thanks for your great material, although I meet some problems in the 
step-by-step
process, and failed at this way to setup mainline kernel environment on 
Exynos chromebooks.

But i do find another way to install mainline kernel to Exynos Chromebook:
1. Install any ChromeOS image into a USB media device (like dd tools)
2. "enable_dev_usb_boot" on Exynos chromebooks which would allowed boot 
from USB.
3. Flash the mainline kernel into the KERNEL-A and KERNEL-B partitions 
on host PC.
4. Insert USB device into Exynos chromebooks, and press CTRL+U, boot 
into USB OS.

And it's better to enable pstore function on mainline kernel, so we can 
analysis the last log when
the mainline kernel crashed. After enable PSTORE_RAM in .config, we 
still need add ramoops node
into file, like:
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -750,6 +750,15 @@
                 iommu = <&sysmmu_gsc3>;
         };

+       ramoops: ramoops {
+               compatible = "ramoops";
+               name = "ramoops";
+               reg = <0x41f00000 0x100000>;
+               record-size = <0x20000>;
+               dump-oops;
+               status = "okay";
+       };
+
         hdmi: hdmi {
                 compatible = "samsung,exynos4212-hdmi";
                 reg = <0x14530000 0x70000>;


Aha, I have tested this series on two Exynos Chromebooks that I 
borrowed(Snow and Peach Pit)
with previously method (actually I believed it's a common method without 
broken the original
ChromeOS image).

And I do find the crash place that make you failed at this series, here 
is the diff changes:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 5f8fc11..bcbc009 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1169,6 +1169,7 @@ static int analogix_dp_create_bridge(struct 
drm_device *drm_dev,

         dp->bridge = bridge;

+       dp->encoder->bridge = bridge;
         bridge->driver_private = dp;
         bridge->encoder = dp->encoder;
         bridge->funcs = &analogix_dp_bridge_funcs;
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -151,7 +151,7 @@
         samsung,color-depth = <1>;
         samsung,link-rate = <0x06>;
         samsung,lane-count = <2>;
-       hpd-gpio = <&gpx2 6 0>;
+       hpd-gpios = <&gpx2 6 0>;

         ports {
                 port at 0 {


Anyway I'm going to send the v6 series, thanks for your good idea.

- Yakir

>
> - Yakir
>
>>>> Also, there is Kconfig recursive dependency that you may want to fix:
>>>>
>>>> $ make exynos_defconfig
>>>> drivers/video/fbdev/Kconfig:5:error: recursive dependency detected!
>>>> drivers/video/fbdev/Kconfig:5: symbol FB is selected by 
>>>> DRM_KMS_FB_HELPER
>>>> drivers/gpu/drm/Kconfig:34: symbol DRM_KMS_FB_HELPER depends on 
>>>> DRM_KMS_HELPER
>>>> drivers/gpu/drm/Kconfig:28: symbol DRM_KMS_HELPER is selected by 
>>>> DRM_ANALOGIX_DP
>>>> drivers/gpu/drm/bridge/analogix/Kconfig:1: symbol DRM_ANALOGIX_DP 
>>>> is selected by DRM_EXYNOS_DP
>>>> drivers/gpu/drm/exynos/Kconfig:57: symbol DRM_EXYNOS_DP depends on 
>>>> DRM_EXYNOS_FIMD
>>>> drivers/gpu/drm/exynos/Kconfig:19: symbol DRM_EXYNOS_FIMD depends 
>>>> on FB_S3C
>>>> drivers/video/fbdev/Kconfig:2023: symbol FB_S3C depends on FB
>>> Yeah, recursive dependency detected, guess I should remove the
>>> "DRM_KMS_HELPER" from bridge analogix_dp Kconfig file, thanks
>>> for your remind.
>>>
>>> --- a/drivers/gpu/drm/bridge/analogix/Kconfig
>>> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
>>> @@ -1,4 +1,3 @@
>>>   config DRM_ANALOGIX_DP
>>>          tristate
>>>          depends on DRM
>>> -       select DRM_KMS_HELPER
>>>
>>>
>> That fixes the recursive dependency issue indeed. Thanks.
>>
>>> Thanks,
>>> - Yakir
>> Best regards,
>

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 0/17] Add Analogix Core Display Port Driver
  2015-09-01  5:46 ` Yakir Yang
@ 2015-10-10 15:35   ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:35 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel


Hi all,

   The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
controller, so I decide to name dp core driver with "analogix" which I
find in rk3288 eDP TRM :)

But  there are still three light registers setting differents bewteen
exynos and rk3288.
1. RK3288 have five special pll resigters which not indicata in exynos
   dp controller.
2. The address of DP_PHY_PD(dp phy power manager register) are different
   between rk3288 and exynos.
3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
   register).

This series have been well tested on Rockchip platform with eDP panel
on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
to Javier@Samsung help me to find a way to install mainline kernel to
Samsung Exynos Chromebooks, so this series also have been tested on Samsung
Snow and Peach Pit Chromebooks which borrowed from my friends.

Besides, This version was build on linux-next branch (tag next-20150918), and
the above test experiments also base on that tag. But I know the latest tag is
next-20151009, so i do rebase this series again on next-20151009, there were
little conflicts(exynos_dp removed the suspend/resume).

But after I retest this series on next-20151009, I saw kernel crashed in mmc
driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
module(after all I boot with USB device), and I can see eDP light up normally
in startup stage, but kernel keep crashed when it try to mount the filesystem.
I thought this isn't related to dp driver directly, so i choice not to debug
more depth.

That's to say if someone want to test this series, I suggest you applied this
series on tag-20150918, just need to fix some light conflicts with the 01 & 02
patches (or just email me, I can send you directly).

Thanks,
- Yakir

Changes in v6:
- Fix the wrong code in previous series, and test on Samsung snow Chromebook
  successfully, here are the detail changes:
=============>
-       if (!dp->panel && !dp->bridge) {
+       if (!dp->panel && !dp->ptn_bridge) {
                ret = exynos_dp_dt_parse_panel(dp);
                if (ret)
=============>
+       encoder->bridge = bridge;
	bridge->driver_private = dp;
        bridge->encoder = encoder;
        bridge->funcs = &exynos_dp_bridge_funcs;
        ret = drm_bridge_attach(drm_dev, bridge);
- Fix the Kconfig recursive dependency (Javier)
- Fix Peach Pit hpd property name error:
-       hpd-gpio = <&gpx2 6 0>;
+       hpd-gpios = <&gpx2 6 0>;

Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
  the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
  attch function. Cause once platform failed at attach, core driver should
  still failed, so no need to init connector before platform attached (Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
  patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)
- Resequence this patch after analogix_dp driver have been split
  from exynos_dp code, and rephrase reasonable commit message, and
  remove some controversial style (Krzysztof)
    -		analogix_dp_write_byte_to_dpcd(
    - 				dp, DP_TEST_RESPONSE,
    +		analogix_dp_write_byte_to_dpcd(dp,
    +				DP_TEST_RESPONSE,
				DP_TEST_EDID_CHECKSUM_WRITE);
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).
- Correct the misspell in commit message. (Krzysztof)
- Remove the empty line at the end of document, and correct the endpoint
  numbers in the example DT node, and remove the regulator iomux setting
  in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
  support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
  the exist "grf" syscon already. And rename the example DT node from
  "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
  struct" to "static const struct". And correct the input paramters of
  devm_phy_create() interfaces. (Heiko)
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
  elemets in document. (Rob & Heiko)
- Fix compiled error (Heiko)
- Using the connector display info message to configure eDP driver input
  video mode, but hard code CRTC video output mode to RGBaaa.

Changes in v4:
- Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
- Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
- Create a separate folder for analogix code in bridge/ (Archit)
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
- Provide backword compatibility with samsung. (Krzysztof)
- Split all DTS changes, and provide backward compatibility. Mark old
  properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"
- Separate all DTS changes to a separate patch. (Krzysztof)
- Remove some deprecated DT properties in rockchip dp document.
- Add commit message, and remove the redundant rockchip_dp_phy_init()
  function, move those code to probe() method. And remove driver .owner
  number. (Kishon)
- Seprate the link-rate and lane-count limit out with the device_type
  flag. (Thierry)
- Take Jingoo suggest, add commit messages.
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Move exynos's video_timing code to analogix_dp-exynos platform driver,
  add get_modes method to struct analogix_dp_plat_data. (Thierry)
- Rename some "samsung*" dts propery to "analogix*". (Heiko)
- The link_rate and lane_count shouldn't config to the DT property value
  directly, but we can take those as hardware limite. For example, RK3288
  only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
  like "link-rate = 0x0a" "lane-count = 4". (Thierry)
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
  devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
  and leave "sclk_edp" to analogix dp core driver which name to "dp",
  and leave "pclk_edp" to rockchip dp platform driver which name to
  "pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
  node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.
- Suggest, add rockchip dp phy driver, collect the phy clocks and
  power control. (Heiko)
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.
- move dp hpd detect to connector detect function.
- Add edid modes parse support

Changes in v2:
- Keep author name list no changed (Jingoo)
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
  uncommon style like bellow: (Joe Preches)
    -  retval = exynos_dp_read_bytes_from_i2c(...
  				  ...);
    +  retval =
    +  exynos_dp_read_bytes_from_i2c(......);
- Get panel node with remote-endpoint method, and create devicetree binding
  for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.
- Fix compile failed dut to phy_pd_addr variable misspell error

Mark Yao (1):
  drm: rockchip: vop: add bpc and color mode setting

Yakir Yang (16):
  drm: exynos: dp: convert to drm bridge mode
  drm: bridge: analogix/dp: split exynos dp driver to bridge directory
  drm: bridge: analogix/dp: fix some obvious code style
  drm: bridge: analogix/dp: remove duplicate configuration of link rate
    and link count
  drm: bridge: analogix/dp: dynamic parse sync_pol & interlace &
    dynamic_range
  Documentation: drm/bridge: add document for analogix_dp
  ARM: dts: exynos/dp: remove some properties that deprecated by
    analogix_dp driver
  drm: rockchip: dp: add rockchip platform dp driver
  Documentation: drm/bridge: add document for analogix_dp
  phy: Add driver for rockchip Display Port PHY
  Documentation: phy: add document for rockchip dp phy
  drm: bridge: analogix/dp: add some rk3288 special registers setting
  drm: bridge: analogix/dp: add max link rate and lane count limit for
    RK3288
  drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  drm: bridge: analogix/dp: move hpd detect to connector detect function
  drm: bridge: analogix/dp: add edid modes parse in get_modes method

 .../devicetree/bindings/drm/bridge/analogix_dp.txt |   52 +
 .../devicetree/bindings/phy/rockchip-dp-phy.txt    |   22 +
 .../bindings/video/analogix_dp-rockchip.txt        |   91 ++
 .../devicetree/bindings/video/exynos_dp.txt        |   64 +-
 arch/arm/boot/dts/exynos5250-arndale.dts           |    2 -
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 -
 arch/arm/boot/dts/exynos5250-snow-common.dtsi      |    4 +-
 arch/arm/boot/dts/exynos5250-spring.dts            |    4 +-
 arch/arm/boot/dts/exynos5420-peach-pit.dts         |    4 +-
 arch/arm/boot/dts/exynos5420-smdk5420.dts          |    2 -
 arch/arm/boot/dts/exynos5800-peach-pi.dts          |    4 +-
 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    3 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1373 +++++++++++++++++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  286 ++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1294 ++++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  270 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  349 +++++
 drivers/gpu/drm/exynos/exynos_dp_core.c            | 1404 --------------------
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  281 ----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 ------------------
 drivers/gpu/drm/rockchip/Kconfig                   |    9 +
 drivers/gpu/drm/rockchip/Makefile                  |    1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    |  457 +++++++
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c        |    2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h        |    2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c        |   32 +-
 drivers/phy/Kconfig                                |    7 +
 drivers/phy/Makefile                               |    1 +
 drivers/phy/phy-rockchip-dp.c                      |  151 +++
 include/drm/bridge/analogix_dp.h                   |   42 +
 35 files changed, 4343 insertions(+), 3144 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (62%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 create mode 100644 drivers/phy/phy-rockchip-dp.c
 create mode 100644 include/drm/bridge/analogix_dp.h

-- 
1.9.1



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 0/17] Add Analogix Core Display Port Driver
@ 2015-10-10 15:35   ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:35 UTC (permalink / raw)
  To: linux-arm-kernel


Hi all,

   The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
controller, so I decide to name dp core driver with "analogix" which I
find in rk3288 eDP TRM :)

But  there are still three light registers setting differents bewteen
exynos and rk3288.
1. RK3288 have five special pll resigters which not indicata in exynos
   dp controller.
2. The address of DP_PHY_PD(dp phy power manager register) are different
   between rk3288 and exynos.
3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
   register).

This series have been well tested on Rockchip platform with eDP panel
on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
to Javier at Samsung help me to find a way to install mainline kernel to
Samsung Exynos Chromebooks, so this series also have been tested on Samsung
Snow and Peach Pit Chromebooks which borrowed from my friends.

Besides, This version was build on linux-next branch (tag next-20150918), and
the above test experiments also base on that tag. But I know the latest tag is
next-20151009, so i do rebase this series again on next-20151009, there were
little conflicts(exynos_dp removed the suspend/resume).

But after I retest this series on next-20151009, I saw kernel crashed in mmc
driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
module(after all I boot with USB device), and I can see eDP light up normally
in startup stage, but kernel keep crashed when it try to mount the filesystem.
I thought this isn't related to dp driver directly, so i choice not to debug
more depth.

That's to say if someone want to test this series, I suggest you applied this
series on tag-20150918, just need to fix some light conflicts with the 01 & 02
patches (or just email me, I can send you directly).

Thanks,
- Yakir

Changes in v6:
- Fix the wrong code in previous series, and test on Samsung snow Chromebook
  successfully, here are the detail changes:
=============>
-       if (!dp->panel && !dp->bridge) {
+       if (!dp->panel && !dp->ptn_bridge) {
                ret = exynos_dp_dt_parse_panel(dp);
                if (ret)
=============>
+       encoder->bridge = bridge;
	bridge->driver_private = dp;
        bridge->encoder = encoder;
        bridge->funcs = &exynos_dp_bridge_funcs;
        ret = drm_bridge_attach(drm_dev, bridge);
- Fix the Kconfig recursive dependency (Javier)
- Fix Peach Pit hpd property name error:
-       hpd-gpio = <&gpx2 6 0>;
+       hpd-gpios = <&gpx2 6 0>;

Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
  the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
  attch function. Cause once platform failed at attach, core driver should
  still failed, so no need to init connector before platform attached (Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
  patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)
- Resequence this patch after analogix_dp driver have been split
  from exynos_dp code, and rephrase reasonable commit message, and
  remove some controversial style (Krzysztof)
    -		analogix_dp_write_byte_to_dpcd(
    - 				dp, DP_TEST_RESPONSE,
    +		analogix_dp_write_byte_to_dpcd(dp,
    +				DP_TEST_RESPONSE,
				DP_TEST_EDID_CHECKSUM_WRITE);
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).
- Correct the misspell in commit message. (Krzysztof)
- Remove the empty line at the end of document, and correct the endpoint
  numbers in the example DT node, and remove the regulator iomux setting
  in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
  support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
  the exist "grf" syscon already. And rename the example DT node from
  "edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
  struct" to "static const struct". And correct the input paramters of
  devm_phy_create() interfaces. (Heiko)
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
  elemets in document. (Rob & Heiko)
- Fix compiled error (Heiko)
- Using the connector display info message to configure eDP driver input
  video mode, but hard code CRTC video output mode to RGBaaa.

Changes in v4:
- Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
- Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
- Create a separate folder for analogix code in bridge/ (Archit)
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
- Provide backword compatibility with samsung. (Krzysztof)
- Split all DTS changes, and provide backward compatibility. Mark old
  properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"
- Separate all DTS changes to a separate patch. (Krzysztof)
- Remove some deprecated DT properties in rockchip dp document.
- Add commit message, and remove the redundant rockchip_dp_phy_init()
  function, move those code to probe() method. And remove driver .owner
  number. (Kishon)
- Seprate the link-rate and lane-count limit out with the device_type
  flag. (Thierry)
- Take Jingoo suggest, add commit messages.
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Move exynos's video_timing code to analogix_dp-exynos platform driver,
  add get_modes method to struct analogix_dp_plat_data. (Thierry)
- Rename some "samsung*" dts propery to "analogix*". (Heiko)
- The link_rate and lane_count shouldn't config to the DT property value
  directly, but we can take those as hardware limite. For example, RK3288
  only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
  like "link-rate = 0x0a" "lane-count = 4". (Thierry)
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
  devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
  and leave "sclk_edp" to analogix dp core driver which name to "dp",
  and leave "pclk_edp" to rockchip dp platform driver which name to
  "pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
  node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.
- Suggest, add rockchip dp phy driver, collect the phy clocks and
  power control. (Heiko)
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.
- move dp hpd detect to connector detect function.
- Add edid modes parse support

Changes in v2:
- Keep author name list no changed (Jingoo)
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
  uncommon style like bellow: (Joe Preches)
    -  retval = exynos_dp_read_bytes_from_i2c(...
  				  ...);
    +  retval =
    +  exynos_dp_read_bytes_from_i2c(......);
- Get panel node with remote-endpoint method, and create devicetree binding
  for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.
- Fix compile failed dut to phy_pd_addr variable misspell error

Mark Yao (1):
  drm: rockchip: vop: add bpc and color mode setting

Yakir Yang (16):
  drm: exynos: dp: convert to drm bridge mode
  drm: bridge: analogix/dp: split exynos dp driver to bridge directory
  drm: bridge: analogix/dp: fix some obvious code style
  drm: bridge: analogix/dp: remove duplicate configuration of link rate
    and link count
  drm: bridge: analogix/dp: dynamic parse sync_pol & interlace &
    dynamic_range
  Documentation: drm/bridge: add document for analogix_dp
  ARM: dts: exynos/dp: remove some properties that deprecated by
    analogix_dp driver
  drm: rockchip: dp: add rockchip platform dp driver
  Documentation: drm/bridge: add document for analogix_dp
  phy: Add driver for rockchip Display Port PHY
  Documentation: phy: add document for rockchip dp phy
  drm: bridge: analogix/dp: add some rk3288 special registers setting
  drm: bridge: analogix/dp: add max link rate and lane count limit for
    RK3288
  drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  drm: bridge: analogix/dp: move hpd detect to connector detect function
  drm: bridge: analogix/dp: add edid modes parse in get_modes method

 .../devicetree/bindings/drm/bridge/analogix_dp.txt |   52 +
 .../devicetree/bindings/phy/rockchip-dp-phy.txt    |   22 +
 .../bindings/video/analogix_dp-rockchip.txt        |   91 ++
 .../devicetree/bindings/video/exynos_dp.txt        |   64 +-
 arch/arm/boot/dts/exynos5250-arndale.dts           |    2 -
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 -
 arch/arm/boot/dts/exynos5250-snow-common.dtsi      |    4 +-
 arch/arm/boot/dts/exynos5250-spring.dts            |    4 +-
 arch/arm/boot/dts/exynos5420-peach-pit.dts         |    4 +-
 arch/arm/boot/dts/exynos5420-smdk5420.dts          |    2 -
 arch/arm/boot/dts/exynos5800-peach-pi.dts          |    4 +-
 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    3 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1373 +++++++++++++++++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  286 ++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1294 ++++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  270 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  349 +++++
 drivers/gpu/drm/exynos/exynos_dp_core.c            | 1404 --------------------
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  281 ----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 ------------------
 drivers/gpu/drm/rockchip/Kconfig                   |    9 +
 drivers/gpu/drm/rockchip/Makefile                  |    1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    |  457 +++++++
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c        |    2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h        |    2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c        |   32 +-
 drivers/phy/Kconfig                                |    7 +
 drivers/phy/Makefile                               |    1 +
 drivers/phy/phy-rockchip-dp.c                      |  151 +++
 include/drm/bridge/analogix_dp.h                   |   42 +
 35 files changed, 4343 insertions(+), 3144 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (62%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 create mode 100644 drivers/phy/phy-rockchip-dp.c
 create mode 100644 include/drm/bridge/analogix_dp.h

-- 
1.9.1

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 01/17] drm: exynos: dp: convert to drm bridge mode
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 15:38     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:38 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6:
- Fix the wrong code in previous series, and test on Samsung snow Chromebook
  successfully, here are the detail changes:
=============>
-       if (!dp->panel && !dp->bridge) {
+       if (!dp->panel && !dp->ptn_bridge) {
                ret = exynos_dp_dt_parse_panel(dp);
                if (ret)
=============>
+       encoder->bridge = bridge;
	bridge->driver_private = dp;
        bridge->encoder = encoder;
        bridge->funcs = &exynos_dp_bridge_funcs;
        ret = drm_bridge_attach(drm_dev, bridge);

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Keep author name list no changed (Jingoo)

 drivers/gpu/drm/exynos/exynos_dp_core.c | 103 ++++++++++++++++++++++++--------
 drivers/gpu/drm/exynos/exynos_dp_core.h |   1 +
 2 files changed, 78 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 124fb9a..aedd074 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -1009,9 +1009,9 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
 {
 	int ret;
 
-	encoder->bridge = dp->bridge;
-	dp->bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->bridge);
+	encoder->bridge->next = dp->ptn_bridge;
+	dp->ptn_bridge->encoder = encoder;
+	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
 	if (ret) {
 		DRM_ERROR("Failed to attach bridge to drm\n");
 		return ret;
@@ -1020,14 +1020,15 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
 	return 0;
 }
 
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = &dp->encoder;
 	struct drm_connector *connector = &dp->connector;
 	int ret;
 
 	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->bridge) {
+	if (dp->ptn_bridge) {
 		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
 		if (!ret)
 			return 0;
@@ -1052,22 +1053,9 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	return ret;
 }
 
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
-				 const struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
 	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
 
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
@@ -1092,9 +1080,9 @@ static void exynos_dp_enable(struct drm_encoder *encoder)
 	dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
-static void exynos_dp_disable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
 	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
 
 	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
@@ -1123,6 +1111,69 @@ static void exynos_dp_disable(struct drm_encoder *encoder)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+{
+	/* do nothing */
+}
+
+static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
+	.enable = exynos_dp_bridge_enable,
+	.disable = exynos_dp_bridge_disable,
+	.pre_enable = exynos_dp_bridge_nop,
+	.post_disable = exynos_dp_bridge_nop,
+	.attach = exynos_dp_bridge_attach,
+};
+
+static int exynos_dp_create_connector(struct drm_encoder *encoder)
+{
+	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct drm_bridge *bridge;
+	int ret;
+
+	bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
+	if (!bridge) {
+		DRM_ERROR("failed to allocate for drm bridge\n");
+		return -ENOMEM;
+	}
+
+	dp->bridge = bridge;
+
+	encoder->bridge = bridge;
+	bridge->driver_private = dp;
+	bridge->encoder = encoder;
+	bridge->funcs = &exynos_dp_bridge_funcs;
+
+	ret = drm_bridge_attach(drm_dev, bridge);
+	if (ret) {
+		DRM_ERROR("failed to attach drm bridge\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+				 const struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
 static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
 	.mode_fixup = exynos_dp_mode_fixup,
 	.mode_set = exynos_dp_mode_set,
@@ -1238,7 +1289,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		}
 	}
 
-	if (!dp->panel && !dp->bridge) {
+	if (!dp->panel && !dp->ptn_bridge) {
 		ret = exynos_dp_dt_parse_panel(dp);
 		if (ret)
 			return ret;
@@ -1365,9 +1416,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	if (endpoint) {
 		bridge_node = of_graph_get_remote_port_parent(endpoint);
 		if (bridge_node) {
-			dp->bridge = of_drm_find_bridge(bridge_node);
+			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
 			of_node_put(bridge_node);
-			if (!dp->bridge)
+			if (!dp->ptn_bridge)
 				return -EPROBE_DEFER;
 		} else
 			return -EPROBE_DEFER;
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
index e413b6f..66eec4b 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
@@ -153,6 +153,7 @@ struct exynos_dp_device {
 	struct drm_connector	connector;
 	struct drm_panel	*panel;
 	struct drm_bridge	*bridge;
+	struct drm_bridge	*ptn_bridge;
 	struct clk		*clock;
 	unsigned int		irq;
 	void __iomem		*reg_base;
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 01/17] drm: exynos: dp: convert to drm bridge mode
@ 2015-10-10 15:38     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:38 UTC (permalink / raw)
  To: linux-arm-kernel

In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6:
- Fix the wrong code in previous series, and test on Samsung snow Chromebook
  successfully, here are the detail changes:
=============>
-       if (!dp->panel && !dp->bridge) {
+       if (!dp->panel && !dp->ptn_bridge) {
                ret = exynos_dp_dt_parse_panel(dp);
                if (ret)
=============>
+       encoder->bridge = bridge;
	bridge->driver_private = dp;
        bridge->encoder = encoder;
        bridge->funcs = &exynos_dp_bridge_funcs;
        ret = drm_bridge_attach(drm_dev, bridge);

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Keep author name list no changed (Jingoo)

 drivers/gpu/drm/exynos/exynos_dp_core.c | 103 ++++++++++++++++++++++++--------
 drivers/gpu/drm/exynos/exynos_dp_core.h |   1 +
 2 files changed, 78 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 124fb9a..aedd074 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -1009,9 +1009,9 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
 {
 	int ret;
 
-	encoder->bridge = dp->bridge;
-	dp->bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->bridge);
+	encoder->bridge->next = dp->ptn_bridge;
+	dp->ptn_bridge->encoder = encoder;
+	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
 	if (ret) {
 		DRM_ERROR("Failed to attach bridge to drm\n");
 		return ret;
@@ -1020,14 +1020,15 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
 	return 0;
 }
 
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = &dp->encoder;
 	struct drm_connector *connector = &dp->connector;
 	int ret;
 
 	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->bridge) {
+	if (dp->ptn_bridge) {
 		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
 		if (!ret)
 			return 0;
@@ -1052,22 +1053,9 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	return ret;
 }
 
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
-				 const struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
 	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
 
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
@@ -1092,9 +1080,9 @@ static void exynos_dp_enable(struct drm_encoder *encoder)
 	dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
-static void exynos_dp_disable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct exynos_dp_device *dp = bridge->driver_private;
 	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
 
 	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
@@ -1123,6 +1111,69 @@ static void exynos_dp_disable(struct drm_encoder *encoder)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+{
+	/* do nothing */
+}
+
+static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
+	.enable = exynos_dp_bridge_enable,
+	.disable = exynos_dp_bridge_disable,
+	.pre_enable = exynos_dp_bridge_nop,
+	.post_disable = exynos_dp_bridge_nop,
+	.attach = exynos_dp_bridge_attach,
+};
+
+static int exynos_dp_create_connector(struct drm_encoder *encoder)
+{
+	struct exynos_dp_device *dp = encoder_to_dp(encoder);
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct drm_bridge *bridge;
+	int ret;
+
+	bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
+	if (!bridge) {
+		DRM_ERROR("failed to allocate for drm bridge\n");
+		return -ENOMEM;
+	}
+
+	dp->bridge = bridge;
+
+	encoder->bridge = bridge;
+	bridge->driver_private = dp;
+	bridge->encoder = encoder;
+	bridge->funcs = &exynos_dp_bridge_funcs;
+
+	ret = drm_bridge_attach(drm_dev, bridge);
+	if (ret) {
+		DRM_ERROR("failed to attach drm bridge\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+				 const struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
 static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
 	.mode_fixup = exynos_dp_mode_fixup,
 	.mode_set = exynos_dp_mode_set,
@@ -1238,7 +1289,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		}
 	}
 
-	if (!dp->panel && !dp->bridge) {
+	if (!dp->panel && !dp->ptn_bridge) {
 		ret = exynos_dp_dt_parse_panel(dp);
 		if (ret)
 			return ret;
@@ -1365,9 +1416,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	if (endpoint) {
 		bridge_node = of_graph_get_remote_port_parent(endpoint);
 		if (bridge_node) {
-			dp->bridge = of_drm_find_bridge(bridge_node);
+			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
 			of_node_put(bridge_node);
-			if (!dp->bridge)
+			if (!dp->ptn_bridge)
 				return -EPROBE_DEFER;
 		} else
 			return -EPROBE_DEFER;
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
index e413b6f..66eec4b 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
@@ -153,6 +153,7 @@ struct exynos_dp_device {
 	struct drm_connector	connector;
 	struct drm_panel	*panel;
 	struct drm_bridge	*bridge;
+	struct drm_bridge	*ptn_bridge;
 	struct clk		*clock;
 	unsigned int		irq;
 	void __iomem		*reg_base;
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
@ 2015-10-10 15:39     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:39 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.

Beside the new analogix_dp driver would export four hooks.
"analogix_dp_bind()" and "analogix_dp_unbind()"
"analogix_dp_detect()" and "analogix_dp_get_modes()"

The bind/unbind symbols is used for analogix platform driver to connect
with analogix_dp core driver. And the detect/get_modes is used for analogix
platform driver to init the connector.

They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6:
- Fix the Kconfig recursive dependency (Javier)

Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
  the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
  attch function. Cause once platform failed at attach, core driver should
  still failed, so no need to init connector before platform attached (Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
  patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)

Changes in v4:
- Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
- Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
- Create a separate folder for analogix code in bridge/ (Archit)

Changes in v3:
- Move exynos's video_timing code to analogix_dp-exynos platform driver,
  add get_modes method to struct analogix_dp_plat_data. (Thierry)
- Rename some "samsung*" dts propery to "analogix*". (Heiko)

Changes in v2:
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell

 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    3 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 .../analogix/analogix_dp_core.c}                   |  753 +++++-------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  277 +++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1263 ++++++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  258 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  349 ++++++
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 -----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 --------------------
 include/drm/bridge/analogix_dp.h                   |   41 +
 14 files changed, 2365 insertions(+), 2133 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 rename drivers/gpu/drm/{exynos/exynos_dp_core.c => bridge/analogix/analogix_dp_core.c} (51%)
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (64%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 include/drm/bridge/analogix_dp.h

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 2de52a5..7b5b77a 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -29,4 +29,6 @@ config DRM_PARADE_PS8622
 	---help---
 	  Parade eDP-LVDS bridge chip driver.
 
+source "drivers/gpu/drm/bridge/analogix/Kconfig"
+
 endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index e2eef1c..5366c6b 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -3,3 +3,4 @@ ccflags-y := -Iinclude/drm
 obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
new file mode 100644
index 0000000..80f286f
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -0,0 +1,3 @@
+config DRM_ANALOGIX_DP
+	tristate
+	depends on DRM
diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
new file mode 100644
index 0000000..9107b86
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
similarity index 51%
rename from drivers/gpu/drm/exynos/exynos_dp_core.c
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index aedd074..e561590 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1,14 +1,14 @@
 /*
- * Samsung SoC DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
+* Analogix DP (Display Port) core interface driver.
+*
+* Copyright (C) 2012 Samsung Electronics Co., Ltd.
+* Author: Jingoo Han <jg1.han@samsung.com>
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2 of the License, or (at your
+* option) any later version.
+*/
 
 #include <linux/module.h>
 #include <linux/platform_device.h>
@@ -18,65 +18,48 @@
 #include <linux/interrupt.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
-#include <linux/of_graph.h>
 #include <linux/gpio.h>
 #include <linux/component.h>
 #include <linux/phy/phy.h>
-#include <video/of_display_timing.h>
-#include <video/of_videomode.h>
 
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
-#include <drm/drm_atomic_helper.h>
 #include <drm/drm_panel.h>
 
-#include "exynos_dp_core.h"
-#include "exynos_drm_crtc.h"
+#include <drm/bridge/analogix_dp.h>
 
-#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
-					connector)
-
-static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
-{
-	return to_exynos_crtc(dp->encoder.crtc);
-}
-
-static inline struct exynos_dp_device *encoder_to_dp(
-						struct drm_encoder *e)
-{
-	return container_of(e, struct exynos_dp_device, encoder);
-}
+#include "analogix_dp_core.h"
 
 struct bridge_init {
 	struct i2c_client *client;
 	struct device_node *node;
 };
 
-static void exynos_dp_init_dp(struct exynos_dp_device *dp)
+static void analogix_dp_init_dp(struct analogix_dp_device *dp)
 {
-	exynos_dp_reset(dp);
+	analogix_dp_reset(dp);
 
-	exynos_dp_swreset(dp);
+	analogix_dp_swreset(dp);
 
-	exynos_dp_init_analog_param(dp);
-	exynos_dp_init_interrupt(dp);
+	analogix_dp_init_analog_param(dp);
+	analogix_dp_init_interrupt(dp);
 
 	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_function(dp);
+	analogix_dp_enable_sw_function(dp);
 
-	exynos_dp_config_interrupt(dp);
-	exynos_dp_init_analog_func(dp);
+	analogix_dp_config_interrupt(dp);
+	analogix_dp_init_analog_func(dp);
 
-	exynos_dp_init_hpd(dp);
-	exynos_dp_init_aux(dp);
+	analogix_dp_init_hpd(dp);
+	analogix_dp_init_aux(dp);
 }
 
-static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
+static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (exynos_dp_get_plug_in_status(dp) != 0) {
+	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
@@ -88,7 +71,7 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
 	return 0;
 }
 
-static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
+static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 {
 	int i;
 	unsigned char sum = 0;
@@ -99,7 +82,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
 	return sum;
 }
 
-static int exynos_dp_read_edid(struct exynos_dp_device *dp)
+static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
 	unsigned char edid[EDID_BLOCK_LENGTH * 2];
 	unsigned int extend_block = 0;
@@ -114,7 +97,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 	 */
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 				EDID_EXTENSION_FLAG,
 				&extend_block);
 	if (retval)
@@ -124,7 +107,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -132,14 +115,14 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
+		sum = analogix_dp_calc_edid_check_sum(edid);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
 				I2C_EDID_DEVICE_ADDR,
 				EDID_BLOCK_LENGTH,
 				EDID_BLOCK_LENGTH,
@@ -148,19 +131,19 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
+		sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
 					&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_RESPONSE,
 				DP_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -168,7 +151,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_info(dp->dev, "EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
 				I2C_EDID_DEVICE_ADDR,
 				EDID_HEADER_PATTERN,
 				EDID_BLOCK_LENGTH,
@@ -177,20 +160,20 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
+		sum = analogix_dp_calc_edid_check_sum(edid);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp,
+		analogix_dp_read_byte_from_dpcd(dp,
 			DP_TEST_REQUEST,
 			&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
 				edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_RESPONSE,
 				DP_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -200,21 +183,21 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 	return 0;
 }
 
-static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
+static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 {
 	u8 buf[12];
 	int i;
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
 				12, buf);
 	if (retval)
 		return retval;
 
 	/* Read EDID */
 	for (i = 0; i < 3; i++) {
-		retval = exynos_dp_read_edid(dp);
+		retval = analogix_dp_read_edid(dp);
 		if (!retval)
 			break;
 	}
@@ -222,73 +205,73 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
+static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
 						bool enable)
 {
 	u8 data;
 
-	exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
 
 	if (enable)
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 			DP_LANE_COUNT_ENHANCED_FRAME_EN |
 			DPCD_LANE_COUNT_SET(data));
 	else
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 			DPCD_LANE_COUNT_SET(data));
 }
 
-static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
+static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
 {
 	u8 data;
 	int retval;
 
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 	retval = DPCD_ENHANCED_FRAME_CAP(data);
 
 	return retval;
 }
 
-static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
+static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 {
 	u8 data;
 
-	data = exynos_dp_is_enhanced_mode_available(dp);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, data);
-	exynos_dp_enable_enhanced_mode(dp, data);
+	data = analogix_dp_is_enhanced_mode_available(dp);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, data);
+	analogix_dp_enable_enhanced_mode(dp, data);
 }
 
-static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
+static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
-	exynos_dp_set_training_pattern(dp, DP_NONE);
+	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	exynos_dp_write_byte_to_dpcd(dp,
+	analogix_dp_write_byte_to_dpcd(dp,
 		DP_TRAINING_PATTERN_SET,
 		DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
+static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
 					int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
-		exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 		break;
 	case 1:
-		exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 		break;
 
 	case 2:
-		exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 		break;
 
 	case 3:
-		exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 		break;
 	}
 }
 
-static int exynos_dp_link_start(struct exynos_dp_device *dp)
+static int analogix_dp_link_start(struct analogix_dp_device *dp)
 {
 	u8 buf[4];
 	int lane, lane_count, pll_tries, retval;
@@ -302,25 +285,25 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		dp->link_train.cr_loop[lane] = 0;
 
 	/* Set link rate and count as you want to establish*/
-	exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
-	exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
+	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
 				2, buf);
 	if (retval)
 		return retval;
 
 	/* Set TX pre-emphasis to minimum */
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_lane_pre_emphasis(dp,
+		analogix_dp_set_lane_lane_pre_emphasis(dp,
 			PRE_EMPHASIS_LEVEL_0, lane);
 
 	/* Wait for PLL lock */
 	pll_tries = 0;
-	while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+	while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 		if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Wait for PLL lock timed out\n");
 			return -ETIMEDOUT;
@@ -331,10 +314,10 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 	}
 
 	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
+	analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 
 	/* Set RX training pattern */
-	retval = exynos_dp_write_byte_to_dpcd(dp,
+	retval = analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
 	if (retval)
@@ -344,13 +327,13 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 			lane_count, buf);
 
 	return retval;
 }
 
-static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
+static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
 	u8 link_value = link_status[lane>>1];
@@ -358,20 +341,20 @@ static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
 	return (link_value >> shift) & 0xf;
 }
 
-static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
+static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 {
 	int lane;
 	u8 lane_status;
 
 	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
 		if ((lane_status & DP_LANE_CR_DONE) == 0)
 			return -EINVAL;
 	}
 	return 0;
 }
 
-static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
+static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 				int lane_count)
 {
 	int lane;
@@ -381,7 +364,7 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 		return -EINVAL;
 
 	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
 		lane_status &= DP_CHANNEL_EQ_BITS;
 		if (lane_status != DP_CHANNEL_EQ_BITS)
 			return -EINVAL;
@@ -390,7 +373,7 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
+static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
 							int lane)
 {
 	int shift = (lane & 1) * 4;
@@ -399,7 +382,7 @@ static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 	return (link_value >> shift) & 0x3;
 }
 
-static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
+static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					u8 adjust_request[2],
 					int lane)
 {
@@ -409,45 +392,45 @@ static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
-static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
+static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 					u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
-		exynos_dp_set_lane0_link_training(dp, training_lane_set);
+		analogix_dp_set_lane0_link_training(dp, training_lane_set);
 		break;
 	case 1:
-		exynos_dp_set_lane1_link_training(dp, training_lane_set);
+		analogix_dp_set_lane1_link_training(dp, training_lane_set);
 		break;
 
 	case 2:
-		exynos_dp_set_lane2_link_training(dp, training_lane_set);
+		analogix_dp_set_lane2_link_training(dp, training_lane_set);
 		break;
 
 	case 3:
-		exynos_dp_set_lane3_link_training(dp, training_lane_set);
+		analogix_dp_set_lane3_link_training(dp, training_lane_set);
 		break;
 	}
 }
 
-static unsigned int exynos_dp_get_lane_link_training(
-				struct exynos_dp_device *dp,
+static unsigned int analogix_dp_get_lane_link_training(
+				struct analogix_dp_device *dp,
 				int lane)
 {
 	u32 reg;
 
 	switch (lane) {
 	case 0:
-		reg = exynos_dp_get_lane0_link_training(dp);
+		reg = analogix_dp_get_lane0_link_training(dp);
 		break;
 	case 1:
-		reg = exynos_dp_get_lane1_link_training(dp);
+		reg = analogix_dp_get_lane1_link_training(dp);
 		break;
 	case 2:
-		reg = exynos_dp_get_lane2_link_training(dp);
+		reg = analogix_dp_get_lane2_link_training(dp);
 		break;
 	case 3:
-		reg = exynos_dp_get_lane3_link_training(dp);
+		reg = analogix_dp_get_lane3_link_training(dp);
 		break;
 	default:
 		WARN_ON(1);
@@ -457,15 +440,15 @@ static unsigned int exynos_dp_get_lane_link_training(
 	return reg;
 }
 
-static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
+static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 {
-	exynos_dp_training_pattern_dis(dp);
-	exynos_dp_set_enhanced_mode(dp);
+	analogix_dp_training_pattern_dis(dp);
+	analogix_dp_set_enhanced_mode(dp);
 
 	dp->link_train.lt_state = FAILED;
 }
 
-static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
+static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
 					u8 adjust_request[2])
 {
 	int lane, lane_count;
@@ -473,9 +456,9 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
 
 	lane_count = dp->link_train.lane_count;
 	for (lane = 0; lane < lane_count; lane++) {
-		voltage_swing = exynos_dp_get_adjust_request_voltage(
+		voltage_swing = analogix_dp_get_adjust_request_voltage(
 						adjust_request, lane);
-		pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
+		pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 						adjust_request, lane);
 		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
@@ -489,7 +472,7 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
 	}
 }
 
-static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
+static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 {
 	int lane, lane_count, retval;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -499,21 +482,21 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
+	retval =  analogix_dp_read_bytes_from_dpcd(dp,
 			DP_LANE0_1_STATUS, 2, link_status);
 	if (retval)
 		return retval;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
+	retval =  analogix_dp_read_bytes_from_dpcd(dp,
 			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 	if (retval)
 		return retval;
 
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 		/* set training pattern 2 for EQ */
-		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
+		analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 
-		retval = exynos_dp_write_byte_to_dpcd(dp,
+		retval = analogix_dp_write_byte_to_dpcd(dp,
 				DP_TRAINING_PATTERN_SET,
 				DP_LINK_SCRAMBLING_DISABLE |
 				DP_TRAINING_PATTERN_2);
@@ -524,11 +507,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 		dp->link_train.lt_state = EQUALIZER_TRAINING;
 	} else {
 		for (lane = 0; lane < lane_count; lane++) {
-			training_lane = exynos_dp_get_lane_link_training(
+			training_lane = analogix_dp_get_lane_link_training(
 							dp, lane);
-			voltage_swing = exynos_dp_get_adjust_request_voltage(
+			voltage_swing = analogix_dp_get_adjust_request_voltage(
 							adjust_request, lane);
-			pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
+			pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 							adjust_request, lane);
 
 			if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
@@ -543,19 +526,19 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 				dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 					dp->link_train.cr_loop[lane],
 					voltage_swing, pre_emphasis);
-				exynos_dp_reduce_link_rate(dp);
+				analogix_dp_reduce_link_rate(dp);
 				return -EIO;
 			}
 		}
 	}
 
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
+		analogix_dp_set_lane_link_training(dp,
 			dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp,
+	retval = analogix_dp_write_bytes_to_dpcd(dp,
 			DP_TRAINING_LANE0_SET, lane_count,
 			dp->link_train.training_lane);
 	if (retval)
@@ -564,7 +547,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
+static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 {
 	int lane, lane_count, retval;
 	u32 reg;
@@ -574,46 +557,46 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
+	retval = analogix_dp_read_bytes_from_dpcd(dp,
 			DP_LANE0_1_STATUS, 2, link_status);
 	if (retval)
 		return retval;
 
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
-		exynos_dp_reduce_link_rate(dp);
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
+		analogix_dp_reduce_link_rate(dp);
 		return -EIO;
 	}
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
+	retval = analogix_dp_read_bytes_from_dpcd(dp,
 			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 	if (retval)
 		return retval;
 
-	retval = exynos_dp_read_byte_from_dpcd(dp,
+	retval = analogix_dp_read_byte_from_dpcd(dp,
 			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
 	if (retval)
 		return retval;
 
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 
-	if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
+	if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 		/* traing pattern Set to Normal */
-		exynos_dp_training_pattern_dis(dp);
+		analogix_dp_training_pattern_dis(dp);
 
 		dev_info(dp->dev, "Link Training success!\n");
 
-		exynos_dp_get_link_bandwidth(dp, &reg);
+		analogix_dp_get_link_bandwidth(dp, &reg);
 		dp->link_train.link_rate = reg;
 		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 			dp->link_train.link_rate);
 
-		exynos_dp_get_lane_count(dp, &reg);
+		analogix_dp_get_lane_count(dp, &reg);
 		dp->link_train.lane_count = reg;
 		dev_dbg(dp->dev, "final lane count = %.2x\n",
 			dp->link_train.lane_count);
 
 		/* set enhanced mode if available */
-		exynos_dp_set_enhanced_mode(dp);
+		analogix_dp_set_enhanced_mode(dp);
 		dp->link_train.lt_state = FINISHED;
 
 		return 0;
@@ -624,21 +607,21 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 		dev_err(dp->dev, "EQ Max loop\n");
-		exynos_dp_reduce_link_rate(dp);
+		analogix_dp_reduce_link_rate(dp);
 		return -EIO;
 	}
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
+		analogix_dp_set_lane_link_training(dp,
 			dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 			lane_count, dp->link_train.training_lane);
 
 	return retval;
 }
 
-static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
+static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 					u8 *bandwidth)
 {
 	u8 data;
@@ -647,11 +630,11 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
 }
 
-static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
+static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 					u8 *lane_count)
 {
 	u8 data;
@@ -660,11 +643,11 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 	 * For DP rev.1.1, Maximum number of Main Link lanes
 	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 	*lane_count = DPCD_MAX_LANE_COUNT(data);
 }
 
-static void exynos_dp_init_training(struct exynos_dp_device *dp,
+static void analogix_dp_init_training(struct analogix_dp_device *dp,
 			enum link_lane_count_type max_lane,
 			enum link_rate_type max_rate)
 {
@@ -672,11 +655,11 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 	 * the DP inter pair skew issue for at least 10 us
 	 */
-	exynos_dp_reset_macro(dp);
+	analogix_dp_reset_macro(dp);
 
 	/* Initialize by reading RX's DPCD */
-	exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
-	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
+	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
+	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
@@ -698,10 +681,10 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
 		dp->link_train.link_rate = max_rate;
 
 	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 }
 
-static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
+static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 {
 	int retval = 0, training_finished = 0;
 
@@ -711,17 +694,17 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 	while (!retval && !training_finished) {
 		switch (dp->link_train.lt_state) {
 		case START:
-			retval = exynos_dp_link_start(dp);
+			retval = analogix_dp_link_start(dp);
 			if (retval)
 				dev_err(dp->dev, "LT link start failed!\n");
 			break;
 		case CLOCK_RECOVERY:
-			retval = exynos_dp_process_clock_recovery(dp);
+			retval = analogix_dp_process_clock_recovery(dp);
 			if (retval)
 				dev_err(dp->dev, "LT CR failed!\n");
 			break;
 		case EQUALIZER_TRAINING:
-			retval = exynos_dp_process_equalizer_training(dp);
+			retval = analogix_dp_process_equalizer_training(dp);
 			if (retval)
 				dev_err(dp->dev, "LT EQ failed!\n");
 			break;
@@ -738,7 +721,7 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
+static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
 				u32 count,
 				u32 bwtype)
 {
@@ -746,8 +729,8 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 	int retval;
 
 	for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
-		exynos_dp_init_training(dp, count, bwtype);
-		retval = exynos_dp_sw_link_training(dp);
+		analogix_dp_init_training(dp, count, bwtype);
+		retval = analogix_dp_sw_link_training(dp);
 		if (retval == 0)
 			break;
 
@@ -757,24 +740,24 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 	return retval;
 }
 
-static int exynos_dp_config_video(struct exynos_dp_device *dp)
+static int analogix_dp_config_video(struct analogix_dp_device *dp)
 {
 	int retval = 0;
 	int timeout_loop = 0;
 	int done_count = 0;
 
-	exynos_dp_config_video_slave_mode(dp);
+	analogix_dp_config_video_slave_mode(dp);
 
-	exynos_dp_set_video_color_format(dp);
+	analogix_dp_set_video_color_format(dp);
 
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 		dev_err(dp->dev, "PLL is not locked yet.\n");
 		return -EINVAL;
 	}
 
 	for (;;) {
 		timeout_loop++;
-		if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
+		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
@@ -785,22 +768,22 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
 	}
 
 	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
+	analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 
 	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
+	analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 
 	/* Disable video mute */
-	exynos_dp_enable_video_mute(dp, 0);
+	analogix_dp_enable_video_mute(dp, 0);
 
 	/* Configure video slave mode */
-	exynos_dp_enable_video_master(dp, 0);
+	analogix_dp_enable_video_master(dp, 0);
 
 	timeout_loop = 0;
 
 	for (;;) {
 		timeout_loop++;
-		if (exynos_dp_is_video_stream_on(dp) == 0) {
+		if (analogix_dp_is_video_stream_on(dp) == 0) {
 			done_count++;
 			if (done_count > 10)
 				break;
@@ -821,47 +804,47 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
 {
 	u8 data;
 
 	if (enable) {
-		exynos_dp_enable_scrambling(dp);
+		analogix_dp_enable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp,
+		analogix_dp_read_byte_from_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
+		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
-		exynos_dp_disable_scrambling(dp);
+		analogix_dp_disable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp,
+		analogix_dp_read_byte_from_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
+		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 	}
 }
 
-static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
+static irqreturn_t analogix_dp_irq_handler(int irq, void *arg)
 {
-	struct exynos_dp_device *dp = arg;
+	struct analogix_dp_device *dp = arg;
 
 	enum dp_irq_type irq_type;
 
-	irq_type = exynos_dp_get_irq_type(dp);
+	irq_type = analogix_dp_get_irq_type(dp);
 	switch (irq_type) {
 	case DP_IRQ_TYPE_HP_CABLE_IN:
 		dev_dbg(dp->dev, "Received irq - cable in\n");
 		schedule_work(&dp->hotplug_work);
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	case DP_IRQ_TYPE_HP_CABLE_OUT:
 		dev_dbg(dp->dev, "Received irq - cable out\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	case DP_IRQ_TYPE_HP_CHANGE:
 		/*
@@ -870,7 +853,7 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 		 * only handle cable changes.
 		 */
 		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	default:
 		dev_err(dp->dev, "Received irq - unknown type!\n");
@@ -879,217 +862,160 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
-static void exynos_dp_hotplug(struct work_struct *work)
+static void analogix_dp_hotplug(struct work_struct *work)
 {
-	struct exynos_dp_device *dp;
+	struct analogix_dp_device *dp;
 
-	dp = container_of(work, struct exynos_dp_device, hotplug_work);
+	dp = container_of(work, struct analogix_dp_device, hotplug_work);
 
 	if (dp->drm_dev)
 		drm_helper_hpd_irq_event(dp->drm_dev);
 }
 
-static void exynos_dp_commit(struct drm_encoder *encoder)
+static void analogix_dp_commit(struct analogix_dp_device *dp)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
 	int ret;
 
 	/* Keep the panel disabled while we configure video */
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel))
+	if (dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel))
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = exynos_dp_detect_hpd(dp);
+	ret = analogix_dp_detect_hpd(dp);
 	if (ret) {
 		/* Cable has been disconnected, we're done */
 		return;
 	}
 
-	ret = exynos_dp_handle_edid(dp);
+	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
 		return;
 	}
 
-	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
+	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
 					dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
 	}
 
-	exynos_dp_enable_scramble(dp, 1);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
-	exynos_dp_enable_enhanced_mode(dp, 1);
+	analogix_dp_enable_scramble(dp, 1);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
+	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
-	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
+	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 
-	exynos_dp_init_video(dp);
-	ret = exynos_dp_config_video(dp);
+	analogix_dp_init_video(dp);
+	ret = analogix_dp_config_video(dp);
 	if (ret)
 		dev_err(dp->dev, "unable to config video\n");
 
 	/* Safe to enable the panel now */
-	if (dp->panel) {
-		if (drm_panel_enable(dp->panel))
+	if (dp->plat_data->panel) {
+		if (drm_panel_enable(dp->plat_data->panel))
 			DRM_ERROR("failed to enable the panel\n");
 	}
 
 	/* Enable video */
-	exynos_dp_start_video(dp);
+	analogix_dp_start_video(dp);
 }
 
-static enum drm_connector_status exynos_dp_detect(
-				struct drm_connector *connector, bool force)
+enum drm_connector_status analogix_dp_detect(struct device *dev, bool force)
 {
 	return connector_status_connected;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_detect);
 
-static void exynos_dp_connector_destroy(struct drm_connector *connector)
+int analogix_dp_get_modes(struct device *dev)
 {
-	drm_connector_unregister(connector);
-	drm_connector_cleanup(connector);
-}
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+	int num_modes = 0;
 
-static struct drm_connector_funcs exynos_dp_connector_funcs = {
-	.dpms = drm_atomic_helper_connector_dpms,
-	.fill_modes = drm_helper_probe_single_connector_modes,
-	.detect = exynos_dp_detect,
-	.destroy = exynos_dp_connector_destroy,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static int exynos_dp_get_modes(struct drm_connector *connector)
-{
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
-	struct drm_display_mode *mode;
+	if (dp->plat_data->panel)
+		num_modes += drm_panel_get_modes(dp->plat_data->panel);
 
-	if (dp->panel)
-		return drm_panel_get_modes(dp->panel);
-
-	mode = drm_mode_create(connector->dev);
-	if (!mode) {
-		DRM_ERROR("failed to create a new display mode.\n");
-		return 0;
-	}
-
-	drm_display_mode_from_videomode(&dp->priv.vm, mode);
-	mode->width_mm = dp->priv.width_mm;
-	mode->height_mm = dp->priv.height_mm;
-	connector->display_info.width_mm = mode->width_mm;
-	connector->display_info.height_mm = mode->height_mm;
-
-	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-	drm_mode_set_name(mode);
-	drm_mode_probed_add(connector, mode);
-
-	return 1;
-}
-
-static struct drm_encoder *exynos_dp_best_encoder(
-			struct drm_connector *connector)
-{
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
-
-	return &dp->encoder;
+	return num_modes;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_get_modes);
 
-static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
-	.get_modes = exynos_dp_get_modes,
-	.best_encoder = exynos_dp_best_encoder,
-};
-
-/* returns the number of bridges attached */
-static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
-		struct drm_encoder *encoder)
+static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
 {
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = dp->encoder;
 	int ret;
 
-	encoder->bridge->next = dp->ptn_bridge;
-	dp->ptn_bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
-	if (ret) {
-		DRM_ERROR("Failed to attach bridge to drm\n");
-		return ret;
+	if (!bridge->encoder) {
+		DRM_ERROR("Parent encoder object not found");
+		return -ENODEV;
 	}
 
-	return 0;
-}
-
-static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
-{
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct drm_encoder *encoder = &dp->encoder;
-	struct drm_connector *connector = &dp->connector;
-	int ret;
+	encoder->bridge = bridge;
 
-	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->ptn_bridge) {
-		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
-		if (!ret)
-			return 0;
+	/*
+	 * NOTE: the connector registration is implemented in analogix
+	 * platform driver, that to say connector would be exist after
+	 * plat_data->attch return, that's why we record the connector
+	 * point after plat attached.
+	 */
+	 if (dp->plat_data->attach) {
+		 ret = dp->plat_data->attach(dp->plat_data, bridge);
+		 if (ret) {
+			 DRM_ERROR("Failed at platform attch func\n");
+			 return ret;
+		 }
 	}
 
-	connector->polled = DRM_CONNECTOR_POLL_HPD;
+	dp->connector = dp->plat_data->connector;
 
-	ret = drm_connector_init(dp->drm_dev, connector,
-			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
-	if (ret) {
-		DRM_ERROR("Failed to initialize connector with drm\n");
-		return ret;
+	if (dp->plat_data->panel) {
+		ret = drm_panel_attach(dp->plat_data->panel, dp->connector);
+		if (ret) {
+			DRM_ERROR("Failed to attach panel\n");
+			return ret;
+		}
 	}
 
-	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
-	drm_connector_register(connector);
-	drm_mode_connector_attach_encoder(connector, encoder);
-
-	if (dp->panel)
-		ret = drm_panel_attach(dp->panel, &dp->connector);
-
-	return ret;
+	return 0;
 }
 
-static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
+static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
+	struct analogix_dp_device *dp = bridge->driver_private;
 
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->panel) {
-		if (drm_panel_prepare(dp->panel)) {
+	if (dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
 			DRM_ERROR("failed to setup the panel\n");
 			return;
 		}
 	}
 
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), true);
+	if (dp->plat_data->power_on)
+		dp->plat_data->power_on(dp->plat_data);
 
 	clk_prepare_enable(dp->clock);
 	phy_power_on(dp->phy);
-	exynos_dp_init_dp(dp);
+	analogix_dp_init_dp(dp);
 	enable_irq(dp->irq);
-	exynos_dp_commit(&dp->encoder);
+	analogix_dp_commit(dp);
 
 	dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
-static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
+static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
+	struct analogix_dp_device *dp = bridge->driver_private;
 
 	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel)) {
+	if (dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel)) {
 			DRM_ERROR("failed to disable the panel\n");
 			return;
 		}
@@ -1100,34 +1026,33 @@ static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 	phy_power_off(dp->phy);
 	clk_disable_unprepare(dp->clock);
 
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), false);
+	if (dp->plat_data->power_off)
+		dp->plat_data->power_off(dp->plat_data);
 
-	if (dp->panel) {
-		if (drm_panel_unprepare(dp->panel))
+	if (dp->plat_data->panel) {
+		if (drm_panel_unprepare(dp->plat_data->panel))
 			DRM_ERROR("failed to turnoff the panel\n");
 	}
 
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
-static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
 }
 
-static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
-	.enable = exynos_dp_bridge_enable,
-	.disable = exynos_dp_bridge_disable,
-	.pre_enable = exynos_dp_bridge_nop,
-	.post_disable = exynos_dp_bridge_nop,
-	.attach = exynos_dp_bridge_attach,
+static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
+	.enable = analogix_dp_bridge_enable,
+	.disable = analogix_dp_bridge_disable,
+	.pre_enable = analogix_dp_bridge_nop,
+	.post_disable = analogix_dp_bridge_nop,
+	.attach = analogix_dp_bridge_attach,
 };
 
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int analogix_dp_create_bridge(struct drm_device *drm_dev,
+				     struct analogix_dp_device *dp)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
-	struct drm_device *drm_dev = dp->drm_dev;
 	struct drm_bridge *bridge;
 	int ret;
 
@@ -1139,10 +1064,10 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 
 	dp->bridge = bridge;
 
-	encoder->bridge = bridge;
+	dp->encoder->bridge = bridge;
 	bridge->driver_private = dp;
-	bridge->encoder = encoder;
-	bridge->funcs = &exynos_dp_bridge_funcs;
+	bridge->encoder = dp->encoder;
+	bridge->funcs = &analogix_dp_bridge_funcs;
 
 	ret = drm_bridge_attach(drm_dev, bridge);
 	if (ret) {
@@ -1153,39 +1078,7 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	return 0;
 }
 
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
-				 const struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
-{
-}
-
-static void exynos_dp_disable(struct drm_encoder *encoder)
-{
-}
-
-static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
-	.mode_fixup = exynos_dp_mode_fixup,
-	.mode_set = exynos_dp_mode_set,
-	.enable = exynos_dp_enable,
-	.disable = exynos_dp_disable,
-};
-
-static struct drm_encoder_funcs exynos_dp_encoder_funcs = {
-	.destroy = drm_encoder_cleanup,
-};
-
-static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
+static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 {
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
@@ -1243,33 +1136,37 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
 	return dp_video_config;
 }
 
-static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct analogix_dp_plat_data *plat_data)
 {
+	struct platform_device *pdev = to_platform_device(dev);
+	struct analogix_dp_device *dp;
+	struct resource *res;
+	unsigned int irq_flags;
 	int ret;
 
-	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
-			OF_USE_NATIVE_MODE);
-	if (ret) {
-		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
-		return ret;
+	if (!plat_data) {
+		dev_err(dev, "Invalided input plat_data\n");
+		return -EINVAL;
 	}
-	return 0;
-}
 
-static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
-{
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-	struct platform_device *pdev = to_platform_device(dev);
-	struct drm_device *drm_dev = data;
-	struct drm_encoder *encoder = &dp->encoder;
-	struct resource *res;
-	unsigned int irq_flags;
-	int pipe, ret = 0;
+	dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, dp);
 
 	dp->dev = &pdev->dev;
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 
-	dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
+	/*
+	 * platform dp driver need containor_of the plat_data to get
+	 * the driver private data, so we need to store the point of
+	 * plat_data, not the context of plat_data.
+	 */
+	dp->plat_data = plat_data;
+
+	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
 	if (IS_ERR(dp->video_info))
 		return PTR_ERR(dp->video_info);
 
@@ -1289,12 +1186,6 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		}
 	}
 
-	if (!dp->panel && !dp->ptn_bridge) {
-		ret = exynos_dp_dt_parse_panel(dp);
-		if (ret)
-			return ret;
-	}
-
 	dp->clock = devm_clk_get(&pdev->dev, "dp");
 	if (IS_ERR(dp->clock)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
@@ -1309,7 +1200,10 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
-	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
+	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
+	if (!gpio_is_valid(dp->hpd_gpio))
+		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
+						 "samsung,hpd-gpio", 0);
 
 	if (gpio_is_valid(dp->hpd_gpio)) {
 		/*
@@ -1338,14 +1232,14 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		return -ENODEV;
 	}
 
-	INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
+	INIT_WORK(&dp->hotplug_work, analogix_dp_hotplug);
 
 	phy_power_on(dp->phy);
 
-	exynos_dp_init_dp(dp);
+	analogix_dp_init_dp(dp);
 
-	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
-			irq_flags, "exynos-dp", dp);
+	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
+			irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		return ret;
@@ -1353,103 +1247,48 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	disable_irq(dp->irq);
 
 	dp->drm_dev = drm_dev;
+	dp->encoder = dp->plat_data->encoder;
 
-	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
-						  EXYNOS_DISPLAY_TYPE_LCD);
-	if (pipe < 0)
-		return pipe;
-
-	encoder->possible_crtcs = 1 << pipe;
-
-	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
-
-	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
-			 DRM_MODE_ENCODER_TMDS);
-
-	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
-
-	ret = exynos_dp_create_connector(encoder);
+	ret = analogix_dp_create_bridge(drm_dev, dp);
 	if (ret) {
-		DRM_ERROR("failed to create connector ret = %d\n", ret);
-		drm_encoder_cleanup(encoder);
+		DRM_ERROR("failed to create bridge (%d)\n", ret);
+		drm_encoder_cleanup(dp->encoder);
 		return ret;
 	}
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_bind);
 
-static void exynos_dp_unbind(struct device *dev, struct device *master,
-				void *data)
+void analogix_dp_unbind(struct device *dev, struct device *master,
+			void *data)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_disable(&dp->encoder);
+	analogix_dp_bridge_disable(dp->bridge);
 }
+EXPORT_SYMBOL_GPL(analogix_dp_unbind);
 
-static const struct component_ops exynos_dp_ops = {
-	.bind	= exynos_dp_bind,
-	.unbind	= exynos_dp_unbind,
-};
-
-static int exynos_dp_probe(struct platform_device *pdev)
+#ifdef CONFIG_PM_SLEEP
+int analogix_dp_suspend(struct device *dev)
 {
-	struct device *dev = &pdev->dev;
-	struct device_node *panel_node, *bridge_node, *endpoint;
-	struct exynos_dp_device *dp;
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
-				GFP_KERNEL);
-	if (!dp)
-		return -ENOMEM;
-
-	platform_set_drvdata(pdev, dp);
-
-	panel_node = of_parse_phandle(dev->of_node, "panel", 0);
-	if (panel_node) {
-		dp->panel = of_drm_find_panel(panel_node);
-		of_node_put(panel_node);
-		if (!dp->panel)
-			return -EPROBE_DEFER;
-	}
-
-	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
-	if (endpoint) {
-		bridge_node = of_graph_get_remote_port_parent(endpoint);
-		if (bridge_node) {
-			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
-			of_node_put(bridge_node);
-			if (!dp->ptn_bridge)
-				return -EPROBE_DEFER;
-		} else
-			return -EPROBE_DEFER;
-	}
-
-	return component_add(&pdev->dev, &exynos_dp_ops);
+	analogix_dp_bridge_disable(dp->bridge);
+	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_suspend);
 
-static int exynos_dp_remove(struct platform_device *pdev)
+int analogix_dp_resume(struct device *dev)
 {
-	component_del(&pdev->dev, &exynos_dp_ops);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
+	analogix_dp_bridge_enable(dp->bridge);
 	return 0;
 }
-
-static const struct of_device_id exynos_dp_match[] = {
-	{ .compatible = "samsung,exynos5-dp" },
-	{},
-};
-MODULE_DEVICE_TABLE(of, exynos_dp_match);
-
-struct platform_driver dp_driver = {
-	.probe		= exynos_dp_probe,
-	.remove		= exynos_dp_remove,
-	.driver		= {
-		.name	= "exynos-dp",
-		.owner	= THIS_MODULE,
-		.of_match_table = exynos_dp_match,
-	},
-};
+EXPORT_SYMBOL_GPL(analogix_dp_resume);
+#endif
 
 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
-MODULE_DESCRIPTION("Samsung SoC DP Driver");
+MODULE_DESCRIPTION("Analogix DP Core Driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
new file mode 100644
index 0000000..65ce7f1
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -0,0 +1,277 @@
+/*
+ * Header file for Analogix DP (Display Port) core interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _ANALOGIX_DP_CORE_H
+#define _ANALOGIX_DP_CORE_H
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_dp_helper.h>
+
+#define DP_TIMEOUT_LOOP_COUNT 100
+#define MAX_CR_LOOP 5
+#define MAX_EQ_LOOP 5
+
+enum link_rate_type {
+	LINK_RATE_1_62GBPS = 0x06,
+	LINK_RATE_2_70GBPS = 0x0a
+};
+
+enum link_lane_count_type {
+	LANE_COUNT1 = 1,
+	LANE_COUNT2 = 2,
+	LANE_COUNT4 = 4
+};
+
+enum link_training_state {
+	START,
+	CLOCK_RECOVERY,
+	EQUALIZER_TRAINING,
+	FINISHED,
+	FAILED
+};
+
+enum voltage_swing_level {
+	VOLTAGE_LEVEL_0,
+	VOLTAGE_LEVEL_1,
+	VOLTAGE_LEVEL_2,
+	VOLTAGE_LEVEL_3,
+};
+
+enum pre_emphasis_level {
+	PRE_EMPHASIS_LEVEL_0,
+	PRE_EMPHASIS_LEVEL_1,
+	PRE_EMPHASIS_LEVEL_2,
+	PRE_EMPHASIS_LEVEL_3,
+};
+
+enum pattern_set {
+	PRBS7,
+	D10_2,
+	TRAINING_PTN1,
+	TRAINING_PTN2,
+	DP_NONE
+};
+
+enum color_space {
+	COLOR_RGB,
+	COLOR_YCBCR422,
+	COLOR_YCBCR444
+};
+
+enum color_depth {
+	COLOR_6,
+	COLOR_8,
+	COLOR_10,
+	COLOR_12
+};
+
+enum color_coefficient {
+	COLOR_YCBCR601,
+	COLOR_YCBCR709
+};
+
+enum dynamic_range {
+	VESA,
+	CEA
+};
+
+enum pll_status {
+	PLL_UNLOCKED,
+	PLL_LOCKED
+};
+
+enum clock_recovery_m_value_type {
+	CALCULATED_M,
+	REGISTER_M
+};
+
+enum video_timing_recognition_type {
+	VIDEO_TIMING_FROM_CAPTURE,
+	VIDEO_TIMING_FROM_REGISTER
+};
+
+enum analog_power_block {
+	AUX_BLOCK,
+	CH0_BLOCK,
+	CH1_BLOCK,
+	CH2_BLOCK,
+	CH3_BLOCK,
+	ANALOG_TOTAL,
+	POWER_ALL
+};
+
+enum dp_irq_type {
+	DP_IRQ_TYPE_HP_CABLE_IN,
+	DP_IRQ_TYPE_HP_CABLE_OUT,
+	DP_IRQ_TYPE_HP_CHANGE,
+	DP_IRQ_TYPE_UNKNOWN,
+};
+
+struct video_info {
+	char *name;
+
+	bool h_sync_polarity;
+	bool v_sync_polarity;
+	bool interlaced;
+
+	enum color_space color_space;
+	enum dynamic_range dynamic_range;
+	enum color_coefficient ycbcr_coeff;
+	enum color_depth color_depth;
+
+	enum link_rate_type link_rate;
+	enum link_lane_count_type lane_count;
+};
+
+struct link_train {
+	int eq_loop;
+	int cr_loop[4];
+
+	u8 link_rate;
+	u8 lane_count;
+	u8 training_lane[4];
+
+	enum link_training_state lt_state;
+};
+
+struct analogix_dp_device {
+	struct drm_encoder	*encoder;
+	struct drm_connector	*connector;
+	struct device		*dev;
+	struct drm_device	*drm_dev;
+	struct drm_bridge	*bridge;
+	struct clk		*clock;
+	unsigned int		irq;
+	void __iomem		*reg_base;
+
+	struct video_info	*video_info;
+	struct link_train	link_train;
+	struct work_struct	hotplug_work;
+	struct phy		*phy;
+	int			dpms_mode;
+	int			hpd_gpio;
+
+	struct analogix_dp_plat_data *plat_data;
+};
+
+/* analogix_dp_reg.c */
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_stop_video(struct analogix_dp_device *dp);
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
+void analogix_dp_reset(struct analogix_dp_device *dp);
+void analogix_dp_swreset(struct analogix_dp_device *dp);
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				       enum analog_power_block block,
+				       bool enable);
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
+void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
+void analogix_dp_reset_aux(struct analogix_dp_device *dp);
+void analogix_dp_init_aux(struct analogix_dp_device *dp);
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char data);
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char *data);
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[]);
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[]);
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr);
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int *data);
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char edid[]);
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
+void analogix_dp_reset_macro(struct analogix_dp_device *dp);
+void analogix_dp_init_video(struct analogix_dp_device *dp);
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+			enum clock_recovery_m_value_type type,
+			u32 m_value,
+			u32 n_value);
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_start_video(struct analogix_dp_device *dp);
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
+#endif /* _ANALOGIX_DP_CORE_H */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
new file mode 100644
index 0000000..442cc66
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -0,0 +1,1263 @@
+/*
+ * Analogix DP (Display port) core register interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include "analogix_dp_core.h"
+#include "analogix_dp_reg.h"
+
+#define COMMON_INT_MASK_1	0
+#define COMMON_INT_MASK_2	0
+#define COMMON_INT_MASK_3	0
+#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
+#define INT_STA_MASK		INT_HPD
+
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+		reg |= HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+		reg &= ~HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	}
+}
+
+void analogix_dp_stop_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	reg &= ~VIDEO_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+}
+
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable)
+		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
+			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+	else
+		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
+			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
+}
+
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = TX_TERMINAL_CTRL_50_OHM;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
+
+	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
+
+	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
+
+	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
+		TX_CUR1_2X | TX_CUR_16_MA;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
+
+	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
+		CH1_AMP_400_MV | CH0_AMP_400_MV;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
+}
+
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
+{
+	/* Set interrupt pin assertion polarity as high */
+	writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
+
+	/* Clear pending regisers */
+	writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+	writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
+	writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
+	writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+	writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	/* 0:mask,1: unmask */
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+void analogix_dp_reset(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	analogix_dp_stop_video(dp);
+	analogix_dp_enable_video_mute(dp, 0);
+
+	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
+		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
+		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+
+	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
+		SERDES_FIFO_FUNC_EN_N |
+		LS_CLK_DOMAIN_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+
+	usleep_range(20, 30);
+
+	analogix_dp_lane_swap(dp, 0);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
+
+	writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
+	writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
+
+	writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
+	writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
+
+	writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
+	writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
+
+	writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_swreset(struct analogix_dp_device *dp)
+{
+	writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
+}
+
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* 0: mask, 1: unmask */
+	reg = COMMON_INT_MASK_1;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+
+	reg = COMMON_INT_MASK_2;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+
+	reg = COMMON_INT_MASK_3;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+
+	reg = COMMON_INT_MASK_4;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+
+	reg = INT_STA_MASK;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+	if (reg & PLL_LOCK)
+		return PLL_LOCKED;
+	else
+		return PLL_UNLOCKED;
+}
+
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
+		reg |= DP_PLL_PD;
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
+		reg &= ~DP_PLL_PD;
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+	}
+}
+
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				enum analog_power_block block,
+				bool enable)
+{
+	u32 reg;
+
+	switch (block) {
+	case AUX_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= AUX_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~AUX_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH0_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH1_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH1_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH1_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH2_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH2_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH2_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH3_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH3_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH3_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case ANALOG_TOTAL:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= DP_PHY_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~DP_PHY_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case POWER_ALL:
+		if (enable) {
+			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
+				CH1_PD | CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
+{
+	u32 reg;
+	int timeout_loop = 0;
+
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
+
+	reg = PLL_LOCK_CHG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+
+	/* Power up PLL */
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		analogix_dp_set_pll_power_down(dp, 0);
+
+		while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+			timeout_loop++;
+			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+				dev_err(dp->dev, "failed to get pll lock status\n");
+				return;
+			}
+			usleep_range(10, 20);
+		}
+	}
+
+	/* Enable Serdes FIFO function and Link symbol clock domain module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
+		| AUX_FUNC_EN_N);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+
+	reg = INT_HPD;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+}
+
+void analogix_dp_init_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	analogix_dp_clear_hotplug_interrupts(dp);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg &= ~(F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		reg = gpio_get_value(dp->hpd_gpio);
+		if (reg)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+		else
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+	} else {
+		/* Parse hotplug interrupt status register */
+		reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+
+		if (reg & PLUG)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+
+		if (reg & HPD_LOST)
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+
+		if (reg & HOTPLUG_CHG)
+			return DP_IRQ_TYPE_HP_CHANGE;
+
+		return DP_IRQ_TYPE_UNKNOWN;
+	}
+}
+
+void analogix_dp_reset_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Disable AUX channel module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg |= AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+void analogix_dp_init_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Clear inerrupts related to AUX channel */
+	reg = RPLY_RECEIV | AUX_ERR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	analogix_dp_reset_aux(dp);
+
+	/* Disable AUX transaction H/W retry */
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
+		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
+
+	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
+	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
+
+	/* Enable AUX channel module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg &= ~AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		if (gpio_get_value(dp->hpd_gpio))
+			return 0;
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+		if (reg & HPD_STATUS)
+			return 0;
+	}
+
+	return -EINVAL;
+}
+
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+	reg &= ~SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+}
+
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
+{
+	int reg;
+	int retval = 0;
+	int timeout_loop = 0;
+
+	/* Enable AUX CH operation */
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+	reg |= AUX_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+
+	/* Is AUX CH command reply received? */
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+	while (!(reg & RPLY_RECEIV)) {
+		timeout_loop++;
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "AUX CH command reply failed!\n");
+			return -ETIMEDOUT;
+		}
+		reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+		usleep_range(10, 11);
+	}
+
+	/* Clear interrupt source for AUX CH command reply */
+	writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	/* Clear interrupt source for AUX CH access error */
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+	if (reg & AUX_ERR) {
+		writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
+		return -EREMOTEIO;
+	}
+
+	/* Check AUX CH error access status */
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
+	if ((reg & AUX_STATUS_MASK) != 0) {
+		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
+			reg & AUX_STATUS_MASK);
+		return -EREMOTEIO;
+	}
+
+	return retval;
+}
+
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+		/* Write data buffer */
+		reg = (unsigned int)data;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+		/*
+		 * Set DisplayPort transaction and write 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+		/*
+		 * Set DisplayPort transaction and read 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	/* Read data buffer */
+	reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+	*data = (unsigned char)(reg & 0xff);
+
+	return retval;
+}
+
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+			     cur_data_idx++) {
+				reg = data[start_offset + cur_data_idx];
+				writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+							  + 4 * cur_data_idx);
+			}
+
+			/*
+			 * Set DisplayPort transaction and write
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+			else
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		/* AUX CH Request Transaction process */
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+			/*
+			 * Set DisplayPort transaction and read
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+			else
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+		    cur_data_idx++) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			data[start_offset + cur_data_idx] =
+				(unsigned char)reg;
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr)
+{
+	u32 reg;
+	int retval;
+
+	/* Set EDID device address */
+	reg = device_addr;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+	/* Set offset from base address of EDID device */
+	writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+	/*
+	 * Set I2C transaction and write address
+	 * If bit 3 is 1, DisplayPort transaction.
+	 * If Bit 3 is 0, I2C transaction.
+	 */
+	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
+		AUX_TX_COMM_WRITE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+	/* Start AUX transaction */
+	retval = analogix_dp_start_aux_transaction(dp);
+	if (retval != 0)
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select EDID device */
+		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+		if (retval != 0)
+			continue;
+
+		/*
+		 * Set I2C transaction and read data
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_I2C_TRANSACTION |
+			AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	/* Read data */
+	if (retval == 0)
+		*data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char edid[])
+{
+	u32 reg;
+	unsigned int i, j;
+	unsigned int cur_data_idx;
+	unsigned int defer = 0;
+	int retval = 0;
+
+	for (i = 0; i < count; i += 16) {
+		for (j = 0; j < 3; j++) {
+			/* Clear AUX CH data buffer */
+			reg = BUF_CLR;
+			writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+			/* Set normal AUX CH command */
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+			reg &= ~ADDR_ONLY;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+
+			/*
+			 * If Rx sends defer, Tx sends only reads
+			 * request without sending address
+			 */
+			if (!defer)
+				retval = analogix_dp_select_i2c_device(dp,
+						device_addr, reg_addr + i);
+			else
+				defer = 0;
+
+			if (retval == 0) {
+				/*
+				 * Set I2C transaction and write data
+				 * If bit 3 is 1, DisplayPort transaction.
+				 * If Bit 3 is 0, I2C transaction.
+				 */
+				reg = AUX_LENGTH(16) |
+					AUX_TX_COMM_I2C_TRANSACTION |
+					AUX_TX_COMM_READ;
+				writel(reg, dp->reg_base +
+					ANALOGIX_DP_AUX_CH_CTL_1);
+
+				/* Start AUX transaction */
+				retval = analogix_dp_start_aux_transaction(dp);
+				if (retval == 0)
+					break;
+				else
+					dev_dbg(dp->dev,
+						"%s: Aux Transaction fail!\n",
+						__func__);
+			}
+			/* Check if Rx sends defer */
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
+			if (reg == AUX_RX_COMM_AUX_DEFER ||
+				reg == AUX_RX_COMM_I2C_DEFER) {
+				dev_err(dp->dev, "Defer: %d\n\n", reg);
+				defer = 1;
+			}
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			edid[i + cur_data_idx] = (unsigned char)reg;
+		}
+	}
+
+	return retval;
+}
+
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
+{
+	u32 reg;
+
+	reg = bwtype;
+	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
+		writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
+}
+
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
+	*bwtype = reg;
+}
+
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
+{
+	u32 reg;
+
+	reg = count;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
+}
+
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
+	*count = reg;
+}
+
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg |= ENHANCED;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg &= ~ENHANCED;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+	}
+}
+
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				enum pattern_set pattern)
+{
+	u32 reg;
+
+	switch (pattern) {
+	case PRBS7:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case D10_2:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN1:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN2:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case DP_NONE:
+		reg = SCRAMBLING_ENABLE |
+			LINK_QUAL_PATTERN_SET_DISABLE |
+			SW_TRAINING_PATTERN_SET_NORMAL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+}
+
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+	return reg;
+}
+
+void analogix_dp_reset_macro(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
+	reg |= MACRO_RST;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+
+	/* 10 us is the minimum reset time. */
+	usleep_range(10, 20);
+
+	reg &= ~MACRO_RST;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+}
+
+void analogix_dp_init_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	reg = CHA_CRI(4) | CHA_CTRL;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+
+	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
+}
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Configure the input color depth, color space, dynamic range */
+	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info->color_depth << IN_BPC_SHIFT) |
+		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
+
+	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
+	reg &= ~IN_YC_COEFFI_MASK;
+	if (dp->video_info->ycbcr_coeff)
+		reg |= IN_YC_COEFFI_ITU709;
+	else
+		reg |= IN_YC_COEFFI_ITU601;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
+}
+
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	if (!(reg & DET_STA)) {
+		dev_dbg(dp->dev, "Input stream clock not detected.\n");
+		return -EINVAL;
+	}
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
+
+	if (reg & CHA_STA) {
+		dev_dbg(dp->dev, "Input stream clk is changing\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+		enum clock_recovery_m_value_type type,
+		u32 m_value,
+		u32 n_value)
+{
+	u32 reg;
+
+	if (type == REGISTER_M) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg |= FIX_M_VID;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg = m_value & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
+		reg = (m_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
+		reg = (m_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
+
+		reg = n_value & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		reg = (n_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		reg = (n_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
+	} else  {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg &= ~FIX_M_VID;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
+	}
+}
+
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
+{
+	u32 reg;
+
+	if (type == VIDEO_TIMING_FROM_CAPTURE) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+		reg &= ~FORMAT_SEL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+		reg |= FORMAT_SEL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	}
+}
+
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MODE_SLAVE_MODE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+	}
+}
+
+void analogix_dp_start_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	reg |= VIDEO_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+}
+
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	if (!(reg & STRM_VALID)) {
+		dev_dbg(dp->dev, "Input video stream is not detected.\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg |= MASTER_VID_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~INTERACE_SCAN_CFG;
+	reg |= (dp->video_info->interlaced << 2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~VSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->v_sync_polarity << 1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~HSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->h_sync_polarity << 0);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+	reg &= ~SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+}
+
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+	reg |= SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
similarity index 64%
rename from drivers/gpu/drm/exynos/exynos_dp_reg.h
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 2e9bd0e..738db4c 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -1,5 +1,5 @@
 /*
- * Register definition file for Samsung DP driver
+ * Register definition file for Analogix DP core driver
  *
  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  * Author: Jingoo Han <jg1.han@samsung.com>
@@ -9,96 +9,96 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef _EXYNOS_DP_REG_H
-#define _EXYNOS_DP_REG_H
-
-#define EXYNOS_DP_TX_SW_RESET			0x14
-#define EXYNOS_DP_FUNC_EN_1			0x18
-#define EXYNOS_DP_FUNC_EN_2			0x1C
-#define EXYNOS_DP_VIDEO_CTL_1			0x20
-#define EXYNOS_DP_VIDEO_CTL_2			0x24
-#define EXYNOS_DP_VIDEO_CTL_3			0x28
-
-#define EXYNOS_DP_VIDEO_CTL_8			0x3C
-#define EXYNOS_DP_VIDEO_CTL_10			0x44
-
-#define EXYNOS_DP_LANE_MAP			0x35C
-
-#define EXYNOS_DP_ANALOG_CTL_1			0x370
-#define EXYNOS_DP_ANALOG_CTL_2			0x374
-#define EXYNOS_DP_ANALOG_CTL_3			0x378
-#define EXYNOS_DP_PLL_FILTER_CTL_1		0x37C
-#define EXYNOS_DP_TX_AMP_TUNING_CTL		0x380
-
-#define EXYNOS_DP_AUX_HW_RETRY_CTL		0x390
-
-#define EXYNOS_DP_COMMON_INT_STA_1		0x3C4
-#define EXYNOS_DP_COMMON_INT_STA_2		0x3C8
-#define EXYNOS_DP_COMMON_INT_STA_3		0x3CC
-#define EXYNOS_DP_COMMON_INT_STA_4		0x3D0
-#define EXYNOS_DP_INT_STA			0x3DC
-#define EXYNOS_DP_COMMON_INT_MASK_1		0x3E0
-#define EXYNOS_DP_COMMON_INT_MASK_2		0x3E4
-#define EXYNOS_DP_COMMON_INT_MASK_3		0x3E8
-#define EXYNOS_DP_COMMON_INT_MASK_4		0x3EC
-#define EXYNOS_DP_INT_STA_MASK			0x3F8
-#define EXYNOS_DP_INT_CTL			0x3FC
-
-#define EXYNOS_DP_SYS_CTL_1			0x600
-#define EXYNOS_DP_SYS_CTL_2			0x604
-#define EXYNOS_DP_SYS_CTL_3			0x608
-#define EXYNOS_DP_SYS_CTL_4			0x60C
-
-#define EXYNOS_DP_PKT_SEND_CTL			0x640
-#define EXYNOS_DP_HDCP_CTL			0x648
-
-#define EXYNOS_DP_LINK_BW_SET			0x680
-#define EXYNOS_DP_LANE_COUNT_SET		0x684
-#define EXYNOS_DP_TRAINING_PTN_SET		0x688
-#define EXYNOS_DP_LN0_LINK_TRAINING_CTL		0x68C
-#define EXYNOS_DP_LN1_LINK_TRAINING_CTL		0x690
-#define EXYNOS_DP_LN2_LINK_TRAINING_CTL		0x694
-#define EXYNOS_DP_LN3_LINK_TRAINING_CTL		0x698
-
-#define EXYNOS_DP_DEBUG_CTL			0x6C0
-#define EXYNOS_DP_HPD_DEGLITCH_L		0x6C4
-#define EXYNOS_DP_HPD_DEGLITCH_H		0x6C8
-#define EXYNOS_DP_LINK_DEBUG_CTL		0x6E0
-
-#define EXYNOS_DP_M_VID_0			0x700
-#define EXYNOS_DP_M_VID_1			0x704
-#define EXYNOS_DP_M_VID_2			0x708
-#define EXYNOS_DP_N_VID_0			0x70C
-#define EXYNOS_DP_N_VID_1			0x710
-#define EXYNOS_DP_N_VID_2			0x714
-
-#define EXYNOS_DP_PLL_CTL			0x71C
-#define EXYNOS_DP_PHY_PD			0x720
-#define EXYNOS_DP_PHY_TEST			0x724
-
-#define EXYNOS_DP_VIDEO_FIFO_THRD		0x730
-#define EXYNOS_DP_AUDIO_MARGIN			0x73C
-
-#define EXYNOS_DP_M_VID_GEN_FILTER_TH		0x764
-#define EXYNOS_DP_M_AUD_GEN_FILTER_TH		0x778
-#define EXYNOS_DP_AUX_CH_STA			0x780
-#define EXYNOS_DP_AUX_CH_DEFER_CTL		0x788
-#define EXYNOS_DP_AUX_RX_COMM			0x78C
-#define EXYNOS_DP_BUFFER_DATA_CTL		0x790
-#define EXYNOS_DP_AUX_CH_CTL_1			0x794
-#define EXYNOS_DP_AUX_ADDR_7_0			0x798
-#define EXYNOS_DP_AUX_ADDR_15_8			0x79C
-#define EXYNOS_DP_AUX_ADDR_19_16		0x7A0
-#define EXYNOS_DP_AUX_CH_CTL_2			0x7A4
-
-#define EXYNOS_DP_BUF_DATA_0			0x7C0
-
-#define EXYNOS_DP_SOC_GENERAL_CTL		0x800
-
-/* EXYNOS_DP_TX_SW_RESET */
+#ifndef _ANALOGIX_DP_REG_H
+#define _ANALOGIX_DP_REG_H
+
+#define ANALOGIX_DP_TX_SW_RESET			0x14
+#define ANALOGIX_DP_FUNC_EN_1			0x18
+#define ANALOGIX_DP_FUNC_EN_2			0x1C
+#define ANALOGIX_DP_VIDEO_CTL_1			0x20
+#define ANALOGIX_DP_VIDEO_CTL_2			0x24
+#define ANALOGIX_DP_VIDEO_CTL_3			0x28
+
+#define ANALOGIX_DP_VIDEO_CTL_8			0x3C
+#define ANALOGIX_DP_VIDEO_CTL_10		0x44
+
+#define ANALOGIX_DP_LANE_MAP			0x35C
+
+#define ANALOGIX_DP_ANALOG_CTL_1		0x370
+#define ANALOGIX_DP_ANALOG_CTL_2		0x374
+#define ANALOGIX_DP_ANALOG_CTL_3		0x378
+#define ANALOGIX_DP_PLL_FILTER_CTL_1		0x37C
+#define ANALOGIX_DP_TX_AMP_TUNING_CTL		0x380
+
+#define ANALOGIX_DP_AUX_HW_RETRY_CTL		0x390
+
+#define ANALOGIX_DP_COMMON_INT_STA_1		0x3C4
+#define ANALOGIX_DP_COMMON_INT_STA_2		0x3C8
+#define ANALOGIX_DP_COMMON_INT_STA_3		0x3CC
+#define ANALOGIX_DP_COMMON_INT_STA_4		0x3D0
+#define ANALOGIX_DP_INT_STA			0x3DC
+#define ANALOGIX_DP_COMMON_INT_MASK_1		0x3E0
+#define ANALOGIX_DP_COMMON_INT_MASK_2		0x3E4
+#define ANALOGIX_DP_COMMON_INT_MASK_3		0x3E8
+#define ANALOGIX_DP_COMMON_INT_MASK_4		0x3EC
+#define ANALOGIX_DP_INT_STA_MASK		0x3F8
+#define ANALOGIX_DP_INT_CTL			0x3FC
+
+#define ANALOGIX_DP_SYS_CTL_1			0x600
+#define ANALOGIX_DP_SYS_CTL_2			0x604
+#define ANALOGIX_DP_SYS_CTL_3			0x608
+#define ANALOGIX_DP_SYS_CTL_4			0x60C
+
+#define ANALOGIX_DP_PKT_SEND_CTL		0x640
+#define ANALOGIX_DP_HDCP_CTL			0x648
+
+#define ANALOGIX_DP_LINK_BW_SET			0x680
+#define ANALOGIX_DP_LANE_COUNT_SET		0x684
+#define ANALOGIX_DP_TRAINING_PTN_SET		0x688
+#define ANALOGIX_DP_LN0_LINK_TRAINING_CTL	0x68C
+#define ANALOGIX_DP_LN1_LINK_TRAINING_CTL	0x690
+#define ANALOGIX_DP_LN2_LINK_TRAINING_CTL	0x694
+#define ANALOGIX_DP_LN3_LINK_TRAINING_CTL	0x698
+
+#define ANALOGIX_DP_DEBUG_CTL			0x6C0
+#define ANALOGIX_DP_HPD_DEGLITCH_L		0x6C4
+#define ANALOGIX_DP_HPD_DEGLITCH_H		0x6C8
+#define ANALOGIX_DP_LINK_DEBUG_CTL		0x6E0
+
+#define ANALOGIX_DP_M_VID_0			0x700
+#define ANALOGIX_DP_M_VID_1			0x704
+#define ANALOGIX_DP_M_VID_2			0x708
+#define ANALOGIX_DP_N_VID_0			0x70C
+#define ANALOGIX_DP_N_VID_1			0x710
+#define ANALOGIX_DP_N_VID_2			0x714
+
+#define ANALOGIX_DP_PLL_CTL			0x71C
+#define ANALOGIX_DP_PHY_PD			0x720
+#define ANALOGIX_DP_PHY_TEST			0x724
+
+#define ANALOGIX_DP_VIDEO_FIFO_THRD		0x730
+#define ANALOGIX_DP_AUDIO_MARGIN		0x73C
+
+#define ANALOGIX_DP_M_VID_GEN_FILTER_TH		0x764
+#define ANALOGIX_DP_M_AUD_GEN_FILTER_TH		0x778
+#define ANALOGIX_DP_AUX_CH_STA			0x780
+#define ANALOGIX_DP_AUX_CH_DEFER_CTL		0x788
+#define ANALOGIX_DP_AUX_RX_COMM			0x78C
+#define ANALOGIX_DP_BUFFER_DATA_CTL		0x790
+#define ANALOGIX_DP_AUX_CH_CTL_1		0x794
+#define ANALOGIX_DP_AUX_ADDR_7_0		0x798
+#define ANALOGIX_DP_AUX_ADDR_15_8		0x79C
+#define ANALOGIX_DP_AUX_ADDR_19_16		0x7A0
+#define ANALOGIX_DP_AUX_CH_CTL_2		0x7A4
+
+#define ANALOGIX_DP_BUF_DATA_0			0x7C0
+
+#define ANALOGIX_DP_SOC_GENERAL_CTL		0x800
+
+/* ANALOGIX_DP_TX_SW_RESET */
 #define RESET_DP_TX				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_1 */
+/* ANALOGIX_DP_FUNC_EN_1 */
 #define MASTER_VID_FUNC_EN_N			(0x1 << 7)
 #define SLAVE_VID_FUNC_EN_N			(0x1 << 5)
 #define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
@@ -107,17 +107,17 @@
 #define CRC_FUNC_EN_N				(0x1 << 1)
 #define SW_FUNC_EN_N				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_2 */
+/* ANALOGIX_DP_FUNC_EN_2 */
 #define SSC_FUNC_EN_N				(0x1 << 7)
 #define AUX_FUNC_EN_N				(0x1 << 2)
 #define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
 #define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define VIDEO_EN				(0x1 << 7)
 #define HDCP_VIDEO_MUTE				(0x1 << 6)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define IN_D_RANGE_MASK				(0x1 << 7)
 #define IN_D_RANGE_SHIFT			(7)
 #define IN_D_RANGE_CEA				(0x1 << 7)
@@ -134,7 +134,7 @@
 #define IN_COLOR_F_YCBCR422			(0x1 << 0)
 #define IN_COLOR_F_RGB				(0x0 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_3 */
+/* ANALOGIX_DP_VIDEO_CTL_3 */
 #define IN_YC_COEFFI_MASK			(0x1 << 7)
 #define IN_YC_COEFFI_SHIFT			(7)
 #define IN_YC_COEFFI_ITU709			(0x1 << 7)
@@ -144,17 +144,17 @@
 #define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
 #define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
 
-/* EXYNOS_DP_VIDEO_CTL_8 */
+/* ANALOGIX_DP_VIDEO_CTL_8 */
 #define VID_HRES_TH(x)				(((x) & 0xf) << 4)
 #define VID_VRES_TH(x)				(((x) & 0xf) << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_10 */
+/* ANALOGIX_DP_VIDEO_CTL_10 */
 #define FORMAT_SEL				(0x1 << 4)
 #define INTERACE_SCAN_CFG			(0x1 << 2)
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
-/* EXYNOS_DP_LANE_MAP */
+/* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
 #define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
@@ -172,30 +172,30 @@
 #define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
 #define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_1 */
+/* ANALOGIX_DP_ANALOG_CTL_1 */
 #define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
 
-/* EXYNOS_DP_ANALOG_CTL_2 */
+/* ANALOGIX_DP_ANALOG_CTL_2 */
 #define SEL_24M					(0x1 << 3)
 #define TX_DVDD_BIT_1_0625V			(0x4 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_3 */
+/* ANALOGIX_DP_ANALOG_CTL_3 */
 #define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
 #define VCO_BIT_600_MICRO			(0x5 << 0)
 
-/* EXYNOS_DP_PLL_FILTER_CTL_1 */
+/* ANALOGIX_DP_PLL_FILTER_CTL_1 */
 #define PD_RING_OSC				(0x1 << 6)
 #define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
 #define TX_CUR1_2X				(0x1 << 2)
 #define TX_CUR_16_MA				(0x3 << 0)
 
-/* EXYNOS_DP_TX_AMP_TUNING_CTL */
+/* ANALOGIX_DP_TX_AMP_TUNING_CTL */
 #define CH3_AMP_400_MV				(0x0 << 24)
 #define CH2_AMP_400_MV				(0x0 << 16)
 #define CH1_AMP_400_MV				(0x0 << 8)
 #define CH0_AMP_400_MV				(0x0 << 0)
 
-/* EXYNOS_DP_AUX_HW_RETRY_CTL */
+/* ANALOGIX_DP_AUX_HW_RETRY_CTL */
 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x)	(((x) & 0x7) << 8)
 #define AUX_HW_RETRY_INTERVAL_MASK		(0x3 << 3)
 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS	(0x0 << 3)
@@ -204,7 +204,7 @@
 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS	(0x3 << 3)
 #define AUX_HW_RETRY_COUNT_SEL(x)		(((x) & 0x7) << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_1 */
+/* ANALOGIX_DP_COMMON_INT_STA_1 */
 #define VSYNC_DET				(0x1 << 7)
 #define PLL_LOCK_CHG				(0x1 << 6)
 #define SPDIF_ERR				(0x1 << 5)
@@ -214,19 +214,19 @@
 #define VID_CLK_CHG				(0x1 << 1)
 #define SW_INT					(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_2 */
+/* ANALOGIX_DP_COMMON_INT_STA_2 */
 #define ENC_EN_CHG				(0x1 << 6)
 #define HW_BKSV_RDY				(0x1 << 3)
 #define HW_SHA_DONE				(0x1 << 2)
 #define HW_AUTH_STATE_CHG			(0x1 << 1)
 #define HW_AUTH_DONE				(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_3 */
+/* ANALOGIX_DP_COMMON_INT_STA_3 */
 #define AFIFO_UNDER				(0x1 << 7)
 #define AFIFO_OVER				(0x1 << 6)
 #define R0_CHK_FLAG				(0x1 << 5)
 
-/* EXYNOS_DP_COMMON_INT_STA_4 */
+/* ANALOGIX_DP_COMMON_INT_STA_4 */
 #define PSR_ACTIVE				(0x1 << 7)
 #define PSR_INACTIVE				(0x1 << 6)
 #define SPDIF_BI_PHASE_ERR			(0x1 << 5)
@@ -234,29 +234,29 @@
 #define HPD_LOST				(0x1 << 1)
 #define PLUG					(0x1 << 0)
 
-/* EXYNOS_DP_INT_STA */
+/* ANALOGIX_DP_INT_STA */
 #define INT_HPD					(0x1 << 6)
 #define HW_TRAINING_FINISH			(0x1 << 5)
 #define RPLY_RECEIV				(0x1 << 1)
 #define AUX_ERR					(0x1 << 0)
 
-/* EXYNOS_DP_INT_CTL */
+/* ANALOGIX_DP_INT_CTL */
 #define SOFT_INT_CTRL				(0x1 << 2)
 #define INT_POL1				(0x1 << 1)
 #define INT_POL0				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_1 */
+/* ANALOGIX_DP_SYS_CTL_1 */
 #define DET_STA					(0x1 << 2)
 #define FORCE_DET				(0x1 << 1)
 #define DET_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_2 */
+/* ANALOGIX_DP_SYS_CTL_2 */
 #define CHA_CRI(x)				(((x) & 0xf) << 4)
 #define CHA_STA					(0x1 << 2)
 #define FORCE_CHA				(0x1 << 1)
 #define CHA_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_3 */
+/* ANALOGIX_DP_SYS_CTL_3 */
 #define HPD_STATUS				(0x1 << 6)
 #define F_HPD					(0x1 << 5)
 #define HPD_CTRL				(0x1 << 4)
@@ -265,13 +265,13 @@
 #define F_VALID					(0x1 << 1)
 #define VALID_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_4 */
+/* ANALOGIX_DP_SYS_CTL_4 */
 #define FIX_M_AUD				(0x1 << 4)
 #define ENHANCED				(0x1 << 3)
 #define FIX_M_VID				(0x1 << 2)
 #define M_VID_UPDATE_CTRL			(0x3 << 0)
 
-/* EXYNOS_DP_TRAINING_PTN_SET */
+/* ANALOGIX_DP_TRAINING_PTN_SET */
 #define SCRAMBLER_TYPE				(0x1 << 9)
 #define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
 #define SCRAMBLING_DISABLE			(0x1 << 5)
@@ -285,24 +285,24 @@
 #define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
 #define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
 
-/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+/* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */
 #define PRE_EMPHASIS_SET_MASK			(0x3 << 3)
 #define PRE_EMPHASIS_SET_SHIFT			(3)
 
-/* EXYNOS_DP_DEBUG_CTL */
+/* ANALOGIX_DP_DEBUG_CTL */
 #define PLL_LOCK				(0x1 << 4)
 #define F_PLL_LOCK				(0x1 << 3)
 #define PLL_LOCK_CTRL				(0x1 << 2)
 #define PN_INV					(0x1 << 0)
 
-/* EXYNOS_DP_PLL_CTL */
+/* ANALOGIX_DP_PLL_CTL */
 #define DP_PLL_PD				(0x1 << 7)
 #define DP_PLL_RESET				(0x1 << 6)
 #define DP_PLL_LOOP_BIT_DEFAULT			(0x1 << 4)
 #define DP_PLL_REF_BIT_1_1250V			(0x5 << 0)
 #define DP_PLL_REF_BIT_1_2500V			(0x7 << 0)
 
-/* EXYNOS_DP_PHY_PD */
+/* ANALOGIX_DP_PHY_PD */
 #define DP_PHY_PD				(0x1 << 5)
 #define AUX_PD					(0x1 << 4)
 #define CH3_PD					(0x1 << 3)
@@ -310,28 +310,28 @@
 #define CH1_PD					(0x1 << 1)
 #define CH0_PD					(0x1 << 0)
 
-/* EXYNOS_DP_PHY_TEST */
+/* ANALOGIX_DP_PHY_TEST */
 #define MACRO_RST				(0x1 << 5)
 #define CH1_TEST				(0x1 << 1)
 #define CH0_TEST				(0x1 << 0)
 
-/* EXYNOS_DP_AUX_CH_STA */
+/* ANALOGIX_DP_AUX_CH_STA */
 #define AUX_BUSY				(0x1 << 4)
 #define AUX_STATUS_MASK				(0xf << 0)
 
-/* EXYNOS_DP_AUX_CH_DEFER_CTL */
+/* ANALOGIX_DP_AUX_CH_DEFER_CTL */
 #define DEFER_CTRL_EN				(0x1 << 7)
 #define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
 
-/* EXYNOS_DP_AUX_RX_COMM */
+/* ANALOGIX_DP_AUX_RX_COMM */
 #define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
 #define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
 
-/* EXYNOS_DP_BUFFER_DATA_CTL */
+/* ANALOGIX_DP_BUFFER_DATA_CTL */
 #define BUF_CLR					(0x1 << 7)
 #define BUF_DATA_COUNT(x)			(((x) & 0x1f) << 0)
 
-/* EXYNOS_DP_AUX_CH_CTL_1 */
+/* ANALOGIX_DP_AUX_CH_CTL_1 */
 #define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
 #define AUX_TX_COMM_MASK			(0xf << 0)
 #define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
@@ -340,20 +340,20 @@
 #define AUX_TX_COMM_WRITE			(0x0 << 0)
 #define AUX_TX_COMM_READ			(0x1 << 0)
 
-/* EXYNOS_DP_AUX_ADDR_7_0 */
+/* ANALOGIX_DP_AUX_ADDR_7_0 */
 #define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_15_8 */
+/* ANALOGIX_DP_AUX_ADDR_15_8 */
 #define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_19_16 */
+/* ANALOGIX_DP_AUX_ADDR_19_16 */
 #define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
 
-/* EXYNOS_DP_AUX_CH_CTL_2 */
+/* ANALOGIX_DP_AUX_CH_CTL_2 */
 #define ADDR_ONLY				(0x1 << 1)
 #define AUX_EN					(0x1 << 0)
 
-/* EXYNOS_DP_SOC_GENERAL_CTL */
+/* ANALOGIX_DP_SOC_GENERAL_CTL */
 #define AUDIO_MODE_SPDIF_MODE			(0x1 << 8)
 #define AUDIO_MODE_MASTER_MODE			(0x0 << 8)
 #define MASTER_VIDEO_INTERLACE_EN		(0x1 << 4)
@@ -363,4 +363,4 @@
 #define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
 #define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
 
-#endif /* _EXYNOS_DP_REG_H */
+#endif /* _ANALOGIX_DP_REG_H */
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index bd1a415..5f74f80 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -55,8 +55,9 @@ config DRM_EXYNOS_DSI
 	  This enables support for Exynos MIPI-DSI device.
 
 config DRM_EXYNOS_DP
-	bool "EXYNOS DRM DP driver support"
+	bool "EXYNOS specific extensions for Analogix DP driver"
 	depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON)
+	select DRM_ANALOGIX_DP
 	default DRM_EXYNOS
 	select DRM_PANEL
 	help
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index 02aecfe..4453798 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -13,7 +13,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON)	+= exynos5433_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON)	+= exynos7_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DPI)	+= exynos_drm_dpi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DSI)	+= exynos_drm_dsi.o
-exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o exynos_dp_reg.o
+exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)	+= exynos_hdmi.o exynos_mixer.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI)	+= exynos_drm_vidi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_G2D)	+= exynos_drm_g2d.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
new file mode 100644
index 0000000..83feb21
--- /dev/null
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -0,0 +1,349 @@
+/*
+ * Samsung SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_graph.h>
+#include <video/of_display_timing.h>
+#include <video/of_videomode.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+
+#include <drm/bridge/analogix_dp.h>
+#include <drm/exynos_drm.h>
+
+#include "exynos_drm_crtc.h"
+
+#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
+
+struct exynos_dp_device {
+	struct drm_encoder         encoder;
+	struct drm_connector       connector;
+	struct drm_bridge          *ptn_bridge;
+	struct drm_device          *drm_dev;
+	struct device              *dev;
+
+	struct exynos_drm_panel_info priv;
+	struct analogix_dp_plat_data plat_data;
+};
+
+int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
+				bool enable)
+{
+	struct exynos_dp_device *dp = to_dp(plat_data);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct exynos_drm_crtc *crtc;
+
+	if (!encoder)
+		return -1;
+
+	crtc = to_exynos_crtc(encoder->crtc);
+	if (crtc && crtc->ops && crtc->ops->clock_enable)
+		crtc->ops->clock_enable(crtc, enable);
+
+	return 0;
+}
+
+static int exynos_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	return exynos_dp_crtc_clock_enable(plat_data, true);
+}
+
+static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
+{
+	return exynos_dp_crtc_clock_enable(plat_data, false);
+}
+
+static int exynos_dp_get_modes(struct drm_connector *connector)
+{
+	struct exynos_dp_device *dp = to_dp(connector);
+	struct drm_display_mode *mode;
+	int num_modes = 0;
+
+	num_modes += analogix_dp_get_modes(dp->dev);
+
+	if (dp->plat_data.panel)
+		return num_modes;
+
+	mode = drm_mode_create(connector->dev);
+	if (!mode) {
+		DRM_ERROR("failed to create a new display mode.\n");
+		return num_modes;
+	}
+
+	drm_display_mode_from_videomode(&dp->priv.vm, mode);
+	mode->width_mm = dp->priv.width_mm;
+	mode->height_mm = dp->priv.height_mm;
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_set_name(mode);
+	drm_mode_probed_add(connector, mode);
+
+	return num_modes + 1;
+}
+
+static struct drm_encoder *
+exynos_dp_best_encoder(struct drm_connector *connector)
+{
+	struct exynos_dp_device *dp = to_dp(connector);
+
+	return &dp->encoder;
+}
+
+static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
+	.get_modes = exynos_dp_get_modes,
+	.best_encoder = exynos_dp_best_encoder,
+};
+
+static enum drm_connector_status
+exynos_dp_detect(struct drm_connector *connector, bool force)
+{
+	struct exynos_dp_device *dp = to_dp(connector);
+
+	return analogix_dp_detect(dp->dev, force);
+}
+
+static void exynos_dp_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static struct drm_connector_funcs exynos_dp_connector_funcs = {
+	.dpms = drm_atomic_helper_connector_dpms,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.detect = exynos_dp_detect,
+	.destroy = exynos_dp_connector_destroy,
+	.reset = drm_atomic_helper_connector_reset,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+				   struct drm_bridge *bridge)
+{
+	struct exynos_dp_device *dp = to_dp(plat_data);
+	struct drm_connector *connector = &dp->connector;
+	struct drm_encoder *encoder = &dp->encoder;
+	int ret;
+
+	/* Pre-empt DP connector creation if there's a bridge */
+	if (dp->ptn_bridge) {
+		bridge->next = dp->ptn_bridge;
+		dp->ptn_bridge->encoder = encoder;
+		ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
+		if (ret) {
+			DRM_ERROR("Failed to attach bridge to drm\n");
+			bridge->next = NULL;
+			return ret;
+		}
+	}
+
+	connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+	ret = drm_connector_init(dp->drm_dev, connector,
+				 &exynos_dp_connector_funcs,
+				 DRM_MODE_CONNECTOR_eDP);
+	if (ret) {
+		DRM_ERROR("Failed to initialize connector with drm\n");
+		return ret;
+	}
+
+	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
+	drm_connector_register(connector);
+	drm_mode_connector_attach_encoder(connector, encoder);
+
+	dp->plat_data.connector = connector;
+
+	return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+				 const struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
+static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
+	.mode_fixup = exynos_dp_mode_fixup,
+	.mode_set = exynos_dp_mode_set,
+	.enable = exynos_dp_enable,
+	.disable = exynos_dp_disable,
+};
+
+static struct drm_encoder_funcs exynos_dp_encoder_funcs = {
+	.destroy = drm_encoder_cleanup,
+};
+
+static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
+{
+	int ret;
+
+	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
+			       OF_USE_NATIVE_MODE);
+	if (ret) {
+		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
+		return ret;
+	}
+	return 0;
+}
+
+static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
+{
+	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = data;
+	int pipe, ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	dp->dev = dev;
+	dp->drm_dev = drm_dev;
+
+	dp->plat_data.dev_type = EXYNOS_DP;
+	dp->plat_data.power_on = exynos_dp_poweron;
+	dp->plat_data.power_off = exynos_dp_poweroff;
+	dp->plat_data.attach = exynos_dp_bridge_attach;
+
+	if (!dp->plat_data.panel && !dp->ptn_bridge) {
+		ret = exynos_dp_dt_parse_panel(dp);
+		if (ret)
+			return ret;
+	}
+
+	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
+						  EXYNOS_DISPLAY_TYPE_LCD);
+	if (pipe < 0)
+		return pipe;
+
+	encoder->possible_crtcs = 1 << pipe;
+
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
+			 DRM_MODE_ENCODER_TMDS);
+
+	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
+
+	dp->plat_data.encoder = encoder;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
+}
+
+static void exynos_dp_unbind(struct device *dev, struct device *master,
+			     void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops exynos_dp_ops = {
+	.bind	= exynos_dp_bind,
+	.unbind	= exynos_dp_unbind,
+};
+
+static int exynos_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *bridge_node, *endpoint;
+	struct exynos_dp_device *dp;
+
+	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
+			  GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver would take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	panel_node = of_parse_phandle(dev->of_node, "panel", 0);
+	if (panel_node) {
+		dp->plat_data.panel = of_drm_find_panel(panel_node);
+		of_node_put(panel_node);
+		if (!dp->plat_data.panel)
+			return -EPROBE_DEFER;
+	}
+
+	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
+	if (endpoint) {
+		bridge_node = of_graph_get_remote_port_parent(endpoint);
+		if (bridge_node) {
+			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
+			of_node_put(bridge_node);
+			if (!dp->ptn_bridge)
+				return -EPROBE_DEFER;
+		} else {
+			return -EPROBE_DEFER;
+		}
+	}
+
+	return component_add(&pdev->dev, &exynos_dp_ops);
+}
+
+static int exynos_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &exynos_dp_ops);
+
+	return 0;
+}
+
+static const struct of_device_id exynos_dp_match[] = {
+	{ .compatible = "samsung,exynos5-dp" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, exynos_dp_match);
+
+struct platform_driver dp_driver = {
+	.probe		= exynos_dp_probe,
+	.remove		= exynos_dp_remove,
+	.driver		= {
+		.name	= "exynos-dp",
+		.owner	= THIS_MODULE,
+		.of_match_table = exynos_dp_match,
+	},
+};
+
+MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
+MODULE_DESCRIPTION("Samsung Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
deleted file mode 100644
index 66eec4b..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Header file for Samsung DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef _EXYNOS_DP_CORE_H
-#define _EXYNOS_DP_CORE_H
-
-#include <drm/drm_crtc.h>
-#include <drm/drm_dp_helper.h>
-#include <drm/exynos_drm.h>
-
-#include "exynos_drm_drv.h"
-
-#define DP_TIMEOUT_LOOP_COUNT 100
-#define MAX_CR_LOOP 5
-#define MAX_EQ_LOOP 5
-
-enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
-};
-
-enum link_lane_count_type {
-	LANE_COUNT1 = 1,
-	LANE_COUNT2 = 2,
-	LANE_COUNT4 = 4
-};
-
-enum link_training_state {
-	START,
-	CLOCK_RECOVERY,
-	EQUALIZER_TRAINING,
-	FINISHED,
-	FAILED
-};
-
-enum voltage_swing_level {
-	VOLTAGE_LEVEL_0,
-	VOLTAGE_LEVEL_1,
-	VOLTAGE_LEVEL_2,
-	VOLTAGE_LEVEL_3,
-};
-
-enum pre_emphasis_level {
-	PRE_EMPHASIS_LEVEL_0,
-	PRE_EMPHASIS_LEVEL_1,
-	PRE_EMPHASIS_LEVEL_2,
-	PRE_EMPHASIS_LEVEL_3,
-};
-
-enum pattern_set {
-	PRBS7,
-	D10_2,
-	TRAINING_PTN1,
-	TRAINING_PTN2,
-	DP_NONE
-};
-
-enum color_space {
-	COLOR_RGB,
-	COLOR_YCBCR422,
-	COLOR_YCBCR444
-};
-
-enum color_depth {
-	COLOR_6,
-	COLOR_8,
-	COLOR_10,
-	COLOR_12
-};
-
-enum color_coefficient {
-	COLOR_YCBCR601,
-	COLOR_YCBCR709
-};
-
-enum dynamic_range {
-	VESA,
-	CEA
-};
-
-enum pll_status {
-	PLL_UNLOCKED,
-	PLL_LOCKED
-};
-
-enum clock_recovery_m_value_type {
-	CALCULATED_M,
-	REGISTER_M
-};
-
-enum video_timing_recognition_type {
-	VIDEO_TIMING_FROM_CAPTURE,
-	VIDEO_TIMING_FROM_REGISTER
-};
-
-enum analog_power_block {
-	AUX_BLOCK,
-	CH0_BLOCK,
-	CH1_BLOCK,
-	CH2_BLOCK,
-	CH3_BLOCK,
-	ANALOG_TOTAL,
-	POWER_ALL
-};
-
-enum dp_irq_type {
-	DP_IRQ_TYPE_HP_CABLE_IN,
-	DP_IRQ_TYPE_HP_CABLE_OUT,
-	DP_IRQ_TYPE_HP_CHANGE,
-	DP_IRQ_TYPE_UNKNOWN,
-};
-
-struct video_info {
-	char *name;
-
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
-
-	enum color_space color_space;
-	enum dynamic_range dynamic_range;
-	enum color_coefficient ycbcr_coeff;
-	enum color_depth color_depth;
-
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
-};
-
-struct link_train {
-	int eq_loop;
-	int cr_loop[4];
-
-	u8 link_rate;
-	u8 lane_count;
-	u8 training_lane[4];
-
-	enum link_training_state lt_state;
-};
-
-struct exynos_dp_device {
-	struct drm_encoder	encoder;
-	struct device		*dev;
-	struct drm_device	*drm_dev;
-	struct drm_connector	connector;
-	struct drm_panel	*panel;
-	struct drm_bridge	*bridge;
-	struct drm_bridge	*ptn_bridge;
-	struct clk		*clock;
-	unsigned int		irq;
-	void __iomem		*reg_base;
-
-	struct video_info	*video_info;
-	struct link_train	link_train;
-	struct work_struct	hotplug_work;
-	struct phy		*phy;
-	int			dpms_mode;
-	int			hpd_gpio;
-
-	struct exynos_drm_panel_info priv;
-};
-
-/* exynos_dp_reg.c */
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_stop_video(struct exynos_dp_device *dp);
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
-void exynos_dp_reset(struct exynos_dp_device *dp);
-void exynos_dp_swreset(struct exynos_dp_device *dp);
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable);
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
-void exynos_dp_init_hpd(struct exynos_dp_device *dp);
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
-void exynos_dp_reset_aux(struct exynos_dp_device *dp);
-void exynos_dp_init_aux(struct exynos_dp_device *dp);
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern);
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
-void exynos_dp_reset_macro(struct exynos_dp_device *dp);
-void exynos_dp_init_video(struct exynos_dp_device *dp);
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_start_video(struct exynos_dp_device *dp);
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
-#endif /* _EXYNOS_DP_CORE_H */
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
deleted file mode 100644
index c1f87a2..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
+++ /dev/null
@@ -1,1263 +0,0 @@
-/*
- * Samsung DP (Display port) register interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-
-#include "exynos_dp_core.h"
-#include "exynos_dp_reg.h"
-
-#define COMMON_INT_MASK_1	0
-#define COMMON_INT_MASK_2	0
-#define COMMON_INT_MASK_3	0
-#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
-#define INT_STA_MASK		INT_HPD
-
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg |= HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg &= ~HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	}
-}
-
-void exynos_dp_stop_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg &= ~VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable)
-		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
-	else
-		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
-
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
-}
-
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = TX_TERMINAL_CTRL_50_OHM;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
-
-	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
-
-	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
-
-	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
-		TX_CUR1_2X | TX_CUR_16_MA;
-	writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
-
-	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
-		CH1_AMP_400_MV | CH0_AMP_400_MV;
-	writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
-}
-
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
-{
-	/* Set interrupt pin assertion polarity as high */
-	writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
-
-	/* Clear pending regisers */
-	writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-	writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
-	writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
-	writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-	writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* 0:mask,1: unmask */
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-	writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-void exynos_dp_reset(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	exynos_dp_stop_video(dp);
-	exynos_dp_enable_video_mute(dp, 0);
-
-	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
-		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
-		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
-		SERDES_FIFO_FUNC_EN_N |
-		LS_CLK_DOMAIN_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-
-	usleep_range(20, 30);
-
-	exynos_dp_lane_swap(dp, 0);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
-	writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
-
-	writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
-	writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
-
-	writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
-	writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
-
-	writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
-	writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
-
-	writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_swreset(struct exynos_dp_device *dp)
-{
-	writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
-}
-
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* 0: mask, 1: unmask */
-	reg = COMMON_INT_MASK_1;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-
-	reg = COMMON_INT_MASK_2;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-
-	reg = COMMON_INT_MASK_3;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-
-	reg = COMMON_INT_MASK_4;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-
-	reg = INT_STA_MASK;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	if (reg & PLL_LOCK)
-		return PLL_LOCKED;
-	else
-		return PLL_UNLOCKED;
-}
-
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg |= DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg &= ~DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	}
-}
-
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
-{
-	u32 reg;
-
-	switch (block) {
-	case AUX_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH0_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH1_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH2_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH3_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case ANALOG_TOTAL:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case POWER_ALL:
-		if (enable) {
-			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
-				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
-{
-	u32 reg;
-	int timeout_loop = 0;
-
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
-
-	reg = PLL_LOCK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-
-	/* Power up PLL */
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-		exynos_dp_set_pll_power_down(dp, 0);
-
-		while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-			timeout_loop++;
-			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-				dev_err(dp->dev, "failed to get pll lock status\n");
-				return;
-			}
-			usleep_range(10, 20);
-		}
-	}
-
-	/* Enable Serdes FIFO function and Link symbol clock domain module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
-		| AUX_FUNC_EN_N);
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-	reg = INT_HPD;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-}
-
-void exynos_dp_init_hpd(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	exynos_dp_clear_hotplug_interrupts(dp);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	reg &= ~(F_HPD | HPD_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-}
-
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		reg = gpio_get_value(dp->hpd_gpio);
-		if (reg)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-		else
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-	} else {
-		/* Parse hotplug interrupt status register */
-		reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-		if (reg & PLUG)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-
-		if (reg & HPD_LOST)
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-
-		if (reg & HOTPLUG_CHG)
-			return DP_IRQ_TYPE_HP_CHANGE;
-
-		return DP_IRQ_TYPE_UNKNOWN;
-	}
-}
-
-void exynos_dp_reset_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Disable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg |= AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_init_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Clear inerrupts related to AUX channel */
-	reg = RPLY_RECEIV | AUX_ERR;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	exynos_dp_reset_aux(dp);
-
-	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
-
-	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
-	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
-
-	/* Enable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		if (gpio_get_value(dp->hpd_gpio))
-			return 0;
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-		if (reg & HPD_STATUS)
-			return 0;
-	}
-
-	return -EINVAL;
-}
-
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-}
-
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
-{
-	int reg;
-	int retval = 0;
-	int timeout_loop = 0;
-
-	/* Enable AUX CH operation */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-	reg |= AUX_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-	/* Is AUX CH command reply received? */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	while (!(reg & RPLY_RECEIV)) {
-		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "AUX CH command reply failed!\n");
-			return -ETIMEDOUT;
-		}
-		reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-		usleep_range(10, 11);
-	}
-
-	/* Clear interrupt source for AUX CH command reply */
-	writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* Clear interrupt source for AUX CH access error */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	if (reg & AUX_ERR) {
-		writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
-		return -EREMOTEIO;
-	}
-
-	/* Check AUX CH error access status */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
-	if ((reg & AUX_STATUS_MASK) != 0) {
-		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
-			reg & AUX_STATUS_MASK);
-		return -EREMOTEIO;
-	}
-
-	return retval;
-}
-
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/* Write data buffer */
-		reg = (unsigned int)data;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-		/*
-		 * Set DisplayPort transaction and write 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/*
-		 * Set DisplayPort transaction and read 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	/* Read data buffer */
-	reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-	*data = (unsigned char)(reg & 0xff);
-
-	return retval;
-}
-
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-			     cur_data_idx++) {
-				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
-			}
-
-			/*
-			 * Set DisplayPort transaction and write
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		/* AUX CH Request Transaction process */
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			/*
-			 * Set DisplayPort transaction and read
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-		    cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			data[start_offset + cur_data_idx] =
-				(unsigned char)reg;
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
-{
-	u32 reg;
-	int retval;
-
-	/* Set EDID device address */
-	reg = device_addr;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-	/* Set offset from base address of EDID device */
-	writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	/*
-	 * Set I2C transaction and write address
-	 * If bit 3 is 1, DisplayPort transaction.
-	 * If Bit 3 is 0, I2C transaction.
-	 */
-	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
-		AUX_TX_COMM_WRITE;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction(dp);
-	if (retval != 0)
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select EDID device */
-		retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
-		if (retval != 0)
-			continue;
-
-		/*
-		 * Set I2C transaction and read data
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_I2C_TRANSACTION |
-			AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	/* Read data */
-	if (retval == 0)
-		*data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
-{
-	u32 reg;
-	unsigned int i, j;
-	unsigned int cur_data_idx;
-	unsigned int defer = 0;
-	int retval = 0;
-
-	for (i = 0; i < count; i += 16) {
-		for (j = 0; j < 3; j++) {
-			/* Clear AUX CH data buffer */
-			reg = BUF_CLR;
-			writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-			/* Set normal AUX CH command */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-			reg &= ~ADDR_ONLY;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-			/*
-			 * If Rx sends defer, Tx sends only reads
-			 * request without sending address
-			 */
-			if (!defer)
-				retval = exynos_dp_select_i2c_device(dp,
-						device_addr, reg_addr + i);
-			else
-				defer = 0;
-
-			if (retval == 0) {
-				/*
-				 * Set I2C transaction and write data
-				 * If bit 3 is 1, DisplayPort transaction.
-				 * If Bit 3 is 0, I2C transaction.
-				 */
-				reg = AUX_LENGTH(16) |
-					AUX_TX_COMM_I2C_TRANSACTION |
-					AUX_TX_COMM_READ;
-				writel(reg, dp->reg_base +
-					EXYNOS_DP_AUX_CH_CTL_1);
-
-				/* Start AUX transaction */
-				retval = exynos_dp_start_aux_transaction(dp);
-				if (retval == 0)
-					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
-			}
-			/* Check if Rx sends defer */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
-			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
-				dev_err(dp->dev, "Defer: %d\n\n", reg);
-				defer = 1;
-			}
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			edid[i + cur_data_idx] = (unsigned char)reg;
-		}
-	}
-
-	return retval;
-}
-
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
-{
-	u32 reg;
-
-	reg = bwtype;
-	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
-		writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-}
-
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-	*bwtype = reg;
-}
-
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
-{
-	u32 reg;
-
-	reg = count;
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-}
-
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-	*count = reg;
-}
-
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	}
-}
-
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern)
-{
-	u32 reg;
-
-	switch (pattern) {
-	case PRBS7:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case D10_2:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN1:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN2:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case DP_NONE:
-		reg = SCRAMBLING_ENABLE |
-			LINK_QUAL_PATTERN_SET_DISABLE |
-			SW_TRAINING_PATTERN_SET_NORMAL;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	return reg;
-}
-
-void exynos_dp_reset_macro(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
-	reg |= MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	/* 10 us is the minimum reset time. */
-	usleep_range(10, 20);
-
-	reg &= ~MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-}
-
-void exynos_dp_init_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = CHA_CRI(4) | CHA_CTRL;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
-}
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
-
-	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
-		reg |= IN_YC_COEFFI_ITU709;
-	else
-		reg |= IN_YC_COEFFI_ITU601;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-}
-
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	if (!(reg & DET_STA)) {
-		dev_dbg(dp->dev, "Input stream clock not detected.\n");
-		return -EINVAL;
-	}
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
-
-	if (reg & CHA_STA) {
-		dev_dbg(dp->dev, "Input stream clk is changing\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
-{
-	u32 reg;
-
-	if (type == REGISTER_M) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg = m_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
-		reg = (m_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
-		reg = (m_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
-
-		reg = n_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
-		reg = (n_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
-		reg = (n_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
-	} else  {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
-		writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
-	}
-}
-
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
-{
-	u32 reg;
-
-	if (type == VIDEO_TIMING_FROM_CAPTURE) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg &= ~FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg |= FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	}
-}
-
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MODE_SLAVE_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	}
-}
-
-void exynos_dp_start_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg |= VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	if (!(reg & STRM_VALID)) {
-		dev_dbg(dp->dev, "Input video stream is not detected.\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
-	reg |= MASTER_VID_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-	writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg &= ~SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
-
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg |= SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
new file mode 100644
index 0000000..134638af
--- /dev/null
+++ b/include/drm/bridge/analogix_dp.h
@@ -0,0 +1,41 @@
+/*
+ * Analogix DP (Display Port) Core interface driver.
+ *
+ * Copyright (C) 2015 Rockchip Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _ANALOGIX_DP_H_
+#define _ANALOGIX_DP_H_
+
+#include <drm/drm_crtc.h>
+
+enum analogix_dp_devtype {
+	EXYNOS_DP,
+};
+
+struct analogix_dp_plat_data {
+	enum analogix_dp_devtype dev_type;
+	struct drm_panel *panel;
+	struct drm_encoder *encoder;
+	struct drm_connector *connector;
+
+	int (*power_on)(struct analogix_dp_plat_data *);
+	int (*power_off)(struct analogix_dp_plat_data *);
+	int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *);
+};
+
+enum drm_connector_status analogix_dp_detect(struct device *dev, bool force);
+int analogix_dp_get_modes(struct device *dev);
+
+int analogix_dp_resume(struct device *dev);
+int analogix_dp_suspend(struct device *dev);
+
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct analogix_dp_plat_data *plat_data);
+void analogix_dp_unbind(struct device *dev, struct device *master, void *data);
+
+#endif /* _ANALOGIX_DP_H_ */
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
@ 2015-10-10 15:39     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:39 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe-6d6DIl74uiNBDgjK7y7TUQ, Heiko Stuebner,
	Mark Yao
  Cc: Russell King, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	javier-JPH+aEBZ4P+UEJcrhfAQsw, Andy Yan, Yakir Yang,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.

Beside the new analogix_dp driver would export four hooks.
"analogix_dp_bind()" and "analogix_dp_unbind()"
"analogix_dp_detect()" and "analogix_dp_get_modes()"

The bind/unbind symbols is used for analogix platform driver to connect
with analogix_dp core driver. And the detect/get_modes is used for analogix
platform driver to init the connector.

They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v6:
- Fix the Kconfig recursive dependency (Javier)

Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
  the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
  attch function. Cause once platform failed at attach, core driver should
  still failed, so no need to init connector before platform attached (Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
  patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)

Changes in v4:
- Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
- Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
- Create a separate folder for analogix code in bridge/ (Archit)

Changes in v3:
- Move exynos's video_timing code to analogix_dp-exynos platform driver,
  add get_modes method to struct analogix_dp_plat_data. (Thierry)
- Rename some "samsung*" dts propery to "analogix*". (Heiko)

Changes in v2:
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell

 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    3 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 .../analogix/analogix_dp_core.c}                   |  753 +++++-------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  277 +++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1263 ++++++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  258 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  349 ++++++
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 -----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 --------------------
 include/drm/bridge/analogix_dp.h                   |   41 +
 14 files changed, 2365 insertions(+), 2133 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 rename drivers/gpu/drm/{exynos/exynos_dp_core.c => bridge/analogix/analogix_dp_core.c} (51%)
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (64%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 include/drm/bridge/analogix_dp.h

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 2de52a5..7b5b77a 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -29,4 +29,6 @@ config DRM_PARADE_PS8622
 	---help---
 	  Parade eDP-LVDS bridge chip driver.
 
+source "drivers/gpu/drm/bridge/analogix/Kconfig"
+
 endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index e2eef1c..5366c6b 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -3,3 +3,4 @@ ccflags-y := -Iinclude/drm
 obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
new file mode 100644
index 0000000..80f286f
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -0,0 +1,3 @@
+config DRM_ANALOGIX_DP
+	tristate
+	depends on DRM
diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
new file mode 100644
index 0000000..9107b86
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
similarity index 51%
rename from drivers/gpu/drm/exynos/exynos_dp_core.c
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index aedd074..e561590 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1,14 +1,14 @@
 /*
- * Samsung SoC DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
+* Analogix DP (Display Port) core interface driver.
+*
+* Copyright (C) 2012 Samsung Electronics Co., Ltd.
+* Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2 of the License, or (at your
+* option) any later version.
+*/
 
 #include <linux/module.h>
 #include <linux/platform_device.h>
@@ -18,65 +18,48 @@
 #include <linux/interrupt.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
-#include <linux/of_graph.h>
 #include <linux/gpio.h>
 #include <linux/component.h>
 #include <linux/phy/phy.h>
-#include <video/of_display_timing.h>
-#include <video/of_videomode.h>
 
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
-#include <drm/drm_atomic_helper.h>
 #include <drm/drm_panel.h>
 
-#include "exynos_dp_core.h"
-#include "exynos_drm_crtc.h"
+#include <drm/bridge/analogix_dp.h>
 
-#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
-					connector)
-
-static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
-{
-	return to_exynos_crtc(dp->encoder.crtc);
-}
-
-static inline struct exynos_dp_device *encoder_to_dp(
-						struct drm_encoder *e)
-{
-	return container_of(e, struct exynos_dp_device, encoder);
-}
+#include "analogix_dp_core.h"
 
 struct bridge_init {
 	struct i2c_client *client;
 	struct device_node *node;
 };
 
-static void exynos_dp_init_dp(struct exynos_dp_device *dp)
+static void analogix_dp_init_dp(struct analogix_dp_device *dp)
 {
-	exynos_dp_reset(dp);
+	analogix_dp_reset(dp);
 
-	exynos_dp_swreset(dp);
+	analogix_dp_swreset(dp);
 
-	exynos_dp_init_analog_param(dp);
-	exynos_dp_init_interrupt(dp);
+	analogix_dp_init_analog_param(dp);
+	analogix_dp_init_interrupt(dp);
 
 	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_function(dp);
+	analogix_dp_enable_sw_function(dp);
 
-	exynos_dp_config_interrupt(dp);
-	exynos_dp_init_analog_func(dp);
+	analogix_dp_config_interrupt(dp);
+	analogix_dp_init_analog_func(dp);
 
-	exynos_dp_init_hpd(dp);
-	exynos_dp_init_aux(dp);
+	analogix_dp_init_hpd(dp);
+	analogix_dp_init_aux(dp);
 }
 
-static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
+static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (exynos_dp_get_plug_in_status(dp) != 0) {
+	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
@@ -88,7 +71,7 @@ static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
 	return 0;
 }
 
-static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
+static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 {
 	int i;
 	unsigned char sum = 0;
@@ -99,7 +82,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
 	return sum;
 }
 
-static int exynos_dp_read_edid(struct exynos_dp_device *dp)
+static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
 	unsigned char edid[EDID_BLOCK_LENGTH * 2];
 	unsigned int extend_block = 0;
@@ -114,7 +97,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 	 */
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 				EDID_EXTENSION_FLAG,
 				&extend_block);
 	if (retval)
@@ -124,7 +107,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -132,14 +115,14 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
+		sum = analogix_dp_calc_edid_check_sum(edid);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
 				I2C_EDID_DEVICE_ADDR,
 				EDID_BLOCK_LENGTH,
 				EDID_BLOCK_LENGTH,
@@ -148,19 +131,19 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
+		sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
 					&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_RESPONSE,
 				DP_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -168,7 +151,7 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 		dev_info(dp->dev, "EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
 				I2C_EDID_DEVICE_ADDR,
 				EDID_HEADER_PATTERN,
 				EDID_BLOCK_LENGTH,
@@ -177,20 +160,20 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
 		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
+		sum = analogix_dp_calc_edid_check_sum(edid);
 		if (sum != 0) {
 			dev_err(dp->dev, "EDID bad checksum!\n");
 			return -EIO;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp,
+		analogix_dp_read_byte_from_dpcd(dp,
 			DP_TEST_REQUEST,
 			&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
 				edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
+			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_RESPONSE,
 				DP_TEST_EDID_CHECKSUM_WRITE);
 		}
@@ -200,21 +183,21 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 	return 0;
 }
 
-static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
+static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 {
 	u8 buf[12];
 	int i;
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
 				12, buf);
 	if (retval)
 		return retval;
 
 	/* Read EDID */
 	for (i = 0; i < 3; i++) {
-		retval = exynos_dp_read_edid(dp);
+		retval = analogix_dp_read_edid(dp);
 		if (!retval)
 			break;
 	}
@@ -222,73 +205,73 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
+static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
 						bool enable)
 {
 	u8 data;
 
-	exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
 
 	if (enable)
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 			DP_LANE_COUNT_ENHANCED_FRAME_EN |
 			DPCD_LANE_COUNT_SET(data));
 	else
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 			DPCD_LANE_COUNT_SET(data));
 }
 
-static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
+static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
 {
 	u8 data;
 	int retval;
 
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 	retval = DPCD_ENHANCED_FRAME_CAP(data);
 
 	return retval;
 }
 
-static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
+static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 {
 	u8 data;
 
-	data = exynos_dp_is_enhanced_mode_available(dp);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, data);
-	exynos_dp_enable_enhanced_mode(dp, data);
+	data = analogix_dp_is_enhanced_mode_available(dp);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, data);
+	analogix_dp_enable_enhanced_mode(dp, data);
 }
 
-static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
+static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
-	exynos_dp_set_training_pattern(dp, DP_NONE);
+	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	exynos_dp_write_byte_to_dpcd(dp,
+	analogix_dp_write_byte_to_dpcd(dp,
 		DP_TRAINING_PATTERN_SET,
 		DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
+static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
 					int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
-		exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 		break;
 	case 1:
-		exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 		break;
 
 	case 2:
-		exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 		break;
 
 	case 3:
-		exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
+		analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 		break;
 	}
 }
 
-static int exynos_dp_link_start(struct exynos_dp_device *dp)
+static int analogix_dp_link_start(struct analogix_dp_device *dp)
 {
 	u8 buf[4];
 	int lane, lane_count, pll_tries, retval;
@@ -302,25 +285,25 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		dp->link_train.cr_loop[lane] = 0;
 
 	/* Set link rate and count as you want to establish*/
-	exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
-	exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
+	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
 				2, buf);
 	if (retval)
 		return retval;
 
 	/* Set TX pre-emphasis to minimum */
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_lane_pre_emphasis(dp,
+		analogix_dp_set_lane_lane_pre_emphasis(dp,
 			PRE_EMPHASIS_LEVEL_0, lane);
 
 	/* Wait for PLL lock */
 	pll_tries = 0;
-	while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+	while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 		if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Wait for PLL lock timed out\n");
 			return -ETIMEDOUT;
@@ -331,10 +314,10 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 	}
 
 	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
+	analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 
 	/* Set RX training pattern */
-	retval = exynos_dp_write_byte_to_dpcd(dp,
+	retval = analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
 	if (retval)
@@ -344,13 +327,13 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
 		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 			lane_count, buf);
 
 	return retval;
 }
 
-static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
+static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
 	u8 link_value = link_status[lane>>1];
@@ -358,20 +341,20 @@ static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
 	return (link_value >> shift) & 0xf;
 }
 
-static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
+static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 {
 	int lane;
 	u8 lane_status;
 
 	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
 		if ((lane_status & DP_LANE_CR_DONE) == 0)
 			return -EINVAL;
 	}
 	return 0;
 }
 
-static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
+static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 				int lane_count)
 {
 	int lane;
@@ -381,7 +364,7 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 		return -EINVAL;
 
 	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
 		lane_status &= DP_CHANNEL_EQ_BITS;
 		if (lane_status != DP_CHANNEL_EQ_BITS)
 			return -EINVAL;
@@ -390,7 +373,7 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
+static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
 							int lane)
 {
 	int shift = (lane & 1) * 4;
@@ -399,7 +382,7 @@ static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 	return (link_value >> shift) & 0x3;
 }
 
-static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
+static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					u8 adjust_request[2],
 					int lane)
 {
@@ -409,45 +392,45 @@ static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
-static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
+static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 					u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
-		exynos_dp_set_lane0_link_training(dp, training_lane_set);
+		analogix_dp_set_lane0_link_training(dp, training_lane_set);
 		break;
 	case 1:
-		exynos_dp_set_lane1_link_training(dp, training_lane_set);
+		analogix_dp_set_lane1_link_training(dp, training_lane_set);
 		break;
 
 	case 2:
-		exynos_dp_set_lane2_link_training(dp, training_lane_set);
+		analogix_dp_set_lane2_link_training(dp, training_lane_set);
 		break;
 
 	case 3:
-		exynos_dp_set_lane3_link_training(dp, training_lane_set);
+		analogix_dp_set_lane3_link_training(dp, training_lane_set);
 		break;
 	}
 }
 
-static unsigned int exynos_dp_get_lane_link_training(
-				struct exynos_dp_device *dp,
+static unsigned int analogix_dp_get_lane_link_training(
+				struct analogix_dp_device *dp,
 				int lane)
 {
 	u32 reg;
 
 	switch (lane) {
 	case 0:
-		reg = exynos_dp_get_lane0_link_training(dp);
+		reg = analogix_dp_get_lane0_link_training(dp);
 		break;
 	case 1:
-		reg = exynos_dp_get_lane1_link_training(dp);
+		reg = analogix_dp_get_lane1_link_training(dp);
 		break;
 	case 2:
-		reg = exynos_dp_get_lane2_link_training(dp);
+		reg = analogix_dp_get_lane2_link_training(dp);
 		break;
 	case 3:
-		reg = exynos_dp_get_lane3_link_training(dp);
+		reg = analogix_dp_get_lane3_link_training(dp);
 		break;
 	default:
 		WARN_ON(1);
@@ -457,15 +440,15 @@ static unsigned int exynos_dp_get_lane_link_training(
 	return reg;
 }
 
-static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
+static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 {
-	exynos_dp_training_pattern_dis(dp);
-	exynos_dp_set_enhanced_mode(dp);
+	analogix_dp_training_pattern_dis(dp);
+	analogix_dp_set_enhanced_mode(dp);
 
 	dp->link_train.lt_state = FAILED;
 }
 
-static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
+static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
 					u8 adjust_request[2])
 {
 	int lane, lane_count;
@@ -473,9 +456,9 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
 
 	lane_count = dp->link_train.lane_count;
 	for (lane = 0; lane < lane_count; lane++) {
-		voltage_swing = exynos_dp_get_adjust_request_voltage(
+		voltage_swing = analogix_dp_get_adjust_request_voltage(
 						adjust_request, lane);
-		pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
+		pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 						adjust_request, lane);
 		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
@@ -489,7 +472,7 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
 	}
 }
 
-static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
+static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 {
 	int lane, lane_count, retval;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -499,21 +482,21 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
+	retval =  analogix_dp_read_bytes_from_dpcd(dp,
 			DP_LANE0_1_STATUS, 2, link_status);
 	if (retval)
 		return retval;
 
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
+	retval =  analogix_dp_read_bytes_from_dpcd(dp,
 			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 	if (retval)
 		return retval;
 
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 		/* set training pattern 2 for EQ */
-		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
+		analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 
-		retval = exynos_dp_write_byte_to_dpcd(dp,
+		retval = analogix_dp_write_byte_to_dpcd(dp,
 				DP_TRAINING_PATTERN_SET,
 				DP_LINK_SCRAMBLING_DISABLE |
 				DP_TRAINING_PATTERN_2);
@@ -524,11 +507,11 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 		dp->link_train.lt_state = EQUALIZER_TRAINING;
 	} else {
 		for (lane = 0; lane < lane_count; lane++) {
-			training_lane = exynos_dp_get_lane_link_training(
+			training_lane = analogix_dp_get_lane_link_training(
 							dp, lane);
-			voltage_swing = exynos_dp_get_adjust_request_voltage(
+			voltage_swing = analogix_dp_get_adjust_request_voltage(
 							adjust_request, lane);
-			pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
+			pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 							adjust_request, lane);
 
 			if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
@@ -543,19 +526,19 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 				dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 					dp->link_train.cr_loop[lane],
 					voltage_swing, pre_emphasis);
-				exynos_dp_reduce_link_rate(dp);
+				analogix_dp_reduce_link_rate(dp);
 				return -EIO;
 			}
 		}
 	}
 
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
+		analogix_dp_set_lane_link_training(dp,
 			dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp,
+	retval = analogix_dp_write_bytes_to_dpcd(dp,
 			DP_TRAINING_LANE0_SET, lane_count,
 			dp->link_train.training_lane);
 	if (retval)
@@ -564,7 +547,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
+static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 {
 	int lane, lane_count, retval;
 	u32 reg;
@@ -574,46 +557,46 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	lane_count = dp->link_train.lane_count;
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
+	retval = analogix_dp_read_bytes_from_dpcd(dp,
 			DP_LANE0_1_STATUS, 2, link_status);
 	if (retval)
 		return retval;
 
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
-		exynos_dp_reduce_link_rate(dp);
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
+		analogix_dp_reduce_link_rate(dp);
 		return -EIO;
 	}
 
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
+	retval = analogix_dp_read_bytes_from_dpcd(dp,
 			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 	if (retval)
 		return retval;
 
-	retval = exynos_dp_read_byte_from_dpcd(dp,
+	retval = analogix_dp_read_byte_from_dpcd(dp,
 			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
 	if (retval)
 		return retval;
 
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 
-	if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
+	if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 		/* traing pattern Set to Normal */
-		exynos_dp_training_pattern_dis(dp);
+		analogix_dp_training_pattern_dis(dp);
 
 		dev_info(dp->dev, "Link Training success!\n");
 
-		exynos_dp_get_link_bandwidth(dp, &reg);
+		analogix_dp_get_link_bandwidth(dp, &reg);
 		dp->link_train.link_rate = reg;
 		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 			dp->link_train.link_rate);
 
-		exynos_dp_get_lane_count(dp, &reg);
+		analogix_dp_get_lane_count(dp, &reg);
 		dp->link_train.lane_count = reg;
 		dev_dbg(dp->dev, "final lane count = %.2x\n",
 			dp->link_train.lane_count);
 
 		/* set enhanced mode if available */
-		exynos_dp_set_enhanced_mode(dp);
+		analogix_dp_set_enhanced_mode(dp);
 		dp->link_train.lt_state = FINISHED;
 
 		return 0;
@@ -624,21 +607,21 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 
 	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 		dev_err(dp->dev, "EQ Max loop\n");
-		exynos_dp_reduce_link_rate(dp);
+		analogix_dp_reduce_link_rate(dp);
 		return -EIO;
 	}
 
 	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
+		analogix_dp_set_lane_link_training(dp,
 			dp->link_train.training_lane[lane], lane);
 
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 			lane_count, dp->link_train.training_lane);
 
 	return retval;
 }
 
-static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
+static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 					u8 *bandwidth)
 {
 	u8 data;
@@ -647,11 +630,11 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
 }
 
-static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
+static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 					u8 *lane_count)
 {
 	u8 data;
@@ -660,11 +643,11 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 	 * For DP rev.1.1, Maximum number of Main Link lanes
 	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 	*lane_count = DPCD_MAX_LANE_COUNT(data);
 }
 
-static void exynos_dp_init_training(struct exynos_dp_device *dp,
+static void analogix_dp_init_training(struct analogix_dp_device *dp,
 			enum link_lane_count_type max_lane,
 			enum link_rate_type max_rate)
 {
@@ -672,11 +655,11 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 	 * the DP inter pair skew issue for at least 10 us
 	 */
-	exynos_dp_reset_macro(dp);
+	analogix_dp_reset_macro(dp);
 
 	/* Initialize by reading RX's DPCD */
-	exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
-	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
+	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
+	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
@@ -698,10 +681,10 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
 		dp->link_train.link_rate = max_rate;
 
 	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 }
 
-static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
+static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 {
 	int retval = 0, training_finished = 0;
 
@@ -711,17 +694,17 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 	while (!retval && !training_finished) {
 		switch (dp->link_train.lt_state) {
 		case START:
-			retval = exynos_dp_link_start(dp);
+			retval = analogix_dp_link_start(dp);
 			if (retval)
 				dev_err(dp->dev, "LT link start failed!\n");
 			break;
 		case CLOCK_RECOVERY:
-			retval = exynos_dp_process_clock_recovery(dp);
+			retval = analogix_dp_process_clock_recovery(dp);
 			if (retval)
 				dev_err(dp->dev, "LT CR failed!\n");
 			break;
 		case EQUALIZER_TRAINING:
-			retval = exynos_dp_process_equalizer_training(dp);
+			retval = analogix_dp_process_equalizer_training(dp);
 			if (retval)
 				dev_err(dp->dev, "LT EQ failed!\n");
 			break;
@@ -738,7 +721,7 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
+static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
 				u32 count,
 				u32 bwtype)
 {
@@ -746,8 +729,8 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 	int retval;
 
 	for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
-		exynos_dp_init_training(dp, count, bwtype);
-		retval = exynos_dp_sw_link_training(dp);
+		analogix_dp_init_training(dp, count, bwtype);
+		retval = analogix_dp_sw_link_training(dp);
 		if (retval == 0)
 			break;
 
@@ -757,24 +740,24 @@ static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 	return retval;
 }
 
-static int exynos_dp_config_video(struct exynos_dp_device *dp)
+static int analogix_dp_config_video(struct analogix_dp_device *dp)
 {
 	int retval = 0;
 	int timeout_loop = 0;
 	int done_count = 0;
 
-	exynos_dp_config_video_slave_mode(dp);
+	analogix_dp_config_video_slave_mode(dp);
 
-	exynos_dp_set_video_color_format(dp);
+	analogix_dp_set_video_color_format(dp);
 
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 		dev_err(dp->dev, "PLL is not locked yet.\n");
 		return -EINVAL;
 	}
 
 	for (;;) {
 		timeout_loop++;
-		if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
+		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
@@ -785,22 +768,22 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
 	}
 
 	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
+	analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 
 	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
+	analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 
 	/* Disable video mute */
-	exynos_dp_enable_video_mute(dp, 0);
+	analogix_dp_enable_video_mute(dp, 0);
 
 	/* Configure video slave mode */
-	exynos_dp_enable_video_master(dp, 0);
+	analogix_dp_enable_video_master(dp, 0);
 
 	timeout_loop = 0;
 
 	for (;;) {
 		timeout_loop++;
-		if (exynos_dp_is_video_stream_on(dp) == 0) {
+		if (analogix_dp_is_video_stream_on(dp) == 0) {
 			done_count++;
 			if (done_count > 10)
 				break;
@@ -821,47 +804,47 @@ static int exynos_dp_config_video(struct exynos_dp_device *dp)
 	return retval;
 }
 
-static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
 {
 	u8 data;
 
 	if (enable) {
-		exynos_dp_enable_scrambling(dp);
+		analogix_dp_enable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp,
+		analogix_dp_read_byte_from_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
+		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
-		exynos_dp_disable_scrambling(dp);
+		analogix_dp_disable_scrambling(dp);
 
-		exynos_dp_read_byte_from_dpcd(dp,
+		analogix_dp_read_byte_from_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
+		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 	}
 }
 
-static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
+static irqreturn_t analogix_dp_irq_handler(int irq, void *arg)
 {
-	struct exynos_dp_device *dp = arg;
+	struct analogix_dp_device *dp = arg;
 
 	enum dp_irq_type irq_type;
 
-	irq_type = exynos_dp_get_irq_type(dp);
+	irq_type = analogix_dp_get_irq_type(dp);
 	switch (irq_type) {
 	case DP_IRQ_TYPE_HP_CABLE_IN:
 		dev_dbg(dp->dev, "Received irq - cable in\n");
 		schedule_work(&dp->hotplug_work);
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	case DP_IRQ_TYPE_HP_CABLE_OUT:
 		dev_dbg(dp->dev, "Received irq - cable out\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	case DP_IRQ_TYPE_HP_CHANGE:
 		/*
@@ -870,7 +853,7 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 		 * only handle cable changes.
 		 */
 		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_clear_hotplug_interrupts(dp);
 		break;
 	default:
 		dev_err(dp->dev, "Received irq - unknown type!\n");
@@ -879,217 +862,160 @@ static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
-static void exynos_dp_hotplug(struct work_struct *work)
+static void analogix_dp_hotplug(struct work_struct *work)
 {
-	struct exynos_dp_device *dp;
+	struct analogix_dp_device *dp;
 
-	dp = container_of(work, struct exynos_dp_device, hotplug_work);
+	dp = container_of(work, struct analogix_dp_device, hotplug_work);
 
 	if (dp->drm_dev)
 		drm_helper_hpd_irq_event(dp->drm_dev);
 }
 
-static void exynos_dp_commit(struct drm_encoder *encoder)
+static void analogix_dp_commit(struct analogix_dp_device *dp)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
 	int ret;
 
 	/* Keep the panel disabled while we configure video */
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel))
+	if (dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel))
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = exynos_dp_detect_hpd(dp);
+	ret = analogix_dp_detect_hpd(dp);
 	if (ret) {
 		/* Cable has been disconnected, we're done */
 		return;
 	}
 
-	ret = exynos_dp_handle_edid(dp);
+	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
 		return;
 	}
 
-	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
+	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
 					dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
 	}
 
-	exynos_dp_enable_scramble(dp, 1);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
-	exynos_dp_enable_enhanced_mode(dp, 1);
+	analogix_dp_enable_scramble(dp, 1);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
+	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
-	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
+	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 
-	exynos_dp_init_video(dp);
-	ret = exynos_dp_config_video(dp);
+	analogix_dp_init_video(dp);
+	ret = analogix_dp_config_video(dp);
 	if (ret)
 		dev_err(dp->dev, "unable to config video\n");
 
 	/* Safe to enable the panel now */
-	if (dp->panel) {
-		if (drm_panel_enable(dp->panel))
+	if (dp->plat_data->panel) {
+		if (drm_panel_enable(dp->plat_data->panel))
 			DRM_ERROR("failed to enable the panel\n");
 	}
 
 	/* Enable video */
-	exynos_dp_start_video(dp);
+	analogix_dp_start_video(dp);
 }
 
-static enum drm_connector_status exynos_dp_detect(
-				struct drm_connector *connector, bool force)
+enum drm_connector_status analogix_dp_detect(struct device *dev, bool force)
 {
 	return connector_status_connected;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_detect);
 
-static void exynos_dp_connector_destroy(struct drm_connector *connector)
+int analogix_dp_get_modes(struct device *dev)
 {
-	drm_connector_unregister(connector);
-	drm_connector_cleanup(connector);
-}
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+	int num_modes = 0;
 
-static struct drm_connector_funcs exynos_dp_connector_funcs = {
-	.dpms = drm_atomic_helper_connector_dpms,
-	.fill_modes = drm_helper_probe_single_connector_modes,
-	.detect = exynos_dp_detect,
-	.destroy = exynos_dp_connector_destroy,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static int exynos_dp_get_modes(struct drm_connector *connector)
-{
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
-	struct drm_display_mode *mode;
+	if (dp->plat_data->panel)
+		num_modes += drm_panel_get_modes(dp->plat_data->panel);
 
-	if (dp->panel)
-		return drm_panel_get_modes(dp->panel);
-
-	mode = drm_mode_create(connector->dev);
-	if (!mode) {
-		DRM_ERROR("failed to create a new display mode.\n");
-		return 0;
-	}
-
-	drm_display_mode_from_videomode(&dp->priv.vm, mode);
-	mode->width_mm = dp->priv.width_mm;
-	mode->height_mm = dp->priv.height_mm;
-	connector->display_info.width_mm = mode->width_mm;
-	connector->display_info.height_mm = mode->height_mm;
-
-	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-	drm_mode_set_name(mode);
-	drm_mode_probed_add(connector, mode);
-
-	return 1;
-}
-
-static struct drm_encoder *exynos_dp_best_encoder(
-			struct drm_connector *connector)
-{
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
-
-	return &dp->encoder;
+	return num_modes;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_get_modes);
 
-static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
-	.get_modes = exynos_dp_get_modes,
-	.best_encoder = exynos_dp_best_encoder,
-};
-
-/* returns the number of bridges attached */
-static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
-		struct drm_encoder *encoder)
+static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
 {
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = dp->encoder;
 	int ret;
 
-	encoder->bridge->next = dp->ptn_bridge;
-	dp->ptn_bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
-	if (ret) {
-		DRM_ERROR("Failed to attach bridge to drm\n");
-		return ret;
+	if (!bridge->encoder) {
+		DRM_ERROR("Parent encoder object not found");
+		return -ENODEV;
 	}
 
-	return 0;
-}
-
-static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
-{
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct drm_encoder *encoder = &dp->encoder;
-	struct drm_connector *connector = &dp->connector;
-	int ret;
+	encoder->bridge = bridge;
 
-	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->ptn_bridge) {
-		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
-		if (!ret)
-			return 0;
+	/*
+	 * NOTE: the connector registration is implemented in analogix
+	 * platform driver, that to say connector would be exist after
+	 * plat_data->attch return, that's why we record the connector
+	 * point after plat attached.
+	 */
+	 if (dp->plat_data->attach) {
+		 ret = dp->plat_data->attach(dp->plat_data, bridge);
+		 if (ret) {
+			 DRM_ERROR("Failed at platform attch func\n");
+			 return ret;
+		 }
 	}
 
-	connector->polled = DRM_CONNECTOR_POLL_HPD;
+	dp->connector = dp->plat_data->connector;
 
-	ret = drm_connector_init(dp->drm_dev, connector,
-			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
-	if (ret) {
-		DRM_ERROR("Failed to initialize connector with drm\n");
-		return ret;
+	if (dp->plat_data->panel) {
+		ret = drm_panel_attach(dp->plat_data->panel, dp->connector);
+		if (ret) {
+			DRM_ERROR("Failed to attach panel\n");
+			return ret;
+		}
 	}
 
-	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
-	drm_connector_register(connector);
-	drm_mode_connector_attach_encoder(connector, encoder);
-
-	if (dp->panel)
-		ret = drm_panel_attach(dp->panel, &dp->connector);
-
-	return ret;
+	return 0;
 }
 
-static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
+static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
+	struct analogix_dp_device *dp = bridge->driver_private;
 
 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->panel) {
-		if (drm_panel_prepare(dp->panel)) {
+	if (dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
 			DRM_ERROR("failed to setup the panel\n");
 			return;
 		}
 	}
 
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), true);
+	if (dp->plat_data->power_on)
+		dp->plat_data->power_on(dp->plat_data);
 
 	clk_prepare_enable(dp->clock);
 	phy_power_on(dp->phy);
-	exynos_dp_init_dp(dp);
+	analogix_dp_init_dp(dp);
 	enable_irq(dp->irq);
-	exynos_dp_commit(&dp->encoder);
+	analogix_dp_commit(dp);
 
 	dp->dpms_mode = DRM_MODE_DPMS_ON;
 }
 
-static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
+static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
+	struct analogix_dp_device *dp = bridge->driver_private;
 
 	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
 		return;
 
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel)) {
+	if (dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel)) {
 			DRM_ERROR("failed to disable the panel\n");
 			return;
 		}
@@ -1100,34 +1026,33 @@ static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
 	phy_power_off(dp->phy);
 	clk_disable_unprepare(dp->clock);
 
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), false);
+	if (dp->plat_data->power_off)
+		dp->plat_data->power_off(dp->plat_data);
 
-	if (dp->panel) {
-		if (drm_panel_unprepare(dp->panel))
+	if (dp->plat_data->panel) {
+		if (drm_panel_unprepare(dp->plat_data->panel))
 			DRM_ERROR("failed to turnoff the panel\n");
 	}
 
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
-static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
 }
 
-static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
-	.enable = exynos_dp_bridge_enable,
-	.disable = exynos_dp_bridge_disable,
-	.pre_enable = exynos_dp_bridge_nop,
-	.post_disable = exynos_dp_bridge_nop,
-	.attach = exynos_dp_bridge_attach,
+static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
+	.enable = analogix_dp_bridge_enable,
+	.disable = analogix_dp_bridge_disable,
+	.pre_enable = analogix_dp_bridge_nop,
+	.post_disable = analogix_dp_bridge_nop,
+	.attach = analogix_dp_bridge_attach,
 };
 
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int analogix_dp_create_bridge(struct drm_device *drm_dev,
+				     struct analogix_dp_device *dp)
 {
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
-	struct drm_device *drm_dev = dp->drm_dev;
 	struct drm_bridge *bridge;
 	int ret;
 
@@ -1139,10 +1064,10 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 
 	dp->bridge = bridge;
 
-	encoder->bridge = bridge;
+	dp->encoder->bridge = bridge;
 	bridge->driver_private = dp;
-	bridge->encoder = encoder;
-	bridge->funcs = &exynos_dp_bridge_funcs;
+	bridge->encoder = dp->encoder;
+	bridge->funcs = &analogix_dp_bridge_funcs;
 
 	ret = drm_bridge_attach(drm_dev, bridge);
 	if (ret) {
@@ -1153,39 +1078,7 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
 	return 0;
 }
 
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
-				 const struct drm_display_mode *mode,
-				 struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
-			       struct drm_display_mode *mode,
-			       struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
-{
-}
-
-static void exynos_dp_disable(struct drm_encoder *encoder)
-{
-}
-
-static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
-	.mode_fixup = exynos_dp_mode_fixup,
-	.mode_set = exynos_dp_mode_set,
-	.enable = exynos_dp_enable,
-	.disable = exynos_dp_disable,
-};
-
-static struct drm_encoder_funcs exynos_dp_encoder_funcs = {
-	.destroy = drm_encoder_cleanup,
-};
-
-static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
+static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 {
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
@@ -1243,33 +1136,37 @@ static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
 	return dp_video_config;
 }
 
-static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct analogix_dp_plat_data *plat_data)
 {
+	struct platform_device *pdev = to_platform_device(dev);
+	struct analogix_dp_device *dp;
+	struct resource *res;
+	unsigned int irq_flags;
 	int ret;
 
-	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
-			OF_USE_NATIVE_MODE);
-	if (ret) {
-		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
-		return ret;
+	if (!plat_data) {
+		dev_err(dev, "Invalided input plat_data\n");
+		return -EINVAL;
 	}
-	return 0;
-}
 
-static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
-{
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-	struct platform_device *pdev = to_platform_device(dev);
-	struct drm_device *drm_dev = data;
-	struct drm_encoder *encoder = &dp->encoder;
-	struct resource *res;
-	unsigned int irq_flags;
-	int pipe, ret = 0;
+	dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, dp);
 
 	dp->dev = &pdev->dev;
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 
-	dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
+	/*
+	 * platform dp driver need containor_of the plat_data to get
+	 * the driver private data, so we need to store the point of
+	 * plat_data, not the context of plat_data.
+	 */
+	dp->plat_data = plat_data;
+
+	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
 	if (IS_ERR(dp->video_info))
 		return PTR_ERR(dp->video_info);
 
@@ -1289,12 +1186,6 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		}
 	}
 
-	if (!dp->panel && !dp->ptn_bridge) {
-		ret = exynos_dp_dt_parse_panel(dp);
-		if (ret)
-			return ret;
-	}
-
 	dp->clock = devm_clk_get(&pdev->dev, "dp");
 	if (IS_ERR(dp->clock)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
@@ -1309,7 +1200,10 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
-	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
+	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
+	if (!gpio_is_valid(dp->hpd_gpio))
+		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
+						 "samsung,hpd-gpio", 0);
 
 	if (gpio_is_valid(dp->hpd_gpio)) {
 		/*
@@ -1338,14 +1232,14 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 		return -ENODEV;
 	}
 
-	INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
+	INIT_WORK(&dp->hotplug_work, analogix_dp_hotplug);
 
 	phy_power_on(dp->phy);
 
-	exynos_dp_init_dp(dp);
+	analogix_dp_init_dp(dp);
 
-	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
-			irq_flags, "exynos-dp", dp);
+	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
+			irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		return ret;
@@ -1353,103 +1247,48 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 	disable_irq(dp->irq);
 
 	dp->drm_dev = drm_dev;
+	dp->encoder = dp->plat_data->encoder;
 
-	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
-						  EXYNOS_DISPLAY_TYPE_LCD);
-	if (pipe < 0)
-		return pipe;
-
-	encoder->possible_crtcs = 1 << pipe;
-
-	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
-
-	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
-			 DRM_MODE_ENCODER_TMDS);
-
-	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
-
-	ret = exynos_dp_create_connector(encoder);
+	ret = analogix_dp_create_bridge(drm_dev, dp);
 	if (ret) {
-		DRM_ERROR("failed to create connector ret = %d\n", ret);
-		drm_encoder_cleanup(encoder);
+		DRM_ERROR("failed to create bridge (%d)\n", ret);
+		drm_encoder_cleanup(dp->encoder);
 		return ret;
 	}
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_bind);
 
-static void exynos_dp_unbind(struct device *dev, struct device *master,
-				void *data)
+void analogix_dp_unbind(struct device *dev, struct device *master,
+			void *data)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	exynos_dp_disable(&dp->encoder);
+	analogix_dp_bridge_disable(dp->bridge);
 }
+EXPORT_SYMBOL_GPL(analogix_dp_unbind);
 
-static const struct component_ops exynos_dp_ops = {
-	.bind	= exynos_dp_bind,
-	.unbind	= exynos_dp_unbind,
-};
-
-static int exynos_dp_probe(struct platform_device *pdev)
+#ifdef CONFIG_PM_SLEEP
+int analogix_dp_suspend(struct device *dev)
 {
-	struct device *dev = &pdev->dev;
-	struct device_node *panel_node, *bridge_node, *endpoint;
-	struct exynos_dp_device *dp;
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
-	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
-				GFP_KERNEL);
-	if (!dp)
-		return -ENOMEM;
-
-	platform_set_drvdata(pdev, dp);
-
-	panel_node = of_parse_phandle(dev->of_node, "panel", 0);
-	if (panel_node) {
-		dp->panel = of_drm_find_panel(panel_node);
-		of_node_put(panel_node);
-		if (!dp->panel)
-			return -EPROBE_DEFER;
-	}
-
-	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
-	if (endpoint) {
-		bridge_node = of_graph_get_remote_port_parent(endpoint);
-		if (bridge_node) {
-			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
-			of_node_put(bridge_node);
-			if (!dp->ptn_bridge)
-				return -EPROBE_DEFER;
-		} else
-			return -EPROBE_DEFER;
-	}
-
-	return component_add(&pdev->dev, &exynos_dp_ops);
+	analogix_dp_bridge_disable(dp->bridge);
+	return 0;
 }
+EXPORT_SYMBOL_GPL(analogix_dp_suspend);
 
-static int exynos_dp_remove(struct platform_device *pdev)
+int analogix_dp_resume(struct device *dev)
 {
-	component_del(&pdev->dev, &exynos_dp_ops);
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
+	analogix_dp_bridge_enable(dp->bridge);
 	return 0;
 }
-
-static const struct of_device_id exynos_dp_match[] = {
-	{ .compatible = "samsung,exynos5-dp" },
-	{},
-};
-MODULE_DEVICE_TABLE(of, exynos_dp_match);
-
-struct platform_driver dp_driver = {
-	.probe		= exynos_dp_probe,
-	.remove		= exynos_dp_remove,
-	.driver		= {
-		.name	= "exynos-dp",
-		.owner	= THIS_MODULE,
-		.of_match_table = exynos_dp_match,
-	},
-};
+EXPORT_SYMBOL_GPL(analogix_dp_resume);
+#endif
 
 MODULE_AUTHOR("Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
-MODULE_DESCRIPTION("Samsung SoC DP Driver");
+MODULE_DESCRIPTION("Analogix DP Core Driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
new file mode 100644
index 0000000..65ce7f1
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -0,0 +1,277 @@
+/*
+ * Header file for Analogix DP (Display Port) core interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _ANALOGIX_DP_CORE_H
+#define _ANALOGIX_DP_CORE_H
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_dp_helper.h>
+
+#define DP_TIMEOUT_LOOP_COUNT 100
+#define MAX_CR_LOOP 5
+#define MAX_EQ_LOOP 5
+
+enum link_rate_type {
+	LINK_RATE_1_62GBPS = 0x06,
+	LINK_RATE_2_70GBPS = 0x0a
+};
+
+enum link_lane_count_type {
+	LANE_COUNT1 = 1,
+	LANE_COUNT2 = 2,
+	LANE_COUNT4 = 4
+};
+
+enum link_training_state {
+	START,
+	CLOCK_RECOVERY,
+	EQUALIZER_TRAINING,
+	FINISHED,
+	FAILED
+};
+
+enum voltage_swing_level {
+	VOLTAGE_LEVEL_0,
+	VOLTAGE_LEVEL_1,
+	VOLTAGE_LEVEL_2,
+	VOLTAGE_LEVEL_3,
+};
+
+enum pre_emphasis_level {
+	PRE_EMPHASIS_LEVEL_0,
+	PRE_EMPHASIS_LEVEL_1,
+	PRE_EMPHASIS_LEVEL_2,
+	PRE_EMPHASIS_LEVEL_3,
+};
+
+enum pattern_set {
+	PRBS7,
+	D10_2,
+	TRAINING_PTN1,
+	TRAINING_PTN2,
+	DP_NONE
+};
+
+enum color_space {
+	COLOR_RGB,
+	COLOR_YCBCR422,
+	COLOR_YCBCR444
+};
+
+enum color_depth {
+	COLOR_6,
+	COLOR_8,
+	COLOR_10,
+	COLOR_12
+};
+
+enum color_coefficient {
+	COLOR_YCBCR601,
+	COLOR_YCBCR709
+};
+
+enum dynamic_range {
+	VESA,
+	CEA
+};
+
+enum pll_status {
+	PLL_UNLOCKED,
+	PLL_LOCKED
+};
+
+enum clock_recovery_m_value_type {
+	CALCULATED_M,
+	REGISTER_M
+};
+
+enum video_timing_recognition_type {
+	VIDEO_TIMING_FROM_CAPTURE,
+	VIDEO_TIMING_FROM_REGISTER
+};
+
+enum analog_power_block {
+	AUX_BLOCK,
+	CH0_BLOCK,
+	CH1_BLOCK,
+	CH2_BLOCK,
+	CH3_BLOCK,
+	ANALOG_TOTAL,
+	POWER_ALL
+};
+
+enum dp_irq_type {
+	DP_IRQ_TYPE_HP_CABLE_IN,
+	DP_IRQ_TYPE_HP_CABLE_OUT,
+	DP_IRQ_TYPE_HP_CHANGE,
+	DP_IRQ_TYPE_UNKNOWN,
+};
+
+struct video_info {
+	char *name;
+
+	bool h_sync_polarity;
+	bool v_sync_polarity;
+	bool interlaced;
+
+	enum color_space color_space;
+	enum dynamic_range dynamic_range;
+	enum color_coefficient ycbcr_coeff;
+	enum color_depth color_depth;
+
+	enum link_rate_type link_rate;
+	enum link_lane_count_type lane_count;
+};
+
+struct link_train {
+	int eq_loop;
+	int cr_loop[4];
+
+	u8 link_rate;
+	u8 lane_count;
+	u8 training_lane[4];
+
+	enum link_training_state lt_state;
+};
+
+struct analogix_dp_device {
+	struct drm_encoder	*encoder;
+	struct drm_connector	*connector;
+	struct device		*dev;
+	struct drm_device	*drm_dev;
+	struct drm_bridge	*bridge;
+	struct clk		*clock;
+	unsigned int		irq;
+	void __iomem		*reg_base;
+
+	struct video_info	*video_info;
+	struct link_train	link_train;
+	struct work_struct	hotplug_work;
+	struct phy		*phy;
+	int			dpms_mode;
+	int			hpd_gpio;
+
+	struct analogix_dp_plat_data *plat_data;
+};
+
+/* analogix_dp_reg.c */
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_stop_video(struct analogix_dp_device *dp);
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
+void analogix_dp_reset(struct analogix_dp_device *dp);
+void analogix_dp_swreset(struct analogix_dp_device *dp);
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				       enum analog_power_block block,
+				       bool enable);
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
+void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
+void analogix_dp_reset_aux(struct analogix_dp_device *dp);
+void analogix_dp_init_aux(struct analogix_dp_device *dp);
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char data);
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char *data);
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[]);
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[]);
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr);
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int *data);
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char edid[]);
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
+void analogix_dp_reset_macro(struct analogix_dp_device *dp);
+void analogix_dp_init_video(struct analogix_dp_device *dp);
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+			enum clock_recovery_m_value_type type,
+			u32 m_value,
+			u32 n_value);
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_start_video(struct analogix_dp_device *dp);
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
+#endif /* _ANALOGIX_DP_CORE_H */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
new file mode 100644
index 0000000..442cc66
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -0,0 +1,1263 @@
+/*
+ * Analogix DP (Display port) core register interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include "analogix_dp_core.h"
+#include "analogix_dp_reg.h"
+
+#define COMMON_INT_MASK_1	0
+#define COMMON_INT_MASK_2	0
+#define COMMON_INT_MASK_3	0
+#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
+#define INT_STA_MASK		INT_HPD
+
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+		reg |= HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+		reg &= ~HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	}
+}
+
+void analogix_dp_stop_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	reg &= ~VIDEO_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+}
+
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable)
+		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
+			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+	else
+		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
+			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
+}
+
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = TX_TERMINAL_CTRL_50_OHM;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
+
+	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
+
+	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
+
+	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
+		TX_CUR1_2X | TX_CUR_16_MA;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
+
+	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
+		CH1_AMP_400_MV | CH0_AMP_400_MV;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
+}
+
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
+{
+	/* Set interrupt pin assertion polarity as high */
+	writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
+
+	/* Clear pending regisers */
+	writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+	writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
+	writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
+	writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+	writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	/* 0:mask,1: unmask */
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+void analogix_dp_reset(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	analogix_dp_stop_video(dp);
+	analogix_dp_enable_video_mute(dp, 0);
+
+	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
+		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
+		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+
+	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
+		SERDES_FIFO_FUNC_EN_N |
+		LS_CLK_DOMAIN_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+
+	usleep_range(20, 30);
+
+	analogix_dp_lane_swap(dp, 0);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
+
+	writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
+	writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
+
+	writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+
+	writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
+	writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
+
+	writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
+	writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
+
+	writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_swreset(struct analogix_dp_device *dp)
+{
+	writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
+}
+
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* 0: mask, 1: unmask */
+	reg = COMMON_INT_MASK_1;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+
+	reg = COMMON_INT_MASK_2;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+
+	reg = COMMON_INT_MASK_3;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+
+	reg = COMMON_INT_MASK_4;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+
+	reg = INT_STA_MASK;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+	if (reg & PLL_LOCK)
+		return PLL_LOCKED;
+	else
+		return PLL_UNLOCKED;
+}
+
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
+		reg |= DP_PLL_PD;
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
+		reg &= ~DP_PLL_PD;
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+	}
+}
+
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				enum analog_power_block block,
+				bool enable)
+{
+	u32 reg;
+
+	switch (block) {
+	case AUX_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= AUX_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~AUX_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH0_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH1_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH1_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH1_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH2_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH2_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH2_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case CH3_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= CH3_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~CH3_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case ANALOG_TOTAL:
+		if (enable) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg |= DP_PHY_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg &= ~DP_PHY_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	case POWER_ALL:
+		if (enable) {
+			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
+				CH1_PD | CH0_PD;
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		} else {
+			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
+{
+	u32 reg;
+	int timeout_loop = 0;
+
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
+
+	reg = PLL_LOCK_CHG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
+
+	/* Power up PLL */
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		analogix_dp_set_pll_power_down(dp, 0);
+
+		while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+			timeout_loop++;
+			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+				dev_err(dp->dev, "failed to get pll lock status\n");
+				return;
+			}
+			usleep_range(10, 20);
+		}
+	}
+
+	/* Enable Serdes FIFO function and Link symbol clock domain module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
+		| AUX_FUNC_EN_N);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+
+	reg = INT_HPD;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+}
+
+void analogix_dp_init_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	analogix_dp_clear_hotplug_interrupts(dp);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg &= ~(F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		reg = gpio_get_value(dp->hpd_gpio);
+		if (reg)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+		else
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+	} else {
+		/* Parse hotplug interrupt status register */
+		reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+
+		if (reg & PLUG)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+
+		if (reg & HPD_LOST)
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+
+		if (reg & HOTPLUG_CHG)
+			return DP_IRQ_TYPE_HP_CHANGE;
+
+		return DP_IRQ_TYPE_UNKNOWN;
+	}
+}
+
+void analogix_dp_reset_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Disable AUX channel module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg |= AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+void analogix_dp_init_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Clear inerrupts related to AUX channel */
+	reg = RPLY_RECEIV | AUX_ERR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	analogix_dp_reset_aux(dp);
+
+	/* Disable AUX transaction H/W retry */
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
+		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
+
+	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
+	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
+
+	/* Enable AUX channel module */
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+	reg &= ~AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+}
+
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		if (gpio_get_value(dp->hpd_gpio))
+			return 0;
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+		if (reg & HPD_STATUS)
+			return 0;
+	}
+
+	return -EINVAL;
+}
+
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+	reg &= ~SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+}
+
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
+{
+	int reg;
+	int retval = 0;
+	int timeout_loop = 0;
+
+	/* Enable AUX CH operation */
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+	reg |= AUX_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+
+	/* Is AUX CH command reply received? */
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+	while (!(reg & RPLY_RECEIV)) {
+		timeout_loop++;
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "AUX CH command reply failed!\n");
+			return -ETIMEDOUT;
+		}
+		reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+		usleep_range(10, 11);
+	}
+
+	/* Clear interrupt source for AUX CH command reply */
+	writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
+
+	/* Clear interrupt source for AUX CH access error */
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
+	if (reg & AUX_ERR) {
+		writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
+		return -EREMOTEIO;
+	}
+
+	/* Check AUX CH error access status */
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
+	if ((reg & AUX_STATUS_MASK) != 0) {
+		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
+			reg & AUX_STATUS_MASK);
+		return -EREMOTEIO;
+	}
+
+	return retval;
+}
+
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+		/* Write data buffer */
+		reg = (unsigned int)data;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+		/*
+		 * Set DisplayPort transaction and write 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+		/*
+		 * Set DisplayPort transaction and read 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	/* Read data buffer */
+	reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+	*data = (unsigned char)(reg & 0xff);
+
+	return retval;
+}
+
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+			     cur_data_idx++) {
+				reg = data[start_offset + cur_data_idx];
+				writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+							  + 4 * cur_data_idx);
+			}
+
+			/*
+			 * Set DisplayPort transaction and write
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+			else
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		/* AUX CH Request Transaction process */
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+			/*
+			 * Set DisplayPort transaction and read
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+			else
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+		    cur_data_idx++) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			data[start_offset + cur_data_idx] =
+				(unsigned char)reg;
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr)
+{
+	u32 reg;
+	int retval;
+
+	/* Set EDID device address */
+	reg = device_addr;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
+
+	/* Set offset from base address of EDID device */
+	writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+	/*
+	 * Set I2C transaction and write address
+	 * If bit 3 is 1, DisplayPort transaction.
+	 * If Bit 3 is 0, I2C transaction.
+	 */
+	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
+		AUX_TX_COMM_WRITE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+	/* Start AUX transaction */
+	retval = analogix_dp_start_aux_transaction(dp);
+	if (retval != 0)
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+		/* Select EDID device */
+		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+		if (retval != 0)
+			continue;
+
+		/*
+		 * Set I2C transaction and read data
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_I2C_TRANSACTION |
+			AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	/* Read data */
+	if (retval == 0)
+		*data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char edid[])
+{
+	u32 reg;
+	unsigned int i, j;
+	unsigned int cur_data_idx;
+	unsigned int defer = 0;
+	int retval = 0;
+
+	for (i = 0; i < count; i += 16) {
+		for (j = 0; j < 3; j++) {
+			/* Clear AUX CH data buffer */
+			reg = BUF_CLR;
+			writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
+
+			/* Set normal AUX CH command */
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+			reg &= ~ADDR_ONLY;
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
+
+			/*
+			 * If Rx sends defer, Tx sends only reads
+			 * request without sending address
+			 */
+			if (!defer)
+				retval = analogix_dp_select_i2c_device(dp,
+						device_addr, reg_addr + i);
+			else
+				defer = 0;
+
+			if (retval == 0) {
+				/*
+				 * Set I2C transaction and write data
+				 * If bit 3 is 1, DisplayPort transaction.
+				 * If Bit 3 is 0, I2C transaction.
+				 */
+				reg = AUX_LENGTH(16) |
+					AUX_TX_COMM_I2C_TRANSACTION |
+					AUX_TX_COMM_READ;
+				writel(reg, dp->reg_base +
+					ANALOGIX_DP_AUX_CH_CTL_1);
+
+				/* Start AUX transaction */
+				retval = analogix_dp_start_aux_transaction(dp);
+				if (retval == 0)
+					break;
+				else
+					dev_dbg(dp->dev,
+						"%s: Aux Transaction fail!\n",
+						__func__);
+			}
+			/* Check if Rx sends defer */
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
+			if (reg == AUX_RX_COMM_AUX_DEFER ||
+				reg == AUX_RX_COMM_I2C_DEFER) {
+				dev_err(dp->dev, "Defer: %d\n\n", reg);
+				defer = 1;
+			}
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			edid[i + cur_data_idx] = (unsigned char)reg;
+		}
+	}
+
+	return retval;
+}
+
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
+{
+	u32 reg;
+
+	reg = bwtype;
+	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
+		writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
+}
+
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
+	*bwtype = reg;
+}
+
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
+{
+	u32 reg;
+
+	reg = count;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
+}
+
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
+	*count = reg;
+}
+
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg |= ENHANCED;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg &= ~ENHANCED;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+	}
+}
+
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				enum pattern_set pattern)
+{
+	u32 reg;
+
+	switch (pattern) {
+	case PRBS7:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case D10_2:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN1:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN2:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	case DP_NONE:
+		reg = SCRAMBLING_ENABLE |
+			LINK_QUAL_PATTERN_SET_DISABLE |
+			SW_TRAINING_PATTERN_SET_NORMAL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+}
+
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
+	return reg;
+}
+
+void analogix_dp_reset_macro(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
+	reg |= MACRO_RST;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+
+	/* 10 us is the minimum reset time. */
+	usleep_range(10, 20);
+
+	reg &= ~MACRO_RST;
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
+}
+
+void analogix_dp_init_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	reg = CHA_CRI(4) | CHA_CTRL;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+
+	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
+}
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Configure the input color depth, color space, dynamic range */
+	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info->color_depth << IN_BPC_SHIFT) |
+		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
+
+	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
+	reg &= ~IN_YC_COEFFI_MASK;
+	if (dp->video_info->ycbcr_coeff)
+		reg |= IN_YC_COEFFI_ITU709;
+	else
+		reg |= IN_YC_COEFFI_ITU601;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
+}
+
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+
+	if (!(reg & DET_STA)) {
+		dev_dbg(dp->dev, "Input stream clock not detected.\n");
+		return -EINVAL;
+	}
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
+
+	if (reg & CHA_STA) {
+		dev_dbg(dp->dev, "Input stream clk is changing\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+		enum clock_recovery_m_value_type type,
+		u32 m_value,
+		u32 n_value)
+{
+	u32 reg;
+
+	if (type == REGISTER_M) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg |= FIX_M_VID;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg = m_value & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
+		reg = (m_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
+		reg = (m_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
+
+		reg = n_value & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		reg = (n_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		reg = (n_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
+	} else  {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+		reg &= ~FIX_M_VID;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
+
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
+	}
+}
+
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
+{
+	u32 reg;
+
+	if (type == VIDEO_TIMING_FROM_CAPTURE) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+		reg &= ~FORMAT_SEL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+		reg |= FORMAT_SEL;
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	}
+}
+
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+	} else {
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MODE_SLAVE_MODE;
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+	}
+}
+
+void analogix_dp_start_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+	reg |= VIDEO_EN;
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
+}
+
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	if (!(reg & STRM_VALID)) {
+		dev_dbg(dp->dev, "Input video stream is not detected.\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg |= MASTER_VID_FUNC_EN_N;
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~INTERACE_SCAN_CFG;
+	reg |= (dp->video_info->interlaced << 2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~VSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->v_sync_polarity << 1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+	reg &= ~HSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->h_sync_polarity << 0);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
+
+	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+	reg &= ~SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+}
+
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+	reg |= SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
similarity index 64%
rename from drivers/gpu/drm/exynos/exynos_dp_reg.h
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 2e9bd0e..738db4c 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -1,5 +1,5 @@
 /*
- * Register definition file for Samsung DP driver
+ * Register definition file for Analogix DP core driver
  *
  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
@@ -9,96 +9,96 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef _EXYNOS_DP_REG_H
-#define _EXYNOS_DP_REG_H
-
-#define EXYNOS_DP_TX_SW_RESET			0x14
-#define EXYNOS_DP_FUNC_EN_1			0x18
-#define EXYNOS_DP_FUNC_EN_2			0x1C
-#define EXYNOS_DP_VIDEO_CTL_1			0x20
-#define EXYNOS_DP_VIDEO_CTL_2			0x24
-#define EXYNOS_DP_VIDEO_CTL_3			0x28
-
-#define EXYNOS_DP_VIDEO_CTL_8			0x3C
-#define EXYNOS_DP_VIDEO_CTL_10			0x44
-
-#define EXYNOS_DP_LANE_MAP			0x35C
-
-#define EXYNOS_DP_ANALOG_CTL_1			0x370
-#define EXYNOS_DP_ANALOG_CTL_2			0x374
-#define EXYNOS_DP_ANALOG_CTL_3			0x378
-#define EXYNOS_DP_PLL_FILTER_CTL_1		0x37C
-#define EXYNOS_DP_TX_AMP_TUNING_CTL		0x380
-
-#define EXYNOS_DP_AUX_HW_RETRY_CTL		0x390
-
-#define EXYNOS_DP_COMMON_INT_STA_1		0x3C4
-#define EXYNOS_DP_COMMON_INT_STA_2		0x3C8
-#define EXYNOS_DP_COMMON_INT_STA_3		0x3CC
-#define EXYNOS_DP_COMMON_INT_STA_4		0x3D0
-#define EXYNOS_DP_INT_STA			0x3DC
-#define EXYNOS_DP_COMMON_INT_MASK_1		0x3E0
-#define EXYNOS_DP_COMMON_INT_MASK_2		0x3E4
-#define EXYNOS_DP_COMMON_INT_MASK_3		0x3E8
-#define EXYNOS_DP_COMMON_INT_MASK_4		0x3EC
-#define EXYNOS_DP_INT_STA_MASK			0x3F8
-#define EXYNOS_DP_INT_CTL			0x3FC
-
-#define EXYNOS_DP_SYS_CTL_1			0x600
-#define EXYNOS_DP_SYS_CTL_2			0x604
-#define EXYNOS_DP_SYS_CTL_3			0x608
-#define EXYNOS_DP_SYS_CTL_4			0x60C
-
-#define EXYNOS_DP_PKT_SEND_CTL			0x640
-#define EXYNOS_DP_HDCP_CTL			0x648
-
-#define EXYNOS_DP_LINK_BW_SET			0x680
-#define EXYNOS_DP_LANE_COUNT_SET		0x684
-#define EXYNOS_DP_TRAINING_PTN_SET		0x688
-#define EXYNOS_DP_LN0_LINK_TRAINING_CTL		0x68C
-#define EXYNOS_DP_LN1_LINK_TRAINING_CTL		0x690
-#define EXYNOS_DP_LN2_LINK_TRAINING_CTL		0x694
-#define EXYNOS_DP_LN3_LINK_TRAINING_CTL		0x698
-
-#define EXYNOS_DP_DEBUG_CTL			0x6C0
-#define EXYNOS_DP_HPD_DEGLITCH_L		0x6C4
-#define EXYNOS_DP_HPD_DEGLITCH_H		0x6C8
-#define EXYNOS_DP_LINK_DEBUG_CTL		0x6E0
-
-#define EXYNOS_DP_M_VID_0			0x700
-#define EXYNOS_DP_M_VID_1			0x704
-#define EXYNOS_DP_M_VID_2			0x708
-#define EXYNOS_DP_N_VID_0			0x70C
-#define EXYNOS_DP_N_VID_1			0x710
-#define EXYNOS_DP_N_VID_2			0x714
-
-#define EXYNOS_DP_PLL_CTL			0x71C
-#define EXYNOS_DP_PHY_PD			0x720
-#define EXYNOS_DP_PHY_TEST			0x724
-
-#define EXYNOS_DP_VIDEO_FIFO_THRD		0x730
-#define EXYNOS_DP_AUDIO_MARGIN			0x73C
-
-#define EXYNOS_DP_M_VID_GEN_FILTER_TH		0x764
-#define EXYNOS_DP_M_AUD_GEN_FILTER_TH		0x778
-#define EXYNOS_DP_AUX_CH_STA			0x780
-#define EXYNOS_DP_AUX_CH_DEFER_CTL		0x788
-#define EXYNOS_DP_AUX_RX_COMM			0x78C
-#define EXYNOS_DP_BUFFER_DATA_CTL		0x790
-#define EXYNOS_DP_AUX_CH_CTL_1			0x794
-#define EXYNOS_DP_AUX_ADDR_7_0			0x798
-#define EXYNOS_DP_AUX_ADDR_15_8			0x79C
-#define EXYNOS_DP_AUX_ADDR_19_16		0x7A0
-#define EXYNOS_DP_AUX_CH_CTL_2			0x7A4
-
-#define EXYNOS_DP_BUF_DATA_0			0x7C0
-
-#define EXYNOS_DP_SOC_GENERAL_CTL		0x800
-
-/* EXYNOS_DP_TX_SW_RESET */
+#ifndef _ANALOGIX_DP_REG_H
+#define _ANALOGIX_DP_REG_H
+
+#define ANALOGIX_DP_TX_SW_RESET			0x14
+#define ANALOGIX_DP_FUNC_EN_1			0x18
+#define ANALOGIX_DP_FUNC_EN_2			0x1C
+#define ANALOGIX_DP_VIDEO_CTL_1			0x20
+#define ANALOGIX_DP_VIDEO_CTL_2			0x24
+#define ANALOGIX_DP_VIDEO_CTL_3			0x28
+
+#define ANALOGIX_DP_VIDEO_CTL_8			0x3C
+#define ANALOGIX_DP_VIDEO_CTL_10		0x44
+
+#define ANALOGIX_DP_LANE_MAP			0x35C
+
+#define ANALOGIX_DP_ANALOG_CTL_1		0x370
+#define ANALOGIX_DP_ANALOG_CTL_2		0x374
+#define ANALOGIX_DP_ANALOG_CTL_3		0x378
+#define ANALOGIX_DP_PLL_FILTER_CTL_1		0x37C
+#define ANALOGIX_DP_TX_AMP_TUNING_CTL		0x380
+
+#define ANALOGIX_DP_AUX_HW_RETRY_CTL		0x390
+
+#define ANALOGIX_DP_COMMON_INT_STA_1		0x3C4
+#define ANALOGIX_DP_COMMON_INT_STA_2		0x3C8
+#define ANALOGIX_DP_COMMON_INT_STA_3		0x3CC
+#define ANALOGIX_DP_COMMON_INT_STA_4		0x3D0
+#define ANALOGIX_DP_INT_STA			0x3DC
+#define ANALOGIX_DP_COMMON_INT_MASK_1		0x3E0
+#define ANALOGIX_DP_COMMON_INT_MASK_2		0x3E4
+#define ANALOGIX_DP_COMMON_INT_MASK_3		0x3E8
+#define ANALOGIX_DP_COMMON_INT_MASK_4		0x3EC
+#define ANALOGIX_DP_INT_STA_MASK		0x3F8
+#define ANALOGIX_DP_INT_CTL			0x3FC
+
+#define ANALOGIX_DP_SYS_CTL_1			0x600
+#define ANALOGIX_DP_SYS_CTL_2			0x604
+#define ANALOGIX_DP_SYS_CTL_3			0x608
+#define ANALOGIX_DP_SYS_CTL_4			0x60C
+
+#define ANALOGIX_DP_PKT_SEND_CTL		0x640
+#define ANALOGIX_DP_HDCP_CTL			0x648
+
+#define ANALOGIX_DP_LINK_BW_SET			0x680
+#define ANALOGIX_DP_LANE_COUNT_SET		0x684
+#define ANALOGIX_DP_TRAINING_PTN_SET		0x688
+#define ANALOGIX_DP_LN0_LINK_TRAINING_CTL	0x68C
+#define ANALOGIX_DP_LN1_LINK_TRAINING_CTL	0x690
+#define ANALOGIX_DP_LN2_LINK_TRAINING_CTL	0x694
+#define ANALOGIX_DP_LN3_LINK_TRAINING_CTL	0x698
+
+#define ANALOGIX_DP_DEBUG_CTL			0x6C0
+#define ANALOGIX_DP_HPD_DEGLITCH_L		0x6C4
+#define ANALOGIX_DP_HPD_DEGLITCH_H		0x6C8
+#define ANALOGIX_DP_LINK_DEBUG_CTL		0x6E0
+
+#define ANALOGIX_DP_M_VID_0			0x700
+#define ANALOGIX_DP_M_VID_1			0x704
+#define ANALOGIX_DP_M_VID_2			0x708
+#define ANALOGIX_DP_N_VID_0			0x70C
+#define ANALOGIX_DP_N_VID_1			0x710
+#define ANALOGIX_DP_N_VID_2			0x714
+
+#define ANALOGIX_DP_PLL_CTL			0x71C
+#define ANALOGIX_DP_PHY_PD			0x720
+#define ANALOGIX_DP_PHY_TEST			0x724
+
+#define ANALOGIX_DP_VIDEO_FIFO_THRD		0x730
+#define ANALOGIX_DP_AUDIO_MARGIN		0x73C
+
+#define ANALOGIX_DP_M_VID_GEN_FILTER_TH		0x764
+#define ANALOGIX_DP_M_AUD_GEN_FILTER_TH		0x778
+#define ANALOGIX_DP_AUX_CH_STA			0x780
+#define ANALOGIX_DP_AUX_CH_DEFER_CTL		0x788
+#define ANALOGIX_DP_AUX_RX_COMM			0x78C
+#define ANALOGIX_DP_BUFFER_DATA_CTL		0x790
+#define ANALOGIX_DP_AUX_CH_CTL_1		0x794
+#define ANALOGIX_DP_AUX_ADDR_7_0		0x798
+#define ANALOGIX_DP_AUX_ADDR_15_8		0x79C
+#define ANALOGIX_DP_AUX_ADDR_19_16		0x7A0
+#define ANALOGIX_DP_AUX_CH_CTL_2		0x7A4
+
+#define ANALOGIX_DP_BUF_DATA_0			0x7C0
+
+#define ANALOGIX_DP_SOC_GENERAL_CTL		0x800
+
+/* ANALOGIX_DP_TX_SW_RESET */
 #define RESET_DP_TX				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_1 */
+/* ANALOGIX_DP_FUNC_EN_1 */
 #define MASTER_VID_FUNC_EN_N			(0x1 << 7)
 #define SLAVE_VID_FUNC_EN_N			(0x1 << 5)
 #define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
@@ -107,17 +107,17 @@
 #define CRC_FUNC_EN_N				(0x1 << 1)
 #define SW_FUNC_EN_N				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_2 */
+/* ANALOGIX_DP_FUNC_EN_2 */
 #define SSC_FUNC_EN_N				(0x1 << 7)
 #define AUX_FUNC_EN_N				(0x1 << 2)
 #define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
 #define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define VIDEO_EN				(0x1 << 7)
 #define HDCP_VIDEO_MUTE				(0x1 << 6)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define IN_D_RANGE_MASK				(0x1 << 7)
 #define IN_D_RANGE_SHIFT			(7)
 #define IN_D_RANGE_CEA				(0x1 << 7)
@@ -134,7 +134,7 @@
 #define IN_COLOR_F_YCBCR422			(0x1 << 0)
 #define IN_COLOR_F_RGB				(0x0 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_3 */
+/* ANALOGIX_DP_VIDEO_CTL_3 */
 #define IN_YC_COEFFI_MASK			(0x1 << 7)
 #define IN_YC_COEFFI_SHIFT			(7)
 #define IN_YC_COEFFI_ITU709			(0x1 << 7)
@@ -144,17 +144,17 @@
 #define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
 #define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
 
-/* EXYNOS_DP_VIDEO_CTL_8 */
+/* ANALOGIX_DP_VIDEO_CTL_8 */
 #define VID_HRES_TH(x)				(((x) & 0xf) << 4)
 #define VID_VRES_TH(x)				(((x) & 0xf) << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_10 */
+/* ANALOGIX_DP_VIDEO_CTL_10 */
 #define FORMAT_SEL				(0x1 << 4)
 #define INTERACE_SCAN_CFG			(0x1 << 2)
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
-/* EXYNOS_DP_LANE_MAP */
+/* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
 #define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
@@ -172,30 +172,30 @@
 #define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
 #define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_1 */
+/* ANALOGIX_DP_ANALOG_CTL_1 */
 #define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
 
-/* EXYNOS_DP_ANALOG_CTL_2 */
+/* ANALOGIX_DP_ANALOG_CTL_2 */
 #define SEL_24M					(0x1 << 3)
 #define TX_DVDD_BIT_1_0625V			(0x4 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_3 */
+/* ANALOGIX_DP_ANALOG_CTL_3 */
 #define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
 #define VCO_BIT_600_MICRO			(0x5 << 0)
 
-/* EXYNOS_DP_PLL_FILTER_CTL_1 */
+/* ANALOGIX_DP_PLL_FILTER_CTL_1 */
 #define PD_RING_OSC				(0x1 << 6)
 #define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
 #define TX_CUR1_2X				(0x1 << 2)
 #define TX_CUR_16_MA				(0x3 << 0)
 
-/* EXYNOS_DP_TX_AMP_TUNING_CTL */
+/* ANALOGIX_DP_TX_AMP_TUNING_CTL */
 #define CH3_AMP_400_MV				(0x0 << 24)
 #define CH2_AMP_400_MV				(0x0 << 16)
 #define CH1_AMP_400_MV				(0x0 << 8)
 #define CH0_AMP_400_MV				(0x0 << 0)
 
-/* EXYNOS_DP_AUX_HW_RETRY_CTL */
+/* ANALOGIX_DP_AUX_HW_RETRY_CTL */
 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x)	(((x) & 0x7) << 8)
 #define AUX_HW_RETRY_INTERVAL_MASK		(0x3 << 3)
 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS	(0x0 << 3)
@@ -204,7 +204,7 @@
 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS	(0x3 << 3)
 #define AUX_HW_RETRY_COUNT_SEL(x)		(((x) & 0x7) << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_1 */
+/* ANALOGIX_DP_COMMON_INT_STA_1 */
 #define VSYNC_DET				(0x1 << 7)
 #define PLL_LOCK_CHG				(0x1 << 6)
 #define SPDIF_ERR				(0x1 << 5)
@@ -214,19 +214,19 @@
 #define VID_CLK_CHG				(0x1 << 1)
 #define SW_INT					(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_2 */
+/* ANALOGIX_DP_COMMON_INT_STA_2 */
 #define ENC_EN_CHG				(0x1 << 6)
 #define HW_BKSV_RDY				(0x1 << 3)
 #define HW_SHA_DONE				(0x1 << 2)
 #define HW_AUTH_STATE_CHG			(0x1 << 1)
 #define HW_AUTH_DONE				(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_3 */
+/* ANALOGIX_DP_COMMON_INT_STA_3 */
 #define AFIFO_UNDER				(0x1 << 7)
 #define AFIFO_OVER				(0x1 << 6)
 #define R0_CHK_FLAG				(0x1 << 5)
 
-/* EXYNOS_DP_COMMON_INT_STA_4 */
+/* ANALOGIX_DP_COMMON_INT_STA_4 */
 #define PSR_ACTIVE				(0x1 << 7)
 #define PSR_INACTIVE				(0x1 << 6)
 #define SPDIF_BI_PHASE_ERR			(0x1 << 5)
@@ -234,29 +234,29 @@
 #define HPD_LOST				(0x1 << 1)
 #define PLUG					(0x1 << 0)
 
-/* EXYNOS_DP_INT_STA */
+/* ANALOGIX_DP_INT_STA */
 #define INT_HPD					(0x1 << 6)
 #define HW_TRAINING_FINISH			(0x1 << 5)
 #define RPLY_RECEIV				(0x1 << 1)
 #define AUX_ERR					(0x1 << 0)
 
-/* EXYNOS_DP_INT_CTL */
+/* ANALOGIX_DP_INT_CTL */
 #define SOFT_INT_CTRL				(0x1 << 2)
 #define INT_POL1				(0x1 << 1)
 #define INT_POL0				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_1 */
+/* ANALOGIX_DP_SYS_CTL_1 */
 #define DET_STA					(0x1 << 2)
 #define FORCE_DET				(0x1 << 1)
 #define DET_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_2 */
+/* ANALOGIX_DP_SYS_CTL_2 */
 #define CHA_CRI(x)				(((x) & 0xf) << 4)
 #define CHA_STA					(0x1 << 2)
 #define FORCE_CHA				(0x1 << 1)
 #define CHA_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_3 */
+/* ANALOGIX_DP_SYS_CTL_3 */
 #define HPD_STATUS				(0x1 << 6)
 #define F_HPD					(0x1 << 5)
 #define HPD_CTRL				(0x1 << 4)
@@ -265,13 +265,13 @@
 #define F_VALID					(0x1 << 1)
 #define VALID_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_4 */
+/* ANALOGIX_DP_SYS_CTL_4 */
 #define FIX_M_AUD				(0x1 << 4)
 #define ENHANCED				(0x1 << 3)
 #define FIX_M_VID				(0x1 << 2)
 #define M_VID_UPDATE_CTRL			(0x3 << 0)
 
-/* EXYNOS_DP_TRAINING_PTN_SET */
+/* ANALOGIX_DP_TRAINING_PTN_SET */
 #define SCRAMBLER_TYPE				(0x1 << 9)
 #define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
 #define SCRAMBLING_DISABLE			(0x1 << 5)
@@ -285,24 +285,24 @@
 #define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
 #define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
 
-/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+/* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */
 #define PRE_EMPHASIS_SET_MASK			(0x3 << 3)
 #define PRE_EMPHASIS_SET_SHIFT			(3)
 
-/* EXYNOS_DP_DEBUG_CTL */
+/* ANALOGIX_DP_DEBUG_CTL */
 #define PLL_LOCK				(0x1 << 4)
 #define F_PLL_LOCK				(0x1 << 3)
 #define PLL_LOCK_CTRL				(0x1 << 2)
 #define PN_INV					(0x1 << 0)
 
-/* EXYNOS_DP_PLL_CTL */
+/* ANALOGIX_DP_PLL_CTL */
 #define DP_PLL_PD				(0x1 << 7)
 #define DP_PLL_RESET				(0x1 << 6)
 #define DP_PLL_LOOP_BIT_DEFAULT			(0x1 << 4)
 #define DP_PLL_REF_BIT_1_1250V			(0x5 << 0)
 #define DP_PLL_REF_BIT_1_2500V			(0x7 << 0)
 
-/* EXYNOS_DP_PHY_PD */
+/* ANALOGIX_DP_PHY_PD */
 #define DP_PHY_PD				(0x1 << 5)
 #define AUX_PD					(0x1 << 4)
 #define CH3_PD					(0x1 << 3)
@@ -310,28 +310,28 @@
 #define CH1_PD					(0x1 << 1)
 #define CH0_PD					(0x1 << 0)
 
-/* EXYNOS_DP_PHY_TEST */
+/* ANALOGIX_DP_PHY_TEST */
 #define MACRO_RST				(0x1 << 5)
 #define CH1_TEST				(0x1 << 1)
 #define CH0_TEST				(0x1 << 0)
 
-/* EXYNOS_DP_AUX_CH_STA */
+/* ANALOGIX_DP_AUX_CH_STA */
 #define AUX_BUSY				(0x1 << 4)
 #define AUX_STATUS_MASK				(0xf << 0)
 
-/* EXYNOS_DP_AUX_CH_DEFER_CTL */
+/* ANALOGIX_DP_AUX_CH_DEFER_CTL */
 #define DEFER_CTRL_EN				(0x1 << 7)
 #define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
 
-/* EXYNOS_DP_AUX_RX_COMM */
+/* ANALOGIX_DP_AUX_RX_COMM */
 #define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
 #define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
 
-/* EXYNOS_DP_BUFFER_DATA_CTL */
+/* ANALOGIX_DP_BUFFER_DATA_CTL */
 #define BUF_CLR					(0x1 << 7)
 #define BUF_DATA_COUNT(x)			(((x) & 0x1f) << 0)
 
-/* EXYNOS_DP_AUX_CH_CTL_1 */
+/* ANALOGIX_DP_AUX_CH_CTL_1 */
 #define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
 #define AUX_TX_COMM_MASK			(0xf << 0)
 #define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
@@ -340,20 +340,20 @@
 #define AUX_TX_COMM_WRITE			(0x0 << 0)
 #define AUX_TX_COMM_READ			(0x1 << 0)
 
-/* EXYNOS_DP_AUX_ADDR_7_0 */
+/* ANALOGIX_DP_AUX_ADDR_7_0 */
 #define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_15_8 */
+/* ANALOGIX_DP_AUX_ADDR_15_8 */
 #define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_19_16 */
+/* ANALOGIX_DP_AUX_ADDR_19_16 */
 #define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
 
-/* EXYNOS_DP_AUX_CH_CTL_2 */
+/* ANALOGIX_DP_AUX_CH_CTL_2 */
 #define ADDR_ONLY				(0x1 << 1)
 #define AUX_EN					(0x1 << 0)
 
-/* EXYNOS_DP_SOC_GENERAL_CTL */
+/* ANALOGIX_DP_SOC_GENERAL_CTL */
 #define AUDIO_MODE_SPDIF_MODE			(0x1 << 8)
 #define AUDIO_MODE_MASTER_MODE			(0x0 << 8)
 #define MASTER_VIDEO_INTERLACE_EN		(0x1 << 4)
@@ -363,4 +363,4 @@
 #define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
 #define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
 
-#endif /* _EXYNOS_DP_REG_H */
+#endif /* _ANALOGIX_DP_REG_H */
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index bd1a415..5f74f80 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -55,8 +55,9 @@ config DRM_EXYNOS_DSI
 	  This enables support for Exynos MIPI-DSI device.
 
 config DRM_EXYNOS_DP
-	bool "EXYNOS DRM DP driver support"
+	bool "EXYNOS specific extensions for Analogix DP driver"
 	depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON)
+	select DRM_ANALOGIX_DP
 	default DRM_EXYNOS
 	select DRM_PANEL
 	help
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index 02aecfe..4453798 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -13,7 +13,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON)	+= exynos5433_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON)	+= exynos7_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DPI)	+= exynos_drm_dpi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DSI)	+= exynos_drm_dsi.o
-exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o exynos_dp_reg.o
+exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)	+= exynos_hdmi.o exynos_mixer.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI)	+= exynos_drm_vidi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_G2D)	+= exynos_drm_g2d.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
new file mode 100644
index 0000000..83feb21
--- /dev/null
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -0,0 +1,349 @@
+/*
+ * Samsung SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_graph.h>
+#include <video/of_display_timing.h>
+#include <video/of_videomode.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+
+#include <drm/bridge/analogix_dp.h>
+#include <drm/exynos_drm.h>
+
+#include "exynos_drm_crtc.h"
+
+#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
+
+struct exynos_dp_device {
+	struct drm_encoder         encoder;
+	struct drm_connector       connector;
+	struct drm_bridge          *ptn_bridge;
+	struct drm_device          *drm_dev;
+	struct device              *dev;
+
+	struct exynos_drm_panel_info priv;
+	struct analogix_dp_plat_data plat_data;
+};
+
+int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
+				bool enable)
+{
+	struct exynos_dp_device *dp = to_dp(plat_data);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct exynos_drm_crtc *crtc;
+
+	if (!encoder)
+		return -1;
+
+	crtc = to_exynos_crtc(encoder->crtc);
+	if (crtc && crtc->ops && crtc->ops->clock_enable)
+		crtc->ops->clock_enable(crtc, enable);
+
+	return 0;
+}
+
+static int exynos_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	return exynos_dp_crtc_clock_enable(plat_data, true);
+}
+
+static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
+{
+	return exynos_dp_crtc_clock_enable(plat_data, false);
+}
+
+static int exynos_dp_get_modes(struct drm_connector *connector)
+{
+	struct exynos_dp_device *dp = to_dp(connector);
+	struct drm_display_mode *mode;
+	int num_modes = 0;
+
+	num_modes += analogix_dp_get_modes(dp->dev);
+
+	if (dp->plat_data.panel)
+		return num_modes;
+
+	mode = drm_mode_create(connector->dev);
+	if (!mode) {
+		DRM_ERROR("failed to create a new display mode.\n");
+		return num_modes;
+	}
+
+	drm_display_mode_from_videomode(&dp->priv.vm, mode);
+	mode->width_mm = dp->priv.width_mm;
+	mode->height_mm = dp->priv.height_mm;
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_set_name(mode);
+	drm_mode_probed_add(connector, mode);
+
+	return num_modes + 1;
+}
+
+static struct drm_encoder *
+exynos_dp_best_encoder(struct drm_connector *connector)
+{
+	struct exynos_dp_device *dp = to_dp(connector);
+
+	return &dp->encoder;
+}
+
+static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
+	.get_modes = exynos_dp_get_modes,
+	.best_encoder = exynos_dp_best_encoder,
+};
+
+static enum drm_connector_status
+exynos_dp_detect(struct drm_connector *connector, bool force)
+{
+	struct exynos_dp_device *dp = to_dp(connector);
+
+	return analogix_dp_detect(dp->dev, force);
+}
+
+static void exynos_dp_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static struct drm_connector_funcs exynos_dp_connector_funcs = {
+	.dpms = drm_atomic_helper_connector_dpms,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.detect = exynos_dp_detect,
+	.destroy = exynos_dp_connector_destroy,
+	.reset = drm_atomic_helper_connector_reset,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+				   struct drm_bridge *bridge)
+{
+	struct exynos_dp_device *dp = to_dp(plat_data);
+	struct drm_connector *connector = &dp->connector;
+	struct drm_encoder *encoder = &dp->encoder;
+	int ret;
+
+	/* Pre-empt DP connector creation if there's a bridge */
+	if (dp->ptn_bridge) {
+		bridge->next = dp->ptn_bridge;
+		dp->ptn_bridge->encoder = encoder;
+		ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
+		if (ret) {
+			DRM_ERROR("Failed to attach bridge to drm\n");
+			bridge->next = NULL;
+			return ret;
+		}
+	}
+
+	connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+	ret = drm_connector_init(dp->drm_dev, connector,
+				 &exynos_dp_connector_funcs,
+				 DRM_MODE_CONNECTOR_eDP);
+	if (ret) {
+		DRM_ERROR("Failed to initialize connector with drm\n");
+		return ret;
+	}
+
+	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
+	drm_connector_register(connector);
+	drm_mode_connector_attach_encoder(connector, encoder);
+
+	dp->plat_data.connector = connector;
+
+	return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+				 const struct drm_display_mode *mode,
+				 struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
+static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
+	.mode_fixup = exynos_dp_mode_fixup,
+	.mode_set = exynos_dp_mode_set,
+	.enable = exynos_dp_enable,
+	.disable = exynos_dp_disable,
+};
+
+static struct drm_encoder_funcs exynos_dp_encoder_funcs = {
+	.destroy = drm_encoder_cleanup,
+};
+
+static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
+{
+	int ret;
+
+	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
+			       OF_USE_NATIVE_MODE);
+	if (ret) {
+		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
+		return ret;
+	}
+	return 0;
+}
+
+static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
+{
+	struct exynos_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = data;
+	int pipe, ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	dp->dev = dev;
+	dp->drm_dev = drm_dev;
+
+	dp->plat_data.dev_type = EXYNOS_DP;
+	dp->plat_data.power_on = exynos_dp_poweron;
+	dp->plat_data.power_off = exynos_dp_poweroff;
+	dp->plat_data.attach = exynos_dp_bridge_attach;
+
+	if (!dp->plat_data.panel && !dp->ptn_bridge) {
+		ret = exynos_dp_dt_parse_panel(dp);
+		if (ret)
+			return ret;
+	}
+
+	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
+						  EXYNOS_DISPLAY_TYPE_LCD);
+	if (pipe < 0)
+		return pipe;
+
+	encoder->possible_crtcs = 1 << pipe;
+
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	drm_encoder_init(drm_dev, encoder, &exynos_dp_encoder_funcs,
+			 DRM_MODE_ENCODER_TMDS);
+
+	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
+
+	dp->plat_data.encoder = encoder;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
+}
+
+static void exynos_dp_unbind(struct device *dev, struct device *master,
+			     void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops exynos_dp_ops = {
+	.bind	= exynos_dp_bind,
+	.unbind	= exynos_dp_unbind,
+};
+
+static int exynos_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *bridge_node, *endpoint;
+	struct exynos_dp_device *dp;
+
+	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
+			  GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver would take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	panel_node = of_parse_phandle(dev->of_node, "panel", 0);
+	if (panel_node) {
+		dp->plat_data.panel = of_drm_find_panel(panel_node);
+		of_node_put(panel_node);
+		if (!dp->plat_data.panel)
+			return -EPROBE_DEFER;
+	}
+
+	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
+	if (endpoint) {
+		bridge_node = of_graph_get_remote_port_parent(endpoint);
+		if (bridge_node) {
+			dp->ptn_bridge = of_drm_find_bridge(bridge_node);
+			of_node_put(bridge_node);
+			if (!dp->ptn_bridge)
+				return -EPROBE_DEFER;
+		} else {
+			return -EPROBE_DEFER;
+		}
+	}
+
+	return component_add(&pdev->dev, &exynos_dp_ops);
+}
+
+static int exynos_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &exynos_dp_ops);
+
+	return 0;
+}
+
+static const struct of_device_id exynos_dp_match[] = {
+	{ .compatible = "samsung,exynos5-dp" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, exynos_dp_match);
+
+struct platform_driver dp_driver = {
+	.probe		= exynos_dp_probe,
+	.remove		= exynos_dp_remove,
+	.driver		= {
+		.name	= "exynos-dp",
+		.owner	= THIS_MODULE,
+		.of_match_table = exynos_dp_match,
+	},
+};
+
+MODULE_AUTHOR("Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
+MODULE_DESCRIPTION("Samsung Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
deleted file mode 100644
index 66eec4b..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Header file for Samsung DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef _EXYNOS_DP_CORE_H
-#define _EXYNOS_DP_CORE_H
-
-#include <drm/drm_crtc.h>
-#include <drm/drm_dp_helper.h>
-#include <drm/exynos_drm.h>
-
-#include "exynos_drm_drv.h"
-
-#define DP_TIMEOUT_LOOP_COUNT 100
-#define MAX_CR_LOOP 5
-#define MAX_EQ_LOOP 5
-
-enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
-};
-
-enum link_lane_count_type {
-	LANE_COUNT1 = 1,
-	LANE_COUNT2 = 2,
-	LANE_COUNT4 = 4
-};
-
-enum link_training_state {
-	START,
-	CLOCK_RECOVERY,
-	EQUALIZER_TRAINING,
-	FINISHED,
-	FAILED
-};
-
-enum voltage_swing_level {
-	VOLTAGE_LEVEL_0,
-	VOLTAGE_LEVEL_1,
-	VOLTAGE_LEVEL_2,
-	VOLTAGE_LEVEL_3,
-};
-
-enum pre_emphasis_level {
-	PRE_EMPHASIS_LEVEL_0,
-	PRE_EMPHASIS_LEVEL_1,
-	PRE_EMPHASIS_LEVEL_2,
-	PRE_EMPHASIS_LEVEL_3,
-};
-
-enum pattern_set {
-	PRBS7,
-	D10_2,
-	TRAINING_PTN1,
-	TRAINING_PTN2,
-	DP_NONE
-};
-
-enum color_space {
-	COLOR_RGB,
-	COLOR_YCBCR422,
-	COLOR_YCBCR444
-};
-
-enum color_depth {
-	COLOR_6,
-	COLOR_8,
-	COLOR_10,
-	COLOR_12
-};
-
-enum color_coefficient {
-	COLOR_YCBCR601,
-	COLOR_YCBCR709
-};
-
-enum dynamic_range {
-	VESA,
-	CEA
-};
-
-enum pll_status {
-	PLL_UNLOCKED,
-	PLL_LOCKED
-};
-
-enum clock_recovery_m_value_type {
-	CALCULATED_M,
-	REGISTER_M
-};
-
-enum video_timing_recognition_type {
-	VIDEO_TIMING_FROM_CAPTURE,
-	VIDEO_TIMING_FROM_REGISTER
-};
-
-enum analog_power_block {
-	AUX_BLOCK,
-	CH0_BLOCK,
-	CH1_BLOCK,
-	CH2_BLOCK,
-	CH3_BLOCK,
-	ANALOG_TOTAL,
-	POWER_ALL
-};
-
-enum dp_irq_type {
-	DP_IRQ_TYPE_HP_CABLE_IN,
-	DP_IRQ_TYPE_HP_CABLE_OUT,
-	DP_IRQ_TYPE_HP_CHANGE,
-	DP_IRQ_TYPE_UNKNOWN,
-};
-
-struct video_info {
-	char *name;
-
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
-
-	enum color_space color_space;
-	enum dynamic_range dynamic_range;
-	enum color_coefficient ycbcr_coeff;
-	enum color_depth color_depth;
-
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
-};
-
-struct link_train {
-	int eq_loop;
-	int cr_loop[4];
-
-	u8 link_rate;
-	u8 lane_count;
-	u8 training_lane[4];
-
-	enum link_training_state lt_state;
-};
-
-struct exynos_dp_device {
-	struct drm_encoder	encoder;
-	struct device		*dev;
-	struct drm_device	*drm_dev;
-	struct drm_connector	connector;
-	struct drm_panel	*panel;
-	struct drm_bridge	*bridge;
-	struct drm_bridge	*ptn_bridge;
-	struct clk		*clock;
-	unsigned int		irq;
-	void __iomem		*reg_base;
-
-	struct video_info	*video_info;
-	struct link_train	link_train;
-	struct work_struct	hotplug_work;
-	struct phy		*phy;
-	int			dpms_mode;
-	int			hpd_gpio;
-
-	struct exynos_drm_panel_info priv;
-};
-
-/* exynos_dp_reg.c */
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_stop_video(struct exynos_dp_device *dp);
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
-void exynos_dp_reset(struct exynos_dp_device *dp);
-void exynos_dp_swreset(struct exynos_dp_device *dp);
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable);
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
-void exynos_dp_init_hpd(struct exynos_dp_device *dp);
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
-void exynos_dp_reset_aux(struct exynos_dp_device *dp);
-void exynos_dp_init_aux(struct exynos_dp_device *dp);
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern);
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
-void exynos_dp_reset_macro(struct exynos_dp_device *dp);
-void exynos_dp_init_video(struct exynos_dp_device *dp);
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_start_video(struct exynos_dp_device *dp);
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
-#endif /* _EXYNOS_DP_CORE_H */
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
deleted file mode 100644
index c1f87a2..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
+++ /dev/null
@@ -1,1263 +0,0 @@
-/*
- * Samsung DP (Display port) register interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-
-#include "exynos_dp_core.h"
-#include "exynos_dp_reg.h"
-
-#define COMMON_INT_MASK_1	0
-#define COMMON_INT_MASK_2	0
-#define COMMON_INT_MASK_3	0
-#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
-#define INT_STA_MASK		INT_HPD
-
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg |= HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg &= ~HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	}
-}
-
-void exynos_dp_stop_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg &= ~VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable)
-		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
-	else
-		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
-
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
-}
-
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = TX_TERMINAL_CTRL_50_OHM;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
-
-	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
-
-	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
-
-	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
-		TX_CUR1_2X | TX_CUR_16_MA;
-	writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
-
-	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
-		CH1_AMP_400_MV | CH0_AMP_400_MV;
-	writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
-}
-
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
-{
-	/* Set interrupt pin assertion polarity as high */
-	writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
-
-	/* Clear pending regisers */
-	writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-	writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
-	writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
-	writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-	writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* 0:mask,1: unmask */
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-	writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-void exynos_dp_reset(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	exynos_dp_stop_video(dp);
-	exynos_dp_enable_video_mute(dp, 0);
-
-	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
-		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
-		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
-		SERDES_FIFO_FUNC_EN_N |
-		LS_CLK_DOMAIN_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-
-	usleep_range(20, 30);
-
-	exynos_dp_lane_swap(dp, 0);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
-	writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
-
-	writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
-	writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
-
-	writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
-	writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
-
-	writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
-	writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
-
-	writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_swreset(struct exynos_dp_device *dp)
-{
-	writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
-}
-
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* 0: mask, 1: unmask */
-	reg = COMMON_INT_MASK_1;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-
-	reg = COMMON_INT_MASK_2;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-
-	reg = COMMON_INT_MASK_3;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-
-	reg = COMMON_INT_MASK_4;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-
-	reg = INT_STA_MASK;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	if (reg & PLL_LOCK)
-		return PLL_LOCKED;
-	else
-		return PLL_UNLOCKED;
-}
-
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg |= DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg &= ~DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	}
-}
-
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
-{
-	u32 reg;
-
-	switch (block) {
-	case AUX_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH0_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH1_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH2_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH3_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case ANALOG_TOTAL:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case POWER_ALL:
-		if (enable) {
-			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
-				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
-{
-	u32 reg;
-	int timeout_loop = 0;
-
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
-
-	reg = PLL_LOCK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-
-	/* Power up PLL */
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-		exynos_dp_set_pll_power_down(dp, 0);
-
-		while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-			timeout_loop++;
-			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-				dev_err(dp->dev, "failed to get pll lock status\n");
-				return;
-			}
-			usleep_range(10, 20);
-		}
-	}
-
-	/* Enable Serdes FIFO function and Link symbol clock domain module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
-		| AUX_FUNC_EN_N);
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-	reg = INT_HPD;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-}
-
-void exynos_dp_init_hpd(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	exynos_dp_clear_hotplug_interrupts(dp);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	reg &= ~(F_HPD | HPD_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-}
-
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		reg = gpio_get_value(dp->hpd_gpio);
-		if (reg)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-		else
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-	} else {
-		/* Parse hotplug interrupt status register */
-		reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-		if (reg & PLUG)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-
-		if (reg & HPD_LOST)
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-
-		if (reg & HOTPLUG_CHG)
-			return DP_IRQ_TYPE_HP_CHANGE;
-
-		return DP_IRQ_TYPE_UNKNOWN;
-	}
-}
-
-void exynos_dp_reset_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Disable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg |= AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_init_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Clear inerrupts related to AUX channel */
-	reg = RPLY_RECEIV | AUX_ERR;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	exynos_dp_reset_aux(dp);
-
-	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
-
-	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
-	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
-
-	/* Enable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		if (gpio_get_value(dp->hpd_gpio))
-			return 0;
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-		if (reg & HPD_STATUS)
-			return 0;
-	}
-
-	return -EINVAL;
-}
-
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-}
-
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
-{
-	int reg;
-	int retval = 0;
-	int timeout_loop = 0;
-
-	/* Enable AUX CH operation */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-	reg |= AUX_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-	/* Is AUX CH command reply received? */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	while (!(reg & RPLY_RECEIV)) {
-		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "AUX CH command reply failed!\n");
-			return -ETIMEDOUT;
-		}
-		reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-		usleep_range(10, 11);
-	}
-
-	/* Clear interrupt source for AUX CH command reply */
-	writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* Clear interrupt source for AUX CH access error */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	if (reg & AUX_ERR) {
-		writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
-		return -EREMOTEIO;
-	}
-
-	/* Check AUX CH error access status */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
-	if ((reg & AUX_STATUS_MASK) != 0) {
-		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
-			reg & AUX_STATUS_MASK);
-		return -EREMOTEIO;
-	}
-
-	return retval;
-}
-
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/* Write data buffer */
-		reg = (unsigned int)data;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-		/*
-		 * Set DisplayPort transaction and write 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/*
-		 * Set DisplayPort transaction and read 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	/* Read data buffer */
-	reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-	*data = (unsigned char)(reg & 0xff);
-
-	return retval;
-}
-
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-			     cur_data_idx++) {
-				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
-			}
-
-			/*
-			 * Set DisplayPort transaction and write
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		/* AUX CH Request Transaction process */
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			/*
-			 * Set DisplayPort transaction and read
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-		    cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			data[start_offset + cur_data_idx] =
-				(unsigned char)reg;
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
-{
-	u32 reg;
-	int retval;
-
-	/* Set EDID device address */
-	reg = device_addr;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-	/* Set offset from base address of EDID device */
-	writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	/*
-	 * Set I2C transaction and write address
-	 * If bit 3 is 1, DisplayPort transaction.
-	 * If Bit 3 is 0, I2C transaction.
-	 */
-	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
-		AUX_TX_COMM_WRITE;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction(dp);
-	if (retval != 0)
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select EDID device */
-		retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
-		if (retval != 0)
-			continue;
-
-		/*
-		 * Set I2C transaction and read data
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_I2C_TRANSACTION |
-			AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	/* Read data */
-	if (retval == 0)
-		*data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
-{
-	u32 reg;
-	unsigned int i, j;
-	unsigned int cur_data_idx;
-	unsigned int defer = 0;
-	int retval = 0;
-
-	for (i = 0; i < count; i += 16) {
-		for (j = 0; j < 3; j++) {
-			/* Clear AUX CH data buffer */
-			reg = BUF_CLR;
-			writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-			/* Set normal AUX CH command */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-			reg &= ~ADDR_ONLY;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-			/*
-			 * If Rx sends defer, Tx sends only reads
-			 * request without sending address
-			 */
-			if (!defer)
-				retval = exynos_dp_select_i2c_device(dp,
-						device_addr, reg_addr + i);
-			else
-				defer = 0;
-
-			if (retval == 0) {
-				/*
-				 * Set I2C transaction and write data
-				 * If bit 3 is 1, DisplayPort transaction.
-				 * If Bit 3 is 0, I2C transaction.
-				 */
-				reg = AUX_LENGTH(16) |
-					AUX_TX_COMM_I2C_TRANSACTION |
-					AUX_TX_COMM_READ;
-				writel(reg, dp->reg_base +
-					EXYNOS_DP_AUX_CH_CTL_1);
-
-				/* Start AUX transaction */
-				retval = exynos_dp_start_aux_transaction(dp);
-				if (retval == 0)
-					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
-			}
-			/* Check if Rx sends defer */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
-			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
-				dev_err(dp->dev, "Defer: %d\n\n", reg);
-				defer = 1;
-			}
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			edid[i + cur_data_idx] = (unsigned char)reg;
-		}
-	}
-
-	return retval;
-}
-
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
-{
-	u32 reg;
-
-	reg = bwtype;
-	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
-		writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-}
-
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-	*bwtype = reg;
-}
-
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
-{
-	u32 reg;
-
-	reg = count;
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-}
-
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-	*count = reg;
-}
-
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	}
-}
-
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern)
-{
-	u32 reg;
-
-	switch (pattern) {
-	case PRBS7:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case D10_2:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN1:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN2:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case DP_NONE:
-		reg = SCRAMBLING_ENABLE |
-			LINK_QUAL_PATTERN_SET_DISABLE |
-			SW_TRAINING_PATTERN_SET_NORMAL;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	return reg;
-}
-
-void exynos_dp_reset_macro(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
-	reg |= MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	/* 10 us is the minimum reset time. */
-	usleep_range(10, 20);
-
-	reg &= ~MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-}
-
-void exynos_dp_init_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = CHA_CRI(4) | CHA_CTRL;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
-}
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
-
-	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
-		reg |= IN_YC_COEFFI_ITU709;
-	else
-		reg |= IN_YC_COEFFI_ITU601;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-}
-
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	if (!(reg & DET_STA)) {
-		dev_dbg(dp->dev, "Input stream clock not detected.\n");
-		return -EINVAL;
-	}
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
-
-	if (reg & CHA_STA) {
-		dev_dbg(dp->dev, "Input stream clk is changing\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
-{
-	u32 reg;
-
-	if (type == REGISTER_M) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg = m_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
-		reg = (m_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
-		reg = (m_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
-
-		reg = n_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
-		reg = (n_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
-		reg = (n_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
-	} else  {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
-		writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
-	}
-}
-
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
-{
-	u32 reg;
-
-	if (type == VIDEO_TIMING_FROM_CAPTURE) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg &= ~FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg |= FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	}
-}
-
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MODE_SLAVE_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	}
-}
-
-void exynos_dp_start_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg |= VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	if (!(reg & STRM_VALID)) {
-		dev_dbg(dp->dev, "Input video stream is not detected.\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
-	reg |= MASTER_VID_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-	writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg &= ~SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
-
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg |= SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
new file mode 100644
index 0000000..134638af
--- /dev/null
+++ b/include/drm/bridge/analogix_dp.h
@@ -0,0 +1,41 @@
+/*
+ * Analogix DP (Display Port) Core interface driver.
+ *
+ * Copyright (C) 2015 Rockchip Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _ANALOGIX_DP_H_
+#define _ANALOGIX_DP_H_
+
+#include <drm/drm_crtc.h>
+
+enum analogix_dp_devtype {
+	EXYNOS_DP,
+};
+
+struct analogix_dp_plat_data {
+	enum analogix_dp_devtype dev_type;
+	struct drm_panel *panel;
+	struct drm_encoder *encoder;
+	struct drm_connector *connector;
+
+	int (*power_on)(struct analogix_dp_plat_data *);
+	int (*power_off)(struct analogix_dp_plat_data *);
+	int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *);
+};
+
+enum drm_connector_status analogix_dp_detect(struct device *dev, bool force);
+int analogix_dp_get_modes(struct device *dev);
+
+int analogix_dp_resume(struct device *dev);
+int analogix_dp_suspend(struct device *dev);
+
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct analogix_dp_plat_data *plat_data);
+void analogix_dp_unbind(struct device *dev, struct device *master, void *data);
+
+#endif /* _ANALOGIX_DP_H_ */
-- 
1.9.1


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^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 03/17] drm: bridge: analogix/dp: fix some obvious code style
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 15:41     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:41 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
  from exynos_dp code, and rephrase reasonable commit message, and
  remove some controversial style (Krzysztof)
    -		analogix_dp_write_byte_to_dpcd(
    - 				dp, DP_TEST_RESPONSE,
    +		analogix_dp_write_byte_to_dpcd(dp,
    +				DP_TEST_RESPONSE,
				DP_TEST_EDID_CHECKSUM_WRITE);

Changes in v4: None
Changes in v3: None
Changes in v2:
- Improved commit message more readable, and avoid using some
  uncommon style like bellow: (Joe Preches)
    -  retval = exynos_dp_read_bytes_from_i2c(...
  				  ...);
    +  retval =
    +  exynos_dp_read_bytes_from_i2c(......);

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++++++++++-----------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  72 ++++++------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 124 ++++++++++----------
 3 files changed, 163 insertions(+), 162 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index e561590..334181c 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -61,7 +61,7 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 
 	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
 			return -ETIMEDOUT;
 		}
@@ -98,8 +98,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
 	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-				EDID_EXTENSION_FLAG,
-				&extend_block);
+						EDID_EXTENSION_FLAG,
+						&extend_block);
 	if (retval)
 		return retval;
 
@@ -107,7 +107,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
+						I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -138,7 +139,7 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		}
 
 		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					&test_vector);
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
@@ -152,10 +153,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 		/* Read EDID data */
 		retval = analogix_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_HEADER_PATTERN,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_HEADER_PATTERN]);
+				I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
+				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -166,16 +165,13 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 			return -EIO;
 		}
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TEST_REQUEST,
-			&test_vector);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
+				DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
+				DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE);
 		}
 	}
 
@@ -190,8 +186,7 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
-				12, buf);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
 	if (retval)
 		return retval;
 
@@ -205,8 +200,9 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
-						bool enable)
+static void
+analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
+				       bool enable)
 {
 	u8 data;
 
@@ -214,11 +210,11 @@ static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp
 
 	if (enable)
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DP_LANE_COUNT_ENHANCED_FRAME_EN |
-			DPCD_LANE_COUNT_SET(data));
+					       DP_LANE_COUNT_ENHANCED_FRAME_EN |
+					       DPCD_LANE_COUNT_SET(data));
 	else
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DPCD_LANE_COUNT_SET(data));
+					       DPCD_LANE_COUNT_SET(data));
 }
 
 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
@@ -245,13 +241,13 @@ static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
 	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	analogix_dp_write_byte_to_dpcd(dp,
-		DP_TRAINING_PATTERN_SET,
-		DP_TRAINING_PATTERN_DISABLE);
+	analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+				       DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
-					int pre_emphasis, int lane)
+static void
+analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
+				       int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -291,8 +287,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
-				2, buf);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
 	if (retval)
 		return retval;
 
@@ -328,7 +323,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
 	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, buf);
+						 lane_count, buf);
 
 	return retval;
 }
@@ -336,7 +331,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = link_status[lane>>1];
+	u8 link_value = link_status[lane >> 1];
 
 	return (link_value >> shift) & 0xf;
 }
@@ -355,7 +350,7 @@ static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 }
 
 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				int lane_count)
+				     int lane_count)
 {
 	int lane;
 	u8 lane_status;
@@ -373,11 +368,11 @@ static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							int lane)
+static unsigned char
+analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return (link_value >> shift) & 0x3;
 }
@@ -387,13 +382,13 @@ static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
-					u8 training_lane_set, int lane)
+					       u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -413,9 +408,9 @@ static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 	}
 }
 
-static unsigned int analogix_dp_get_lane_link_training(
-				struct analogix_dp_device *dp,
-				int lane)
+static unsigned int
+analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
+				   int lane)
 {
 	u32 reg;
 
@@ -449,7 +444,7 @@ static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
-					u8 adjust_request[2])
+						 u8 adjust_request[2])
 {
 	int lane, lane_count;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -622,7 +617,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
-					u8 *bandwidth)
+					     u8 *bandwidth)
 {
 	u8 data;
 
@@ -635,7 +630,7 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
-					u8 *lane_count)
+					      u8 *lane_count)
 {
 	u8 data;
 
@@ -648,8 +643,8 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_init_training(struct analogix_dp_device *dp,
-			enum link_lane_count_type max_lane,
-			enum link_rate_type max_rate)
+				      enum link_lane_count_type max_lane,
+				      enum link_rate_type max_rate)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
@@ -662,7 +657,7 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -722,8 +717,7 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 }
 
 static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
-				u32 count,
-				u32 bwtype)
+				      u32 count, u32 bwtype)
 {
 	int i;
 	int retval;
@@ -759,7 +753,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		timeout_loop++;
 		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -790,7 +784,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		} else if (done_count) {
 			done_count = 0;
 		}
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -804,25 +798,24 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
+					bool enable)
 {
 	u8 data;
 
 	if (enable) {
 		analogix_dp_enable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
 		analogix_dp_disable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
@@ -895,7 +888,7 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	}
 
 	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					dp->video_info->link_rate);
+					 dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1083,8 +1076,8 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
 
-	dp_video_config = devm_kzalloc(dev,
-				sizeof(*dp_video_config), GFP_KERNEL);
+	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
+				       GFP_KERNEL);
 	if (!dp_video_config)
 		return ERR_PTR(-ENOMEM);
 
@@ -1098,37 +1091,37 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 		of_property_read_bool(dp_node, "interlaced");
 
 	if (of_property_read_u32(dp_node, "samsung,color-space",
-				&dp_video_config->color_space)) {
+				 &dp_video_config->color_space)) {
 		dev_err(dev, "failed to get color-space\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				&dp_video_config->dynamic_range)) {
+				 &dp_video_config->dynamic_range)) {
 		dev_err(dev, "failed to get dynamic-range\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				&dp_video_config->ycbcr_coeff)) {
+				 &dp_video_config->ycbcr_coeff)) {
 		dev_err(dev, "failed to get ycbcr-coeff\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				&dp_video_config->color_depth)) {
+				 &dp_video_config->color_depth)) {
 		dev_err(dev, "failed to get color-depth\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				&dp_video_config->link_rate)) {
+				 &dp_video_config->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				&dp_video_config->lane_count)) {
+				 &dp_video_config->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
 		return ERR_PTR(-EINVAL);
 	}
@@ -1239,7 +1232,7 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	analogix_dp_init_dp(dp);
 
 	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
-			irq_flags, "analogix-dp", dp);
+			       irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		return ret;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 65ce7f1..14d20be 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -187,50 +187,55 @@ int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
+				   unsigned int reg_addr,
+				   unsigned char data);
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
+				    unsigned int reg_addr,
+				    unsigned char *data);
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[]);
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[]);
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
+				  unsigned int device_addr,
+				  unsigned int reg_addr);
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data);
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[]);
 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable);
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern);
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+				      enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
@@ -241,11 +246,12 @@ void analogix_dp_init_video(struct analogix_dp_device *dp);
 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value,
+				 u32 n_value);
 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
-void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
+				     bool enable);
 void analogix_dp_start_video(struct analogix_dp_device *dp);
 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 442cc66..a388c0a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -54,10 +54,10 @@ void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
 
 	if (enable)
 		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+		      LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
 	else
 		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+		      LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
 
 	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
 }
@@ -202,8 +202,8 @@ void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
 }
 
 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
+				       enum analog_power_block block,
+				       bool enable)
 {
 	u32 reg;
 
@@ -399,8 +399,8 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
+	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
@@ -483,8 +483,8 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
 }
 
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
+				   unsigned int reg_addr,
+				   unsigned char data)
 {
 	u32 reg;
 	int i;
@@ -519,17 +519,16 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	return retval;
 }
 
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
+				    unsigned int reg_addr,
+				    unsigned char *data)
 {
 	u32 reg;
 	int i;
@@ -560,9 +559,8 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data buffer */
@@ -573,9 +571,9 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -608,8 +606,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 			     cur_data_idx++) {
 				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
+				writel(reg, dp->reg_base +
+				       ANALOGIX_DP_BUF_DATA_0 +
+				       4 * cur_data_idx);
 			}
 
 			/*
@@ -625,9 +624,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		start_offset += cur_data_count;
@@ -637,9 +636,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -683,9 +682,9 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
@@ -703,8 +702,8 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
+				  unsigned int device_addr,
+				  unsigned int reg_addr)
 {
 	u32 reg;
 	int retval;
@@ -736,9 +735,9 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data)
 {
 	u32 reg;
 	int i;
@@ -750,7 +749,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 		/* Select EDID device */
-		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+		retval = analogix_dp_select_i2c_device(dp, device_addr,
+						       reg_addr);
 		if (retval != 0)
 			continue;
 
@@ -767,9 +767,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data */
@@ -780,10 +779,10 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[])
 {
 	u32 reg;
 	unsigned int i, j;
@@ -828,15 +827,14 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 				retval = analogix_dp_start_aux_transaction(dp);
 				if (retval == 0)
 					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
+
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
 			}
 			/* Check if Rx sends defer */
 			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
 			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
+			    reg == AUX_RX_COMM_I2C_DEFER) {
 				dev_err(dp->dev, "Defer: %d\n\n", reg);
 				defer = 1;
 			}
@@ -885,7 +883,8 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
 	*count = reg;
 }
 
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable)
 {
 	u32 reg;
 
@@ -901,7 +900,7 @@ void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable
 }
 
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern)
+				      enum pattern_set pattern)
 {
 	u32 reg;
 
@@ -933,7 +932,8 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
 	}
 }
 
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -943,7 +943,8 @@ void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -953,7 +954,8 @@ void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -963,7 +965,8 @@ void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -974,7 +977,7 @@ void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level
 }
 
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -983,7 +986,7 @@ void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1001,7 +1004,7 @@ void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1125,9 +1128,8 @@ int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
 }
 
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value, u32 n_value)
 {
 	u32 reg;
 
@@ -1221,7 +1223,7 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 	u32 reg;
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
 	reg |= MASTER_VID_FUNC_EN_N;
 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 03/17] drm: bridge: analogix/dp: fix some obvious code style
@ 2015-10-10 15:41     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:41 UTC (permalink / raw)
  To: linux-arm-kernel

Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
  from exynos_dp code, and rephrase reasonable commit message, and
  remove some controversial style (Krzysztof)
    -		analogix_dp_write_byte_to_dpcd(
    - 				dp, DP_TEST_RESPONSE,
    +		analogix_dp_write_byte_to_dpcd(dp,
    +				DP_TEST_RESPONSE,
				DP_TEST_EDID_CHECKSUM_WRITE);

Changes in v4: None
Changes in v3: None
Changes in v2:
- Improved commit message more readable, and avoid using some
  uncommon style like bellow: (Joe Preches)
    -  retval = exynos_dp_read_bytes_from_i2c(...
  				  ...);
    +  retval =
    +  exynos_dp_read_bytes_from_i2c(......);

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++++++++++-----------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  72 ++++++------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 124 ++++++++++----------
 3 files changed, 163 insertions(+), 162 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index e561590..334181c 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -61,7 +61,7 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 
 	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
 			return -ETIMEDOUT;
 		}
@@ -98,8 +98,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
 	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-				EDID_EXTENSION_FLAG,
-				&extend_block);
+						EDID_EXTENSION_FLAG,
+						&extend_block);
 	if (retval)
 		return retval;
 
@@ -107,7 +107,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
+						I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -138,7 +139,7 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		}
 
 		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					&test_vector);
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
@@ -152,10 +153,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 		/* Read EDID data */
 		retval = analogix_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_HEADER_PATTERN,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_HEADER_PATTERN]);
+				I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
+				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -166,16 +165,13 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 			return -EIO;
 		}
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TEST_REQUEST,
-			&test_vector);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
+				DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
+				DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE);
 		}
 	}
 
@@ -190,8 +186,7 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
-				12, buf);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
 	if (retval)
 		return retval;
 
@@ -205,8 +200,9 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
-						bool enable)
+static void
+analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
+				       bool enable)
 {
 	u8 data;
 
@@ -214,11 +210,11 @@ static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp
 
 	if (enable)
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DP_LANE_COUNT_ENHANCED_FRAME_EN |
-			DPCD_LANE_COUNT_SET(data));
+					       DP_LANE_COUNT_ENHANCED_FRAME_EN |
+					       DPCD_LANE_COUNT_SET(data));
 	else
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DPCD_LANE_COUNT_SET(data));
+					       DPCD_LANE_COUNT_SET(data));
 }
 
 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
@@ -245,13 +241,13 @@ static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
 	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	analogix_dp_write_byte_to_dpcd(dp,
-		DP_TRAINING_PATTERN_SET,
-		DP_TRAINING_PATTERN_DISABLE);
+	analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+				       DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
-					int pre_emphasis, int lane)
+static void
+analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
+				       int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -291,8 +287,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
-				2, buf);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
 	if (retval)
 		return retval;
 
@@ -328,7 +323,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
 	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, buf);
+						 lane_count, buf);
 
 	return retval;
 }
@@ -336,7 +331,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = link_status[lane>>1];
+	u8 link_value = link_status[lane >> 1];
 
 	return (link_value >> shift) & 0xf;
 }
@@ -355,7 +350,7 @@ static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 }
 
 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				int lane_count)
+				     int lane_count)
 {
 	int lane;
 	u8 lane_status;
@@ -373,11 +368,11 @@ static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							int lane)
+static unsigned char
+analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return (link_value >> shift) & 0x3;
 }
@@ -387,13 +382,13 @@ static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
-					u8 training_lane_set, int lane)
+					       u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -413,9 +408,9 @@ static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 	}
 }
 
-static unsigned int analogix_dp_get_lane_link_training(
-				struct analogix_dp_device *dp,
-				int lane)
+static unsigned int
+analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
+				   int lane)
 {
 	u32 reg;
 
@@ -449,7 +444,7 @@ static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
-					u8 adjust_request[2])
+						 u8 adjust_request[2])
 {
 	int lane, lane_count;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -622,7 +617,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
-					u8 *bandwidth)
+					     u8 *bandwidth)
 {
 	u8 data;
 
@@ -635,7 +630,7 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
-					u8 *lane_count)
+					      u8 *lane_count)
 {
 	u8 data;
 
@@ -648,8 +643,8 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_init_training(struct analogix_dp_device *dp,
-			enum link_lane_count_type max_lane,
-			enum link_rate_type max_rate)
+				      enum link_lane_count_type max_lane,
+				      enum link_rate_type max_rate)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
@@ -662,7 +657,7 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -722,8 +717,7 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 }
 
 static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
-				u32 count,
-				u32 bwtype)
+				      u32 count, u32 bwtype)
 {
 	int i;
 	int retval;
@@ -759,7 +753,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		timeout_loop++;
 		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -790,7 +784,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		} else if (done_count) {
 			done_count = 0;
 		}
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -804,25 +798,24 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
+					bool enable)
 {
 	u8 data;
 
 	if (enable) {
 		analogix_dp_enable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
 		analogix_dp_disable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
@@ -895,7 +888,7 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	}
 
 	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					dp->video_info->link_rate);
+					 dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1083,8 +1076,8 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
 
-	dp_video_config = devm_kzalloc(dev,
-				sizeof(*dp_video_config), GFP_KERNEL);
+	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
+				       GFP_KERNEL);
 	if (!dp_video_config)
 		return ERR_PTR(-ENOMEM);
 
@@ -1098,37 +1091,37 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 		of_property_read_bool(dp_node, "interlaced");
 
 	if (of_property_read_u32(dp_node, "samsung,color-space",
-				&dp_video_config->color_space)) {
+				 &dp_video_config->color_space)) {
 		dev_err(dev, "failed to get color-space\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				&dp_video_config->dynamic_range)) {
+				 &dp_video_config->dynamic_range)) {
 		dev_err(dev, "failed to get dynamic-range\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				&dp_video_config->ycbcr_coeff)) {
+				 &dp_video_config->ycbcr_coeff)) {
 		dev_err(dev, "failed to get ycbcr-coeff\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				&dp_video_config->color_depth)) {
+				 &dp_video_config->color_depth)) {
 		dev_err(dev, "failed to get color-depth\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				&dp_video_config->link_rate)) {
+				 &dp_video_config->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				&dp_video_config->lane_count)) {
+				 &dp_video_config->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
 		return ERR_PTR(-EINVAL);
 	}
@@ -1239,7 +1232,7 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	analogix_dp_init_dp(dp);
 
 	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
-			irq_flags, "analogix-dp", dp);
+			       irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		return ret;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 65ce7f1..14d20be 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -187,50 +187,55 @@ int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
+				   unsigned int reg_addr,
+				   unsigned char data);
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
+				    unsigned int reg_addr,
+				    unsigned char *data);
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[]);
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[]);
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
+				  unsigned int device_addr,
+				  unsigned int reg_addr);
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data);
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[]);
 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable);
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern);
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+				      enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
@@ -241,11 +246,12 @@ void analogix_dp_init_video(struct analogix_dp_device *dp);
 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value,
+				 u32 n_value);
 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
-void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
+				     bool enable);
 void analogix_dp_start_video(struct analogix_dp_device *dp);
 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 442cc66..a388c0a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -54,10 +54,10 @@ void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
 
 	if (enable)
 		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+		      LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
 	else
 		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+		      LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
 
 	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
 }
@@ -202,8 +202,8 @@ void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
 }
 
 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
+				       enum analog_power_block block,
+				       bool enable)
 {
 	u32 reg;
 
@@ -399,8 +399,8 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
+	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
@@ -483,8 +483,8 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
 }
 
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
+				   unsigned int reg_addr,
+				   unsigned char data)
 {
 	u32 reg;
 	int i;
@@ -519,17 +519,16 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	return retval;
 }
 
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
+				    unsigned int reg_addr,
+				    unsigned char *data)
 {
 	u32 reg;
 	int i;
@@ -560,9 +559,8 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data buffer */
@@ -573,9 +571,9 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -608,8 +606,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 			     cur_data_idx++) {
 				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
+				writel(reg, dp->reg_base +
+				       ANALOGIX_DP_BUF_DATA_0 +
+				       4 * cur_data_idx);
 			}
 
 			/*
@@ -625,9 +624,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		start_offset += cur_data_count;
@@ -637,9 +636,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -683,9 +682,9 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
@@ -703,8 +702,8 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
+				  unsigned int device_addr,
+				  unsigned int reg_addr)
 {
 	u32 reg;
 	int retval;
@@ -736,9 +735,9 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data)
 {
 	u32 reg;
 	int i;
@@ -750,7 +749,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 		/* Select EDID device */
-		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+		retval = analogix_dp_select_i2c_device(dp, device_addr,
+						       reg_addr);
 		if (retval != 0)
 			continue;
 
@@ -767,9 +767,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data */
@@ -780,10 +779,10 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[])
 {
 	u32 reg;
 	unsigned int i, j;
@@ -828,15 +827,14 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 				retval = analogix_dp_start_aux_transaction(dp);
 				if (retval == 0)
 					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
+
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
 			}
 			/* Check if Rx sends defer */
 			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
 			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
+			    reg == AUX_RX_COMM_I2C_DEFER) {
 				dev_err(dp->dev, "Defer: %d\n\n", reg);
 				defer = 1;
 			}
@@ -885,7 +883,8 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
 	*count = reg;
 }
 
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable)
 {
 	u32 reg;
 
@@ -901,7 +900,7 @@ void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable
 }
 
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern)
+				      enum pattern_set pattern)
 {
 	u32 reg;
 
@@ -933,7 +932,8 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
 	}
 }
 
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -943,7 +943,8 @@ void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -953,7 +954,8 @@ void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -963,7 +965,8 @@ void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -974,7 +977,7 @@ void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level
 }
 
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -983,7 +986,7 @@ void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1001,7 +1004,7 @@ void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1125,9 +1128,8 @@ int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
 }
 
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value, u32 n_value)
 {
 	u32 reg;
 
@@ -1221,7 +1223,7 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 	u32 reg;
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
 	reg |= MASTER_VID_FUNC_EN_N;
 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
@ 2015-10-10 15:43     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:43 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.

Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04

Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
  directly, but we can take those as hardware limite. For example, RK3288
  only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
  like "link-rate = 0x0a" "lane-count = 4". (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 334181c..96afb67 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -624,6 +624,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 	/*
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+	 * For DP rev.1.2, Maximum link rate of Main Link lanes
+	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 	 */
 	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
@@ -657,7 +659,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS) &&
+	    (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -898,9 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
 	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
-	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
 	analogix_dp_init_video(dp);
 	ret = analogix_dp_config_video(dp);
 	if (ret)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 14d20be..9a90a18 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -21,8 +21,9 @@
 #define MAX_EQ_LOOP 5
 
 enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
+	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
+	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
+	LINK_RATE_5_40GBPS = DP_LINK_BW_5_4,
 };
 
 enum link_lane_count_type {
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
@ 2015-10-10 15:43     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:43 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe-6d6DIl74uiNBDgjK7y7TUQ, Heiko Stuebner,
	Mark Yao
  Cc: djkurtz-F7+t8E8rja9g9hUCZPvPmw, dianders-F7+t8E8rja9g9hUCZPvPmw,
	Yakir Yang, Gustavo Padovan,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Russell King,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	Kishon Vijay Abraham I, javier-JPH+aEBZ4P+UEJcrhfAQsw,
	Kukjin Kim, robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Ian Campbell,
	Sean Paul, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA, Kumar Gala,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan

link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.

Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04

Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
  directly, but we can take those as hardware limite. For example, RK3288
  only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
  like "link-rate = 0x0a" "lane-count = 4". (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 334181c..96afb67 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -624,6 +624,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 	/*
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+	 * For DP rev.1.2, Maximum link rate of Main Link lanes
+	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 	 */
 	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
@@ -657,7 +659,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS) &&
+	    (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -898,9 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
 	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
-	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
 	analogix_dp_init_video(dp);
 	ret = analogix_dp_config_video(dp);
 	if (ret)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 14d20be..9a90a18 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -21,8 +21,9 @@
 #define MAX_EQ_LOOP 5
 
 enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
+	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
+	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
+	LINK_RATE_5_40GBPS = DP_LINK_BW_5_4,
 };
 
 enum link_lane_count_type {
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
@ 2015-10-10 15:43     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:43 UTC (permalink / raw)
  To: linux-arm-kernel

link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.

Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04

Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
  directly, but we can take those as hardware limite. For example, RK3288
  only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
  like "link-rate = 0x0a" "lane-count = 4". (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 334181c..96afb67 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -624,6 +624,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 	/*
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+	 * For DP rev.1.2, Maximum link rate of Main Link lanes
+	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 	 */
 	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
@@ -657,7 +659,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS) &&
+	    (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -898,9 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
 	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
-	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
 	analogix_dp_init_video(dp);
 	ret = analogix_dp_config_video(dp);
 	if (ret)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 14d20be..9a90a18 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -21,8 +21,9 @@
 #define MAX_EQ_LOOP 5
 
 enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
+	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
+	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
+	LINK_RATE_5_40GBPS = DP_LINK_BW_5_4,
 };
 
 enum link_lane_count_type {
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 15:46     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:46 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.

But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).

Changes in v4:
- Provide backword compatibility with samsung. (Krzysztof)

Changes in v3:
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   8 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
 3 files changed, 106 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 96afb67..9d802ef 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					 dp->video_info->link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
+					 dp->video_info.link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
+					struct drm_display_mode *orig_mode,
+					struct drm_display_mode *mode)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_display_info *display_info = &dp->connector->display_info;
+	struct video_info *video = &dp->video_info;
+	struct device_node *dp_node = dp->dev->of_node;
+	int vic;
+
+	/* Input video interlaces & hsync pol & vsync pol */
+	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+	/* Input video dynamic_range & colorimetry */
+	vic = drm_match_cea_mode(mode);
+	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
+	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR601;
+	} else if (vic) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	} else {
+		video->dynamic_range = VESA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	}
+
+	/* Input vide bpc and color_formats */
+	switch (display_info->bpc) {
+	case 12:
+		video->color_depth = COLOR_12;
+		break;
+	case 10:
+		video->color_depth = COLOR_10;
+		break;
+	case 8:
+		video->color_depth = COLOR_8;
+		break;
+	case 6:
+		video->color_depth = COLOR_6;
+		break;
+	default:
+		video->color_depth = COLOR_8;
+		break;
+	}
+	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
+		video->color_space = COLOR_YCBCR444;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
+		video->color_space = COLOR_YCBCR422;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
+		video->color_space = COLOR_RGB;
+	else
+		video->color_space = COLOR_RGB;
+
+	/*
+	 * NOTE: those property parsing code is used for providing backward
+	 * compatibility for samsung platform.
+	 * Due to we used the "of_property_read_u32" interfaces, when this
+	 * property isn't present, the "video_info" can keep the original
+	 * values and wouldn't be modified.
+	 */
+	of_property_read_u32(dp_node, "samsung,color-space",
+			     &video->color_space);
+	of_property_read_u32(dp_node, "samsung,dynamic-range",
+			     &video->dynamic_range);
+	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+			     &video->ycbcr_coeff);
+	of_property_read_u32(dp_node, "samsung,color-depth",
+			     &video->color_depth);
+	of_property_read_u32(dp_node, "hsync-active-high",
+			     &video->h_sync_polarity);
+	of_property_read_u32(dp_node, "vsync-active-high",
+			     &video->v_sync_polarity);
+	of_property_read_u32(dp_node, "interlaced",
+			     &video->interlaced);
+}
+
 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
@@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
 	.disable = analogix_dp_bridge_disable,
 	.pre_enable = analogix_dp_bridge_nop,
 	.post_disable = analogix_dp_bridge_nop,
+	.mode_set = analogix_dp_bridge_mode_set,
 	.attach = analogix_dp_bridge_attach,
 };
 
@@ -1071,62 +1151,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 	return 0;
 }
 
-static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
-	struct device_node *dp_node = dev->of_node;
-	struct video_info *dp_video_config;
-
-	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
-				       GFP_KERNEL);
-	if (!dp_video_config)
-		return ERR_PTR(-ENOMEM);
-
-	dp_video_config->h_sync_polarity =
-		of_property_read_bool(dp_node, "hsync-active-high");
-
-	dp_video_config->v_sync_polarity =
-		of_property_read_bool(dp_node, "vsync-active-high");
-
-	dp_video_config->interlaced =
-		of_property_read_bool(dp_node, "interlaced");
-
-	if (of_property_read_u32(dp_node, "samsung,color-space",
-				 &dp_video_config->color_space)) {
-		dev_err(dev, "failed to get color-space\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				 &dp_video_config->dynamic_range)) {
-		dev_err(dev, "failed to get dynamic-range\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				 &dp_video_config->ycbcr_coeff)) {
-		dev_err(dev, "failed to get ycbcr-coeff\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				 &dp_video_config->color_depth)) {
-		dev_err(dev, "failed to get color-depth\n");
-		return ERR_PTR(-EINVAL);
-	}
+	struct device_node *dp_node = dp->dev->of_node;
+	struct video_info *video_info = &dp->video_info;
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &dp_video_config->link_rate)) {
-		dev_err(dev, "failed to get link-rate\n");
-		return ERR_PTR(-EINVAL);
+				 &video_info->link_rate)) {
+		dev_err(dp->dev, "failed to get link-rate\n");
+		return -EINVAL;
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &dp_video_config->lane_count)) {
-		dev_err(dev, "failed to get lane-count\n");
-		return ERR_PTR(-EINVAL);
+				 &video_info->lane_count)) {
+		dev_err(dp->dev, "failed to get lane-count\n");
+		return -EINVAL;
 	}
 
-	return dp_video_config;
+	return 0;
 }
 
 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
@@ -1159,9 +1201,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	 */
 	dp->plat_data = plat_data;
 
-	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
-	if (IS_ERR(dp->video_info))
-		return PTR_ERR(dp->video_info);
+	ret = analogix_dp_dt_parse_pdata(dp);
+	if (ret)
+		return ret;
 
 	dp->phy = devm_phy_get(dp->dev, "dp");
 	if (IS_ERR(dp->phy)) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 9a90a18..730486d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -120,9 +120,9 @@ enum dp_irq_type {
 struct video_info {
 	char *name;
 
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
+	u32 h_sync_polarity;
+	u32 v_sync_polarity;
+	u32 interlaced;
 
 	enum color_space color_space;
 	enum dynamic_range dynamic_range;
@@ -154,7 +154,7 @@ struct analogix_dp_device {
 	unsigned int		irq;
 	void __iomem		*reg_base;
 
-	struct video_info	*video_info;
+	struct video_info	video_info;
 	struct link_train	link_train;
 	struct work_struct	hotplug_work;
 	struct phy		*phy;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index a388c0a..861097a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
 	u32 reg;
 
 	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info.color_depth << IN_BPC_SHIFT) |
+		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
 	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
+	if (dp->video_info.ycbcr_coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
@@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
+	reg |= (dp->video_info.interlaced << 2);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
+	reg |= (dp->video_info.v_sync_polarity << 1);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
+	reg |= (dp->video_info.h_sync_polarity << 0);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-10 15:46     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:46 UTC (permalink / raw)
  To: linux-arm-kernel

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.

But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).

Changes in v4:
- Provide backword compatibility with samsung. (Krzysztof)

Changes in v3:
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   8 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
 3 files changed, 106 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 96afb67..9d802ef 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					 dp->video_info->link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
+					 dp->video_info.link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
+					struct drm_display_mode *orig_mode,
+					struct drm_display_mode *mode)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_display_info *display_info = &dp->connector->display_info;
+	struct video_info *video = &dp->video_info;
+	struct device_node *dp_node = dp->dev->of_node;
+	int vic;
+
+	/* Input video interlaces & hsync pol & vsync pol */
+	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+	/* Input video dynamic_range & colorimetry */
+	vic = drm_match_cea_mode(mode);
+	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
+	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR601;
+	} else if (vic) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	} else {
+		video->dynamic_range = VESA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	}
+
+	/* Input vide bpc and color_formats */
+	switch (display_info->bpc) {
+	case 12:
+		video->color_depth = COLOR_12;
+		break;
+	case 10:
+		video->color_depth = COLOR_10;
+		break;
+	case 8:
+		video->color_depth = COLOR_8;
+		break;
+	case 6:
+		video->color_depth = COLOR_6;
+		break;
+	default:
+		video->color_depth = COLOR_8;
+		break;
+	}
+	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
+		video->color_space = COLOR_YCBCR444;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
+		video->color_space = COLOR_YCBCR422;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
+		video->color_space = COLOR_RGB;
+	else
+		video->color_space = COLOR_RGB;
+
+	/*
+	 * NOTE: those property parsing code is used for providing backward
+	 * compatibility for samsung platform.
+	 * Due to we used the "of_property_read_u32" interfaces, when this
+	 * property isn't present, the "video_info" can keep the original
+	 * values and wouldn't be modified.
+	 */
+	of_property_read_u32(dp_node, "samsung,color-space",
+			     &video->color_space);
+	of_property_read_u32(dp_node, "samsung,dynamic-range",
+			     &video->dynamic_range);
+	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+			     &video->ycbcr_coeff);
+	of_property_read_u32(dp_node, "samsung,color-depth",
+			     &video->color_depth);
+	of_property_read_u32(dp_node, "hsync-active-high",
+			     &video->h_sync_polarity);
+	of_property_read_u32(dp_node, "vsync-active-high",
+			     &video->v_sync_polarity);
+	of_property_read_u32(dp_node, "interlaced",
+			     &video->interlaced);
+}
+
 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
@@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
 	.disable = analogix_dp_bridge_disable,
 	.pre_enable = analogix_dp_bridge_nop,
 	.post_disable = analogix_dp_bridge_nop,
+	.mode_set = analogix_dp_bridge_mode_set,
 	.attach = analogix_dp_bridge_attach,
 };
 
@@ -1071,62 +1151,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 	return 0;
 }
 
-static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
-	struct device_node *dp_node = dev->of_node;
-	struct video_info *dp_video_config;
-
-	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
-				       GFP_KERNEL);
-	if (!dp_video_config)
-		return ERR_PTR(-ENOMEM);
-
-	dp_video_config->h_sync_polarity =
-		of_property_read_bool(dp_node, "hsync-active-high");
-
-	dp_video_config->v_sync_polarity =
-		of_property_read_bool(dp_node, "vsync-active-high");
-
-	dp_video_config->interlaced =
-		of_property_read_bool(dp_node, "interlaced");
-
-	if (of_property_read_u32(dp_node, "samsung,color-space",
-				 &dp_video_config->color_space)) {
-		dev_err(dev, "failed to get color-space\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				 &dp_video_config->dynamic_range)) {
-		dev_err(dev, "failed to get dynamic-range\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				 &dp_video_config->ycbcr_coeff)) {
-		dev_err(dev, "failed to get ycbcr-coeff\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				 &dp_video_config->color_depth)) {
-		dev_err(dev, "failed to get color-depth\n");
-		return ERR_PTR(-EINVAL);
-	}
+	struct device_node *dp_node = dp->dev->of_node;
+	struct video_info *video_info = &dp->video_info;
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &dp_video_config->link_rate)) {
-		dev_err(dev, "failed to get link-rate\n");
-		return ERR_PTR(-EINVAL);
+				 &video_info->link_rate)) {
+		dev_err(dp->dev, "failed to get link-rate\n");
+		return -EINVAL;
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &dp_video_config->lane_count)) {
-		dev_err(dev, "failed to get lane-count\n");
-		return ERR_PTR(-EINVAL);
+				 &video_info->lane_count)) {
+		dev_err(dp->dev, "failed to get lane-count\n");
+		return -EINVAL;
 	}
 
-	return dp_video_config;
+	return 0;
 }
 
 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
@@ -1159,9 +1201,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	 */
 	dp->plat_data = plat_data;
 
-	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
-	if (IS_ERR(dp->video_info))
-		return PTR_ERR(dp->video_info);
+	ret = analogix_dp_dt_parse_pdata(dp);
+	if (ret)
+		return ret;
 
 	dp->phy = devm_phy_get(dp->dev, "dp");
 	if (IS_ERR(dp->phy)) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 9a90a18..730486d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -120,9 +120,9 @@ enum dp_irq_type {
 struct video_info {
 	char *name;
 
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
+	u32 h_sync_polarity;
+	u32 v_sync_polarity;
+	u32 interlaced;
 
 	enum color_space color_space;
 	enum dynamic_range dynamic_range;
@@ -154,7 +154,7 @@ struct analogix_dp_device {
 	unsigned int		irq;
 	void __iomem		*reg_base;
 
-	struct video_info	*video_info;
+	struct video_info	video_info;
 	struct link_train	link_train;
 	struct work_struct	hotplug_work;
 	struct phy		*phy;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index a388c0a..861097a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
 	u32 reg;
 
 	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info.color_depth << IN_BPC_SHIFT) |
+		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
 	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
+	if (dp->video_info.ycbcr_coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
@@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
+	reg |= (dp->video_info.interlaced << 2);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
+	reg |= (dp->video_info.v_sync_polarity << 1);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
+	reg |= (dp->video_info.h_sync_polarity << 0);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 06/17] Documentation: drm/bridge: add document for analogix_dp
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 15:49     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:49 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt

Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Split all DTS changes, and provide backward compatibility. Mark old
  properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"

Changes in v3:
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
  devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.

Changes in v2: None

 .../devicetree/bindings/drm/bridge/analogix_dp.txt | 50 +++++++++++++++++
 .../devicetree/bindings/video/exynos_dp.txt        | 63 ++++++++--------------
 2 files changed, 71 insertions(+), 42 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt

diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
new file mode 100644
index 0000000..f54dc3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -0,0 +1,50 @@
+Analogix Display Port bridge bindings
+
+Required properties for dp-controller:
+	-compatible:
+		platform specific such as:
+		 * "samsung,exynos5-dp"
+		 * "rockchip,rk3288-dp"
+	-reg:
+		physical base address of the controller and length
+		of memory mapped region.
+	-interrupts:
+		interrupt combiner values.
+	-clocks:
+		from common clock binding: handle to dp clock.
+	-clock-names:
+		from common clock binding: Shall be "dp".
+	-interrupt-parent:
+		phandle to Interrupt combiner node.
+	-phys:
+		from general PHY binding: the phandle for the PHY device.
+	-phy-names:
+		from general PHY binding: Should be "dp".
+
+Optional properties for dp-controller:
+	-hpd-gpios:
+		Hotplug detect GPIO.
+		Indicates which GPIO should be used for hotplug detection
+	-port@[X]: SoC specific port nodes with endpoint definitions as defined
+		in Documentation/devicetree/bindings/media/video-interfaces.txt,
+		please refer to the SoC specific binding document:
+		* Documentation/devicetree/bindings/video/exynos_dp.txt
+		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+-------------------------------------------------------------------------------
+
+Example:
+
+	dp-controller {
+		compatible = "samsung,exynos5-dp";
+		reg = <0x145b0000 0x10000>;
+		interrupts = <10 3>;
+		interrupt-parent = <&combiner>;
+		clocks = <&clock 342>;
+		clock-names = "dp";
+
+		phys = <&dp_phy>;
+		phy-names = "dp";
+	};
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index 7a3a9cd..ea03b3a 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -31,45 +31,31 @@ Required properties for dp-controller:
 		from general PHY binding: the phandle for the PHY device.
 	-phy-names:
 		from general PHY binding: Should be "dp".
-	-samsung,color-space:
-		input video data format.
-			COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
-	-samsung,dynamic-range:
-		dynamic range for input video data.
-			VESA = 0, CEA = 1
-	-samsung,ycbcr-coeff:
-		YCbCr co-efficients for input video.
-			COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
-	-samsung,color-depth:
-		number of bits per colour component.
-			COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
-	-samsung,link-rate:
-		link rate supported by the panel.
-			LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
-	-samsung,lane-count:
-		number of lanes supported by the panel.
-			LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
+
+Optional properties for dp-controller:
 	- display-timings: timings for the connected panel as described by
 		Documentation/devicetree/bindings/video/display-timing.txt
 
-Optional properties for dp-controller:
-	-interlaced:
-		interlace scan mode.
-			Progressive if defined, Interlaced if not defined
-	-vsync-active-high:
-		VSYNC polarity configuration.
-			High if defined, Low if not defined
-	-hsync-active-high:
-		HSYNC polarity configuration.
-			High if defined, Low if not defined
-	-samsung,hpd-gpio:
-		Hotplug detect GPIO.
-			Indicates which GPIO should be used for hotplug
-			detection
-	-video interfaces: Device node can contain video interface port
-			    nodes according to [1].
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+	-phys (required)
+	-phy-names (required)
+	-hpd-gpios (optional)
+	-video interfaces (optional)
 
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+Deprecated properties for DisplayPort:
+-interlaced:            deprecated prop that can parsed frm drm_display_mode.
+-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-samsung,ycbcr-coeff:   deprecated prop that can parsed frm drm_display_mode.
+-samsung,dynamic-range: deprecated prop that can parsed frm drm_display_mode.
+-samsung,color-space:   deprecated prop that can parsed from drm_display_info.
+-samsung,color-depth:   deprecated prop that can parsed from drm_display_info.
+-samsung,link-rate:     deprecated prop that can reading from monitor by dpcd method.
+-samsung,lane-count:    deprecated prop that can reading from monitor by dpcd method.
+-samsung,hpd-gpio:      deprecated name for hpd-gpios.
+
+-------------------------------------------------------------------------------
 
 Example:
 
@@ -88,13 +74,6 @@ SOC specific portion:
 
 Board Specific portion:
 	dp-controller {
-		samsung,color-space = <0>;
-		samsung,dynamic-range = <0>;
-		samsung,ycbcr-coeff = <0>;
-		samsung,color-depth = <1>;
-		samsung,link-rate = <0x0a>;
-		samsung,lane-count = <4>;
-
 		display-timings {
 			native-mode = <&lcd_timing>;
 			lcd_timing: 1366x768 {
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 06/17] Documentation: drm/bridge: add document for analogix_dp
@ 2015-10-10 15:49     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:49 UTC (permalink / raw)
  To: linux-arm-kernel

Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt

Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Split all DTS changes, and provide backward compatibility. Mark old
  properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"

Changes in v3:
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
  devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.

Changes in v2: None

 .../devicetree/bindings/drm/bridge/analogix_dp.txt | 50 +++++++++++++++++
 .../devicetree/bindings/video/exynos_dp.txt        | 63 ++++++++--------------
 2 files changed, 71 insertions(+), 42 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt

diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
new file mode 100644
index 0000000..f54dc3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -0,0 +1,50 @@
+Analogix Display Port bridge bindings
+
+Required properties for dp-controller:
+	-compatible:
+		platform specific such as:
+		 * "samsung,exynos5-dp"
+		 * "rockchip,rk3288-dp"
+	-reg:
+		physical base address of the controller and length
+		of memory mapped region.
+	-interrupts:
+		interrupt combiner values.
+	-clocks:
+		from common clock binding: handle to dp clock.
+	-clock-names:
+		from common clock binding: Shall be "dp".
+	-interrupt-parent:
+		phandle to Interrupt combiner node.
+	-phys:
+		from general PHY binding: the phandle for the PHY device.
+	-phy-names:
+		from general PHY binding: Should be "dp".
+
+Optional properties for dp-controller:
+	-hpd-gpios:
+		Hotplug detect GPIO.
+		Indicates which GPIO should be used for hotplug detection
+	-port@[X]: SoC specific port nodes with endpoint definitions as defined
+		in Documentation/devicetree/bindings/media/video-interfaces.txt,
+		please refer to the SoC specific binding document:
+		* Documentation/devicetree/bindings/video/exynos_dp.txt
+		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+-------------------------------------------------------------------------------
+
+Example:
+
+	dp-controller {
+		compatible = "samsung,exynos5-dp";
+		reg = <0x145b0000 0x10000>;
+		interrupts = <10 3>;
+		interrupt-parent = <&combiner>;
+		clocks = <&clock 342>;
+		clock-names = "dp";
+
+		phys = <&dp_phy>;
+		phy-names = "dp";
+	};
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index 7a3a9cd..ea03b3a 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -31,45 +31,31 @@ Required properties for dp-controller:
 		from general PHY binding: the phandle for the PHY device.
 	-phy-names:
 		from general PHY binding: Should be "dp".
-	-samsung,color-space:
-		input video data format.
-			COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
-	-samsung,dynamic-range:
-		dynamic range for input video data.
-			VESA = 0, CEA = 1
-	-samsung,ycbcr-coeff:
-		YCbCr co-efficients for input video.
-			COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
-	-samsung,color-depth:
-		number of bits per colour component.
-			COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
-	-samsung,link-rate:
-		link rate supported by the panel.
-			LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
-	-samsung,lane-count:
-		number of lanes supported by the panel.
-			LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
+
+Optional properties for dp-controller:
 	- display-timings: timings for the connected panel as described by
 		Documentation/devicetree/bindings/video/display-timing.txt
 
-Optional properties for dp-controller:
-	-interlaced:
-		interlace scan mode.
-			Progressive if defined, Interlaced if not defined
-	-vsync-active-high:
-		VSYNC polarity configuration.
-			High if defined, Low if not defined
-	-hsync-active-high:
-		HSYNC polarity configuration.
-			High if defined, Low if not defined
-	-samsung,hpd-gpio:
-		Hotplug detect GPIO.
-			Indicates which GPIO should be used for hotplug
-			detection
-	-video interfaces: Device node can contain video interface port
-			    nodes according to [1].
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+	-phys (required)
+	-phy-names (required)
+	-hpd-gpios (optional)
+	-video interfaces (optional)
 
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+Deprecated properties for DisplayPort:
+-interlaced:            deprecated prop that can parsed frm drm_display_mode.
+-vsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-hsync-active-high:     deprecated prop that can parsed frm drm_display_mode.
+-samsung,ycbcr-coeff:   deprecated prop that can parsed frm drm_display_mode.
+-samsung,dynamic-range: deprecated prop that can parsed frm drm_display_mode.
+-samsung,color-space:   deprecated prop that can parsed from drm_display_info.
+-samsung,color-depth:   deprecated prop that can parsed from drm_display_info.
+-samsung,link-rate:     deprecated prop that can reading from monitor by dpcd method.
+-samsung,lane-count:    deprecated prop that can reading from monitor by dpcd method.
+-samsung,hpd-gpio:      deprecated name for hpd-gpios.
+
+-------------------------------------------------------------------------------
 
 Example:
 
@@ -88,13 +74,6 @@ SOC specific portion:
 
 Board Specific portion:
 	dp-controller {
-		samsung,color-space = <0>;
-		samsung,dynamic-range = <0>;
-		samsung,ycbcr-coeff = <0>;
-		samsung,color-depth = <1>;
-		samsung,link-rate = <0x0a>;
-		samsung,lane-count = <4>;
-
 		display-timings {
 			native-mode = <&lcd_timing>;
 			lcd_timing: 1366x768 {
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 15:49     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:49 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.

Beside the backward compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6:
- Fix Peach Pit hpd property name error:
-       hpd-gpio = <&gpx2 6 0>;
+       hpd-gpios = <&gpx2 6 0>;

Changes in v5:
- Correct the misspell in commit message. (Krzysztof)

Changes in v4:
- Separate all DTS changes to a separate patch. (Krzysztof)

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/exynos5250-arndale.dts      | 2 --
 arch/arm/boot/dts/exynos5250-smdk5250.dts     | 2 --
 arch/arm/boot/dts/exynos5250-snow-common.dtsi | 4 +---
 arch/arm/boot/dts/exynos5250-spring.dts       | 4 +---
 arch/arm/boot/dts/exynos5420-peach-pit.dts    | 4 +---
 arch/arm/boot/dts/exynos5420-smdk5420.dts     | 2 --
 arch/arm/boot/dts/exynos5800-peach-pi.dts     | 4 +---
 7 files changed, 4 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index c000532..b1790cf 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -124,8 +124,6 @@
 &dp {
 	status = "okay";
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 0f5dcd4..f30c2db 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -80,8 +80,6 @@
 
 &dp {
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index 0a7f408..ee94110 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -236,12 +236,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
 
 	ports {
 		port@0 {
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index c1edd6d..91881d7 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -74,12 +74,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <1>;
-	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
 };
 
 &ehci {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index e722c22..776cae9 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -148,12 +148,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x06>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
 
 	ports {
 		port@0 {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index ac35aef..f67344f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -93,8 +93,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 56275a6..f6b7a58 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -142,12 +142,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
 	panel = <&panel>;
 };
 
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
@ 2015-10-10 15:49     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:49 UTC (permalink / raw)
  To: linux-arm-kernel

After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.

Beside the backward compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6:
- Fix Peach Pit hpd property name error:
-       hpd-gpio = <&gpx2 6 0>;
+       hpd-gpios = <&gpx2 6 0>;

Changes in v5:
- Correct the misspell in commit message. (Krzysztof)

Changes in v4:
- Separate all DTS changes to a separate patch. (Krzysztof)

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/exynos5250-arndale.dts      | 2 --
 arch/arm/boot/dts/exynos5250-smdk5250.dts     | 2 --
 arch/arm/boot/dts/exynos5250-snow-common.dtsi | 4 +---
 arch/arm/boot/dts/exynos5250-spring.dts       | 4 +---
 arch/arm/boot/dts/exynos5420-peach-pit.dts    | 4 +---
 arch/arm/boot/dts/exynos5420-smdk5420.dts     | 2 --
 arch/arm/boot/dts/exynos5800-peach-pi.dts     | 4 +---
 7 files changed, 4 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index c000532..b1790cf 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -124,8 +124,6 @@
 &dp {
 	status = "okay";
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 0f5dcd4..f30c2db 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -80,8 +80,6 @@
 
 &dp {
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index 0a7f408..ee94110 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -236,12 +236,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
 
 	ports {
 		port at 0 {
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index c1edd6d..91881d7 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -74,12 +74,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <1>;
-	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
 };
 
 &ehci {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index e722c22..776cae9 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -148,12 +148,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x06>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
 
 	ports {
 		port at 0 {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index ac35aef..f67344f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -93,8 +93,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 56275a6..f6b7a58 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -142,12 +142,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
 	panel = <&panel>;
 };
 
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 08/17] drm: rockchip: dp: add rockchip platform dp driver
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 15:51     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:51 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
  numbers in the example DT node, and remove the regulator iomux setting
  in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
  support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)

Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.

Changes in v3:
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
  and leave "sclk_edp" to analogix dp core driver which name to "dp",
  and leave "pclk_edp" to rockchip dp platform driver which name to
  "pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
  node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.

Changes in v2:
- Get panel node with remote-endpoint method, and create devicetree binding
  for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.

 drivers/gpu/drm/rockchip/Kconfig                |   9 +
 drivers/gpu/drm/rockchip/Makefile               |   1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 442 ++++++++++++++++++++++++
 include/drm/bridge/analogix_dp.h                |   1 +
 4 files changed, 453 insertions(+)
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..c2ba945 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
 	  for the Synopsys DesignWare HDMI driver. If you want to
 	  enable HDMI on RK3288 based SoC, you should selet this
 	  option.
+
+config ROCKCHIP_ANALOGIX_DP
+        tristate "Rockchip specific extensions for Analogix DP driver"
+        depends on DRM_ROCKCHIP
+        select DRM_ANALOGIX_DP
+        help
+	  This selects support for Rockchip SoC specific extensions
+	  for the Analogix Core DP driver. If you want to enable DP
+	  on RK3288 based SoC, you should selet this option.
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..8ad01fb 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \
 		rockchip_drm_gem.o
 
 obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 
 obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
new file mode 100644
index 0000000..2c82a9a
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -0,0 +1,442 @@
+/*
+ * Rockchip SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ *         Yakir Yang <ykk@rock-chips.com>
+ *         Jeff Chen <jeff.chen@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)
+
+/* dp grf register offset */
+#define GRF_SOC_CON6                            0x025c
+#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
+#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
+#define GRF_EDP_SEL_VOP_BIG                     0
+
+struct rockchip_dp_device {
+	struct drm_device        *drm_dev;
+	struct device            *dev;
+	struct drm_encoder       encoder;
+	struct drm_connector     connector;
+	struct drm_display_mode  mode;
+
+	struct clk               *pclk;
+	struct regmap            *grf;
+	struct reset_control     *rst;
+
+	struct analogix_dp_plat_data plat_data;
+};
+
+static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+{
+	reset_control_assert(dp->rst);
+	usleep_range(10, 20);
+	reset_control_deassert(dp->rst);
+
+	return 0;
+}
+
+static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+	int ret;
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+
+	clk_disable_unprepare(dp->pclk);
+
+	return 0;
+}
+
+static int rockchip_dp_get_modes(struct drm_connector *connector)
+{
+	struct rockchip_dp_device *dp = to_dp(connector);
+
+	return analogix_dp_get_modes(dp->dev);
+}
+
+static struct drm_encoder *
+rockchip_dp_best_encoder(struct drm_connector *connector)
+{
+	struct rockchip_dp_device *dp = to_dp(connector);
+
+	return &dp->encoder;
+}
+
+static struct drm_connector_helper_funcs rockchip_dp_connector_helper_funcs = {
+	.get_modes = rockchip_dp_get_modes,
+	.best_encoder = rockchip_dp_best_encoder,
+};
+
+static enum drm_connector_status
+rockchip_dp_detect(struct drm_connector *connector, bool force)
+{
+	struct rockchip_dp_device *dp = to_dp(connector);
+
+	return analogix_dp_detect(dp->dev, force);
+}
+
+static void rockchip_dp_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static struct drm_connector_funcs rockchip_dp_connector_funcs = {
+	.dpms = drm_helper_connector_dpms,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.detect = rockchip_dp_detect,
+	.destroy = rockchip_dp_connector_destroy,
+};
+
+static int rockchip_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+				     struct drm_bridge *bridge)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+	struct drm_connector *connector = &dp->connector;
+	struct drm_encoder *encoder = &dp->encoder;
+	int ret;
+
+	connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+	ret = drm_connector_init(dp->drm_dev, connector,
+				 &rockchip_dp_connector_funcs,
+				 DRM_MODE_CONNECTOR_eDP);
+	if (ret) {
+		DRM_ERROR("Failed to initialize connector with drm\n");
+		return ret;
+	}
+
+	drm_connector_helper_add(connector,
+				 &rockchip_dp_connector_helper_funcs);
+	drm_mode_connector_attach_encoder(connector, encoder);
+
+	dp->plat_data.connector = connector;
+
+	return 0;
+}
+
+static bool
+rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
+				   const struct drm_display_mode *mode,
+				   struct drm_display_mode *adjusted_mode)
+{
+	/* do nothing */
+	return true;
+}
+
+static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
+					     struct drm_display_mode *mode,
+					     struct drm_display_mode *adjusted)
+{
+	/* do nothing */
+}
+
+static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
+{
+	struct rockchip_dp_device *dp = to_dp(encoder);
+	u32 val;
+	int ret;
+
+	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					    DRM_MODE_CONNECTOR_eDP,
+					    ROCKCHIP_OUT_MODE_AAAA);
+	if (ret < 0) {
+		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+		return;
+	}
+
+	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
+	if (ret < 0)
+		return;
+
+	if (ret)
+		val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
+	else
+		val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
+
+	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+		return;
+	}
+}
+
+static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
+{
+	/* do nothing */
+}
+
+static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
+	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
+	.mode_set = rockchip_dp_drm_encoder_mode_set,
+	.prepare = rockchip_dp_drm_encoder_prepare,
+	.commit = rockchip_dp_drm_encoder_nop,
+	.disable = rockchip_dp_drm_encoder_nop,
+};
+
+static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
+	.destroy = rockchip_dp_drm_encoder_destroy,
+};
+
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+	struct device *dev = dp->dev;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "failed to get rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	dp->pclk = devm_clk_get(dev, "pclk");
+	if (IS_ERR(dp->pclk)) {
+		dev_err(dev, "failed to get pclk property\n");
+		return PTR_ERR(dp->pclk);
+	}
+
+	dp->rst = devm_reset_control_get(dev, "dp");
+	if (IS_ERR(dp->rst)) {
+		dev_err(dev, "failed to get dp reset control\n");
+		return PTR_ERR(dp->rst);
+	}
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
+{
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct device *dev = dp->dev;
+	int ret;
+
+	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+							     dev->of_node);
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
+			       DRM_MODE_ENCODER_TMDS);
+	if (ret) {
+		DRM_ERROR("failed to initialize encoder with drm\n");
+		return ret;
+	}
+
+	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
+
+	return 0;
+}
+
+static int rockchip_dp_bind(struct device *dev, struct device *master,
+			    void *data)
+{
+	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_device *drm_dev = data;
+	int ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	ret = rockchip_dp_init(dp);
+	if (ret < 0)
+		return ret;
+
+	dp->drm_dev = drm_dev;
+
+	ret = rockchip_dp_drm_create_encoder(dp);
+	if (ret) {
+		DRM_ERROR("failed to create drm encoder\n");
+		return ret;
+	}
+
+	dp->plat_data.encoder = &dp->encoder;
+
+	dp->plat_data.dev_type = RK3288_DP;
+	dp->plat_data.power_on = rockchip_dp_poweron;
+	dp->plat_data.power_off = rockchip_dp_powerdown;
+	dp->plat_data.attach = rockchip_dp_bridge_attach;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
+}
+
+static void rockchip_dp_unbind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops rockchip_dp_component_ops = {
+	.bind = rockchip_dp_bind,
+	.unbind = rockchip_dp_unbind,
+};
+
+static int rockchip_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *port, *endpoint;
+	struct rockchip_dp_device *dp;
+	struct drm_panel *panel;
+
+	port = of_graph_get_port_by_id(dev->of_node, 1);
+	if (!port) {
+		dev_err(dev, "can't find output port\n");
+		return -EINVAL;
+	}
+
+	endpoint = of_get_child_by_name(port, "endpoint");
+	of_node_put(port);
+	if (!endpoint) {
+		dev_err(dev, "no output endpoint found\n");
+		return -EINVAL;
+	}
+
+	panel_node = of_graph_get_remote_port_parent(endpoint);
+	of_node_put(endpoint);
+	if (!panel_node) {
+		dev_err(dev, "no output node found\n");
+		return -EINVAL;
+	}
+
+	panel = of_drm_find_panel(panel_node);
+	if (!panel) {
+		DRM_ERROR("failed to find panel\n");
+		of_node_put(panel_node);
+		return -EPROBE_DEFER;
+	}
+
+	of_node_put(panel_node);
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->plat_data.panel = panel;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver could take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	return component_add(dev, &rockchip_dp_component_ops);
+}
+
+static int rockchip_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &rockchip_dp_component_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int rockchip_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops rockchip_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
+};
+
+static const struct of_device_id rockchip_dp_dt_ids[] = {
+	{.compatible = "rockchip,rk3288-dp",},
+	{}
+};
+MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
+
+static struct platform_driver rockchip_dp_driver = {
+	.probe = rockchip_dp_probe,
+	.remove = rockchip_dp_remove,
+	.driver = {
+		   .name = "rockchip-dp",
+		   .owner = THIS_MODULE,
+		   .pm = &rockchip_dp_pm_ops,
+		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
+	},
+};
+
+module_platform_driver(rockchip_dp_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index 134638af..7d9857a 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -15,6 +15,7 @@
 
 enum analogix_dp_devtype {
 	EXYNOS_DP,
+	RK3288_DP,
 };
 
 struct analogix_dp_plat_data {
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 08/17] drm: rockchip: dp: add rockchip platform dp driver
@ 2015-10-10 15:51     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:51 UTC (permalink / raw)
  To: linux-arm-kernel

Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
  numbers in the example DT node, and remove the regulator iomux setting
  in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
  support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)

Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.

Changes in v3:
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
  and leave "sclk_edp" to analogix dp core driver which name to "dp",
  and leave "pclk_edp" to rockchip dp platform driver which name to
  "pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
  node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.

Changes in v2:
- Get panel node with remote-endpoint method, and create devicetree binding
  for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.

 drivers/gpu/drm/rockchip/Kconfig                |   9 +
 drivers/gpu/drm/rockchip/Makefile               |   1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 442 ++++++++++++++++++++++++
 include/drm/bridge/analogix_dp.h                |   1 +
 4 files changed, 453 insertions(+)
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..c2ba945 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
 	  for the Synopsys DesignWare HDMI driver. If you want to
 	  enable HDMI on RK3288 based SoC, you should selet this
 	  option.
+
+config ROCKCHIP_ANALOGIX_DP
+        tristate "Rockchip specific extensions for Analogix DP driver"
+        depends on DRM_ROCKCHIP
+        select DRM_ANALOGIX_DP
+        help
+	  This selects support for Rockchip SoC specific extensions
+	  for the Analogix Core DP driver. If you want to enable DP
+	  on RK3288 based SoC, you should selet this option.
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..8ad01fb 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \
 		rockchip_drm_gem.o
 
 obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 
 obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
new file mode 100644
index 0000000..2c82a9a
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -0,0 +1,442 @@
+/*
+ * Rockchip SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ *         Yakir Yang <ykk@rock-chips.com>
+ *         Jeff Chen <jeff.chen@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)
+
+/* dp grf register offset */
+#define GRF_SOC_CON6                            0x025c
+#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
+#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
+#define GRF_EDP_SEL_VOP_BIG                     0
+
+struct rockchip_dp_device {
+	struct drm_device        *drm_dev;
+	struct device            *dev;
+	struct drm_encoder       encoder;
+	struct drm_connector     connector;
+	struct drm_display_mode  mode;
+
+	struct clk               *pclk;
+	struct regmap            *grf;
+	struct reset_control     *rst;
+
+	struct analogix_dp_plat_data plat_data;
+};
+
+static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+{
+	reset_control_assert(dp->rst);
+	usleep_range(10, 20);
+	reset_control_deassert(dp->rst);
+
+	return 0;
+}
+
+static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+	int ret;
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+
+	clk_disable_unprepare(dp->pclk);
+
+	return 0;
+}
+
+static int rockchip_dp_get_modes(struct drm_connector *connector)
+{
+	struct rockchip_dp_device *dp = to_dp(connector);
+
+	return analogix_dp_get_modes(dp->dev);
+}
+
+static struct drm_encoder *
+rockchip_dp_best_encoder(struct drm_connector *connector)
+{
+	struct rockchip_dp_device *dp = to_dp(connector);
+
+	return &dp->encoder;
+}
+
+static struct drm_connector_helper_funcs rockchip_dp_connector_helper_funcs = {
+	.get_modes = rockchip_dp_get_modes,
+	.best_encoder = rockchip_dp_best_encoder,
+};
+
+static enum drm_connector_status
+rockchip_dp_detect(struct drm_connector *connector, bool force)
+{
+	struct rockchip_dp_device *dp = to_dp(connector);
+
+	return analogix_dp_detect(dp->dev, force);
+}
+
+static void rockchip_dp_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static struct drm_connector_funcs rockchip_dp_connector_funcs = {
+	.dpms = drm_helper_connector_dpms,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.detect = rockchip_dp_detect,
+	.destroy = rockchip_dp_connector_destroy,
+};
+
+static int rockchip_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+				     struct drm_bridge *bridge)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+	struct drm_connector *connector = &dp->connector;
+	struct drm_encoder *encoder = &dp->encoder;
+	int ret;
+
+	connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+	ret = drm_connector_init(dp->drm_dev, connector,
+				 &rockchip_dp_connector_funcs,
+				 DRM_MODE_CONNECTOR_eDP);
+	if (ret) {
+		DRM_ERROR("Failed to initialize connector with drm\n");
+		return ret;
+	}
+
+	drm_connector_helper_add(connector,
+				 &rockchip_dp_connector_helper_funcs);
+	drm_mode_connector_attach_encoder(connector, encoder);
+
+	dp->plat_data.connector = connector;
+
+	return 0;
+}
+
+static bool
+rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
+				   const struct drm_display_mode *mode,
+				   struct drm_display_mode *adjusted_mode)
+{
+	/* do nothing */
+	return true;
+}
+
+static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
+					     struct drm_display_mode *mode,
+					     struct drm_display_mode *adjusted)
+{
+	/* do nothing */
+}
+
+static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
+{
+	struct rockchip_dp_device *dp = to_dp(encoder);
+	u32 val;
+	int ret;
+
+	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					    DRM_MODE_CONNECTOR_eDP,
+					    ROCKCHIP_OUT_MODE_AAAA);
+	if (ret < 0) {
+		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+		return;
+	}
+
+	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
+	if (ret < 0)
+		return;
+
+	if (ret)
+		val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
+	else
+		val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
+
+	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+		return;
+	}
+}
+
+static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
+{
+	/* do nothing */
+}
+
+static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
+	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
+	.mode_set = rockchip_dp_drm_encoder_mode_set,
+	.prepare = rockchip_dp_drm_encoder_prepare,
+	.commit = rockchip_dp_drm_encoder_nop,
+	.disable = rockchip_dp_drm_encoder_nop,
+};
+
+static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
+	.destroy = rockchip_dp_drm_encoder_destroy,
+};
+
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+	struct device *dev = dp->dev;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "failed to get rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	dp->pclk = devm_clk_get(dev, "pclk");
+	if (IS_ERR(dp->pclk)) {
+		dev_err(dev, "failed to get pclk property\n");
+		return PTR_ERR(dp->pclk);
+	}
+
+	dp->rst = devm_reset_control_get(dev, "dp");
+	if (IS_ERR(dp->rst)) {
+		dev_err(dev, "failed to get dp reset control\n");
+		return PTR_ERR(dp->rst);
+	}
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
+{
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct device *dev = dp->dev;
+	int ret;
+
+	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+							     dev->of_node);
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
+			       DRM_MODE_ENCODER_TMDS);
+	if (ret) {
+		DRM_ERROR("failed to initialize encoder with drm\n");
+		return ret;
+	}
+
+	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
+
+	return 0;
+}
+
+static int rockchip_dp_bind(struct device *dev, struct device *master,
+			    void *data)
+{
+	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_device *drm_dev = data;
+	int ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	ret = rockchip_dp_init(dp);
+	if (ret < 0)
+		return ret;
+
+	dp->drm_dev = drm_dev;
+
+	ret = rockchip_dp_drm_create_encoder(dp);
+	if (ret) {
+		DRM_ERROR("failed to create drm encoder\n");
+		return ret;
+	}
+
+	dp->plat_data.encoder = &dp->encoder;
+
+	dp->plat_data.dev_type = RK3288_DP;
+	dp->plat_data.power_on = rockchip_dp_poweron;
+	dp->plat_data.power_off = rockchip_dp_powerdown;
+	dp->plat_data.attach = rockchip_dp_bridge_attach;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
+}
+
+static void rockchip_dp_unbind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops rockchip_dp_component_ops = {
+	.bind = rockchip_dp_bind,
+	.unbind = rockchip_dp_unbind,
+};
+
+static int rockchip_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *port, *endpoint;
+	struct rockchip_dp_device *dp;
+	struct drm_panel *panel;
+
+	port = of_graph_get_port_by_id(dev->of_node, 1);
+	if (!port) {
+		dev_err(dev, "can't find output port\n");
+		return -EINVAL;
+	}
+
+	endpoint = of_get_child_by_name(port, "endpoint");
+	of_node_put(port);
+	if (!endpoint) {
+		dev_err(dev, "no output endpoint found\n");
+		return -EINVAL;
+	}
+
+	panel_node = of_graph_get_remote_port_parent(endpoint);
+	of_node_put(endpoint);
+	if (!panel_node) {
+		dev_err(dev, "no output node found\n");
+		return -EINVAL;
+	}
+
+	panel = of_drm_find_panel(panel_node);
+	if (!panel) {
+		DRM_ERROR("failed to find panel\n");
+		of_node_put(panel_node);
+		return -EPROBE_DEFER;
+	}
+
+	of_node_put(panel_node);
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->plat_data.panel = panel;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver could take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	return component_add(dev, &rockchip_dp_component_ops);
+}
+
+static int rockchip_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &rockchip_dp_component_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int rockchip_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops rockchip_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
+};
+
+static const struct of_device_id rockchip_dp_dt_ids[] = {
+	{.compatible = "rockchip,rk3288-dp",},
+	{}
+};
+MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
+
+static struct platform_driver rockchip_dp_driver = {
+	.probe = rockchip_dp_probe,
+	.remove = rockchip_dp_remove,
+	.driver = {
+		   .name = "rockchip-dp",
+		   .owner = THIS_MODULE,
+		   .pm = &rockchip_dp_pm_ops,
+		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
+	},
+};
+
+module_platform_driver(rockchip_dp_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index 134638af..7d9857a 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -15,6 +15,7 @@
 
 enum analogix_dp_devtype {
 	EXYNOS_DP,
+	RK3288_DP,
 };
 
 struct analogix_dp_plat_data {
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 09/17] Documentation: drm/bridge: add document for analogix_dp
@ 2015-10-10 15:53     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:53 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../bindings/video/analogix_dp-rockchip.txt        | 90 ++++++++++++++++++++++
 1 file changed, 90 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt

diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..ec93917
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -0,0 +1,90 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+	  of memory mapped region.
+
+- clock-names: from common clock binding:
+	       Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+	  See ../reset/reset.txt for details.
+
+- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
+- pinctrl-0: pin-control mode. should be <&edp_hpd>
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+	dp-controller: dp@ff970000 {
+		compatible = "rockchip,rk3288-dp";
+		reg = <0xff970000 0x4000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+		clock-names = "dp", "pclk";
+		phys = <&dp_phy>;
+		phy-names = "dp";
+
+		rockchip,grf = <&grf>;
+		resets = <&cru 111>;
+		reset-names = "dp";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_hpd>;
+
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			edp_in: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_edp>;
+				};
+				edp_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_edp>;
+				};
+			};
+
+			edp_out: port@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_out_panel: endpoint {
+					reg = <0>;
+					remote-endpoint = <&panel_in_edp>
+				};
+			};
+		};
+	};
+
+	pinctrl {
+		edp {
+			edp_hpd: edp-hpd {
+				rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+	};
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 09/17] Documentation: drm/bridge: add document for analogix_dp
@ 2015-10-10 15:53     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:53 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe-6d6DIl74uiNBDgjK7y7TUQ, Heiko Stuebner,
	Mark Yao
  Cc: Russell King, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	javier-JPH+aEBZ4P+UEJcrhfAQsw, Andy Yan, Yakir Yang,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../bindings/video/analogix_dp-rockchip.txt        | 90 ++++++++++++++++++++++
 1 file changed, 90 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt

diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..ec93917
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -0,0 +1,90 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+	  of memory mapped region.
+
+- clock-names: from common clock binding:
+	       Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+	  See ../reset/reset.txt for details.
+
+- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
+- pinctrl-0: pin-control mode. should be <&edp_hpd>
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+	dp-controller: dp@ff970000 {
+		compatible = "rockchip,rk3288-dp";
+		reg = <0xff970000 0x4000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+		clock-names = "dp", "pclk";
+		phys = <&dp_phy>;
+		phy-names = "dp";
+
+		rockchip,grf = <&grf>;
+		resets = <&cru 111>;
+		reset-names = "dp";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_hpd>;
+
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			edp_in: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_edp>;
+				};
+				edp_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_edp>;
+				};
+			};
+
+			edp_out: port@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_out_panel: endpoint {
+					reg = <0>;
+					remote-endpoint = <&panel_in_edp>
+				};
+			};
+		};
+	};
+
+	pinctrl {
+		edp {
+			edp_hpd: edp-hpd {
+				rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+	};
-- 
1.9.1


--
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^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 09/17] Documentation: drm/bridge: add document for analogix_dp
@ 2015-10-10 15:53     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:53 UTC (permalink / raw)
  To: linux-arm-kernel

Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../bindings/video/analogix_dp-rockchip.txt        | 90 ++++++++++++++++++++++
 1 file changed, 90 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt

diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..ec93917
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -0,0 +1,90 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+	  of memory mapped region.
+
+- clock-names: from common clock binding:
+	       Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+	  See ../reset/reset.txt for details.
+
+- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
+- pinctrl-0: pin-control mode. should be <&edp_hpd>
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+	dp-controller: dp at ff970000 {
+		compatible = "rockchip,rk3288-dp";
+		reg = <0xff970000 0x4000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+		clock-names = "dp", "pclk";
+		phys = <&dp_phy>;
+		phy-names = "dp";
+
+		rockchip,grf = <&grf>;
+		resets = <&cru 111>;
+		reset-names = "dp";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_hpd>;
+
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			edp_in: port at 0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_in_vopb: endpoint at 0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_edp>;
+				};
+				edp_in_vopl: endpoint at 1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_edp>;
+				};
+			};
+
+			edp_out: port at 1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_out_panel: endpoint {
+					reg = <0>;
+					remote-endpoint = <&panel_in_edp>
+				};
+			};
+		};
+	};
+
+	pinctrl {
+		edp {
+			edp_hpd: edp-hpd {
+				rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+	};
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 15:55     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:55 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
  the exist "grf" syscon already. And rename the example DT node from
  "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
  struct" to "static const struct". And correct the input paramters of
  devm_phy_create() interfaces. (Heiko)

Changes in v4:
- Add commit message, and remove the redundant rockchip_dp_phy_init()
  function, move those code to probe() method. And remove driver .owner
  number. (Kishon)

Changes in v3:
- Suggest, add rockchip dp phy driver, collect the phy clocks and
  power control. (Heiko)

Changes in v2: None

 drivers/phy/Kconfig           |   7 ++
 drivers/phy/Makefile          |   1 +
 drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 159 insertions(+)
 create mode 100644 drivers/phy/phy-rockchip-dp.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573..8f2bc4f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
 	help
 	  Enable this to support the Rockchip USB 2.0 PHY.
 
+config PHY_ROCKCHIP_DP
+	tristate "Rockchip Display Port PHY Driver"
+	depends on ARCH_ROCKCHIP && OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the Rockchip Display Port PHY.
+
 config PHY_ST_SPEAR1310_MIPHY
 	tristate "ST SPEAR1310-MIPHY driver"
 	select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a5b18c1..e281f35 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
 obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 0000000..3a2ac120
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,151 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#define GRF_SOC_CON12                   0x0274
+#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
+#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
+#define GRF_EDP_PHY_SIDDQ_ON            0
+#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
+
+struct rockchip_dp_phy {
+	struct device  *dev;
+	struct regmap  *grf;
+	struct clk     *phy_24m;
+};
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+	int ret;
+
+	if (enable) {
+		ret = clk_prepare_enable(dp->phy_24m);
+		if (ret < 0) {
+			dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
+			return ret;
+		}
+
+		ret = regmap_write(dp->grf, GRF_SOC_CON12,
+				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
+				   GRF_EDP_PHY_SIDDQ_ON);
+	} else {
+		clk_disable_unprepare(dp->phy_24m);
+		ret = regmap_write(dp->grf, GRF_SOC_CON12,
+				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
+				   GRF_EDP_PHY_SIDDQ_OFF);
+	}
+
+	return ret;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, false);
+}
+
+static const struct phy_ops rockchip_dp_phy_ops = {
+	.power_on	= rockchip_dp_phy_power_on,
+	.power_off	= rockchip_dp_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct phy_provider *phy_provider;
+	struct rockchip_dp_phy *dp;
+	struct resource *res;
+	struct phy *phy;
+	int ret;
+
+	if (!np)
+		return -ENODEV;
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (IS_ERR(dp))
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->phy_24m = devm_clk_get(dev, "24m");
+	if (IS_ERR(dp->phy_24m)) {
+		dev_err(dev, "cannot get clock 24m\n");
+		return PTR_ERR(dp->phy_24m);
+	}
+
+	ret = clk_set_rate(dp->phy_24m, 24000000);
+	if (ret < 0) {
+		dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+		return ret;
+	}
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
+			   (GRF_EDP_REF_CLK_SEL_INTER << 16));
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+		return ret;
+	}
+
+	phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
+	if (IS_ERR(phy)) {
+		dev_err(dev, "failed to create phy\n");
+		return PTR_ERR(phy);
+	}
+	phy_set_drvdata(phy, dp);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+	{ .compatible = "rockchip,rk3288-dp-phy" },
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+	.probe		= rockchip_dp_phy_probe,
+	.driver		= {
+		.name	= "rockchip-dp-phy",
+		.of_match_table = rockchip_dp_phy_dt_ids,
+	},
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY
@ 2015-10-10 15:55     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:55 UTC (permalink / raw)
  To: linux-arm-kernel

This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
  the exist "grf" syscon already. And rename the example DT node from
  "edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
  struct" to "static const struct". And correct the input paramters of
  devm_phy_create() interfaces. (Heiko)

Changes in v4:
- Add commit message, and remove the redundant rockchip_dp_phy_init()
  function, move those code to probe() method. And remove driver .owner
  number. (Kishon)

Changes in v3:
- Suggest, add rockchip dp phy driver, collect the phy clocks and
  power control. (Heiko)

Changes in v2: None

 drivers/phy/Kconfig           |   7 ++
 drivers/phy/Makefile          |   1 +
 drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 159 insertions(+)
 create mode 100644 drivers/phy/phy-rockchip-dp.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573..8f2bc4f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
 	help
 	  Enable this to support the Rockchip USB 2.0 PHY.
 
+config PHY_ROCKCHIP_DP
+	tristate "Rockchip Display Port PHY Driver"
+	depends on ARCH_ROCKCHIP && OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the Rockchip Display Port PHY.
+
 config PHY_ST_SPEAR1310_MIPHY
 	tristate "ST SPEAR1310-MIPHY driver"
 	select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a5b18c1..e281f35 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
 obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 0000000..3a2ac120
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,151 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#define GRF_SOC_CON12                   0x0274
+#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
+#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
+#define GRF_EDP_PHY_SIDDQ_ON            0
+#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
+
+struct rockchip_dp_phy {
+	struct device  *dev;
+	struct regmap  *grf;
+	struct clk     *phy_24m;
+};
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+	int ret;
+
+	if (enable) {
+		ret = clk_prepare_enable(dp->phy_24m);
+		if (ret < 0) {
+			dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
+			return ret;
+		}
+
+		ret = regmap_write(dp->grf, GRF_SOC_CON12,
+				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
+				   GRF_EDP_PHY_SIDDQ_ON);
+	} else {
+		clk_disable_unprepare(dp->phy_24m);
+		ret = regmap_write(dp->grf, GRF_SOC_CON12,
+				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
+				   GRF_EDP_PHY_SIDDQ_OFF);
+	}
+
+	return ret;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+	return rockchip_set_phy_state(phy, false);
+}
+
+static const struct phy_ops rockchip_dp_phy_ops = {
+	.power_on	= rockchip_dp_phy_power_on,
+	.power_off	= rockchip_dp_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct phy_provider *phy_provider;
+	struct rockchip_dp_phy *dp;
+	struct resource *res;
+	struct phy *phy;
+	int ret;
+
+	if (!np)
+		return -ENODEV;
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (IS_ERR(dp))
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->phy_24m = devm_clk_get(dev, "24m");
+	if (IS_ERR(dp->phy_24m)) {
+		dev_err(dev, "cannot get clock 24m\n");
+		return PTR_ERR(dp->phy_24m);
+	}
+
+	ret = clk_set_rate(dp->phy_24m, 24000000);
+	if (ret < 0) {
+		dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+		return ret;
+	}
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
+			   (GRF_EDP_REF_CLK_SEL_INTER << 16));
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+		return ret;
+	}
+
+	phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
+	if (IS_ERR(phy)) {
+		dev_err(dev, "failed to create phy\n");
+		return PTR_ERR(phy);
+	}
+	phy_set_drvdata(phy, dp);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+	{ .compatible = "rockchip,rk3288-dp-phy" },
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+	.probe		= rockchip_dp_phy_probe,
+	.driver		= {
+		.name	= "rockchip-dp-phy",
+		.of_match_table = rockchip_dp_phy_dt_ids,
+	},
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 15:58     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:58 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

This phy driver is binded with the Rockchip DisplayPort
driver, here are the brief properties:
	edp_phy: edp-phy@ff770274 {
		compatible = "rockchip,rk3288-dp-phy";
		rockchip,grf = <&grf>;
		clocks = <&cru SCLK_EDP_24M>;
		clock-names = "24m";
		#phy-cells = <0>;
	};

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
  elemets in document. (Rob & Heiko)

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../devicetree/bindings/phy/rockchip-dp-phy.txt    | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
new file mode 100644
index 0000000..505194e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
@@ -0,0 +1,22 @@
+Rockchip Soc Seroes Display Port PHY
+------------------------------------
+
+Required properties:
+- compatible : should be one of the following supported values:
+	 - "rockchip.rk3288-dp-phy"
+- clocks: from common clock binding: handle to dp clock.
+	of memory mapped region.
+- clock-names: from common clock binding:
+	Required elements: "24m"
+- rockchip,grf: phandle to the syscon managing the "general register files"
+- #phy-cells : from the generic PHY bindings, must be 0;
+
+Example:
+
+edp_phy: edp-phy@ff770274 {
+	compatible = "rockchip,rk3288-dp-phy";
+	rockchip,grf = <&grf>;
+	clocks = <&cru SCLK_EDP_24M>;
+	clock-names = "24m";
+	#phy-cells = <0>;
+};
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy
@ 2015-10-10 15:58     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 15:58 UTC (permalink / raw)
  To: linux-arm-kernel

This phy driver is binded with the Rockchip DisplayPort
driver, here are the brief properties:
	edp_phy: edp-phy at ff770274 {
		compatible = "rockchip,rk3288-dp-phy";
		rockchip,grf = <&grf>;
		clocks = <&cru SCLK_EDP_24M>;
		clock-names = "24m";
		#phy-cells = <0>;
	};

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
  elemets in document. (Rob & Heiko)

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../devicetree/bindings/phy/rockchip-dp-phy.txt    | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
new file mode 100644
index 0000000..505194e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
@@ -0,0 +1,22 @@
+Rockchip Soc Seroes Display Port PHY
+------------------------------------
+
+Required properties:
+- compatible : should be one of the following supported values:
+	 - "rockchip.rk3288-dp-phy"
+- clocks: from common clock binding: handle to dp clock.
+	of memory mapped region.
+- clock-names: from common clock binding:
+	Required elements: "24m"
+- rockchip,grf: phandle to the syscon managing the "general register files"
+- #phy-cells : from the generic PHY bindings, must be 0;
+
+Example:
+
+edp_phy: edp-phy at ff770274 {
+	compatible = "rockchip,rk3288-dp-phy";
+	rockchip,grf = <&grf>;
+	clocks = <&cru SCLK_EDP_24M>;
+	clock-names = "24m";
+	#phy-cells = <0>;
+};
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 12/17] drm: rockchip: vop: add bpc and color mode setting
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 16:00     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:00 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel, Mark Yao

From: Mark Yao <yzq@rock-chips.com>

Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.

Signed-off-by: Mark Yao <yzq@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Fix compiled error (Heiko)
- Using the connector display info message to configure eDP driver input
  video mode, but hard code CRTC video output mode to RGBaaa.

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 25 +++++++++++++++----
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 32 ++++++++++++++++++++++---
 4 files changed, 51 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 2c82a9a..3990951 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -180,14 +180,29 @@ static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
 static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct rockchip_dp_device *dp = to_dp(encoder);
+	struct drm_connector *cn = &dp->connector;
+	int ret = -1;
 	u32 val;
-	int ret;
 
-	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
-					    DRM_MODE_CONNECTOR_eDP,
-					    ROCKCHIP_OUT_MODE_AAAA);
+	/*
+	 * FIXME(Yakir): driver should configure the CRTC output video
+	 * mode with the display information which indicated the monitor
+	 * support colorimetry.
+	 *
+	 * But don't know why the CRTC driver seems could only output the
+	 * RGBaaa rightly. For example, if connect the "innolux,n116bge"
+	 * eDP screen, EDID would indicated that screen only accepted the
+	 * 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
+	 * screen would show a blue picture (RGB888 show a green picture).
+	 * But if I configure CTRC to RGBaaa, and eDP driver still keep
+	 * RGB666 input video mode, then screen would works prefect.
+	 */
+	if (cn->display_info.color_formats & DRM_COLOR_FORMAT_RGB444)
+		ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					DRM_MODE_CONNECTOR_eDP,
+					10, DRM_COLOR_FORMAT_RGB444);
 	if (ret < 0) {
-		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+		dev_err(dp->dev, "Could not set crtc mode config (%d)\n", ret);
 		return;
 	}
 
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 80d6fc8..428a3c1 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
 static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
 {
 	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
-				      ROCKCHIP_OUT_MODE_AAAA);
+				      10, DRM_COLOR_FORMAT_RGB444);
 }
 
 static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index dc4e5f0..ef1d7fb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe);
 int rockchip_drm_encoder_get_mux_id(struct device_node *node,
 				    struct drm_encoder *encoder);
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
-				  int out_mode);
+				  int bpc, int color);
 int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
 				   struct device *dev);
 void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e..9ef4a1f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1062,14 +1062,40 @@ static const struct drm_plane_funcs vop_plane_funcs = {
 
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
 				  int connector_type,
-				  int out_mode)
+				  int bpc, int color)
 {
 	struct vop *vop = to_vop(crtc);
 
+	/*
+	 * RK3288 vop only support RGB Color output.
+	 */
+	if (color != DRM_COLOR_FORMAT_RGB444) {
+		DRM_ERROR("Only support output RGB444, not support%d\n",
+			  color);
+		return -EINVAL;
+	}
+
 	vop->connector_type = connector_type;
-	vop->connector_out_mode = out_mode;
 
-	return 0;
+	/*
+	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
+	 * bpc, 5 or 6?
+	 */
+	if (bpc >= 10) {
+		bpc = 10;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
+	} else if (bpc >= 8) {
+		bpc = 8;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+	} else if (bpc >= 6) {
+		bpc = 6;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P666;
+	} else {
+		DRM_ERROR("unsupport bpc %d\n", bpc);
+		return -EINVAL;
+	}
+
+	return bpc;
 }
 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
 
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 12/17] drm: rockchip: vop: add bpc and color mode setting
@ 2015-10-10 16:00     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:00 UTC (permalink / raw)
  To: linux-arm-kernel

From: Mark Yao <yzq@rock-chips.com>

Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.

Signed-off-by: Mark Yao <yzq@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Fix compiled error (Heiko)
- Using the connector display info message to configure eDP driver input
  video mode, but hard code CRTC video output mode to RGBaaa.

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 25 +++++++++++++++----
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c     | 32 ++++++++++++++++++++++---
 4 files changed, 51 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 2c82a9a..3990951 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -180,14 +180,29 @@ static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
 static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct rockchip_dp_device *dp = to_dp(encoder);
+	struct drm_connector *cn = &dp->connector;
+	int ret = -1;
 	u32 val;
-	int ret;
 
-	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
-					    DRM_MODE_CONNECTOR_eDP,
-					    ROCKCHIP_OUT_MODE_AAAA);
+	/*
+	 * FIXME(Yakir): driver should configure the CRTC output video
+	 * mode with the display information which indicated the monitor
+	 * support colorimetry.
+	 *
+	 * But don't know why the CRTC driver seems could only output the
+	 * RGBaaa rightly. For example, if connect the "innolux,n116bge"
+	 * eDP screen, EDID would indicated that screen only accepted the
+	 * 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
+	 * screen would show a blue picture (RGB888 show a green picture).
+	 * But if I configure CTRC to RGBaaa, and eDP driver still keep
+	 * RGB666 input video mode, then screen would works prefect.
+	 */
+	if (cn->display_info.color_formats & DRM_COLOR_FORMAT_RGB444)
+		ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					DRM_MODE_CONNECTOR_eDP,
+					10, DRM_COLOR_FORMAT_RGB444);
 	if (ret < 0) {
-		dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+		dev_err(dp->dev, "Could not set crtc mode config (%d)\n", ret);
 		return;
 	}
 
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 80d6fc8..428a3c1 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
 static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
 {
 	rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
-				      ROCKCHIP_OUT_MODE_AAAA);
+				      10, DRM_COLOR_FORMAT_RGB444);
 }
 
 static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index dc4e5f0..ef1d7fb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe);
 int rockchip_drm_encoder_get_mux_id(struct device_node *node,
 				    struct drm_encoder *encoder);
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
-				  int out_mode);
+				  int bpc, int color);
 int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
 				   struct device *dev);
 void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e..9ef4a1f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1062,14 +1062,40 @@ static const struct drm_plane_funcs vop_plane_funcs = {
 
 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
 				  int connector_type,
-				  int out_mode)
+				  int bpc, int color)
 {
 	struct vop *vop = to_vop(crtc);
 
+	/*
+	 * RK3288 vop only support RGB Color output.
+	 */
+	if (color != DRM_COLOR_FORMAT_RGB444) {
+		DRM_ERROR("Only support output RGB444, not support%d\n",
+			  color);
+		return -EINVAL;
+	}
+
 	vop->connector_type = connector_type;
-	vop->connector_out_mode = out_mode;
 
-	return 0;
+	/*
+	 * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
+	 * bpc, 5 or 6?
+	 */
+	if (bpc >= 10) {
+		bpc = 10;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
+	} else if (bpc >= 8) {
+		bpc = 8;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+	} else if (bpc >= 6) {
+		bpc = 6;
+		vop->connector_out_mode = ROCKCHIP_OUT_MODE_P666;
+	} else {
+		DRM_ERROR("unsupport bpc %d\n", bpc);
+		return -EINVAL;
+	}
+
+	return bpc;
 }
 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
 
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting
@ 2015-10-10 16:05     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:05 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++++++++++++++---------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 ++++
 2 files changed, 60 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 861097a..21a3287 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -15,6 +15,8 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
+#include <drm/bridge/analogix_dp.h>
+
 #include "analogix_dp_core.h"
 #include "analogix_dp_reg.h"
 
@@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
 	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
 
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
+		writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
+		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
+		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
+		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
+	}
+
 	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
 
@@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable)
 {
 	u32 reg;
+	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		phy_pd_addr = ANALOGIX_DP_PD;
 
 	switch (block) {
 	case AUX_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH0_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH1_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH2_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH3_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case ANALOG_TOTAL:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case POWER_ALL:
 		if (enable) {
 			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(0x00, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	default:
@@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
-	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
+		      AUX_HW_RETRY_COUNT_SEL(3) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	else
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
+		      AUX_HW_RETRY_COUNT_SEL(0) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 738db4c..337912b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -22,6 +22,14 @@
 #define ANALOGIX_DP_VIDEO_CTL_8			0x3C
 #define ANALOGIX_DP_VIDEO_CTL_10		0x44
 
+#define ANALOGIX_DP_PLL_REG_1			0xfc
+#define ANALOGIX_DP_PLL_REG_2			0x9e4
+#define ANALOGIX_DP_PLL_REG_3			0x9e8
+#define ANALOGIX_DP_PLL_REG_4			0x9ec
+#define ANALOGIX_DP_PLL_REG_5			0xa00
+
+#define ANALOGIX_DP_PD				0x12c
+
 #define ANALOGIX_DP_LANE_MAP			0x35C
 
 #define ANALOGIX_DP_ANALOG_CTL_1		0x370
@@ -154,6 +162,10 @@
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
+/* ANALOGIX_DP_PLL_REG_1 */
+#define REF_CLK_24M				(0x1 << 1)
+#define REF_CLK_27M				(0x0 << 1)
+
 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting
@ 2015-10-10 16:05     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:05 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe-6d6DIl74uiNBDgjK7y7TUQ, Heiko Stuebner,
	Mark Yao
  Cc: Russell King, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	javier-JPH+aEBZ4P+UEJcrhfAQsw, Andy Yan, Yakir Yang,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++++++++++++++---------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 ++++
 2 files changed, 60 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 861097a..21a3287 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -15,6 +15,8 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
+#include <drm/bridge/analogix_dp.h>
+
 #include "analogix_dp_core.h"
 #include "analogix_dp_reg.h"
 
@@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
 	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
 
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
+		writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
+		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
+		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
+		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
+	}
+
 	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
 
@@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable)
 {
 	u32 reg;
+	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		phy_pd_addr = ANALOGIX_DP_PD;
 
 	switch (block) {
 	case AUX_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH0_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH1_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH2_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH3_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case ANALOG_TOTAL:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case POWER_ALL:
 		if (enable) {
 			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(0x00, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	default:
@@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
-	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
+		      AUX_HW_RETRY_COUNT_SEL(3) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	else
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
+		      AUX_HW_RETRY_COUNT_SEL(0) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 738db4c..337912b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -22,6 +22,14 @@
 #define ANALOGIX_DP_VIDEO_CTL_8			0x3C
 #define ANALOGIX_DP_VIDEO_CTL_10		0x44
 
+#define ANALOGIX_DP_PLL_REG_1			0xfc
+#define ANALOGIX_DP_PLL_REG_2			0x9e4
+#define ANALOGIX_DP_PLL_REG_3			0x9e8
+#define ANALOGIX_DP_PLL_REG_4			0x9ec
+#define ANALOGIX_DP_PLL_REG_5			0xa00
+
+#define ANALOGIX_DP_PD				0x12c
+
 #define ANALOGIX_DP_LANE_MAP			0x35C
 
 #define ANALOGIX_DP_ANALOG_CTL_1		0x370
@@ -154,6 +162,10 @@
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
+/* ANALOGIX_DP_PLL_REG_1 */
+#define REF_CLK_24M				(0x1 << 1)
+#define REF_CLK_27M				(0x0 << 1)
+
 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
-- 
1.9.1


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^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting
@ 2015-10-10 16:05     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:05 UTC (permalink / raw)
  To: linux-arm-kernel

RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++++++++++++++---------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 ++++
 2 files changed, 60 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 861097a..21a3287 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -15,6 +15,8 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
+#include <drm/bridge/analogix_dp.h>
+
 #include "analogix_dp_core.h"
 #include "analogix_dp_reg.h"
 
@@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
 	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
 
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
+		writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
+		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
+		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
+		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
+	}
+
 	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
 
@@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable)
 {
 	u32 reg;
+	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		phy_pd_addr = ANALOGIX_DP_PD;
 
 	switch (block) {
 	case AUX_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH0_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH1_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH2_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH3_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case ANALOG_TOTAL:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case POWER_ALL:
 		if (enable) {
 			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(0x00, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	default:
@@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
-	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
+		      AUX_HW_RETRY_COUNT_SEL(3) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	else
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
+		      AUX_HW_RETRY_COUNT_SEL(0) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 738db4c..337912b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -22,6 +22,14 @@
 #define ANALOGIX_DP_VIDEO_CTL_8			0x3C
 #define ANALOGIX_DP_VIDEO_CTL_10		0x44
 
+#define ANALOGIX_DP_PLL_REG_1			0xfc
+#define ANALOGIX_DP_PLL_REG_2			0x9e4
+#define ANALOGIX_DP_PLL_REG_3			0x9e8
+#define ANALOGIX_DP_PLL_REG_4			0x9ec
+#define ANALOGIX_DP_PLL_REG_5			0xa00
+
+#define ANALOGIX_DP_PD				0x12c
+
 #define ANALOGIX_DP_LANE_MAP			0x35C
 
 #define ANALOGIX_DP_ANALOG_CTL_1		0x370
@@ -154,6 +162,10 @@
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
+/* ANALOGIX_DP_PLL_REG_1 */
+#define REF_CLK_24M				(0x1 << 1)
+#define REF_CLK_27M				(0x0 << 1)
+
 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 16:05     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:05 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
  flag. (Thierry)

Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 33 ++++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  4 +--
 2 files changed, 23 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 9d802ef..2982dd0 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
-					 dp->video_info.link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
+					 dp->video_info.max_link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1156,16 +1156,25 @@ static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 	struct device_node *dp_node = dp->dev->of_node;
 	struct video_info *video_info = &dp->video_info;
 
-	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &video_info->link_rate)) {
-		dev_err(dp->dev, "failed to get link-rate\n");
-		return -EINVAL;
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &video_info->lane_count)) {
-		dev_err(dp->dev, "failed to get lane-count\n");
-		return -EINVAL;
+	switch (dp->plat_data && dp->plat_data->dev_type) {
+	case RK3288_DP:
+		/*
+		 * Like Rk3288 DisplayPort TRM indicate that "Main link
+		 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
+		 */
+		video_info->max_link_rate = 0x0A;
+		video_info->max_lane_count = 0x04;
+		break;
+	case EXYNOS_DP:
+		/*
+		 * NOTE: those property parseing code is used for
+		 * providing backward compatibility for samsung platform.
+		 */
+		of_property_read_u32(dp_node, "samsung,link-rate",
+				     &video_info->max_link_rate);
+		of_property_read_u32(dp_node, "samsung,lane-count",
+				     &video_info->max_lane_count);
+		break;
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 730486d..f4cb799 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -129,8 +129,8 @@ struct video_info {
 	enum color_coefficient ycbcr_coeff;
 	enum color_depth color_depth;
 
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
+	enum link_rate_type max_link_rate;
+	enum link_lane_count_type max_lane_count;
 };
 
 struct link_train {
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
@ 2015-10-10 16:05     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:05 UTC (permalink / raw)
  To: linux-arm-kernel

There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
  flag. (Thierry)

Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 33 ++++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  4 +--
 2 files changed, 23 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 9d802ef..2982dd0 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
-					 dp->video_info.link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
+					 dp->video_info.max_link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1156,16 +1156,25 @@ static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 	struct device_node *dp_node = dp->dev->of_node;
 	struct video_info *video_info = &dp->video_info;
 
-	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &video_info->link_rate)) {
-		dev_err(dp->dev, "failed to get link-rate\n");
-		return -EINVAL;
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &video_info->lane_count)) {
-		dev_err(dp->dev, "failed to get lane-count\n");
-		return -EINVAL;
+	switch (dp->plat_data && dp->plat_data->dev_type) {
+	case RK3288_DP:
+		/*
+		 * Like Rk3288 DisplayPort TRM indicate that "Main link
+		 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
+		 */
+		video_info->max_link_rate = 0x0A;
+		video_info->max_lane_count = 0x04;
+		break;
+	case EXYNOS_DP:
+		/*
+		 * NOTE: those property parseing code is used for
+		 * providing backward compatibility for samsung platform.
+		 */
+		of_property_read_u32(dp_node, "samsung,link-rate",
+				     &video_info->max_link_rate);
+		of_property_read_u32(dp_node, "samsung,lane-count",
+				     &video_info->max_lane_count);
+		break;
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 730486d..f4cb799 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -129,8 +129,8 @@ struct video_info {
 	enum color_coefficient ycbcr_coeff;
 	enum color_depth color_depth;
 
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
+	enum link_rate_type max_link_rate;
+	enum link_lane_count_type max_lane_count;
 };
 
 struct link_train {
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 16:05     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:05 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.

This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.

Changes in v2: None

 .../devicetree/bindings/drm/bridge/analogix_dp.txt |  4 ++-
 .../bindings/video/analogix_dp-rockchip.txt        |  1 +
 .../devicetree/bindings/video/exynos_dp.txt        |  1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
 6 files changed, 47 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
index f54dc3e..c310367 100644
--- a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -22,6 +22,9 @@ Required properties for dp-controller:
 		from general PHY binding: Should be "dp".
 
 Optional properties for dp-controller:
+	-analogix,need-force-hpd:
+		Indicate driver need force hpd when hpd detect failed, this
+		is used for some eDP screen which don't have hpd signal.
 	-hpd-gpios:
 		Hotplug detect GPIO.
 		Indicates which GPIO should be used for hotplug detection
@@ -31,7 +34,6 @@ Optional properties for dp-controller:
 		* Documentation/devicetree/bindings/video/exynos_dp.txt
 		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 
-
 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
 -------------------------------------------------------------------------------
 
diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
index ec93917..be18388 100644
--- a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -31,6 +31,7 @@ For the below properties, please refer to Analogix DP binding document:
 - phys (required)
 - phy-names (required)
 - hpd-gpios (optional)
+- analogix,need-force-hpd (optional)
 -------------------------------------------------------------------------------
 
 Example:
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index ea03b3a..4f06e80 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
 	-phys (required)
 	-phy-names (required)
 	-hpd-gpios (optional)
+	-analogix,need-force-hpd (optional)
 	-video interfaces (optional)
 
 Deprecated properties for DisplayPort:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 2982dd0..322015e 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -59,15 +59,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (analogix_dp_get_plug_in_status(dp) != 0) {
+	while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
+		if (analogix_dp_get_plug_in_status(dp) == 0)
+			return 0;
+
 		timeout_loop++;
-		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
-			dev_err(dp->dev, "failed to get hpd plug status\n");
-			return -ETIMEDOUT;
-		}
 		usleep_range(10, 11);
 	}
 
+	/*
+	 * Some edp screen do not have hpd signal, so we can't just
+	 * return failed when hpd plug in detect failed, DT property
+	 * "need-force-hpd" would indicate whether driver need this.
+	 */
+	if (!dp->need_force_hpd)
+		return -ETIMEDOUT;
+
+	/*
+	 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
+	 * will not work, so we need to give a force hpd action to
+	 * set HPD_STATUS manually.
+	 */
+	dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
+
+	analogix_dp_force_hpd(dp);
+
+	if (analogix_dp_get_plug_in_status(dp) != 0) {
+		dev_err(dp->dev, "failed to get hpd plug in status\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
+
 	return 0;
 }
 
@@ -1244,6 +1267,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
+	dp->need_force_hpd =
+		of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
+
 	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
 	if (!gpio_is_valid(dp->hpd_gpio))
 		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index f4cb799..3a136b8 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -160,6 +160,7 @@ struct analogix_dp_device {
 	struct phy		*phy;
 	int			dpms_mode;
 	int			hpd_gpio;
+	bool                    need_force_hpd;
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable);
 void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
 void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+void analogix_dp_force_hpd(struct analogix_dp_device *dp);
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
 void analogix_dp_reset_aux(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 21a3287..c7e2959 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 }
 
+void analogix_dp_force_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg = (F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
 {
 	u32 reg;
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
@ 2015-10-10 16:05     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:05 UTC (permalink / raw)
  To: linux-arm-kernel

Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.

This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.

Changes in v2: None

 .../devicetree/bindings/drm/bridge/analogix_dp.txt |  4 ++-
 .../bindings/video/analogix_dp-rockchip.txt        |  1 +
 .../devicetree/bindings/video/exynos_dp.txt        |  1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
 6 files changed, 47 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
index f54dc3e..c310367 100644
--- a/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+++ b/Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
@@ -22,6 +22,9 @@ Required properties for dp-controller:
 		from general PHY binding: Should be "dp".
 
 Optional properties for dp-controller:
+	-analogix,need-force-hpd:
+		Indicate driver need force hpd when hpd detect failed, this
+		is used for some eDP screen which don't have hpd signal.
 	-hpd-gpios:
 		Hotplug detect GPIO.
 		Indicates which GPIO should be used for hotplug detection
@@ -31,7 +34,6 @@ Optional properties for dp-controller:
 		* Documentation/devicetree/bindings/video/exynos_dp.txt
 		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 
-
 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
 -------------------------------------------------------------------------------
 
diff --git a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
index ec93917..be18388 100644
--- a/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+++ b/Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
@@ -31,6 +31,7 @@ For the below properties, please refer to Analogix DP binding document:
 - phys (required)
 - phy-names (required)
 - hpd-gpios (optional)
+- analogix,need-force-hpd (optional)
 -------------------------------------------------------------------------------
 
 Example:
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index ea03b3a..4f06e80 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
 	-phys (required)
 	-phy-names (required)
 	-hpd-gpios (optional)
+	-analogix,need-force-hpd (optional)
 	-video interfaces (optional)
 
 Deprecated properties for DisplayPort:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 2982dd0..322015e 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -59,15 +59,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (analogix_dp_get_plug_in_status(dp) != 0) {
+	while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
+		if (analogix_dp_get_plug_in_status(dp) == 0)
+			return 0;
+
 		timeout_loop++;
-		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
-			dev_err(dp->dev, "failed to get hpd plug status\n");
-			return -ETIMEDOUT;
-		}
 		usleep_range(10, 11);
 	}
 
+	/*
+	 * Some edp screen do not have hpd signal, so we can't just
+	 * return failed when hpd plug in detect failed, DT property
+	 * "need-force-hpd" would indicate whether driver need this.
+	 */
+	if (!dp->need_force_hpd)
+		return -ETIMEDOUT;
+
+	/*
+	 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
+	 * will not work, so we need to give a force hpd action to
+	 * set HPD_STATUS manually.
+	 */
+	dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
+
+	analogix_dp_force_hpd(dp);
+
+	if (analogix_dp_get_plug_in_status(dp) != 0) {
+		dev_err(dp->dev, "failed to get hpd plug in status\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
+
 	return 0;
 }
 
@@ -1244,6 +1267,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
+	dp->need_force_hpd =
+		of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
+
 	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
 	if (!gpio_is_valid(dp->hpd_gpio))
 		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index f4cb799..3a136b8 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -160,6 +160,7 @@ struct analogix_dp_device {
 	struct phy		*phy;
 	int			dpms_mode;
 	int			hpd_gpio;
+	bool                    need_force_hpd;
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable);
 void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
 void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+void analogix_dp_force_hpd(struct analogix_dp_device *dp);
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
 void analogix_dp_reset_aux(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 21a3287..c7e2959 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 }
 
+void analogix_dp_force_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg = (F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
 {
 	u32 reg;
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 16:05     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:05 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit messages.

Changes in v3:
- move dp hpd detect to connector detect function.

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 322015e..a83b159 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_detect_hpd(dp);
-	if (ret) {
-		/* Cable has been disconnected, we're done */
-		return;
-	}
-
 	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
@@ -941,6 +935,11 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 
 enum drm_connector_status analogix_dp_detect(struct device *dev, bool force)
 {
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+
+	if (analogix_dp_detect_hpd(dp))
+		return connector_status_disconnected;
+
 	return connector_status_connected;
 }
 EXPORT_SYMBOL_GPL(analogix_dp_detect);
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function
@ 2015-10-10 16:05     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:05 UTC (permalink / raw)
  To: linux-arm-kernel

This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit messages.

Changes in v3:
- move dp hpd detect to connector detect function.

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 322015e..a83b159 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_detect_hpd(dp);
-	if (ret) {
-		/* Cable has been disconnected, we're done */
-		return;
-	}
-
 	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
@@ -941,6 +935,11 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 
 enum drm_connector_status analogix_dp_detect(struct device *dev, bool force)
 {
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+
+	if (analogix_dp_detect_hpd(dp))
+		return connector_status_disconnected;
+
 	return connector_status_connected;
 }
 EXPORT_SYMBOL_GPL(analogix_dp_detect);
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-10 16:06     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:06 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Add edid modes parse support

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 24 +++++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 46 +++++++++++-----------
 2 files changed, 40 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index a83b159..bcbc009 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -107,7 +107,7 @@ static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 
 static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
-	unsigned char edid[EDID_BLOCK_LENGTH * 2];
+	unsigned char *edid = dp->edid;
 	unsigned int extend_block = 0;
 	unsigned char sum;
 	unsigned char test_vector;
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_handle_edid(dp);
-	if (ret) {
-		dev_err(dp->dev, "unable to handle edid\n");
-		return;
-	}
-
 	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
 					 dp->video_info.max_link_rate);
 	if (ret) {
@@ -947,8 +941,24 @@ EXPORT_SYMBOL_GPL(analogix_dp_detect);
 int analogix_dp_get_modes(struct device *dev)
 {
 	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+	struct edid *edid = (struct edid *)dp->edid;
 	int num_modes = 0;
 
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
+			DRM_ERROR("failed to setup the panel\n");
+			return -EINVAL;
+		}
+	}
+
+	if (analogix_dp_handle_edid(dp)) {
+		dev_err(dp->dev, "unable to handle edid\n");
+		return -EINVAL;
+	}
+
+	drm_mode_connector_update_edid_property(dp->connector, edid);
+	num_modes += drm_add_edid_modes(dp->connector, edid);
+
 	if (dp->plat_data->panel)
 		num_modes += drm_panel_get_modes(dp->plat_data->panel);
 
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 3a136b8..089489d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,28 @@
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
 
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
 enum link_rate_type {
 	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
 	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
@@ -161,6 +183,7 @@ struct analogix_dp_device {
 	int			dpms_mode;
 	int			hpd_gpio;
 	bool                    need_force_hpd;
+	unsigned char           edid[EDID_BLOCK_LENGTH * 2];
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -260,27 +283,4 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
 #endif /* _ANALOGIX_DP_CORE_H */
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v6 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method
@ 2015-10-10 16:06     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-10 16:06 UTC (permalink / raw)
  To: linux-arm-kernel

Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Add edid modes parse support

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 24 +++++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 46 +++++++++++-----------
 2 files changed, 40 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index a83b159..bcbc009 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -107,7 +107,7 @@ static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 
 static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
-	unsigned char edid[EDID_BLOCK_LENGTH * 2];
+	unsigned char *edid = dp->edid;
 	unsigned int extend_block = 0;
 	unsigned char sum;
 	unsigned char test_vector;
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_handle_edid(dp);
-	if (ret) {
-		dev_err(dp->dev, "unable to handle edid\n");
-		return;
-	}
-
 	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
 					 dp->video_info.max_link_rate);
 	if (ret) {
@@ -947,8 +941,24 @@ EXPORT_SYMBOL_GPL(analogix_dp_detect);
 int analogix_dp_get_modes(struct device *dev)
 {
 	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+	struct edid *edid = (struct edid *)dp->edid;
 	int num_modes = 0;
 
+	if (dp->plat_data && dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
+			DRM_ERROR("failed to setup the panel\n");
+			return -EINVAL;
+		}
+	}
+
+	if (analogix_dp_handle_edid(dp)) {
+		dev_err(dp->dev, "unable to handle edid\n");
+		return -EINVAL;
+	}
+
+	drm_mode_connector_update_edid_property(dp->connector, edid);
+	num_modes += drm_add_edid_modes(dp->connector, edid);
+
 	if (dp->plat_data->panel)
 		num_modes += drm_panel_get_modes(dp->plat_data->panel);
 
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 3a136b8..089489d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,28 @@
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
 
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
 enum link_rate_type {
 	LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
 	LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
@@ -161,6 +183,7 @@ struct analogix_dp_device {
 	int			dpms_mode;
 	int			hpd_gpio;
 	bool                    need_force_hpd;
+	unsigned char           edid[EDID_BLOCK_LENGTH * 2];
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -260,27 +283,4 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
 #endif /* _ANALOGIX_DP_CORE_H */
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  2015-10-10 15:46     ` Yakir Yang
@ 2015-10-12  0:37       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-12  0:37 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hi Krzysztof,

On 10/10/2015 11:46 PM, Yakir Yang wrote:
> Both hsync/vsync polarity and interlace mode can be parsed from
> drm display mode, and dynamic_range and ycbcr_coeff can be judge
> by the video code.
>
> But presumably Exynos still relies on the DT properties, so take
> good use of mode_fixup() in to achieve the compatibility hacks.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v6: None

+	of_property_read_u32(dp_node, "hsync-active-high",
+			     &video->h_sync_polarity);
+	of_property_read_u32(dp_node, "vsync-active-high",
+			     &video->v_sync_polarity);
+	of_property_read_u32(dp_node, "interlaced",
+			     &video->interlaced);
+}


Sorry, forget to fix your previous comment here, would
remember to fix it to v7 version, wish v6 would collect
more comment/reviewed/ack.  :)

Best regards,
- Yakir

> Changes in v5:
> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>    to get the backword timing values. Krzysztof suggest me that driver could use
>    the "of_property_read_bool" to get backword timing values, but that interfacs
>    would modify the original drm_display_mode timing directly (whether those
>    properties exists or not).
>
> Changes in v4:
> - Provide backword compatibility with samsung. (Krzysztof)
>
> Changes in v3:
> - Dynamic parse video timing info from struct drm_display_mode and
>    struct drm_display_info. (Thierry)
>
> Changes in v2: None
>
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   8 +-
>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>   3 files changed, 106 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index 96afb67..9d802ef 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
>   		return;
>   	}
>   
> -	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
> -					 dp->video_info->link_rate);
> +	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
> +					 dp->video_info.link_rate);
>   	if (ret) {
>   		dev_err(dp->dev, "unable to do link train\n");
>   		return;
> @@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
>   	dp->dpms_mode = DRM_MODE_DPMS_OFF;
>   }
>   
> +static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
> +					struct drm_display_mode *orig_mode,
> +					struct drm_display_mode *mode)
> +{
> +	struct analogix_dp_device *dp = bridge->driver_private;
> +	struct drm_display_info *display_info = &dp->connector->display_info;
> +	struct video_info *video = &dp->video_info;
> +	struct device_node *dp_node = dp->dev->of_node;
> +	int vic;
> +
> +	/* Input video interlaces & hsync pol & vsync pol */
> +	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
> +	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
> +	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
> +
> +	/* Input video dynamic_range & colorimetry */
> +	vic = drm_match_cea_mode(mode);
> +	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
> +	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
> +		video->dynamic_range = CEA;
> +		video->ycbcr_coeff = COLOR_YCBCR601;
> +	} else if (vic) {
> +		video->dynamic_range = CEA;
> +		video->ycbcr_coeff = COLOR_YCBCR709;
> +	} else {
> +		video->dynamic_range = VESA;
> +		video->ycbcr_coeff = COLOR_YCBCR709;
> +	}
> +
> +	/* Input vide bpc and color_formats */
> +	switch (display_info->bpc) {
> +	case 12:
> +		video->color_depth = COLOR_12;
> +		break;
> +	case 10:
> +		video->color_depth = COLOR_10;
> +		break;
> +	case 8:
> +		video->color_depth = COLOR_8;
> +		break;
> +	case 6:
> +		video->color_depth = COLOR_6;
> +		break;
> +	default:
> +		video->color_depth = COLOR_8;
> +		break;
> +	}
> +	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
> +		video->color_space = COLOR_YCBCR444;
> +	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
> +		video->color_space = COLOR_YCBCR422;
> +	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
> +		video->color_space = COLOR_RGB;
> +	else
> +		video->color_space = COLOR_RGB;
> +
> +	/*
> +	 * NOTE: those property parsing code is used for providing backward
> +	 * compatibility for samsung platform.
> +	 * Due to we used the "of_property_read_u32" interfaces, when this
> +	 * property isn't present, the "video_info" can keep the original
> +	 * values and wouldn't be modified.
> +	 */
> +	of_property_read_u32(dp_node, "samsung,color-space",
> +			     &video->color_space);
> +	of_property_read_u32(dp_node, "samsung,dynamic-range",
> +			     &video->dynamic_range);
> +	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> +			     &video->ycbcr_coeff);
> +	of_property_read_u32(dp_node, "samsung,color-depth",
> +			     &video->color_depth);
> +	of_property_read_u32(dp_node, "hsync-active-high",
> +			     &video->h_sync_polarity);
> +	of_property_read_u32(dp_node, "vsync-active-high",
> +			     &video->v_sync_polarity);
> +	of_property_read_u32(dp_node, "interlaced",
> +			     &video->interlaced);
> +}
> +
>   static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
>   {
>   	/* do nothing */
> @@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
>   	.disable = analogix_dp_bridge_disable,
>   	.pre_enable = analogix_dp_bridge_nop,
>   	.post_disable = analogix_dp_bridge_nop,
> +	.mode_set = analogix_dp_bridge_mode_set,
>   	.attach = analogix_dp_bridge_attach,
>   };
>   
> @@ -1071,62 +1151,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>   	return 0;
>   }
>   
> -static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
> +static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
>   {
> -	struct device_node *dp_node = dev->of_node;
> -	struct video_info *dp_video_config;
> -
> -	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
> -				       GFP_KERNEL);
> -	if (!dp_video_config)
> -		return ERR_PTR(-ENOMEM);
> -
> -	dp_video_config->h_sync_polarity =
> -		of_property_read_bool(dp_node, "hsync-active-high");
> -
> -	dp_video_config->v_sync_polarity =
> -		of_property_read_bool(dp_node, "vsync-active-high");
> -
> -	dp_video_config->interlaced =
> -		of_property_read_bool(dp_node, "interlaced");
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-space",
> -				 &dp_video_config->color_space)) {
> -		dev_err(dev, "failed to get color-space\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
> -				 &dp_video_config->dynamic_range)) {
> -		dev_err(dev, "failed to get dynamic-range\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> -				 &dp_video_config->ycbcr_coeff)) {
> -		dev_err(dev, "failed to get ycbcr-coeff\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-depth",
> -				 &dp_video_config->color_depth)) {
> -		dev_err(dev, "failed to get color-depth\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> +	struct device_node *dp_node = dp->dev->of_node;
> +	struct video_info *video_info = &dp->video_info;
>   
>   	if (of_property_read_u32(dp_node, "samsung,link-rate",
> -				 &dp_video_config->link_rate)) {
> -		dev_err(dev, "failed to get link-rate\n");
> -		return ERR_PTR(-EINVAL);
> +				 &video_info->link_rate)) {
> +		dev_err(dp->dev, "failed to get link-rate\n");
> +		return -EINVAL;
>   	}
>   
>   	if (of_property_read_u32(dp_node, "samsung,lane-count",
> -				 &dp_video_config->lane_count)) {
> -		dev_err(dev, "failed to get lane-count\n");
> -		return ERR_PTR(-EINVAL);
> +				 &video_info->lane_count)) {
> +		dev_err(dp->dev, "failed to get lane-count\n");
> +		return -EINVAL;
>   	}
>   
> -	return dp_video_config;
> +	return 0;
>   }
>   
>   int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
> @@ -1159,9 +1201,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>   	 */
>   	dp->plat_data = plat_data;
>   
> -	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
> -	if (IS_ERR(dp->video_info))
> -		return PTR_ERR(dp->video_info);
> +	ret = analogix_dp_dt_parse_pdata(dp);
> +	if (ret)
> +		return ret;
>   
>   	dp->phy = devm_phy_get(dp->dev, "dp");
>   	if (IS_ERR(dp->phy)) {
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> index 9a90a18..730486d 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> @@ -120,9 +120,9 @@ enum dp_irq_type {
>   struct video_info {
>   	char *name;
>   
> -	bool h_sync_polarity;
> -	bool v_sync_polarity;
> -	bool interlaced;
> +	u32 h_sync_polarity;
> +	u32 v_sync_polarity;
> +	u32 interlaced;
>   
>   	enum color_space color_space;
>   	enum dynamic_range dynamic_range;
> @@ -154,7 +154,7 @@ struct analogix_dp_device {
>   	unsigned int		irq;
>   	void __iomem		*reg_base;
>   
> -	struct video_info	*video_info;
> +	struct video_info	video_info;
>   	struct link_train	link_train;
>   	struct work_struct	hotplug_work;
>   	struct phy		*phy;
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index a388c0a..861097a 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
>   	u32 reg;
>   
>   	/* Configure the input color depth, color space, dynamic range */
> -	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
> -		(dp->video_info->color_depth << IN_BPC_SHIFT) |
> -		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
> +	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
> +		(dp->video_info.color_depth << IN_BPC_SHIFT) |
> +		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
>   
>   	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>   	reg &= ~IN_YC_COEFFI_MASK;
> -	if (dp->video_info->ycbcr_coeff)
> +	if (dp->video_info.ycbcr_coeff)
>   		reg |= IN_YC_COEFFI_ITU709;
>   	else
>   		reg |= IN_YC_COEFFI_ITU601;
> @@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
>   
>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>   	reg &= ~INTERACE_SCAN_CFG;
> -	reg |= (dp->video_info->interlaced << 2);
> +	reg |= (dp->video_info.interlaced << 2);
>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>   
>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>   	reg &= ~VSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->v_sync_polarity << 1);
> +	reg |= (dp->video_info.v_sync_polarity << 1);
>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>   
>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>   	reg &= ~HSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->h_sync_polarity << 0);
> +	reg |= (dp->video_info.h_sync_polarity << 0);
>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>   
>   	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  0:37       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-12  0:37 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Krzysztof,

On 10/10/2015 11:46 PM, Yakir Yang wrote:
> Both hsync/vsync polarity and interlace mode can be parsed from
> drm display mode, and dynamic_range and ycbcr_coeff can be judge
> by the video code.
>
> But presumably Exynos still relies on the DT properties, so take
> good use of mode_fixup() in to achieve the compatibility hacks.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v6: None

+	of_property_read_u32(dp_node, "hsync-active-high",
+			     &video->h_sync_polarity);
+	of_property_read_u32(dp_node, "vsync-active-high",
+			     &video->v_sync_polarity);
+	of_property_read_u32(dp_node, "interlaced",
+			     &video->interlaced);
+}


Sorry, forget to fix your previous comment here, would
remember to fix it to v7 version, wish v6 would collect
more comment/reviewed/ack.  :)

Best regards,
- Yakir

> Changes in v5:
> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>    to get the backword timing values. Krzysztof suggest me that driver could use
>    the "of_property_read_bool" to get backword timing values, but that interfacs
>    would modify the original drm_display_mode timing directly (whether those
>    properties exists or not).
>
> Changes in v4:
> - Provide backword compatibility with samsung. (Krzysztof)
>
> Changes in v3:
> - Dynamic parse video timing info from struct drm_display_mode and
>    struct drm_display_info. (Thierry)
>
> Changes in v2: None
>
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   8 +-
>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>   3 files changed, 106 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index 96afb67..9d802ef 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
>   		return;
>   	}
>   
> -	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
> -					 dp->video_info->link_rate);
> +	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
> +					 dp->video_info.link_rate);
>   	if (ret) {
>   		dev_err(dp->dev, "unable to do link train\n");
>   		return;
> @@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
>   	dp->dpms_mode = DRM_MODE_DPMS_OFF;
>   }
>   
> +static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
> +					struct drm_display_mode *orig_mode,
> +					struct drm_display_mode *mode)
> +{
> +	struct analogix_dp_device *dp = bridge->driver_private;
> +	struct drm_display_info *display_info = &dp->connector->display_info;
> +	struct video_info *video = &dp->video_info;
> +	struct device_node *dp_node = dp->dev->of_node;
> +	int vic;
> +
> +	/* Input video interlaces & hsync pol & vsync pol */
> +	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
> +	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
> +	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
> +
> +	/* Input video dynamic_range & colorimetry */
> +	vic = drm_match_cea_mode(mode);
> +	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
> +	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
> +		video->dynamic_range = CEA;
> +		video->ycbcr_coeff = COLOR_YCBCR601;
> +	} else if (vic) {
> +		video->dynamic_range = CEA;
> +		video->ycbcr_coeff = COLOR_YCBCR709;
> +	} else {
> +		video->dynamic_range = VESA;
> +		video->ycbcr_coeff = COLOR_YCBCR709;
> +	}
> +
> +	/* Input vide bpc and color_formats */
> +	switch (display_info->bpc) {
> +	case 12:
> +		video->color_depth = COLOR_12;
> +		break;
> +	case 10:
> +		video->color_depth = COLOR_10;
> +		break;
> +	case 8:
> +		video->color_depth = COLOR_8;
> +		break;
> +	case 6:
> +		video->color_depth = COLOR_6;
> +		break;
> +	default:
> +		video->color_depth = COLOR_8;
> +		break;
> +	}
> +	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
> +		video->color_space = COLOR_YCBCR444;
> +	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
> +		video->color_space = COLOR_YCBCR422;
> +	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
> +		video->color_space = COLOR_RGB;
> +	else
> +		video->color_space = COLOR_RGB;
> +
> +	/*
> +	 * NOTE: those property parsing code is used for providing backward
> +	 * compatibility for samsung platform.
> +	 * Due to we used the "of_property_read_u32" interfaces, when this
> +	 * property isn't present, the "video_info" can keep the original
> +	 * values and wouldn't be modified.
> +	 */
> +	of_property_read_u32(dp_node, "samsung,color-space",
> +			     &video->color_space);
> +	of_property_read_u32(dp_node, "samsung,dynamic-range",
> +			     &video->dynamic_range);
> +	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> +			     &video->ycbcr_coeff);
> +	of_property_read_u32(dp_node, "samsung,color-depth",
> +			     &video->color_depth);
> +	of_property_read_u32(dp_node, "hsync-active-high",
> +			     &video->h_sync_polarity);
> +	of_property_read_u32(dp_node, "vsync-active-high",
> +			     &video->v_sync_polarity);
> +	of_property_read_u32(dp_node, "interlaced",
> +			     &video->interlaced);
> +}
> +
>   static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
>   {
>   	/* do nothing */
> @@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
>   	.disable = analogix_dp_bridge_disable,
>   	.pre_enable = analogix_dp_bridge_nop,
>   	.post_disable = analogix_dp_bridge_nop,
> +	.mode_set = analogix_dp_bridge_mode_set,
>   	.attach = analogix_dp_bridge_attach,
>   };
>   
> @@ -1071,62 +1151,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>   	return 0;
>   }
>   
> -static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
> +static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
>   {
> -	struct device_node *dp_node = dev->of_node;
> -	struct video_info *dp_video_config;
> -
> -	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
> -				       GFP_KERNEL);
> -	if (!dp_video_config)
> -		return ERR_PTR(-ENOMEM);
> -
> -	dp_video_config->h_sync_polarity =
> -		of_property_read_bool(dp_node, "hsync-active-high");
> -
> -	dp_video_config->v_sync_polarity =
> -		of_property_read_bool(dp_node, "vsync-active-high");
> -
> -	dp_video_config->interlaced =
> -		of_property_read_bool(dp_node, "interlaced");
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-space",
> -				 &dp_video_config->color_space)) {
> -		dev_err(dev, "failed to get color-space\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
> -				 &dp_video_config->dynamic_range)) {
> -		dev_err(dev, "failed to get dynamic-range\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> -				 &dp_video_config->ycbcr_coeff)) {
> -		dev_err(dev, "failed to get ycbcr-coeff\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-depth",
> -				 &dp_video_config->color_depth)) {
> -		dev_err(dev, "failed to get color-depth\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> +	struct device_node *dp_node = dp->dev->of_node;
> +	struct video_info *video_info = &dp->video_info;
>   
>   	if (of_property_read_u32(dp_node, "samsung,link-rate",
> -				 &dp_video_config->link_rate)) {
> -		dev_err(dev, "failed to get link-rate\n");
> -		return ERR_PTR(-EINVAL);
> +				 &video_info->link_rate)) {
> +		dev_err(dp->dev, "failed to get link-rate\n");
> +		return -EINVAL;
>   	}
>   
>   	if (of_property_read_u32(dp_node, "samsung,lane-count",
> -				 &dp_video_config->lane_count)) {
> -		dev_err(dev, "failed to get lane-count\n");
> -		return ERR_PTR(-EINVAL);
> +				 &video_info->lane_count)) {
> +		dev_err(dp->dev, "failed to get lane-count\n");
> +		return -EINVAL;
>   	}
>   
> -	return dp_video_config;
> +	return 0;
>   }
>   
>   int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
> @@ -1159,9 +1201,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>   	 */
>   	dp->plat_data = plat_data;
>   
> -	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
> -	if (IS_ERR(dp->video_info))
> -		return PTR_ERR(dp->video_info);
> +	ret = analogix_dp_dt_parse_pdata(dp);
> +	if (ret)
> +		return ret;
>   
>   	dp->phy = devm_phy_get(dp->dev, "dp");
>   	if (IS_ERR(dp->phy)) {
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> index 9a90a18..730486d 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> @@ -120,9 +120,9 @@ enum dp_irq_type {
>   struct video_info {
>   	char *name;
>   
> -	bool h_sync_polarity;
> -	bool v_sync_polarity;
> -	bool interlaced;
> +	u32 h_sync_polarity;
> +	u32 v_sync_polarity;
> +	u32 interlaced;
>   
>   	enum color_space color_space;
>   	enum dynamic_range dynamic_range;
> @@ -154,7 +154,7 @@ struct analogix_dp_device {
>   	unsigned int		irq;
>   	void __iomem		*reg_base;
>   
> -	struct video_info	*video_info;
> +	struct video_info	video_info;
>   	struct link_train	link_train;
>   	struct work_struct	hotplug_work;
>   	struct phy		*phy;
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index a388c0a..861097a 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
>   	u32 reg;
>   
>   	/* Configure the input color depth, color space, dynamic range */
> -	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
> -		(dp->video_info->color_depth << IN_BPC_SHIFT) |
> -		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
> +	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
> +		(dp->video_info.color_depth << IN_BPC_SHIFT) |
> +		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
>   
>   	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>   	reg &= ~IN_YC_COEFFI_MASK;
> -	if (dp->video_info->ycbcr_coeff)
> +	if (dp->video_info.ycbcr_coeff)
>   		reg |= IN_YC_COEFFI_ITU709;
>   	else
>   		reg |= IN_YC_COEFFI_ITU601;
> @@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
>   
>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>   	reg &= ~INTERACE_SCAN_CFG;
> -	reg |= (dp->video_info->interlaced << 2);
> +	reg |= (dp->video_info.interlaced << 2);
>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>   
>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>   	reg &= ~VSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->v_sync_polarity << 1);
> +	reg |= (dp->video_info.v_sync_polarity << 1);
>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>   
>   	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>   	reg &= ~HSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->h_sync_polarity << 0);
> +	reg |= (dp->video_info.h_sync_polarity << 0);
>   	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
>   
>   	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  0:49         ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-10-12  0:49 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

On 12.10.2015 09:37, Yakir Yang wrote:
> Hi Krzysztof,
> 
> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code.
>>
>> But presumably Exynos still relies on the DT properties, so take
>> good use of mode_fixup() in to achieve the compatibility hacks.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v6: None
> 
> +    of_property_read_u32(dp_node, "hsync-active-high",
> +                 &video->h_sync_polarity);
> +    of_property_read_u32(dp_node, "vsync-active-high",
> +                 &video->v_sync_polarity);
> +    of_property_read_u32(dp_node, "interlaced",
> +                 &video->interlaced);
> +}
> 
> 
> Sorry, forget to fix your previous comment here, would
> remember to fix it to v7 version, wish v6 would collect
> more comment/reviewed/ack.  :)

Right.

You can send a v7 of only this patch.

In the same time I would prefer not to chain-reply next version of
entire patchset to cover letter of previous version. It confuses me
because v6 appears UNDER v4 so I can't really find v6. I see v4 at the
top of my email list.

In the same time the patchset is quite big. Put the latest version (with
this issue above fixed!) on some repo and link it in cover letter.

Best regards,
Krzysztof

> 
> Best regards,
> - Yakir
> 
>> Changes in v5:
>> - Switch video timing type to "u32", so driver could use
>> "of_property_read_u32"
>>    to get the backword timing values. Krzysztof suggest me that driver
>> could use
>>    the "of_property_read_bool" to get backword timing values, but that
>> interfacs
>>    would modify the original drm_display_mode timing directly (whether
>> those
>>    properties exists or not).
>>
>> Changes in v4:
>> - Provide backword compatibility with samsung. (Krzysztof)
>>
>> Changes in v3:
>> - Dynamic parse video timing info from struct drm_display_mode and
>>    struct drm_display_info. (Thierry)
>>
>> Changes in v2: None


^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  0:49         ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-10-12  0:49 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Rob Herring, joe-6d6DIl74uiNBDgjK7y7TUQ, Heiko Stuebner,
	Mark Yao
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Russell King,
	Pawel Moll, Ian Campbell, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w,
	dianders-F7+t8E8rja9g9hUCZPvPmw, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	Kishon Vijay Abraham I, javier-JPH+aEBZ4P+UEJcrhfAQsw,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	Sean Paul, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	Kumar Gala, ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan, Gustavo Padovan,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

On 12.10.2015 09:37, Yakir Yang wrote:
> Hi Krzysztof,
> 
> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code.
>>
>> But presumably Exynos still relies on the DT properties, so take
>> good use of mode_fixup() in to achieve the compatibility hacks.
>>
>> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>> Changes in v6: None
> 
> +    of_property_read_u32(dp_node, "hsync-active-high",
> +                 &video->h_sync_polarity);
> +    of_property_read_u32(dp_node, "vsync-active-high",
> +                 &video->v_sync_polarity);
> +    of_property_read_u32(dp_node, "interlaced",
> +                 &video->interlaced);
> +}
> 
> 
> Sorry, forget to fix your previous comment here, would
> remember to fix it to v7 version, wish v6 would collect
> more comment/reviewed/ack.  :)

Right.

You can send a v7 of only this patch.

In the same time I would prefer not to chain-reply next version of
entire patchset to cover letter of previous version. It confuses me
because v6 appears UNDER v4 so I can't really find v6. I see v4 at the
top of my email list.

In the same time the patchset is quite big. Put the latest version (with
this issue above fixed!) on some repo and link it in cover letter.

Best regards,
Krzysztof

> 
> Best regards,
> - Yakir
> 
>> Changes in v5:
>> - Switch video timing type to "u32", so driver could use
>> "of_property_read_u32"
>>    to get the backword timing values. Krzysztof suggest me that driver
>> could use
>>    the "of_property_read_bool" to get backword timing values, but that
>> interfacs
>>    would modify the original drm_display_mode timing directly (whether
>> those
>>    properties exists or not).
>>
>> Changes in v4:
>> - Provide backword compatibility with samsung. (Krzysztof)
>>
>> Changes in v3:
>> - Dynamic parse video timing info from struct drm_display_mode and
>>    struct drm_display_info. (Thierry)
>>
>> Changes in v2: None

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  0:49         ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-10-12  0:49 UTC (permalink / raw)
  To: linux-arm-kernel

On 12.10.2015 09:37, Yakir Yang wrote:
> Hi Krzysztof,
> 
> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code.
>>
>> But presumably Exynos still relies on the DT properties, so take
>> good use of mode_fixup() in to achieve the compatibility hacks.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v6: None
> 
> +    of_property_read_u32(dp_node, "hsync-active-high",
> +                 &video->h_sync_polarity);
> +    of_property_read_u32(dp_node, "vsync-active-high",
> +                 &video->v_sync_polarity);
> +    of_property_read_u32(dp_node, "interlaced",
> +                 &video->interlaced);
> +}
> 
> 
> Sorry, forget to fix your previous comment here, would
> remember to fix it to v7 version, wish v6 would collect
> more comment/reviewed/ack.  :)

Right.

You can send a v7 of only this patch.

In the same time I would prefer not to chain-reply next version of
entire patchset to cover letter of previous version. It confuses me
because v6 appears UNDER v4 so I can't really find v6. I see v4 at the
top of my email list.

In the same time the patchset is quite big. Put the latest version (with
this issue above fixed!) on some repo and link it in cover letter.

Best regards,
Krzysztof

> 
> Best regards,
> - Yakir
> 
>> Changes in v5:
>> - Switch video timing type to "u32", so driver could use
>> "of_property_read_u32"
>>    to get the backword timing values. Krzysztof suggest me that driver
>> could use
>>    the "of_property_read_bool" to get backword timing values, but that
>> interfacs
>>    would modify the original drm_display_mode timing directly (whether
>> those
>>    properties exists or not).
>>
>> Changes in v4:
>> - Provide backword compatibility with samsung. (Krzysztof)
>>
>> Changes in v3:
>> - Dynamic parse video timing info from struct drm_display_mode and
>>    struct drm_display_info. (Thierry)
>>
>> Changes in v2: None

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  2015-10-12  0:49         ` Krzysztof Kozlowski
@ 2015-10-12  2:43           ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-12  2:43 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel



On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
> On 12.10.2015 09:37, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>> by the video code.
>>>
>>> But presumably Exynos still relies on the DT properties, so take
>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>
>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>> ---
>>> Changes in v6: None
>> +    of_property_read_u32(dp_node, "hsync-active-high",
>> +                 &video->h_sync_polarity);
>> +    of_property_read_u32(dp_node, "vsync-active-high",
>> +                 &video->v_sync_polarity);
>> +    of_property_read_u32(dp_node, "interlaced",
>> +                 &video->interlaced);
>> +}
>>
>>
>> Sorry, forget to fix your previous comment here, would
>> remember to fix it to v7 version, wish v6 would collect
>> more comment/reviewed/ack.  :)
> Right.
>
> You can send a v7 of only this patch.
>
> In the same time I would prefer not to chain-reply next version of
> entire patchset to cover letter of previous version. It confuses me
> because v6 appears UNDER v4 so I can't really find v6. I see v4 at the
> top of my email list.

Okay, I wish this chain-reply would make people easy to find the
previous comments, but actually it is little mess now. I would give
up this way to send patchset  :)

> In the same time the patchset is quite big. Put the latest version (with
> this issue above fixed!) on some repo and link it in cover letter.

Yeah, it's quite big now, I would like to back the patchset to previous
format, like:

---> [PATCH v6 00/17] Cover letter
   |----> [PATCH v6 01/17]
   |----> [PATCH ......]
   |----> [PATCH v6 05/17]
      |----> [PATCH v7 05/17]
   |----> [PATCH ......]
   |----> [PATCH v6 17/17]

Is it right, and can resend the v6 to fix this chain-reply issue with
RESEND flag ([PATCH RESEND v6 ...]) ?

---> [PATCH RESEND v6 00/17] Cover letter
   |----> [PATCH RESEND v6 01/17]
   |----> [PATCH ......]
   |----> [PATCH RESEND v6 05/17]
      |----> [PATCH v7 05/17]
   |----> [PATCH ......]
   |----> [PATCH RESEND v6 17/17]


Thanks :-)
- Yakir

>
> Best regards,
> Krzysztof
>
>> Best regards,
>> - Yakir
>>
>>> Changes in v5:
>>> - Switch video timing type to "u32", so driver could use
>>> "of_property_read_u32"
>>>     to get the backword timing values. Krzysztof suggest me that driver
>>> could use
>>>     the "of_property_read_bool" to get backword timing values, but that
>>> interfacs
>>>     would modify the original drm_display_mode timing directly (whether
>>> those
>>>     properties exists or not).
>>>
>>> Changes in v4:
>>> - Provide backword compatibility with samsung. (Krzysztof)
>>>
>>> Changes in v3:
>>> - Dynamic parse video timing info from struct drm_display_mode and
>>>     struct drm_display_info. (Thierry)
>>>
>>> Changes in v2: None
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  2:43           ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-12  2:43 UTC (permalink / raw)
  To: linux-arm-kernel



On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
> On 12.10.2015 09:37, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>> by the video code.
>>>
>>> But presumably Exynos still relies on the DT properties, so take
>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>
>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>> ---
>>> Changes in v6: None
>> +    of_property_read_u32(dp_node, "hsync-active-high",
>> +                 &video->h_sync_polarity);
>> +    of_property_read_u32(dp_node, "vsync-active-high",
>> +                 &video->v_sync_polarity);
>> +    of_property_read_u32(dp_node, "interlaced",
>> +                 &video->interlaced);
>> +}
>>
>>
>> Sorry, forget to fix your previous comment here, would
>> remember to fix it to v7 version, wish v6 would collect
>> more comment/reviewed/ack.  :)
> Right.
>
> You can send a v7 of only this patch.
>
> In the same time I would prefer not to chain-reply next version of
> entire patchset to cover letter of previous version. It confuses me
> because v6 appears UNDER v4 so I can't really find v6. I see v4 at the
> top of my email list.

Okay, I wish this chain-reply would make people easy to find the
previous comments, but actually it is little mess now. I would give
up this way to send patchset  :)

> In the same time the patchset is quite big. Put the latest version (with
> this issue above fixed!) on some repo and link it in cover letter.

Yeah, it's quite big now, I would like to back the patchset to previous
format, like:

---> [PATCH v6 00/17] Cover letter
   |----> [PATCH v6 01/17]
   |----> [PATCH ......]
   |----> [PATCH v6 05/17]
      |----> [PATCH v7 05/17]
   |----> [PATCH ......]
   |----> [PATCH v6 17/17]

Is it right, and can resend the v6 to fix this chain-reply issue with
RESEND flag ([PATCH RESEND v6 ...]) ?

---> [PATCH RESEND v6 00/17] Cover letter
   |----> [PATCH RESEND v6 01/17]
   |----> [PATCH ......]
   |----> [PATCH RESEND v6 05/17]
      |----> [PATCH v7 05/17]
   |----> [PATCH ......]
   |----> [PATCH RESEND v6 17/17]


Thanks :-)
- Yakir

>
> Best regards,
> Krzysztof
>
>> Best regards,
>> - Yakir
>>
>>> Changes in v5:
>>> - Switch video timing type to "u32", so driver could use
>>> "of_property_read_u32"
>>>     to get the backword timing values. Krzysztof suggest me that driver
>>> could use
>>>     the "of_property_read_bool" to get backword timing values, but that
>>> interfacs
>>>     would modify the original drm_display_mode timing directly (whether
>>> those
>>>     properties exists or not).
>>>
>>> Changes in v4:
>>> - Provide backword compatibility with samsung. (Krzysztof)
>>>
>>> Changes in v3:
>>> - Dynamic parse video timing info from struct drm_display_mode and
>>>     struct drm_display_info. (Thierry)
>>>
>>> Changes in v2: None
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  2015-10-12  2:43           ` Yakir Yang
@ 2015-10-12  3:51             ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-10-12  3:51 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

On 12.10.2015 11:43, Yakir Yang wrote:
> 
> 
> On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
>> On 12.10.2015 09:37, Yakir Yang wrote:
>>> Hi Krzysztof,
>>>
>>> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>> by the video code.
>>>>
>>>> But presumably Exynos still relies on the DT properties, so take
>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>
>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>> ---
>>>> Changes in v6: None
>>> +    of_property_read_u32(dp_node, "hsync-active-high",
>>> +                 &video->h_sync_polarity);
>>> +    of_property_read_u32(dp_node, "vsync-active-high",
>>> +                 &video->v_sync_polarity);
>>> +    of_property_read_u32(dp_node, "interlaced",
>>> +                 &video->interlaced);
>>> +}
>>>
>>>
>>> Sorry, forget to fix your previous comment here, would
>>> remember to fix it to v7 version, wish v6 would collect
>>> more comment/reviewed/ack.  :)
>> Right.
>>
>> You can send a v7 of only this patch.
>>
>> In the same time I would prefer not to chain-reply next version of
>> entire patchset to cover letter of previous version. It confuses me
>> because v6 appears UNDER v4 so I can't really find v6. I see v4 at the
>> top of my email list.
> 
> Okay, I wish this chain-reply would make people easy to find the
> previous comments, but actually it is little mess now. I would give
> up this way to send patchset  :)
> 
>> In the same time the patchset is quite big. Put the latest version (with
>> this issue above fixed!) on some repo and link it in cover letter.
> 
> Yeah, it's quite big now, I would like to back the patchset to previous
> format, like:
> 
> ---> [PATCH v6 00/17] Cover letter
>   |----> [PATCH v6 01/17]
>   |----> [PATCH ......]
>   |----> [PATCH v6 05/17]
>      |----> [PATCH v7 05/17]
>   |----> [PATCH ......]
>   |----> [PATCH v6 17/17]
> 
> Is it right, and can resend the v6 to fix this chain-reply issue with
> RESEND flag ([PATCH RESEND v6 ...]) ?
> 
> ---> [PATCH RESEND v6 00/17] Cover letter
>   |----> [PATCH RESEND v6 01/17]
>   |----> [PATCH ......]
>   |----> [PATCH RESEND v6 05/17]
>      |----> [PATCH v7 05/17]
>   |----> [PATCH ......]
>   |----> [PATCH RESEND v6 17/17]
> 

No, don't resend everything. I mean in this case with such big patchset
if you want to fix one patch just send one email [PATCH v7 05/17]
chained to proper id (cover letter or v6-05/17). Add a short note that
this is resend of only one patch from the set.

Of course you can just wait for some more comments and then send v7 of
everything.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  3:51             ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-10-12  3:51 UTC (permalink / raw)
  To: linux-arm-kernel

On 12.10.2015 11:43, Yakir Yang wrote:
> 
> 
> On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
>> On 12.10.2015 09:37, Yakir Yang wrote:
>>> Hi Krzysztof,
>>>
>>> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>> by the video code.
>>>>
>>>> But presumably Exynos still relies on the DT properties, so take
>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>
>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>> ---
>>>> Changes in v6: None
>>> +    of_property_read_u32(dp_node, "hsync-active-high",
>>> +                 &video->h_sync_polarity);
>>> +    of_property_read_u32(dp_node, "vsync-active-high",
>>> +                 &video->v_sync_polarity);
>>> +    of_property_read_u32(dp_node, "interlaced",
>>> +                 &video->interlaced);
>>> +}
>>>
>>>
>>> Sorry, forget to fix your previous comment here, would
>>> remember to fix it to v7 version, wish v6 would collect
>>> more comment/reviewed/ack.  :)
>> Right.
>>
>> You can send a v7 of only this patch.
>>
>> In the same time I would prefer not to chain-reply next version of
>> entire patchset to cover letter of previous version. It confuses me
>> because v6 appears UNDER v4 so I can't really find v6. I see v4 at the
>> top of my email list.
> 
> Okay, I wish this chain-reply would make people easy to find the
> previous comments, but actually it is little mess now. I would give
> up this way to send patchset  :)
> 
>> In the same time the patchset is quite big. Put the latest version (with
>> this issue above fixed!) on some repo and link it in cover letter.
> 
> Yeah, it's quite big now, I would like to back the patchset to previous
> format, like:
> 
> ---> [PATCH v6 00/17] Cover letter
>   |----> [PATCH v6 01/17]
>   |----> [PATCH ......]
>   |----> [PATCH v6 05/17]
>      |----> [PATCH v7 05/17]
>   |----> [PATCH ......]
>   |----> [PATCH v6 17/17]
> 
> Is it right, and can resend the v6 to fix this chain-reply issue with
> RESEND flag ([PATCH RESEND v6 ...]) ?
> 
> ---> [PATCH RESEND v6 00/17] Cover letter
>   |----> [PATCH RESEND v6 01/17]
>   |----> [PATCH ......]
>   |----> [PATCH RESEND v6 05/17]
>      |----> [PATCH v7 05/17]
>   |----> [PATCH ......]
>   |----> [PATCH RESEND v6 17/17]
> 

No, don't resend everything. I mean in this case with such big patchset
if you want to fix one patch just send one email [PATCH v7 05/17]
chained to proper id (cover letter or v6-05/17). Add a short note that
this is resend of only one patch from the set.

Of course you can just wait for some more comments and then send v7 of
everything.

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  4:09               ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-12  4:09 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel



On 10/12/2015 11:51 AM, Krzysztof Kozlowski wrote:
> On 12.10.2015 11:43, Yakir Yang wrote:
>> On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
>>> On 12.10.2015 09:37, Yakir Yang wrote:
>>>> Hi Krzysztof,
>>>>
>>>> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>>> by the video code.
>>>>>
>>>>> But presumably Exynos still relies on the DT properties, so take
>>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>>
>>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>>> ---
>>>>> Changes in v6: None
>>>> +    of_property_read_u32(dp_node, "hsync-active-high",
>>>> +                 &video->h_sync_polarity);
>>>> +    of_property_read_u32(dp_node, "vsync-active-high",
>>>> +                 &video->v_sync_polarity);
>>>> +    of_property_read_u32(dp_node, "interlaced",
>>>> +                 &video->interlaced);
>>>> +}
>>>>
>>>>
>>>> Sorry, forget to fix your previous comment here, would
>>>> remember to fix it to v7 version, wish v6 would collect
>>>> more comment/reviewed/ack.  :)
>>> Right.
>>>
>>> You can send a v7 of only this patch.
>>>
>>> In the same time I would prefer not to chain-reply next version of
>>> entire patchset to cover letter of previous version. It confuses me
>>> because v6 appears UNDER v4 so I can't really find v6. I see v4 at the
>>> top of my email list.
>> Okay, I wish this chain-reply would make people easy to find the
>> previous comments, but actually it is little mess now. I would give
>> up this way to send patchset  :)
>>
>>> In the same time the patchset is quite big. Put the latest version (with
>>> this issue above fixed!) on some repo and link it in cover letter.
>> Yeah, it's quite big now, I would like to back the patchset to previous
>> format, like:
>>
>> ---> [PATCH v6 00/17] Cover letter
>>    |----> [PATCH v6 01/17]
>>    |----> [PATCH ......]
>>    |----> [PATCH v6 05/17]
>>       |----> [PATCH v7 05/17]
>>    |----> [PATCH ......]
>>    |----> [PATCH v6 17/17]
>>
>> Is it right, and can resend the v6 to fix this chain-reply issue with
>> RESEND flag ([PATCH RESEND v6 ...]) ?
>>
>> ---> [PATCH RESEND v6 00/17] Cover letter
>>    |----> [PATCH RESEND v6 01/17]
>>    |----> [PATCH ......]
>>    |----> [PATCH RESEND v6 05/17]
>>       |----> [PATCH v7 05/17]
>>    |----> [PATCH ......]
>>    |----> [PATCH RESEND v6 17/17]
>>
> No, don't resend everything. I mean in this case with such big patchset
> if you want to fix one patch just send one email [PATCH v7 05/17]
> chained to proper id (cover letter or v6-05/17). Add a short note that
> this is resend of only one patch from the set.

Oh, understand now, just keep this chain-reply no changes for now.

----> [PATCH v4 00/16] Cover letter
    |----> [PATCH v5 00/17] Covert letter
    |----> [PATCH ......]
    |
    |----> [PATCH v6 00/17] Covert letter
    |----> [PATCH v6 01/17]
    |----> [PATCH ......]
    |----> [PATCH v6 17/17]
    |----> [PATCH v7 05/17]


> Of course you can just wait for some more comments and then send v7 of
> everything.

I would choice to send it now :)

Thanks,
- Yakir

> Best regards,
> Krzysztof
>
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  4:09               ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-12  4:09 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Rob Herring, joe-6d6DIl74uiNBDgjK7y7TUQ, Heiko Stuebner,
	Mark Yao
  Cc: Russell King, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	javier-JPH+aEBZ4P+UEJcrhfAQsw, Andy Yan,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r



On 10/12/2015 11:51 AM, Krzysztof Kozlowski wrote:
> On 12.10.2015 11:43, Yakir Yang wrote:
>> On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
>>> On 12.10.2015 09:37, Yakir Yang wrote:
>>>> Hi Krzysztof,
>>>>
>>>> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>>> by the video code.
>>>>>
>>>>> But presumably Exynos still relies on the DT properties, so take
>>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>>
>>>>> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>>>>> ---
>>>>> Changes in v6: None
>>>> +    of_property_read_u32(dp_node, "hsync-active-high",
>>>> +                 &video->h_sync_polarity);
>>>> +    of_property_read_u32(dp_node, "vsync-active-high",
>>>> +                 &video->v_sync_polarity);
>>>> +    of_property_read_u32(dp_node, "interlaced",
>>>> +                 &video->interlaced);
>>>> +}
>>>>
>>>>
>>>> Sorry, forget to fix your previous comment here, would
>>>> remember to fix it to v7 version, wish v6 would collect
>>>> more comment/reviewed/ack.  :)
>>> Right.
>>>
>>> You can send a v7 of only this patch.
>>>
>>> In the same time I would prefer not to chain-reply next version of
>>> entire patchset to cover letter of previous version. It confuses me
>>> because v6 appears UNDER v4 so I can't really find v6. I see v4 at the
>>> top of my email list.
>> Okay, I wish this chain-reply would make people easy to find the
>> previous comments, but actually it is little mess now. I would give
>> up this way to send patchset  :)
>>
>>> In the same time the patchset is quite big. Put the latest version (with
>>> this issue above fixed!) on some repo and link it in cover letter.
>> Yeah, it's quite big now, I would like to back the patchset to previous
>> format, like:
>>
>> ---> [PATCH v6 00/17] Cover letter
>>    |----> [PATCH v6 01/17]
>>    |----> [PATCH ......]
>>    |----> [PATCH v6 05/17]
>>       |----> [PATCH v7 05/17]
>>    |----> [PATCH ......]
>>    |----> [PATCH v6 17/17]
>>
>> Is it right, and can resend the v6 to fix this chain-reply issue with
>> RESEND flag ([PATCH RESEND v6 ...]) ?
>>
>> ---> [PATCH RESEND v6 00/17] Cover letter
>>    |----> [PATCH RESEND v6 01/17]
>>    |----> [PATCH ......]
>>    |----> [PATCH RESEND v6 05/17]
>>       |----> [PATCH v7 05/17]
>>    |----> [PATCH ......]
>>    |----> [PATCH RESEND v6 17/17]
>>
> No, don't resend everything. I mean in this case with such big patchset
> if you want to fix one patch just send one email [PATCH v7 05/17]
> chained to proper id (cover letter or v6-05/17). Add a short note that
> this is resend of only one patch from the set.

Oh, understand now, just keep this chain-reply no changes for now.

----> [PATCH v4 00/16] Cover letter
    |----> [PATCH v5 00/17] Covert letter
    |----> [PATCH ......]
    |
    |----> [PATCH v6 00/17] Covert letter
    |----> [PATCH v6 01/17]
    |----> [PATCH ......]
    |----> [PATCH v6 17/17]
    |----> [PATCH v7 05/17]


> Of course you can just wait for some more comments and then send v7 of
> everything.

I would choice to send it now :)

Thanks,
- Yakir

> Best regards,
> Krzysztof
>
>
>
>


--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  4:09               ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-12  4:09 UTC (permalink / raw)
  To: linux-arm-kernel



On 10/12/2015 11:51 AM, Krzysztof Kozlowski wrote:
> On 12.10.2015 11:43, Yakir Yang wrote:
>> On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
>>> On 12.10.2015 09:37, Yakir Yang wrote:
>>>> Hi Krzysztof,
>>>>
>>>> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>>> by the video code.
>>>>>
>>>>> But presumably Exynos still relies on the DT properties, so take
>>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>>
>>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>>> ---
>>>>> Changes in v6: None
>>>> +    of_property_read_u32(dp_node, "hsync-active-high",
>>>> +                 &video->h_sync_polarity);
>>>> +    of_property_read_u32(dp_node, "vsync-active-high",
>>>> +                 &video->v_sync_polarity);
>>>> +    of_property_read_u32(dp_node, "interlaced",
>>>> +                 &video->interlaced);
>>>> +}
>>>>
>>>>
>>>> Sorry, forget to fix your previous comment here, would
>>>> remember to fix it to v7 version, wish v6 would collect
>>>> more comment/reviewed/ack.  :)
>>> Right.
>>>
>>> You can send a v7 of only this patch.
>>>
>>> In the same time I would prefer not to chain-reply next version of
>>> entire patchset to cover letter of previous version. It confuses me
>>> because v6 appears UNDER v4 so I can't really find v6. I see v4 at the
>>> top of my email list.
>> Okay, I wish this chain-reply would make people easy to find the
>> previous comments, but actually it is little mess now. I would give
>> up this way to send patchset  :)
>>
>>> In the same time the patchset is quite big. Put the latest version (with
>>> this issue above fixed!) on some repo and link it in cover letter.
>> Yeah, it's quite big now, I would like to back the patchset to previous
>> format, like:
>>
>> ---> [PATCH v6 00/17] Cover letter
>>    |----> [PATCH v6 01/17]
>>    |----> [PATCH ......]
>>    |----> [PATCH v6 05/17]
>>       |----> [PATCH v7 05/17]
>>    |----> [PATCH ......]
>>    |----> [PATCH v6 17/17]
>>
>> Is it right, and can resend the v6 to fix this chain-reply issue with
>> RESEND flag ([PATCH RESEND v6 ...]) ?
>>
>> ---> [PATCH RESEND v6 00/17] Cover letter
>>    |----> [PATCH RESEND v6 01/17]
>>    |----> [PATCH ......]
>>    |----> [PATCH RESEND v6 05/17]
>>       |----> [PATCH v7 05/17]
>>    |----> [PATCH ......]
>>    |----> [PATCH RESEND v6 17/17]
>>
> No, don't resend everything. I mean in this case with such big patchset
> if you want to fix one patch just send one email [PATCH v7 05/17]
> chained to proper id (cover letter or v6-05/17). Add a short note that
> this is resend of only one patch from the set.

Oh, understand now, just keep this chain-reply no changes for now.

----> [PATCH v4 00/16] Cover letter
    |----> [PATCH v5 00/17] Covert letter
    |----> [PATCH ......]
    |
    |----> [PATCH v6 00/17] Covert letter
    |----> [PATCH v6 01/17]
    |----> [PATCH ......]
    |----> [PATCH v6 17/17]
    |----> [PATCH v7 05/17]


> Of course you can just wait for some more comments and then send v7 of
> everything.

I would choice to send it now :)

Thanks,
- Yakir

> Best regards,
> Krzysztof
>
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  2015-10-12  4:09               ` Yakir Yang
@ 2015-10-12  4:16                 ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-10-12  4:16 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

On 12.10.2015 13:09, Yakir Yang wrote:
> 
> 
> On 10/12/2015 11:51 AM, Krzysztof Kozlowski wrote:
>> On 12.10.2015 11:43, Yakir Yang wrote:
>>> On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
>>>> On 12.10.2015 09:37, Yakir Yang wrote:
>>>>> Hi Krzysztof,
>>>>>
>>>>> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>>>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>>>> by the video code.
>>>>>>
>>>>>> But presumably Exynos still relies on the DT properties, so take
>>>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>>>
>>>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>>>> ---
>>>>>> Changes in v6: None
>>>>> +    of_property_read_u32(dp_node, "hsync-active-high",
>>>>> +                 &video->h_sync_polarity);
>>>>> +    of_property_read_u32(dp_node, "vsync-active-high",
>>>>> +                 &video->v_sync_polarity);
>>>>> +    of_property_read_u32(dp_node, "interlaced",
>>>>> +                 &video->interlaced);
>>>>> +}
>>>>>
>>>>>
>>>>> Sorry, forget to fix your previous comment here, would
>>>>> remember to fix it to v7 version, wish v6 would collect
>>>>> more comment/reviewed/ack.  :)
>>>> Right.
>>>>
>>>> You can send a v7 of only this patch.
>>>>
>>>> In the same time I would prefer not to chain-reply next version of
>>>> entire patchset to cover letter of previous version. It confuses me
>>>> because v6 appears UNDER v4 so I can't really find v6. I see v4 at the
>>>> top of my email list.
>>> Okay, I wish this chain-reply would make people easy to find the
>>> previous comments, but actually it is little mess now. I would give
>>> up this way to send patchset  :)
>>>
>>>> In the same time the patchset is quite big. Put the latest version
>>>> (with
>>>> this issue above fixed!) on some repo and link it in cover letter.
>>> Yeah, it's quite big now, I would like to back the patchset to previous
>>> format, like:
>>>
>>> ---> [PATCH v6 00/17] Cover letter
>>>    |----> [PATCH v6 01/17]
>>>    |----> [PATCH ......]
>>>    |----> [PATCH v6 05/17]
>>>       |----> [PATCH v7 05/17]
>>>    |----> [PATCH ......]
>>>    |----> [PATCH v6 17/17]
>>>
>>> Is it right, and can resend the v6 to fix this chain-reply issue with
>>> RESEND flag ([PATCH RESEND v6 ...]) ?
>>>
>>> ---> [PATCH RESEND v6 00/17] Cover letter
>>>    |----> [PATCH RESEND v6 01/17]
>>>    |----> [PATCH ......]
>>>    |----> [PATCH RESEND v6 05/17]
>>>       |----> [PATCH v7 05/17]
>>>    |----> [PATCH ......]
>>>    |----> [PATCH RESEND v6 17/17]
>>>
>> No, don't resend everything. I mean in this case with such big patchset
>> if you want to fix one patch just send one email [PATCH v7 05/17]
>> chained to proper id (cover letter or v6-05/17). Add a short note that
>> this is resend of only one patch from the set.
> 
> Oh, understand now, just keep this chain-reply no changes for now.
> 
> ----> [PATCH v4 00/16] Cover letter
>    |----> [PATCH v5 00/17] Covert letter
>    |----> [PATCH ......]
>    |
>    |----> [PATCH v6 00/17] Covert letter
>    |----> [PATCH v6 01/17]
>    |----> [PATCH ......]
>    |----> [PATCH v6 17/17]
>    |----> [PATCH v7 05/17]

Yes, I think it is correct. Maybe just add a note (in patch changelog)
that this is v7 of only fifth patch.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  4:16                 ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-10-12  4:16 UTC (permalink / raw)
  To: linux-arm-kernel

On 12.10.2015 13:09, Yakir Yang wrote:
> 
> 
> On 10/12/2015 11:51 AM, Krzysztof Kozlowski wrote:
>> On 12.10.2015 11:43, Yakir Yang wrote:
>>> On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
>>>> On 12.10.2015 09:37, Yakir Yang wrote:
>>>>> Hi Krzysztof,
>>>>>
>>>>> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>>>>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>>>>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>>>>>> by the video code.
>>>>>>
>>>>>> But presumably Exynos still relies on the DT properties, so take
>>>>>> good use of mode_fixup() in to achieve the compatibility hacks.
>>>>>>
>>>>>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>>>>>> ---
>>>>>> Changes in v6: None
>>>>> +    of_property_read_u32(dp_node, "hsync-active-high",
>>>>> +                 &video->h_sync_polarity);
>>>>> +    of_property_read_u32(dp_node, "vsync-active-high",
>>>>> +                 &video->v_sync_polarity);
>>>>> +    of_property_read_u32(dp_node, "interlaced",
>>>>> +                 &video->interlaced);
>>>>> +}
>>>>>
>>>>>
>>>>> Sorry, forget to fix your previous comment here, would
>>>>> remember to fix it to v7 version, wish v6 would collect
>>>>> more comment/reviewed/ack.  :)
>>>> Right.
>>>>
>>>> You can send a v7 of only this patch.
>>>>
>>>> In the same time I would prefer not to chain-reply next version of
>>>> entire patchset to cover letter of previous version. It confuses me
>>>> because v6 appears UNDER v4 so I can't really find v6. I see v4 at the
>>>> top of my email list.
>>> Okay, I wish this chain-reply would make people easy to find the
>>> previous comments, but actually it is little mess now. I would give
>>> up this way to send patchset  :)
>>>
>>>> In the same time the patchset is quite big. Put the latest version
>>>> (with
>>>> this issue above fixed!) on some repo and link it in cover letter.
>>> Yeah, it's quite big now, I would like to back the patchset to previous
>>> format, like:
>>>
>>> ---> [PATCH v6 00/17] Cover letter
>>>    |----> [PATCH v6 01/17]
>>>    |----> [PATCH ......]
>>>    |----> [PATCH v6 05/17]
>>>       |----> [PATCH v7 05/17]
>>>    |----> [PATCH ......]
>>>    |----> [PATCH v6 17/17]
>>>
>>> Is it right, and can resend the v6 to fix this chain-reply issue with
>>> RESEND flag ([PATCH RESEND v6 ...]) ?
>>>
>>> ---> [PATCH RESEND v6 00/17] Cover letter
>>>    |----> [PATCH RESEND v6 01/17]
>>>    |----> [PATCH ......]
>>>    |----> [PATCH RESEND v6 05/17]
>>>       |----> [PATCH v7 05/17]
>>>    |----> [PATCH ......]
>>>    |----> [PATCH RESEND v6 17/17]
>>>
>> No, don't resend everything. I mean in this case with such big patchset
>> if you want to fix one patch just send one email [PATCH v7 05/17]
>> chained to proper id (cover letter or v6-05/17). Add a short note that
>> this is resend of only one patch from the set.
> 
> Oh, understand now, just keep this chain-reply no changes for now.
> 
> ----> [PATCH v4 00/16] Cover letter
>    |----> [PATCH v5 00/17] Covert letter
>    |----> [PATCH ......]
>    |
>    |----> [PATCH v6 00/17] Covert letter
>    |----> [PATCH v6 01/17]
>    |----> [PATCH ......]
>    |----> [PATCH v6 17/17]
>    |----> [PATCH v7 05/17]

Yes, I think it is correct. Maybe just add a note (in patch changelog)
that this is v7 of only fifth patch.

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  2015-10-10 15:35   ` Yakir Yang
@ 2015-10-12  4:29     ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-12  4:29 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.

But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
*just add a note that this is v7 of only fifth patch.*

Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
  compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
  to avoid -EOVERFLOW error (Krzysztof)

Changes in v6: None
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).

Changes in v4:
- Provide backword compatibility with samsung. (Krzysztof)

Changes in v3:
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
 3 files changed, 103 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 96afb67..6307060 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					 dp->video_info->link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
+					 dp->video_info.link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
+					struct drm_display_mode *orig_mode,
+					struct drm_display_mode *mode)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_display_info *display_info = &dp->connector->display_info;
+	struct video_info *video = &dp->video_info;
+	struct device_node *dp_node = dp->dev->of_node;
+	int vic;
+
+	/* Input video interlaces & hsync pol & vsync pol */
+	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+	/* Input video dynamic_range & colorimetry */
+	vic = drm_match_cea_mode(mode);
+	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
+	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR601;
+	} else if (vic) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	} else {
+		video->dynamic_range = VESA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	}
+
+	/* Input vide bpc and color_formats */
+	switch (display_info->bpc) {
+	case 12:
+		video->color_depth = COLOR_12;
+		break;
+	case 10:
+		video->color_depth = COLOR_10;
+		break;
+	case 8:
+		video->color_depth = COLOR_8;
+		break;
+	case 6:
+		video->color_depth = COLOR_6;
+		break;
+	default:
+		video->color_depth = COLOR_8;
+		break;
+	}
+	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
+		video->color_space = COLOR_YCBCR444;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
+		video->color_space = COLOR_YCBCR422;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
+		video->color_space = COLOR_RGB;
+	else
+		video->color_space = COLOR_RGB;
+
+	/*
+	 * NOTE: those property parsing code is used for providing backward
+	 * compatibility for samsung platform.
+	 * Due to we used the "of_property_read_u32" interfaces, when this
+	 * property isn't present, the "video_info" can keep the original
+	 * values and wouldn't be modified.
+	 */
+	of_property_read_u32(dp_node, "samsung,color-space",
+			     &video->color_space);
+	of_property_read_u32(dp_node, "samsung,dynamic-range",
+			     &video->dynamic_range);
+	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+			     &video->ycbcr_coeff);
+	of_property_read_u32(dp_node, "samsung,color-depth",
+			     &video->color_depth);
+	if (of_property_read_bool(dp_node, "hsync-active-high"))
+		video->h_sync_polarity = true;
+	if (of_property_read_bool(dp_node, "vsync-active-high"))
+		video->v_sync_polarity = true;
+	if (of_property_read_bool(dp_node, "interlaced"))
+		video->interlaced = true;
+}
+
 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
@@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
 	.disable = analogix_dp_bridge_disable,
 	.pre_enable = analogix_dp_bridge_nop,
 	.post_disable = analogix_dp_bridge_nop,
+	.mode_set = analogix_dp_bridge_mode_set,
 	.attach = analogix_dp_bridge_attach,
 };
 
@@ -1071,62 +1151,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 	return 0;
 }
 
-static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
-	struct device_node *dp_node = dev->of_node;
-	struct video_info *dp_video_config;
-
-	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
-				       GFP_KERNEL);
-	if (!dp_video_config)
-		return ERR_PTR(-ENOMEM);
-
-	dp_video_config->h_sync_polarity =
-		of_property_read_bool(dp_node, "hsync-active-high");
-
-	dp_video_config->v_sync_polarity =
-		of_property_read_bool(dp_node, "vsync-active-high");
-
-	dp_video_config->interlaced =
-		of_property_read_bool(dp_node, "interlaced");
-
-	if (of_property_read_u32(dp_node, "samsung,color-space",
-				 &dp_video_config->color_space)) {
-		dev_err(dev, "failed to get color-space\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				 &dp_video_config->dynamic_range)) {
-		dev_err(dev, "failed to get dynamic-range\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				 &dp_video_config->ycbcr_coeff)) {
-		dev_err(dev, "failed to get ycbcr-coeff\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				 &dp_video_config->color_depth)) {
-		dev_err(dev, "failed to get color-depth\n");
-		return ERR_PTR(-EINVAL);
-	}
+	struct device_node *dp_node = dp->dev->of_node;
+	struct video_info *video_info = &dp->video_info;
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &dp_video_config->link_rate)) {
-		dev_err(dev, "failed to get link-rate\n");
-		return ERR_PTR(-EINVAL);
+				 &video_info->link_rate)) {
+		dev_err(dp->dev, "failed to get link-rate\n");
+		return -EINVAL;
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &dp_video_config->lane_count)) {
-		dev_err(dev, "failed to get lane-count\n");
-		return ERR_PTR(-EINVAL);
+				 &video_info->lane_count)) {
+		dev_err(dp->dev, "failed to get lane-count\n");
+		return -EINVAL;
 	}
 
-	return dp_video_config;
+	return 0;
 }
 
 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
@@ -1159,9 +1201,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	 */
 	dp->plat_data = plat_data;
 
-	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
-	if (IS_ERR(dp->video_info))
-		return PTR_ERR(dp->video_info);
+	ret = analogix_dp_dt_parse_pdata(dp);
+	if (ret)
+		return ret;
 
 	dp->phy = devm_phy_get(dp->dev, "dp");
 	if (IS_ERR(dp->phy)) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 9a90a18..e37cef6 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -154,7 +154,7 @@ struct analogix_dp_device {
 	unsigned int		irq;
 	void __iomem		*reg_base;
 
-	struct video_info	*video_info;
+	struct video_info	video_info;
 	struct link_train	link_train;
 	struct work_struct	hotplug_work;
 	struct phy		*phy;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index a388c0a..861097a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
 	u32 reg;
 
 	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info.color_depth << IN_BPC_SHIFT) |
+		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
 	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
+	if (dp->video_info.ycbcr_coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
@@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
+	reg |= (dp->video_info.interlaced << 2);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
+	reg |= (dp->video_info.v_sync_polarity << 1);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
+	reg |= (dp->video_info.h_sync_polarity << 0);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-- 
2.1.2



^ permalink raw reply related	[flat|nested] 370+ messages in thread
* [PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  4:29     ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-12  4:29 UTC (permalink / raw)
  To: linux-arm-kernel

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.

But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
*just add a note that this is v7 of only fifth patch.*

Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
  compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
  to avoid -EOVERFLOW error (Krzysztof)

Changes in v6: None
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).

Changes in v4:
- Provide backword compatibility with samsung. (Krzysztof)

Changes in v3:
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
 3 files changed, 103 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 96afb67..6307060 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					 dp->video_info->link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
+					 dp->video_info.link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
+					struct drm_display_mode *orig_mode,
+					struct drm_display_mode *mode)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_display_info *display_info = &dp->connector->display_info;
+	struct video_info *video = &dp->video_info;
+	struct device_node *dp_node = dp->dev->of_node;
+	int vic;
+
+	/* Input video interlaces & hsync pol & vsync pol */
+	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+	/* Input video dynamic_range & colorimetry */
+	vic = drm_match_cea_mode(mode);
+	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
+	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR601;
+	} else if (vic) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	} else {
+		video->dynamic_range = VESA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	}
+
+	/* Input vide bpc and color_formats */
+	switch (display_info->bpc) {
+	case 12:
+		video->color_depth = COLOR_12;
+		break;
+	case 10:
+		video->color_depth = COLOR_10;
+		break;
+	case 8:
+		video->color_depth = COLOR_8;
+		break;
+	case 6:
+		video->color_depth = COLOR_6;
+		break;
+	default:
+		video->color_depth = COLOR_8;
+		break;
+	}
+	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
+		video->color_space = COLOR_YCBCR444;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
+		video->color_space = COLOR_YCBCR422;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
+		video->color_space = COLOR_RGB;
+	else
+		video->color_space = COLOR_RGB;
+
+	/*
+	 * NOTE: those property parsing code is used for providing backward
+	 * compatibility for samsung platform.
+	 * Due to we used the "of_property_read_u32" interfaces, when this
+	 * property isn't present, the "video_info" can keep the original
+	 * values and wouldn't be modified.
+	 */
+	of_property_read_u32(dp_node, "samsung,color-space",
+			     &video->color_space);
+	of_property_read_u32(dp_node, "samsung,dynamic-range",
+			     &video->dynamic_range);
+	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+			     &video->ycbcr_coeff);
+	of_property_read_u32(dp_node, "samsung,color-depth",
+			     &video->color_depth);
+	if (of_property_read_bool(dp_node, "hsync-active-high"))
+		video->h_sync_polarity = true;
+	if (of_property_read_bool(dp_node, "vsync-active-high"))
+		video->v_sync_polarity = true;
+	if (of_property_read_bool(dp_node, "interlaced"))
+		video->interlaced = true;
+}
+
 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
@@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
 	.disable = analogix_dp_bridge_disable,
 	.pre_enable = analogix_dp_bridge_nop,
 	.post_disable = analogix_dp_bridge_nop,
+	.mode_set = analogix_dp_bridge_mode_set,
 	.attach = analogix_dp_bridge_attach,
 };
 
@@ -1071,62 +1151,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 	return 0;
 }
 
-static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
-	struct device_node *dp_node = dev->of_node;
-	struct video_info *dp_video_config;
-
-	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
-				       GFP_KERNEL);
-	if (!dp_video_config)
-		return ERR_PTR(-ENOMEM);
-
-	dp_video_config->h_sync_polarity =
-		of_property_read_bool(dp_node, "hsync-active-high");
-
-	dp_video_config->v_sync_polarity =
-		of_property_read_bool(dp_node, "vsync-active-high");
-
-	dp_video_config->interlaced =
-		of_property_read_bool(dp_node, "interlaced");
-
-	if (of_property_read_u32(dp_node, "samsung,color-space",
-				 &dp_video_config->color_space)) {
-		dev_err(dev, "failed to get color-space\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				 &dp_video_config->dynamic_range)) {
-		dev_err(dev, "failed to get dynamic-range\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				 &dp_video_config->ycbcr_coeff)) {
-		dev_err(dev, "failed to get ycbcr-coeff\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				 &dp_video_config->color_depth)) {
-		dev_err(dev, "failed to get color-depth\n");
-		return ERR_PTR(-EINVAL);
-	}
+	struct device_node *dp_node = dp->dev->of_node;
+	struct video_info *video_info = &dp->video_info;
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &dp_video_config->link_rate)) {
-		dev_err(dev, "failed to get link-rate\n");
-		return ERR_PTR(-EINVAL);
+				 &video_info->link_rate)) {
+		dev_err(dp->dev, "failed to get link-rate\n");
+		return -EINVAL;
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &dp_video_config->lane_count)) {
-		dev_err(dev, "failed to get lane-count\n");
-		return ERR_PTR(-EINVAL);
+				 &video_info->lane_count)) {
+		dev_err(dp->dev, "failed to get lane-count\n");
+		return -EINVAL;
 	}
 
-	return dp_video_config;
+	return 0;
 }
 
 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
@@ -1159,9 +1201,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	 */
 	dp->plat_data = plat_data;
 
-	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
-	if (IS_ERR(dp->video_info))
-		return PTR_ERR(dp->video_info);
+	ret = analogix_dp_dt_parse_pdata(dp);
+	if (ret)
+		return ret;
 
 	dp->phy = devm_phy_get(dp->dev, "dp");
 	if (IS_ERR(dp->phy)) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 9a90a18..e37cef6 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -154,7 +154,7 @@ struct analogix_dp_device {
 	unsigned int		irq;
 	void __iomem		*reg_base;
 
-	struct video_info	*video_info;
+	struct video_info	video_info;
 	struct link_train	link_train;
 	struct work_struct	hotplug_work;
 	struct phy		*phy;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index a388c0a..861097a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
 	u32 reg;
 
 	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info.color_depth << IN_BPC_SHIFT) |
+		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
 	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
+	if (dp->video_info.ycbcr_coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
@@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
+	reg |= (dp->video_info.interlaced << 2);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
+	reg |= (dp->video_info.v_sync_polarity << 1);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
+	reg |= (dp->video_info.h_sync_polarity << 0);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-- 
2.1.2

^ permalink raw reply related	[flat|nested] 370+ messages in thread
* Re: [PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  2015-10-12  4:29     ` Yakir Yang
@ 2015-10-12  6:54       ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-10-12  6:54 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

On 12.10.2015 13:29, Yakir Yang wrote:
> Both hsync/vsync polarity and interlace mode can be parsed from
> drm display mode, and dynamic_range and ycbcr_coeff can be judge
> by the video code.
> 
> But presumably Exynos still relies on the DT properties, so take
> good use of mode_fixup() in to achieve the compatibility hacks.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> *just add a note that this is v7 of only fifth patch.*
> 
> Changes in v7:
> - Back to use the of_property_read_bool() interfacs to provoid backward
>   compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
>   to avoid -EOVERFLOW error (Krzysztof)
> 
> Changes in v6: None
> Changes in v5:
> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>   to get the backword timing values. Krzysztof suggest me that driver could use
>   the "of_property_read_bool" to get backword timing values, but that interfacs
>   would modify the original drm_display_mode timing directly (whether those
>   properties exists or not).
> 
> Changes in v4:
> - Provide backword compatibility with samsung. (Krzysztof)
> 
> Changes in v3:
> - Dynamic parse video timing info from struct drm_display_mode and
>   struct drm_display_info. (Thierry)
> 
> Changes in v2: None
> 
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>  3 files changed, 103 insertions(+), 61 deletions(-)
> 

Looks good and backward compatible to me:
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  6:54       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 370+ messages in thread
From: Krzysztof Kozlowski @ 2015-10-12  6:54 UTC (permalink / raw)
  To: linux-arm-kernel

On 12.10.2015 13:29, Yakir Yang wrote:
> Both hsync/vsync polarity and interlace mode can be parsed from
> drm display mode, and dynamic_range and ycbcr_coeff can be judge
> by the video code.
> 
> But presumably Exynos still relies on the DT properties, so take
> good use of mode_fixup() in to achieve the compatibility hacks.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> *just add a note that this is v7 of only fifth patch.*
> 
> Changes in v7:
> - Back to use the of_property_read_bool() interfacs to provoid backward
>   compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
>   to avoid -EOVERFLOW error (Krzysztof)
> 
> Changes in v6: None
> Changes in v5:
> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>   to get the backword timing values. Krzysztof suggest me that driver could use
>   the "of_property_read_bool" to get backword timing values, but that interfacs
>   would modify the original drm_display_mode timing directly (whether those
>   properties exists or not).
> 
> Changes in v4:
> - Provide backword compatibility with samsung. (Krzysztof)
> 
> Changes in v3:
> - Dynamic parse video timing info from struct drm_display_mode and
>   struct drm_display_info. (Thierry)
> 
> Changes in v2: None
> 
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
>  drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>  3 files changed, 103 insertions(+), 61 deletions(-)
> 

Looks good and backward compatible to me:
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  7:20         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-12  7:20 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel



On 10/12/2015 02:54 PM, Krzysztof Kozlowski wrote:
> On 12.10.2015 13:29, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code.
>>
>> But presumably Exynos still relies on the DT properties, so take
>> good use of mode_fixup() in to achieve the compatibility hacks.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> *just add a note that this is v7 of only fifth patch.*
>>
>> Changes in v7:
>> - Back to use the of_property_read_bool() interfacs to provoid backward
>>    compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
>>    to avoid -EOVERFLOW error (Krzysztof)
>>
>> Changes in v6: None
>> Changes in v5:
>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>>    to get the backword timing values. Krzysztof suggest me that driver could use
>>    the "of_property_read_bool" to get backword timing values, but that interfacs
>>    would modify the original drm_display_mode timing directly (whether those
>>    properties exists or not).
>>
>> Changes in v4:
>> - Provide backword compatibility with samsung. (Krzysztof)
>>
>> Changes in v3:
>> - Dynamic parse video timing info from struct drm_display_mode and
>>    struct drm_display_info. (Thierry)
>>
>> Changes in v2: None
>>
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>>   3 files changed, 103 insertions(+), 61 deletions(-)
>>
> Looks good and backward compatible to me:
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Thanks,

- Yakir

> Best regards,
> Krzysztof
>
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  7:20         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-12  7:20 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Rob Herring, joe-6d6DIl74uiNBDgjK7y7TUQ, Heiko Stuebner,
	Mark Yao
  Cc: Russell King, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w,
	javier-JPH+aEBZ4P+UEJcrhfAQsw, Andy Yan,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r



On 10/12/2015 02:54 PM, Krzysztof Kozlowski wrote:
> On 12.10.2015 13:29, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code.
>>
>> But presumably Exynos still relies on the DT properties, so take
>> good use of mode_fixup() in to achieve the compatibility hacks.
>>
>> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>> *just add a note that this is v7 of only fifth patch.*
>>
>> Changes in v7:
>> - Back to use the of_property_read_bool() interfacs to provoid backward
>>    compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
>>    to avoid -EOVERFLOW error (Krzysztof)
>>
>> Changes in v6: None
>> Changes in v5:
>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>>    to get the backword timing values. Krzysztof suggest me that driver could use
>>    the "of_property_read_bool" to get backword timing values, but that interfacs
>>    would modify the original drm_display_mode timing directly (whether those
>>    properties exists or not).
>>
>> Changes in v4:
>> - Provide backword compatibility with samsung. (Krzysztof)
>>
>> Changes in v3:
>> - Dynamic parse video timing info from struct drm_display_mode and
>>    struct drm_display_info. (Thierry)
>>
>> Changes in v2: None
>>
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>>   3 files changed, 103 insertions(+), 61 deletions(-)
>>
> Looks good and backward compatible to me:
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>

Thanks,

- Yakir

> Best regards,
> Krzysztof
>
>
>
>


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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
@ 2015-10-12  7:20         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-12  7:20 UTC (permalink / raw)
  To: linux-arm-kernel



On 10/12/2015 02:54 PM, Krzysztof Kozlowski wrote:
> On 12.10.2015 13:29, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code.
>>
>> But presumably Exynos still relies on the DT properties, so take
>> good use of mode_fixup() in to achieve the compatibility hacks.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> *just add a note that this is v7 of only fifth patch.*
>>
>> Changes in v7:
>> - Back to use the of_property_read_bool() interfacs to provoid backward
>>    compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
>>    to avoid -EOVERFLOW error (Krzysztof)
>>
>> Changes in v6: None
>> Changes in v5:
>> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>>    to get the backword timing values. Krzysztof suggest me that driver could use
>>    the "of_property_read_bool" to get backword timing values, but that interfacs
>>    would modify the original drm_display_mode timing directly (whether those
>>    properties exists or not).
>>
>> Changes in v4:
>> - Provide backword compatibility with samsung. (Krzysztof)
>>
>> Changes in v3:
>> - Dynamic parse video timing info from struct drm_display_mode and
>>    struct drm_display_info. (Thierry)
>>
>> Changes in v2: None
>>
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
>>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
>>   3 files changed, 103 insertions(+), 61 deletions(-)
>>
> Looks good and backward compatible to me:
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Thanks,

- Yakir

> Best regards,
> Krzysztof
>
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY
@ 2015-10-12 15:02       ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 370+ messages in thread
From: Kishon Vijay Abraham I @ 2015-10-12 15:02 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Pawel Moll, ajaynumb, robherring2, javier, Andy Yan, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi,

On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.

Add phy driver for the Rockchip DisplayPort PHY module. This is required
to get DisplayPort working in Rockchip SoCs.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v6: None
> Changes in v5:
> - Remove "reg" DT property, cause driver could poweron/poweroff phy via
>   the exist "grf" syscon already. And rename the example DT node from
>   "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
> - Add deivce_node at the front of driver, update phy_ops type from "static
>   struct" to "static const struct". And correct the input paramters of
>   devm_phy_create() interfaces. (Heiko)
> 
> Changes in v4:
> - Add commit message, and remove the redundant rockchip_dp_phy_init()
>   function, move those code to probe() method. And remove driver .owner
>   number. (Kishon)
> 
> Changes in v3:
> - Suggest, add rockchip dp phy driver, collect the phy clocks and
>   power control. (Heiko)
> 
> Changes in v2: None
> 
>  drivers/phy/Kconfig           |   7 ++
>  drivers/phy/Makefile          |   1 +
>  drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 159 insertions(+)
>  create mode 100644 drivers/phy/phy-rockchip-dp.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573..8f2bc4f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>  	help
>  	  Enable this to support the Rockchip USB 2.0 PHY.
>  
> +config PHY_ROCKCHIP_DP
> +	tristate "Rockchip Display Port PHY Driver"
> +	depends on ARCH_ROCKCHIP && OF
> +	select GENERIC_PHY
> +	help
> +	  Enable this to support the Rockchip Display Port PHY.
> +
>  config PHY_ST_SPEAR1310_MIPHY
>  	tristate "ST SPEAR1310-MIPHY driver"
>  	select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a5b18c1..e281f35 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
>  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
>  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
>  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..3a2ac120
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,151 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12                   0x0274
> +#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
> +#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
> +#define GRF_EDP_PHY_SIDDQ_ON            0
> +#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
> +
> +struct rockchip_dp_phy {
> +	struct device  *dev;
> +	struct regmap  *grf;
> +	struct clk     *phy_24m;
> +};
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> +	int ret;
> +
> +	if (enable) {
> +		ret = clk_prepare_enable(dp->phy_24m);
> +		if (ret < 0) {
> +			dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
> +			return ret;
> +		}
> +
> +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
> +				   GRF_EDP_PHY_SIDDQ_ON);
> +	} else {
> +		clk_disable_unprepare(dp->phy_24m);

should clk_disable come after regmap_write? It'll be symmetric to enable?
> +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
> +				   GRF_EDP_PHY_SIDDQ_OFF);

Is this syscon register used only by Display Port PHY? Better to use
regmap_update API?

Thanks
Kishon

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY
@ 2015-10-12 15:02       ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 370+ messages in thread
From: Kishon Vijay Abraham I @ 2015-10-12 15:02 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Heiko Stuebner, Mark Yao
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Russell King,
	Pawel Moll, Ian Campbell,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w,
	dianders-F7+t8E8rja9g9hUCZPvPmw, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	javier-JPH+aEBZ4P+UEJcrhfAQsw, Kukjin Kim, Sean Paul,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Kumar Gala,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan, Gustavo Padovan,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Hi,

On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.

Add phy driver for the Rockchip DisplayPort PHY module. This is required
to get DisplayPort working in Rockchip SoCs.
> 
> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> Changes in v6: None
> Changes in v5:
> - Remove "reg" DT property, cause driver could poweron/poweroff phy via
>   the exist "grf" syscon already. And rename the example DT node from
>   "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
> - Add deivce_node at the front of driver, update phy_ops type from "static
>   struct" to "static const struct". And correct the input paramters of
>   devm_phy_create() interfaces. (Heiko)
> 
> Changes in v4:
> - Add commit message, and remove the redundant rockchip_dp_phy_init()
>   function, move those code to probe() method. And remove driver .owner
>   number. (Kishon)
> 
> Changes in v3:
> - Suggest, add rockchip dp phy driver, collect the phy clocks and
>   power control. (Heiko)
> 
> Changes in v2: None
> 
>  drivers/phy/Kconfig           |   7 ++
>  drivers/phy/Makefile          |   1 +
>  drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 159 insertions(+)
>  create mode 100644 drivers/phy/phy-rockchip-dp.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573..8f2bc4f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>  	help
>  	  Enable this to support the Rockchip USB 2.0 PHY.
>  
> +config PHY_ROCKCHIP_DP
> +	tristate "Rockchip Display Port PHY Driver"
> +	depends on ARCH_ROCKCHIP && OF
> +	select GENERIC_PHY
> +	help
> +	  Enable this to support the Rockchip Display Port PHY.
> +
>  config PHY_ST_SPEAR1310_MIPHY
>  	tristate "ST SPEAR1310-MIPHY driver"
>  	select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a5b18c1..e281f35 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
>  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
>  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
>  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..3a2ac120
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,151 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12                   0x0274
> +#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
> +#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
> +#define GRF_EDP_PHY_SIDDQ_ON            0
> +#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
> +
> +struct rockchip_dp_phy {
> +	struct device  *dev;
> +	struct regmap  *grf;
> +	struct clk     *phy_24m;
> +};
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> +	int ret;
> +
> +	if (enable) {
> +		ret = clk_prepare_enable(dp->phy_24m);
> +		if (ret < 0) {
> +			dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
> +			return ret;
> +		}
> +
> +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
> +				   GRF_EDP_PHY_SIDDQ_ON);
> +	} else {
> +		clk_disable_unprepare(dp->phy_24m);

should clk_disable come after regmap_write? It'll be symmetric to enable?
> +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
> +				   GRF_EDP_PHY_SIDDQ_OFF);

Is this syscon register used only by Display Port PHY? Better to use
regmap_update API?

Thanks
Kishon

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY
@ 2015-10-12 15:02       ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 370+ messages in thread
From: Kishon Vijay Abraham I @ 2015-10-12 15:02 UTC (permalink / raw)
  To: linux-arm-kernel

Hi,

On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
> This phy driver would control the Rockchip DisplayPort module
> phy clock and phy power, it is relate to analogix_dp-rockchip
> dp driver. If you want DP works rightly on rockchip platform,
> then you should select both of them.

Add phy driver for the Rockchip DisplayPort PHY module. This is required
to get DisplayPort working in Rockchip SoCs.
> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v6: None
> Changes in v5:
> - Remove "reg" DT property, cause driver could poweron/poweroff phy via
>   the exist "grf" syscon already. And rename the example DT node from
>   "edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
> - Add deivce_node at the front of driver, update phy_ops type from "static
>   struct" to "static const struct". And correct the input paramters of
>   devm_phy_create() interfaces. (Heiko)
> 
> Changes in v4:
> - Add commit message, and remove the redundant rockchip_dp_phy_init()
>   function, move those code to probe() method. And remove driver .owner
>   number. (Kishon)
> 
> Changes in v3:
> - Suggest, add rockchip dp phy driver, collect the phy clocks and
>   power control. (Heiko)
> 
> Changes in v2: None
> 
>  drivers/phy/Kconfig           |   7 ++
>  drivers/phy/Makefile          |   1 +
>  drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 159 insertions(+)
>  create mode 100644 drivers/phy/phy-rockchip-dp.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573..8f2bc4f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>  	help
>  	  Enable this to support the Rockchip USB 2.0 PHY.
>  
> +config PHY_ROCKCHIP_DP
> +	tristate "Rockchip Display Port PHY Driver"
> +	depends on ARCH_ROCKCHIP && OF
> +	select GENERIC_PHY
> +	help
> +	  Enable this to support the Rockchip Display Port PHY.
> +
>  config PHY_ST_SPEAR1310_MIPHY
>  	tristate "ST SPEAR1310-MIPHY driver"
>  	select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a5b18c1..e281f35 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
>  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
>  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
>  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..3a2ac120
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,151 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12                   0x0274
> +#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
> +#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
> +#define GRF_EDP_PHY_SIDDQ_ON            0
> +#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
> +
> +struct rockchip_dp_phy {
> +	struct device  *dev;
> +	struct regmap  *grf;
> +	struct clk     *phy_24m;
> +};
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> +	int ret;
> +
> +	if (enable) {
> +		ret = clk_prepare_enable(dp->phy_24m);
> +		if (ret < 0) {
> +			dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
> +			return ret;
> +		}
> +
> +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
> +				   GRF_EDP_PHY_SIDDQ_ON);
> +	} else {
> +		clk_disable_unprepare(dp->phy_24m);

should clk_disable come after regmap_write? It'll be symmetric to enable?
> +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
> +				   GRF_EDP_PHY_SIDDQ_OFF);

Is this syscon register used only by Display Port PHY? Better to use
regmap_update API?

Thanks
Kishon

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY
  2015-10-12 15:02       ` Kishon Vijay Abraham I
  (?)
@ 2015-10-12 16:18         ` Heiko Stübner
  -1 siblings, 0 replies; 370+ messages in thread
From: Heiko Stübner @ 2015-10-12 16:18 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, joe, Mark Yao, Russell King,
	djkurtz, dianders, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan, Pawel Moll,
	ajaynumb, robherring2, javier, Andy Yan, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Am Montag, 12. Oktober 2015, 20:32:47 schrieb Kishon Vijay Abraham I:
> Hi,
> 
> On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
> > This phy driver would control the Rockchip DisplayPort module
> > phy clock and phy power, it is relate to analogix_dp-rockchip
> > dp driver. If you want DP works rightly on rockchip platform,
> > then you should select both of them.
> 
> Add phy driver for the Rockchip DisplayPort PHY module. This is required
> to get DisplayPort working in Rockchip SoCs.
> 
> > Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> > ---
> > Changes in v6: None
> > Changes in v5:
> > - Remove "reg" DT property, cause driver could poweron/poweroff phy via
> > 
> >   the exist "grf" syscon already. And rename the example DT node from
> >   "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
> > 
> > - Add deivce_node at the front of driver, update phy_ops type from "static
> > 
> >   struct" to "static const struct". And correct the input paramters of
> >   devm_phy_create() interfaces. (Heiko)
> > 
> > Changes in v4:
> > - Add commit message, and remove the redundant rockchip_dp_phy_init()
> > 
> >   function, move those code to probe() method. And remove driver .owner
> >   number. (Kishon)
> > 
> > Changes in v3:
> > - Suggest, add rockchip dp phy driver, collect the phy clocks and
> > 
> >   power control. (Heiko)
> > 
> > Changes in v2: None
> > 
> >  drivers/phy/Kconfig           |   7 ++
> >  drivers/phy/Makefile          |   1 +
> >  drivers/phy/phy-rockchip-dp.c | 151
> >  ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 159
> >  insertions(+)
> >  create mode 100644 drivers/phy/phy-rockchip-dp.c
> > 
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index 47da573..8f2bc4f 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
> > 
> >  	help
> >  	
> >  	  Enable this to support the Rockchip USB 2.0 PHY.
> > 
> > +config PHY_ROCKCHIP_DP
> > +	tristate "Rockchip Display Port PHY Driver"
> > +	depends on ARCH_ROCKCHIP && OF
> > +	select GENERIC_PHY
> > +	help
> > +	  Enable this to support the Rockchip Display Port PHY.
> > +
> > 
> >  config PHY_ST_SPEAR1310_MIPHY
> >  
> >  	tristate "ST SPEAR1310-MIPHY driver"
> >  	select GENERIC_PHY
> > 
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index a5b18c1..e281f35 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+=
> > phy-s5pv210-usb2.o> 
> >  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
> >  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
> >  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> > 
> > +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
> > 
> >  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
> >  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
> >  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
> > 
> > diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> > new file mode 100644
> > index 0000000..3a2ac120
> > --- /dev/null
> > +++ b/drivers/phy/phy-rockchip-dp.c
> > @@ -0,0 +1,151 @@
> > +/*
> > + * Rockchip DP PHY driver
> > + *
> > + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> > + * Author: Yakir Yang <ykk@@rock-chips.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License.
> > + */
> > +
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/clk.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/regmap.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/platform_device.h>
> > +
> > +#define GRF_SOC_CON12                   0x0274
> > +#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
> > +#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
> > +#define GRF_EDP_PHY_SIDDQ_ON            0
> > +#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
> > +
> > +struct rockchip_dp_phy {
> > +	struct device  *dev;
> > +	struct regmap  *grf;
> > +	struct clk     *phy_24m;
> > +};
> > +
> > +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> > +{
> > +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> > +	int ret;
> > +
> > +	if (enable) {
> > +		ret = clk_prepare_enable(dp->phy_24m);
> > +		if (ret < 0) {
> > +			dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
> > +			return ret;
> > +		}
> > +
> > +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> > +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
> > +				   GRF_EDP_PHY_SIDDQ_ON);
> > +	} else {
> > +		clk_disable_unprepare(dp->phy_24m);
> 
> should clk_disable come after regmap_write? It'll be symmetric to enable?
> 
> > +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> > +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
> > +				   GRF_EDP_PHY_SIDDQ_OFF);
> 
> Is this syscon register used only by Display Port PHY? Better to use
> regmap_update API?

Rockchip's GRF syscon registers use what gets called "Hiword-mask", so when 
writing you actually need to set the write-enable bit (x+16, like 
GRF_EDP_PHY_SIDDQ_WRITE_EN here) if you want to set bit x. No other bits get 
affected by this.


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY
@ 2015-10-12 16:18         ` Heiko Stübner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stübner @ 2015-10-12 16:18 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, joe, Mark Yao, Russell King,
	djkurtz, dianders, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan, Pawel Moll,
	ajaynumb, robherring2, javier, Andy Yan

Am Montag, 12. Oktober 2015, 20:32:47 schrieb Kishon Vijay Abraham I:
> Hi,
> 
> On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
> > This phy driver would control the Rockchip DisplayPort module
> > phy clock and phy power, it is relate to analogix_dp-rockchip
> > dp driver. If you want DP works rightly on rockchip platform,
> > then you should select both of them.
> 
> Add phy driver for the Rockchip DisplayPort PHY module. This is required
> to get DisplayPort working in Rockchip SoCs.
> 
> > Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> > ---
> > Changes in v6: None
> > Changes in v5:
> > - Remove "reg" DT property, cause driver could poweron/poweroff phy via
> > 
> >   the exist "grf" syscon already. And rename the example DT node from
> >   "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
> > 
> > - Add deivce_node at the front of driver, update phy_ops type from "static
> > 
> >   struct" to "static const struct". And correct the input paramters of
> >   devm_phy_create() interfaces. (Heiko)
> > 
> > Changes in v4:
> > - Add commit message, and remove the redundant rockchip_dp_phy_init()
> > 
> >   function, move those code to probe() method. And remove driver .owner
> >   number. (Kishon)
> > 
> > Changes in v3:
> > - Suggest, add rockchip dp phy driver, collect the phy clocks and
> > 
> >   power control. (Heiko)
> > 
> > Changes in v2: None
> > 
> >  drivers/phy/Kconfig           |   7 ++
> >  drivers/phy/Makefile          |   1 +
> >  drivers/phy/phy-rockchip-dp.c | 151
> >  ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 159
> >  insertions(+)
> >  create mode 100644 drivers/phy/phy-rockchip-dp.c
> > 
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index 47da573..8f2bc4f 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
> > 
> >  	help
> >  	
> >  	  Enable this to support the Rockchip USB 2.0 PHY.
> > 
> > +config PHY_ROCKCHIP_DP
> > +	tristate "Rockchip Display Port PHY Driver"
> > +	depends on ARCH_ROCKCHIP && OF
> > +	select GENERIC_PHY
> > +	help
> > +	  Enable this to support the Rockchip Display Port PHY.
> > +
> > 
> >  config PHY_ST_SPEAR1310_MIPHY
> >  
> >  	tristate "ST SPEAR1310-MIPHY driver"
> >  	select GENERIC_PHY
> > 
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index a5b18c1..e281f35 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+=
> > phy-s5pv210-usb2.o> 
> >  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
> >  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
> >  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> > 
> > +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
> > 
> >  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
> >  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
> >  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
> > 
> > diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> > new file mode 100644
> > index 0000000..3a2ac120
> > --- /dev/null
> > +++ b/drivers/phy/phy-rockchip-dp.c
> > @@ -0,0 +1,151 @@
> > +/*
> > + * Rockchip DP PHY driver
> > + *
> > + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> > + * Author: Yakir Yang <ykk@@rock-chips.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License.
> > + */
> > +
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/clk.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/regmap.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/platform_device.h>
> > +
> > +#define GRF_SOC_CON12                   0x0274
> > +#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
> > +#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
> > +#define GRF_EDP_PHY_SIDDQ_ON            0
> > +#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
> > +
> > +struct rockchip_dp_phy {
> > +	struct device  *dev;
> > +	struct regmap  *grf;
> > +	struct clk     *phy_24m;
> > +};
> > +
> > +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> > +{
> > +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> > +	int ret;
> > +
> > +	if (enable) {
> > +		ret = clk_prepare_enable(dp->phy_24m);
> > +		if (ret < 0) {
> > +			dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
> > +			return ret;
> > +		}
> > +
> > +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> > +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
> > +				   GRF_EDP_PHY_SIDDQ_ON);
> > +	} else {
> > +		clk_disable_unprepare(dp->phy_24m);
> 
> should clk_disable come after regmap_write? It'll be symmetric to enable?
> 
> > +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> > +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
> > +				   GRF_EDP_PHY_SIDDQ_OFF);
> 
> Is this syscon register used only by Display Port PHY? Better to use
> regmap_update API?

Rockchip's GRF syscon registers use what gets called "Hiword-mask", so when 
writing you actually need to set the write-enable bit (x+16, like 
GRF_EDP_PHY_SIDDQ_WRITE_EN here) if you want to set bit x. No other bits get 
affected by this.


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY
@ 2015-10-12 16:18         ` Heiko Stübner
  0 siblings, 0 replies; 370+ messages in thread
From: Heiko Stübner @ 2015-10-12 16:18 UTC (permalink / raw)
  To: linux-arm-kernel

Am Montag, 12. Oktober 2015, 20:32:47 schrieb Kishon Vijay Abraham I:
> Hi,
> 
> On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
> > This phy driver would control the Rockchip DisplayPort module
> > phy clock and phy power, it is relate to analogix_dp-rockchip
> > dp driver. If you want DP works rightly on rockchip platform,
> > then you should select both of them.
> 
> Add phy driver for the Rockchip DisplayPort PHY module. This is required
> to get DisplayPort working in Rockchip SoCs.
> 
> > Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> > ---
> > Changes in v6: None
> > Changes in v5:
> > - Remove "reg" DT property, cause driver could poweron/poweroff phy via
> > 
> >   the exist "grf" syscon already. And rename the example DT node from
> >   "edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
> > 
> > - Add deivce_node at the front of driver, update phy_ops type from "static
> > 
> >   struct" to "static const struct". And correct the input paramters of
> >   devm_phy_create() interfaces. (Heiko)
> > 
> > Changes in v4:
> > - Add commit message, and remove the redundant rockchip_dp_phy_init()
> > 
> >   function, move those code to probe() method. And remove driver .owner
> >   number. (Kishon)
> > 
> > Changes in v3:
> > - Suggest, add rockchip dp phy driver, collect the phy clocks and
> > 
> >   power control. (Heiko)
> > 
> > Changes in v2: None
> > 
> >  drivers/phy/Kconfig           |   7 ++
> >  drivers/phy/Makefile          |   1 +
> >  drivers/phy/phy-rockchip-dp.c | 151
> >  ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 159
> >  insertions(+)
> >  create mode 100644 drivers/phy/phy-rockchip-dp.c
> > 
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index 47da573..8f2bc4f 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
> > 
> >  	help
> >  	
> >  	  Enable this to support the Rockchip USB 2.0 PHY.
> > 
> > +config PHY_ROCKCHIP_DP
> > +	tristate "Rockchip Display Port PHY Driver"
> > +	depends on ARCH_ROCKCHIP && OF
> > +	select GENERIC_PHY
> > +	help
> > +	  Enable this to support the Rockchip Display Port PHY.
> > +
> > 
> >  config PHY_ST_SPEAR1310_MIPHY
> >  
> >  	tristate "ST SPEAR1310-MIPHY driver"
> >  	select GENERIC_PHY
> > 
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index a5b18c1..e281f35 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+=
> > phy-s5pv210-usb2.o> 
> >  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
> >  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
> >  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> > 
> > +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
> > 
> >  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
> >  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
> >  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
> > 
> > diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> > new file mode 100644
> > index 0000000..3a2ac120
> > --- /dev/null
> > +++ b/drivers/phy/phy-rockchip-dp.c
> > @@ -0,0 +1,151 @@
> > +/*
> > + * Rockchip DP PHY driver
> > + *
> > + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> > + * Author: Yakir Yang <ykk@@rock-chips.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License.
> > + */
> > +
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/clk.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/regmap.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/platform_device.h>
> > +
> > +#define GRF_SOC_CON12                   0x0274
> > +#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
> > +#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
> > +#define GRF_EDP_PHY_SIDDQ_ON            0
> > +#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
> > +
> > +struct rockchip_dp_phy {
> > +	struct device  *dev;
> > +	struct regmap  *grf;
> > +	struct clk     *phy_24m;
> > +};
> > +
> > +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> > +{
> > +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> > +	int ret;
> > +
> > +	if (enable) {
> > +		ret = clk_prepare_enable(dp->phy_24m);
> > +		if (ret < 0) {
> > +			dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
> > +			return ret;
> > +		}
> > +
> > +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> > +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
> > +				   GRF_EDP_PHY_SIDDQ_ON);
> > +	} else {
> > +		clk_disable_unprepare(dp->phy_24m);
> 
> should clk_disable come after regmap_write? It'll be symmetric to enable?
> 
> > +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> > +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
> > +				   GRF_EDP_PHY_SIDDQ_OFF);
> 
> Is this syscon register used only by Display Port PHY? Better to use
> regmap_update API?

Rockchip's GRF syscon registers use what gets called "Hiword-mask", so when 
writing you actually need to set the write-enable bit (x+16, like 
GRF_EDP_PHY_SIDDQ_WRITE_EN here) if you want to set bit x. No other bits get 
affected by this.


Heiko

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy
@ 2015-10-12 22:28       ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 370+ messages in thread
From: Kishon Vijay Abraham I @ 2015-10-12 22:28 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Pawel Moll, ajaynumb, robherring2, javier, Andy Yan, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi,

On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
> This phy driver is binded with the Rockchip DisplayPort
> driver, here are the brief properties:
> 	edp_phy: edp-phy@ff770274 {
> 		compatible = "rockchip,rk3288-dp-phy";
> 		rockchip,grf = <&grf>;
> 		clocks = <&cru SCLK_EDP_24M>;
> 		clock-names = "24m";
> 		#phy-cells = <0>;
> 	};

The commit message can simply be "Add dt binding documentation for
rockchip display port PHY".

Thanks
Kishon

> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v6: None
> Changes in v5:
> - Split binding doc's from driver changes. (Rob)
> - Update the rockchip,grf explain in document, and correct the clock required
>   elemets in document. (Rob & Heiko)
> 
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  .../devicetree/bindings/phy/rockchip-dp-phy.txt    | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> new file mode 100644
> index 0000000..505194e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> @@ -0,0 +1,22 @@
> +Rockchip Soc Seroes Display Port PHY
> +------------------------------------
> +
> +Required properties:
> +- compatible : should be one of the following supported values:
> +	 - "rockchip.rk3288-dp-phy"
> +- clocks: from common clock binding: handle to dp clock.
> +	of memory mapped region.
> +- clock-names: from common clock binding:
> +	Required elements: "24m"
> +- rockchip,grf: phandle to the syscon managing the "general register files"
> +- #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Example:
> +
> +edp_phy: edp-phy@ff770274 {
> +	compatible = "rockchip,rk3288-dp-phy";
> +	rockchip,grf = <&grf>;
> +	clocks = <&cru SCLK_EDP_24M>;
> +	clock-names = "24m";
> +	#phy-cells = <0>;
> +};
> 

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy
@ 2015-10-12 22:28       ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 370+ messages in thread
From: Kishon Vijay Abraham I @ 2015-10-12 22:28 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Heiko Stuebner, Mark Yao
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Russell King,
	Pawel Moll, Ian Campbell,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w,
	dianders-F7+t8E8rja9g9hUCZPvPmw, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	javier-JPH+aEBZ4P+UEJcrhfAQsw, Kukjin Kim, Sean Paul,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Kumar Gala,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan, Gustavo Padovan,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Hi,

On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
> This phy driver is binded with the Rockchip DisplayPort
> driver, here are the brief properties:
> 	edp_phy: edp-phy@ff770274 {
> 		compatible = "rockchip,rk3288-dp-phy";
> 		rockchip,grf = <&grf>;
> 		clocks = <&cru SCLK_EDP_24M>;
> 		clock-names = "24m";
> 		#phy-cells = <0>;
> 	};

The commit message can simply be "Add dt binding documentation for
rockchip display port PHY".

Thanks
Kishon

> 
> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> Changes in v6: None
> Changes in v5:
> - Split binding doc's from driver changes. (Rob)
> - Update the rockchip,grf explain in document, and correct the clock required
>   elemets in document. (Rob & Heiko)
> 
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  .../devicetree/bindings/phy/rockchip-dp-phy.txt    | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> new file mode 100644
> index 0000000..505194e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> @@ -0,0 +1,22 @@
> +Rockchip Soc Seroes Display Port PHY
> +------------------------------------
> +
> +Required properties:
> +- compatible : should be one of the following supported values:
> +	 - "rockchip.rk3288-dp-phy"
> +- clocks: from common clock binding: handle to dp clock.
> +	of memory mapped region.
> +- clock-names: from common clock binding:
> +	Required elements: "24m"
> +- rockchip,grf: phandle to the syscon managing the "general register files"
> +- #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Example:
> +
> +edp_phy: edp-phy@ff770274 {
> +	compatible = "rockchip,rk3288-dp-phy";
> +	rockchip,grf = <&grf>;
> +	clocks = <&cru SCLK_EDP_24M>;
> +	clock-names = "24m";
> +	#phy-cells = <0>;
> +};
> 

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy
@ 2015-10-12 22:28       ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 370+ messages in thread
From: Kishon Vijay Abraham I @ 2015-10-12 22:28 UTC (permalink / raw)
  To: linux-arm-kernel

Hi,

On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
> This phy driver is binded with the Rockchip DisplayPort
> driver, here are the brief properties:
> 	edp_phy: edp-phy at ff770274 {
> 		compatible = "rockchip,rk3288-dp-phy";
> 		rockchip,grf = <&grf>;
> 		clocks = <&cru SCLK_EDP_24M>;
> 		clock-names = "24m";
> 		#phy-cells = <0>;
> 	};

The commit message can simply be "Add dt binding documentation for
rockchip display port PHY".

Thanks
Kishon

> 
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> Changes in v6: None
> Changes in v5:
> - Split binding doc's from driver changes. (Rob)
> - Update the rockchip,grf explain in document, and correct the clock required
>   elemets in document. (Rob & Heiko)
> 
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  .../devicetree/bindings/phy/rockchip-dp-phy.txt    | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> new file mode 100644
> index 0000000..505194e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> @@ -0,0 +1,22 @@
> +Rockchip Soc Seroes Display Port PHY
> +------------------------------------
> +
> +Required properties:
> +- compatible : should be one of the following supported values:
> +	 - "rockchip.rk3288-dp-phy"
> +- clocks: from common clock binding: handle to dp clock.
> +	of memory mapped region.
> +- clock-names: from common clock binding:
> +	Required elements: "24m"
> +- rockchip,grf: phandle to the syscon managing the "general register files"
> +- #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Example:
> +
> +edp_phy: edp-phy at ff770274 {
> +	compatible = "rockchip,rk3288-dp-phy";
> +	rockchip,grf = <&grf>;
> +	clocks = <&cru SCLK_EDP_24M>;
> +	clock-names = "24m";
> +	#phy-cells = <0>;
> +};
> 

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY
  2015-10-12 15:02       ` Kishon Vijay Abraham I
@ 2015-10-13  1:20         ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-13  1:20 UTC (permalink / raw)
  To: Kishon Vijay Abraham I, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Pawel Moll, ajaynumb, robherring2, javier, Andy Yan, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Kishon

On 10/12/2015 11:02 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you want DP works rightly on rockchip platform,
>> then you should select both of them.
> Add phy driver for the Rockchip DisplayPort PHY module. This is required
> to get DisplayPort working in Rockchip SoCs.

Thanks, take point.

>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v6: None
>> Changes in v5:
>> - Remove "reg" DT property, cause driver could poweron/poweroff phy via
>>    the exist "grf" syscon already. And rename the example DT node from
>>    "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
>> - Add deivce_node at the front of driver, update phy_ops type from "static
>>    struct" to "static const struct". And correct the input paramters of
>>    devm_phy_create() interfaces. (Heiko)
>>
>> Changes in v4:
>> - Add commit message, and remove the redundant rockchip_dp_phy_init()
>>    function, move those code to probe() method. And remove driver .owner
>>    number. (Kishon)
>>
>> Changes in v3:
>> - Suggest, add rockchip dp phy driver, collect the phy clocks and
>>    power control. (Heiko)
>>
>> Changes in v2: None
>>
>>   drivers/phy/Kconfig           |   7 ++
>>   drivers/phy/Makefile          |   1 +
>>   drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
>>   3 files changed, 159 insertions(+)
>>   create mode 100644 drivers/phy/phy-rockchip-dp.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 47da573..8f2bc4f 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>>   	help
>>   	  Enable this to support the Rockchip USB 2.0 PHY.
>>   
>> +config PHY_ROCKCHIP_DP
>> +	tristate "Rockchip Display Port PHY Driver"
>> +	depends on ARCH_ROCKCHIP && OF
>> +	select GENERIC_PHY
>> +	help
>> +	  Enable this to support the Rockchip Display Port PHY.
>> +
>>   config PHY_ST_SPEAR1310_MIPHY
>>   	tristate "ST SPEAR1310-MIPHY driver"
>>   	select GENERIC_PHY
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a5b18c1..e281f35 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
>>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>> +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
>>   obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
>> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
>> new file mode 100644
>> index 0000000..3a2ac120
>> --- /dev/null
>> +++ b/drivers/phy/phy-rockchip-dp.c
>> @@ -0,0 +1,151 @@
>> +/*
>> + * Rockchip DP PHY driver
>> + *
>> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
>> + * Author: Yakir Yang <ykk@@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define GRF_SOC_CON12                   0x0274
>> +#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
>> +#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
>> +#define GRF_EDP_PHY_SIDDQ_ON            0
>> +#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
>> +
>> +struct rockchip_dp_phy {
>> +	struct device  *dev;
>> +	struct regmap  *grf;
>> +	struct clk     *phy_24m;
>> +};
>> +
>> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
>> +{
>> +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
>> +	int ret;
>> +
>> +	if (enable) {
>> +		ret = clk_prepare_enable(dp->phy_24m);
>> +		if (ret < 0) {
>> +			dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
>> +			return ret;
>> +		}
>> +
>> +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
>> +				   GRF_EDP_PHY_SIDDQ_ON);
>> +	} else {
>> +		clk_disable_unprepare(dp->phy_24m);
> should clk_disable come after regmap_write? It'll be symmetric to enable?

I don't see there is a strict limit about this, but thanks for your point, I
would like to change this order to:

     if (enable) {
         // Enable SIDDQ power
         // Enable Clock
     } else {
         // Disable Clock
         // Disable SIDDQ power
     }

>> +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
>> +				   GRF_EDP_PHY_SIDDQ_OFF);
> Is this syscon register used only by Display Port PHY? Better to use
> regmap_update API?

Thanks to Heiko explain, writing you actually need to set the
write-enable bit, some kind of hardware regmap_update.


Thanks,
- Yakir

> Thanks
> Kishon
>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY
@ 2015-10-13  1:20         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-13  1:20 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Kishon

On 10/12/2015 11:02 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you want DP works rightly on rockchip platform,
>> then you should select both of them.
> Add phy driver for the Rockchip DisplayPort PHY module. This is required
> to get DisplayPort working in Rockchip SoCs.

Thanks, take point.

>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v6: None
>> Changes in v5:
>> - Remove "reg" DT property, cause driver could poweron/poweroff phy via
>>    the exist "grf" syscon already. And rename the example DT node from
>>    "edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
>> - Add deivce_node at the front of driver, update phy_ops type from "static
>>    struct" to "static const struct". And correct the input paramters of
>>    devm_phy_create() interfaces. (Heiko)
>>
>> Changes in v4:
>> - Add commit message, and remove the redundant rockchip_dp_phy_init()
>>    function, move those code to probe() method. And remove driver .owner
>>    number. (Kishon)
>>
>> Changes in v3:
>> - Suggest, add rockchip dp phy driver, collect the phy clocks and
>>    power control. (Heiko)
>>
>> Changes in v2: None
>>
>>   drivers/phy/Kconfig           |   7 ++
>>   drivers/phy/Makefile          |   1 +
>>   drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
>>   3 files changed, 159 insertions(+)
>>   create mode 100644 drivers/phy/phy-rockchip-dp.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 47da573..8f2bc4f 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -310,6 +310,13 @@ config PHY_ROCKCHIP_USB
>>   	help
>>   	  Enable this to support the Rockchip USB 2.0 PHY.
>>   
>> +config PHY_ROCKCHIP_DP
>> +	tristate "Rockchip Display Port PHY Driver"
>> +	depends on ARCH_ROCKCHIP && OF
>> +	select GENERIC_PHY
>> +	help
>> +	  Enable this to support the Rockchip Display Port PHY.
>> +
>>   config PHY_ST_SPEAR1310_MIPHY
>>   	tristate "ST SPEAR1310-MIPHY driver"
>>   	select GENERIC_PHY
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index a5b18c1..e281f35 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -34,6 +34,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
>>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
>>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>> +obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
>>   obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)	+= phy-qcom-ipq806x-sata.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o
>>   obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o
>> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
>> new file mode 100644
>> index 0000000..3a2ac120
>> --- /dev/null
>> +++ b/drivers/phy/phy-rockchip-dp.c
>> @@ -0,0 +1,151 @@
>> +/*
>> + * Rockchip DP PHY driver
>> + *
>> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
>> + * Author: Yakir Yang <ykk@@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define GRF_SOC_CON12                   0x0274
>> +#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
>> +#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
>> +#define GRF_EDP_PHY_SIDDQ_ON            0
>> +#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
>> +
>> +struct rockchip_dp_phy {
>> +	struct device  *dev;
>> +	struct regmap  *grf;
>> +	struct clk     *phy_24m;
>> +};
>> +
>> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
>> +{
>> +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
>> +	int ret;
>> +
>> +	if (enable) {
>> +		ret = clk_prepare_enable(dp->phy_24m);
>> +		if (ret < 0) {
>> +			dev_err(dp->dev, "Can't enable clock 24m %d\n", ret);
>> +			return ret;
>> +		}
>> +
>> +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
>> +				   GRF_EDP_PHY_SIDDQ_ON);
>> +	} else {
>> +		clk_disable_unprepare(dp->phy_24m);
> should clk_disable come after regmap_write? It'll be symmetric to enable?

I don't see there is a strict limit about this, but thanks for your point, I
would like to change this order to:

     if (enable) {
         // Enable SIDDQ power
         // Enable Clock
     } else {
         // Disable Clock
         // Disable SIDDQ power
     }

>> +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
>> +				   GRF_EDP_PHY_SIDDQ_OFF);
> Is this syscon register used only by Display Port PHY? Better to use
> regmap_update API?

Thanks to Heiko explain, writing you actually need to set the
write-enable bit, some kind of hardware regmap_update.


Thanks,
- Yakir

> Thanks
> Kishon
>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy
  2015-10-12 22:28       ` Kishon Vijay Abraham I
@ 2015-10-13  1:21         ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-13  1:21 UTC (permalink / raw)
  To: Kishon Vijay Abraham I, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Pawel Moll, ajaynumb, robherring2, javier, Andy Yan, dri-devel,
	devicetree, linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Hi Kishon,

On 10/13/2015 06:28 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
>> This phy driver is binded with the Rockchip DisplayPort
>> driver, here are the brief properties:
>> 	edp_phy: edp-phy@ff770274 {
>> 		compatible = "rockchip,rk3288-dp-phy";
>> 		rockchip,grf = <&grf>;
>> 		clocks = <&cru SCLK_EDP_24M>;
>> 		clock-names = "24m";
>> 		#phy-cells = <0>;
>> 	};
> The commit message can simply be "Add dt binding documentation for
> rockchip display port PHY".

Okay, thanks.

- Yakir

>
> Thanks
> Kishon
>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v6: None
>> Changes in v5:
>> - Split binding doc's from driver changes. (Rob)
>> - Update the rockchip,grf explain in document, and correct the clock required
>>    elemets in document. (Rob & Heiko)
>>
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>>   .../devicetree/bindings/phy/rockchip-dp-phy.txt    | 22 ++++++++++++++++++++++
>>   1 file changed, 22 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> new file mode 100644
>> index 0000000..505194e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> @@ -0,0 +1,22 @@
>> +Rockchip Soc Seroes Display Port PHY
>> +------------------------------------
>> +
>> +Required properties:
>> +- compatible : should be one of the following supported values:
>> +	 - "rockchip.rk3288-dp-phy"
>> +- clocks: from common clock binding: handle to dp clock.
>> +	of memory mapped region.
>> +- clock-names: from common clock binding:
>> +	Required elements: "24m"
>> +- rockchip,grf: phandle to the syscon managing the "general register files"
>> +- #phy-cells : from the generic PHY bindings, must be 0;
>> +
>> +Example:
>> +
>> +edp_phy: edp-phy@ff770274 {
>> +	compatible = "rockchip,rk3288-dp-phy";
>> +	rockchip,grf = <&grf>;
>> +	clocks = <&cru SCLK_EDP_24M>;
>> +	clock-names = "24m";
>> +	#phy-cells = <0>;
>> +};
>>
>
>



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy
@ 2015-10-13  1:21         ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-13  1:21 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Kishon,

On 10/13/2015 06:28 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
>> This phy driver is binded with the Rockchip DisplayPort
>> driver, here are the brief properties:
>> 	edp_phy: edp-phy at ff770274 {
>> 		compatible = "rockchip,rk3288-dp-phy";
>> 		rockchip,grf = <&grf>;
>> 		clocks = <&cru SCLK_EDP_24M>;
>> 		clock-names = "24m";
>> 		#phy-cells = <0>;
>> 	};
> The commit message can simply be "Add dt binding documentation for
> rockchip display port PHY".

Okay, thanks.

- Yakir

>
> Thanks
> Kishon
>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
>> Changes in v6: None
>> Changes in v5:
>> - Split binding doc's from driver changes. (Rob)
>> - Update the rockchip,grf explain in document, and correct the clock required
>>    elemets in document. (Rob & Heiko)
>>
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>>   .../devicetree/bindings/phy/rockchip-dp-phy.txt    | 22 ++++++++++++++++++++++
>>   1 file changed, 22 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> new file mode 100644
>> index 0000000..505194e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> @@ -0,0 +1,22 @@
>> +Rockchip Soc Seroes Display Port PHY
>> +------------------------------------
>> +
>> +Required properties:
>> +- compatible : should be one of the following supported values:
>> +	 - "rockchip.rk3288-dp-phy"
>> +- clocks: from common clock binding: handle to dp clock.
>> +	of memory mapped region.
>> +- clock-names: from common clock binding:
>> +	Required elements: "24m"
>> +- rockchip,grf: phandle to the syscon managing the "general register files"
>> +- #phy-cells : from the generic PHY bindings, must be 0;
>> +
>> +Example:
>> +
>> +edp_phy: edp-phy at ff770274 {
>> +	compatible = "rockchip,rk3288-dp-phy";
>> +	rockchip,grf = <&grf>;
>> +	clocks = <&cru SCLK_EDP_24M>;
>> +	clock-names = "24m";
>> +	#phy-cells = <0>;
>> +};
>>
>
>

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-13  9:21                     ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-13  9:21 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hello Yakir,

Sorry for the delay but I was on holidays.

On 10/10/2015 04:31 PM, Yakir Yang wrote:
> Hi Javier,

[snip]

>>>
>>>> Maybe you can email me the method the run mainline kernel on Peach
>>>> Pit, so I can debug the analogix_dp driver at the same time, that would
>>>> be great.
>>> I wrote a little blog post explaining how to run mainline on these boards:
>>>
>>> http://blogs.s-osg.org/install-linux-mainline-kernel-distro-exynos-chromebooks/
>>>
>>> That explains the simplest setup though so if you need a different one
>>> (i.e: chain loading a non verified u-boot) or if you have any questions,
>>> feel free to contact me in private and I can help you with the setup.
>>>
>>
>> Ah, thanks, gonna to step-by-step.
> 
> Thanks for your great material, although I meet some problems in the step-by-step
> process, and failed at this way to setup mainline kernel environment on Exynos chromebooks.
> 
> But i do find another way to install mainline kernel to Exynos Chromebook:
> 1. Install any ChromeOS image into a USB media device (like dd tools)
> 2. "enable_dev_usb_boot" on Exynos chromebooks which would allowed boot from USB.
> 3. Flash the mainline kernel into the KERNEL-A and KERNEL-B partitions on host PC.
> 4. Insert USB device into Exynos chromebooks, and press CTRL+U, boot into USB OS.

Yes, as I mentioned in the blog, there are many options. In fact I also boot from
a uSD instead of the eMMC since is easier for me to flash from the host machine
and chain load a non-verified u-boot so I can boot non signed kernels.

But thought that the most common use case would be to install it in the KERN-C and
ROOT-C partitions in the eMMC. Anyways, I'm glad that you got it working.

> 
> And it's better to enable pstore function on mainline kernel, so we can analysis the last log when
> the mainline kernel crashed. After enable PSTORE_RAM in .config, we still need add ramoops node

Interesting, I knew about pstore but I never used it with the Exynos Chromebooks.

> into file, like:
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -750,6 +750,15 @@
>                 iommu = <&sysmmu_gsc3>;
>         };
> 
> +       ramoops: ramoops {
> +               compatible = "ramoops";
> +               name = "ramoops";
> +               reg = <0x41f00000 0x100000>;
> +               record-size = <0x20000>;
> +               dump-oops;
> +               status = "okay";
> +       };
> +

Are you using mainline? There isn't a "ramoops" compatible string documented
in the upstream DT bindings, platform_match() would match by driver name as
a fallback but I don't see code in fs/pstore/ram.c that parses the properties
in your device node. I wonder how this works for you or did I missunderstand?

>         hdmi: hdmi {
>                 compatible = "samsung,exynos4212-hdmi";
>                 reg = <0x14530000 0x70000>;
> 
> 
> Aha, I have tested this series on two Exynos Chromebooks that I borrowed(Snow and Peach Pit)
> with previously method (actually I believed it's a common method without broken the original
> ChromeOS image).
> 
> And I do find the crash place that make you failed at this series, here is the diff changes:
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index 5f8fc11..bcbc009 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -1169,6 +1169,7 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
> 
>         dp->bridge = bridge;
> 
> +       dp->encoder->bridge = bridge;
>         bridge->driver_private = dp;
>         bridge->encoder = dp->encoder;
>         bridge->funcs = &analogix_dp_bridge_funcs;
> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> @@ -151,7 +151,7 @@
>         samsung,color-depth = <1>;
>         samsung,link-rate = <0x06>;
>         samsung,lane-count = <2>;
> -       hpd-gpio = <&gpx2 6 0>;
> +       hpd-gpios = <&gpx2 6 0>;
> 
>         ports {
>                 port@0 {
> 
> 
> Anyway I'm going to send the v6 series, thanks for your good idea.
>

Great, I'll try to test your latest series on my Peach Pi today.

> - Yakir
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-13  9:21                     ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-13  9:21 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Hello Yakir,

Sorry for the delay but I was on holidays.

On 10/10/2015 04:31 PM, Yakir Yang wrote:
> Hi Javier,

[snip]

>>>
>>>> Maybe you can email me the method the run mainline kernel on Peach
>>>> Pit, so I can debug the analogix_dp driver at the same time, that would
>>>> be great.
>>> I wrote a little blog post explaining how to run mainline on these boards:
>>>
>>> http://blogs.s-osg.org/install-linux-mainline-kernel-distro-exynos-chromebooks/
>>>
>>> That explains the simplest setup though so if you need a different one
>>> (i.e: chain loading a non verified u-boot) or if you have any questions,
>>> feel free to contact me in private and I can help you with the setup.
>>>
>>
>> Ah, thanks, gonna to step-by-step.
> 
> Thanks for your great material, although I meet some problems in the step-by-step
> process, and failed at this way to setup mainline kernel environment on Exynos chromebooks.
> 
> But i do find another way to install mainline kernel to Exynos Chromebook:
> 1. Install any ChromeOS image into a USB media device (like dd tools)
> 2. "enable_dev_usb_boot" on Exynos chromebooks which would allowed boot from USB.
> 3. Flash the mainline kernel into the KERNEL-A and KERNEL-B partitions on host PC.
> 4. Insert USB device into Exynos chromebooks, and press CTRL+U, boot into USB OS.

Yes, as I mentioned in the blog, there are many options. In fact I also boot from
a uSD instead of the eMMC since is easier for me to flash from the host machine
and chain load a non-verified u-boot so I can boot non signed kernels.

But thought that the most common use case would be to install it in the KERN-C and
ROOT-C partitions in the eMMC. Anyways, I'm glad that you got it working.

> 
> And it's better to enable pstore function on mainline kernel, so we can analysis the last log when
> the mainline kernel crashed. After enable PSTORE_RAM in .config, we still need add ramoops node

Interesting, I knew about pstore but I never used it with the Exynos Chromebooks.

> into file, like:
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -750,6 +750,15 @@
>                 iommu = <&sysmmu_gsc3>;
>         };
> 
> +       ramoops: ramoops {
> +               compatible = "ramoops";
> +               name = "ramoops";
> +               reg = <0x41f00000 0x100000>;
> +               record-size = <0x20000>;
> +               dump-oops;
> +               status = "okay";
> +       };
> +

Are you using mainline? There isn't a "ramoops" compatible string documented
in the upstream DT bindings, platform_match() would match by driver name as
a fallback but I don't see code in fs/pstore/ram.c that parses the properties
in your device node. I wonder how this works for you or did I missunderstand?

>         hdmi: hdmi {
>                 compatible = "samsung,exynos4212-hdmi";
>                 reg = <0x14530000 0x70000>;
> 
> 
> Aha, I have tested this series on two Exynos Chromebooks that I borrowed(Snow and Peach Pit)
> with previously method (actually I believed it's a common method without broken the original
> ChromeOS image).
> 
> And I do find the crash place that make you failed at this series, here is the diff changes:
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index 5f8fc11..bcbc009 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -1169,6 +1169,7 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
> 
>         dp->bridge = bridge;
> 
> +       dp->encoder->bridge = bridge;
>         bridge->driver_private = dp;
>         bridge->encoder = dp->encoder;
>         bridge->funcs = &analogix_dp_bridge_funcs;
> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> @@ -151,7 +151,7 @@
>         samsung,color-depth = <1>;
>         samsung,link-rate = <0x06>;
>         samsung,lane-count = <2>;
> -       hpd-gpio = <&gpx2 6 0>;
> +       hpd-gpios = <&gpx2 6 0>;
> 
>         ports {
>                 port@0 {
> 
> 
> Anyway I'm going to send the v6 series, thanks for your good idea.
>

Great, I'll try to test your latest series on my Peach Pi today.

> - Yakir
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-13  9:21                     ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-13  9:21 UTC (permalink / raw)
  To: linux-arm-kernel

Hello Yakir,

Sorry for the delay but I was on holidays.

On 10/10/2015 04:31 PM, Yakir Yang wrote:
> Hi Javier,

[snip]

>>>
>>>> Maybe you can email me the method the run mainline kernel on Peach
>>>> Pit, so I can debug the analogix_dp driver at the same time, that would
>>>> be great.
>>> I wrote a little blog post explaining how to run mainline on these boards:
>>>
>>> http://blogs.s-osg.org/install-linux-mainline-kernel-distro-exynos-chromebooks/
>>>
>>> That explains the simplest setup though so if you need a different one
>>> (i.e: chain loading a non verified u-boot) or if you have any questions,
>>> feel free to contact me in private and I can help you with the setup.
>>>
>>
>> Ah, thanks, gonna to step-by-step.
> 
> Thanks for your great material, although I meet some problems in the step-by-step
> process, and failed at this way to setup mainline kernel environment on Exynos chromebooks.
> 
> But i do find another way to install mainline kernel to Exynos Chromebook:
> 1. Install any ChromeOS image into a USB media device (like dd tools)
> 2. "enable_dev_usb_boot" on Exynos chromebooks which would allowed boot from USB.
> 3. Flash the mainline kernel into the KERNEL-A and KERNEL-B partitions on host PC.
> 4. Insert USB device into Exynos chromebooks, and press CTRL+U, boot into USB OS.

Yes, as I mentioned in the blog, there are many options. In fact I also boot from
a uSD instead of the eMMC since is easier for me to flash from the host machine
and chain load a non-verified u-boot so I can boot non signed kernels.

But thought that the most common use case would be to install it in the KERN-C and
ROOT-C partitions in the eMMC. Anyways, I'm glad that you got it working.

> 
> And it's better to enable pstore function on mainline kernel, so we can analysis the last log when
> the mainline kernel crashed. After enable PSTORE_RAM in .config, we still need add ramoops node

Interesting, I knew about pstore but I never used it with the Exynos Chromebooks.

> into file, like:
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -750,6 +750,15 @@
>                 iommu = <&sysmmu_gsc3>;
>         };
> 
> +       ramoops: ramoops {
> +               compatible = "ramoops";
> +               name = "ramoops";
> +               reg = <0x41f00000 0x100000>;
> +               record-size = <0x20000>;
> +               dump-oops;
> +               status = "okay";
> +       };
> +

Are you using mainline? There isn't a "ramoops" compatible string documented
in the upstream DT bindings, platform_match() would match by driver name as
a fallback but I don't see code in fs/pstore/ram.c that parses the properties
in your device node. I wonder how this works for you or did I missunderstand?

>         hdmi: hdmi {
>                 compatible = "samsung,exynos4212-hdmi";
>                 reg = <0x14530000 0x70000>;
> 
> 
> Aha, I have tested this series on two Exynos Chromebooks that I borrowed(Snow and Peach Pit)
> with previously method (actually I believed it's a common method without broken the original
> ChromeOS image).
> 
> And I do find the crash place that make you failed at this series, here is the diff changes:
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index 5f8fc11..bcbc009 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -1169,6 +1169,7 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
> 
>         dp->bridge = bridge;
> 
> +       dp->encoder->bridge = bridge;
>         bridge->driver_private = dp;
>         bridge->encoder = dp->encoder;
>         bridge->funcs = &analogix_dp_bridge_funcs;
> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
> @@ -151,7 +151,7 @@
>         samsung,color-depth = <1>;
>         samsung,link-rate = <0x06>;
>         samsung,lane-count = <2>;
> -       hpd-gpio = <&gpx2 6 0>;
> +       hpd-gpios = <&gpx2 6 0>;
> 
>         ports {
>                 port at 0 {
> 
> 
> Anyway I'm going to send the v6 series, thanks for your good idea.
>

Great, I'll try to test your latest series on my Peach Pi today.

> - Yakir
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
  2015-10-13  9:21                     ` Javier Martinez Canillas
@ 2015-10-13 13:50                       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-13 13:50 UTC (permalink / raw)
  To: Javier Martinez Canillas, Inki Dae, Andrzej Hajda,
	Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, Jingoo Han,
	Heiko Stuebner, Mark Yao, Thierry Reding, joe,
	Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hi Javierm

On 10/13/2015 05:21 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> Sorry for the delay but I was on holidays.
>
> On 10/10/2015 04:31 PM, Yakir Yang wrote:
>> Hi Javier,
> [snip]
>
>>>>> Maybe you can email me the method the run mainline kernel on Peach
>>>>> Pit, so I can debug the analogix_dp driver at the same time, that would
>>>>> be great.
>>>> I wrote a little blog post explaining how to run mainline on these boards:
>>>>
>>>> http://blogs.s-osg.org/install-linux-mainline-kernel-distro-exynos-chromebooks/
>>>>
>>>> That explains the simplest setup though so if you need a different one
>>>> (i.e: chain loading a non verified u-boot) or if you have any questions,
>>>> feel free to contact me in private and I can help you with the setup.
>>>>
>>> Ah, thanks, gonna to step-by-step.
>> Thanks for your great material, although I meet some problems in the step-by-step
>> process, and failed at this way to setup mainline kernel environment on Exynos chromebooks.
>>
>> But i do find another way to install mainline kernel to Exynos Chromebook:
>> 1. Install any ChromeOS image into a USB media device (like dd tools)
>> 2. "enable_dev_usb_boot" on Exynos chromebooks which would allowed boot from USB.
>> 3. Flash the mainline kernel into the KERNEL-A and KERNEL-B partitions on host PC.
>> 4. Insert USB device into Exynos chromebooks, and press CTRL+U, boot into USB OS.
> Yes, as I mentioned in the blog, there are many options. In fact I also boot from
> a uSD instead of the eMMC since is easier for me to flash from the host machine
> and chain load a non-verified u-boot so I can boot non signed kernels.
>
> But thought that the most common use case would be to install it in the KERN-C and
> ROOT-C partitions in the eMMC. Anyways, I'm glad that you got it working.

:-P

>> And it's better to enable pstore function on mainline kernel, so we can analysis the last log when
>> the mainline kernel crashed. After enable PSTORE_RAM in .config, we still need add ramoops node
> Interesting, I knew about pstore but I never used it with the Exynos Chromebooks.
>
>> into file, like:
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -750,6 +750,15 @@
>>                  iommu = <&sysmmu_gsc3>;
>>          };
>>
>> +       ramoops: ramoops {
>> +               compatible = "ramoops";
>> +               name = "ramoops";
>> +               reg = <0x41f00000 0x100000>;
>> +               record-size = <0x20000>;
>> +               dump-oops;
>> +               status = "okay";
>> +       };
>> +
> Are you using mainline? There isn't a "ramoops" compatible string documented
> in the upstream DT bindings, platform_match() would match by driver name as
> a fallback but I don't see code in fs/pstore/ram.c that parses the properties
> in your device node. I wonder how this works for you or did I missunderstand?

Aha, I lost some things that I back port the pstore/ram.c from chrome
v3.14 tree which driver would parsed the "ramoops" compatible.

And those "ramoops" device node should be structured by bootloader in
chromeos, so we won't see anything about "ramoops" in DT binding. Due
to I can't upgraded the loader of Peach Pit, so I chose to structure that
device manually. (detailed properties just `cat 
/proc/device-tree/ramoops/*`)

>
>>          hdmi: hdmi {
>>                  compatible = "samsung,exynos4212-hdmi";
>>                  reg = <0x14530000 0x70000>;
>>
>>
>> Aha, I have tested this series on two Exynos Chromebooks that I borrowed(Snow and Peach Pit)
>> with previously method (actually I believed it's a common method without broken the original
>> ChromeOS image).
>>
>> And I do find the crash place that make you failed at this series, here is the diff changes:
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index 5f8fc11..bcbc009 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -1169,6 +1169,7 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>>
>>          dp->bridge = bridge;
>>
>> +       dp->encoder->bridge = bridge;
>>          bridge->driver_private = dp;
>>          bridge->encoder = dp->encoder;
>>          bridge->funcs = &analogix_dp_bridge_funcs;
>> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
>> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
>> @@ -151,7 +151,7 @@
>>          samsung,color-depth = <1>;
>>          samsung,link-rate = <0x06>;
>>          samsung,lane-count = <2>;
>> -       hpd-gpio = <&gpx2 6 0>;
>> +       hpd-gpios = <&gpx2 6 0>;
>>
>>          ports {
>>                  port@0 {
>>
>>
>> Anyway I'm going to send the v6 series, thanks for your good idea.
>>
> Great, I'll try to test your latest series on my Peach Pi today.

Thanks

- Yakir
>
>> - Yakir
>>
> Best regards,



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-13 13:50                       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-13 13:50 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Javierm

On 10/13/2015 05:21 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> Sorry for the delay but I was on holidays.
>
> On 10/10/2015 04:31 PM, Yakir Yang wrote:
>> Hi Javier,
> [snip]
>
>>>>> Maybe you can email me the method the run mainline kernel on Peach
>>>>> Pit, so I can debug the analogix_dp driver at the same time, that would
>>>>> be great.
>>>> I wrote a little blog post explaining how to run mainline on these boards:
>>>>
>>>> http://blogs.s-osg.org/install-linux-mainline-kernel-distro-exynos-chromebooks/
>>>>
>>>> That explains the simplest setup though so if you need a different one
>>>> (i.e: chain loading a non verified u-boot) or if you have any questions,
>>>> feel free to contact me in private and I can help you with the setup.
>>>>
>>> Ah, thanks, gonna to step-by-step.
>> Thanks for your great material, although I meet some problems in the step-by-step
>> process, and failed at this way to setup mainline kernel environment on Exynos chromebooks.
>>
>> But i do find another way to install mainline kernel to Exynos Chromebook:
>> 1. Install any ChromeOS image into a USB media device (like dd tools)
>> 2. "enable_dev_usb_boot" on Exynos chromebooks which would allowed boot from USB.
>> 3. Flash the mainline kernel into the KERNEL-A and KERNEL-B partitions on host PC.
>> 4. Insert USB device into Exynos chromebooks, and press CTRL+U, boot into USB OS.
> Yes, as I mentioned in the blog, there are many options. In fact I also boot from
> a uSD instead of the eMMC since is easier for me to flash from the host machine
> and chain load a non-verified u-boot so I can boot non signed kernels.
>
> But thought that the most common use case would be to install it in the KERN-C and
> ROOT-C partitions in the eMMC. Anyways, I'm glad that you got it working.

:-P

>> And it's better to enable pstore function on mainline kernel, so we can analysis the last log when
>> the mainline kernel crashed. After enable PSTORE_RAM in .config, we still need add ramoops node
> Interesting, I knew about pstore but I never used it with the Exynos Chromebooks.
>
>> into file, like:
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -750,6 +750,15 @@
>>                  iommu = <&sysmmu_gsc3>;
>>          };
>>
>> +       ramoops: ramoops {
>> +               compatible = "ramoops";
>> +               name = "ramoops";
>> +               reg = <0x41f00000 0x100000>;
>> +               record-size = <0x20000>;
>> +               dump-oops;
>> +               status = "okay";
>> +       };
>> +
> Are you using mainline? There isn't a "ramoops" compatible string documented
> in the upstream DT bindings, platform_match() would match by driver name as
> a fallback but I don't see code in fs/pstore/ram.c that parses the properties
> in your device node. I wonder how this works for you or did I missunderstand?

Aha, I lost some things that I back port the pstore/ram.c from chrome
v3.14 tree which driver would parsed the "ramoops" compatible.

And those "ramoops" device node should be structured by bootloader in
chromeos, so we won't see anything about "ramoops" in DT binding. Due
to I can't upgraded the loader of Peach Pit, so I chose to structure that
device manually. (detailed properties just `cat 
/proc/device-tree/ramoops/*`)

>
>>          hdmi: hdmi {
>>                  compatible = "samsung,exynos4212-hdmi";
>>                  reg = <0x14530000 0x70000>;
>>
>>
>> Aha, I have tested this series on two Exynos Chromebooks that I borrowed(Snow and Peach Pit)
>> with previously method (actually I believed it's a common method without broken the original
>> ChromeOS image).
>>
>> And I do find the crash place that make you failed at this series, here is the diff changes:
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> index 5f8fc11..bcbc009 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -1169,6 +1169,7 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
>>
>>          dp->bridge = bridge;
>>
>> +       dp->encoder->bridge = bridge;
>>          bridge->driver_private = dp;
>>          bridge->encoder = dp->encoder;
>>          bridge->funcs = &analogix_dp_bridge_funcs;
>> --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
>> +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
>> @@ -151,7 +151,7 @@
>>          samsung,color-depth = <1>;
>>          samsung,link-rate = <0x06>;
>>          samsung,lane-count = <2>;
>> -       hpd-gpio = <&gpx2 6 0>;
>> +       hpd-gpios = <&gpx2 6 0>;
>>
>>          ports {
>>                  port at 0 {
>>
>>
>> Anyway I'm going to send the v6 series, thanks for your good idea.
>>
> Great, I'll try to test your latest series on my Peach Pi today.

Thanks

- Yakir
>
>> - Yakir
>>
> Best regards,

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-14  8:18                         ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-14  8:18 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe, Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz, dianders, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, Andy Yan, dri-devel, devicetree, linux-kernel,
	linux-samsung-soc, linux-rockchip, linux-arm-kernel

Hello Yakir,

On 10/13/2015 03:50 PM, Yakir Yang wrote:
> On 10/13/2015 05:21 PM, Javier Martinez Canillas wrote:
> 

[snip]

>>> And it's better to enable pstore function on mainline kernel, so we can analysis the last log when
>>> the mainline kernel crashed. After enable PSTORE_RAM in .config, we still need add ramoops node
>> Interesting, I knew about pstore but I never used it with the Exynos Chromebooks.
>>
>>> into file, like:
>>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>>> @@ -750,6 +750,15 @@
>>>                  iommu = <&sysmmu_gsc3>;
>>>          };
>>>
>>> +       ramoops: ramoops {
>>> +               compatible = "ramoops";
>>> +               name = "ramoops";
>>> +               reg = <0x41f00000 0x100000>;
>>> +               record-size = <0x20000>;
>>> +               dump-oops;
>>> +               status = "okay";
>>> +       };
>>> +
>> Are you using mainline? There isn't a "ramoops" compatible string documented
>> in the upstream DT bindings, platform_match() would match by driver name as
>> a fallback but I don't see code in fs/pstore/ram.c that parses the properties
>> in your device node. I wonder how this works for you or did I missunderstand?
> 
> Aha, I lost some things that I back port the pstore/ram.c from chrome
> v3.14 tree which driver would parsed the "ramoops" compatible.
>

Ah, that explains it then.

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-14  8:18                         ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-14  8:18 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Heiko Stuebner,
	Mark Yao, Thierry Reding, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Krzysztof Kozlowski, Rob Herring
  Cc: David Airlie, Russell King, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Hello Yakir,

On 10/13/2015 03:50 PM, Yakir Yang wrote:
> On 10/13/2015 05:21 PM, Javier Martinez Canillas wrote:
> 

[snip]

>>> And it's better to enable pstore function on mainline kernel, so we can analysis the last log when
>>> the mainline kernel crashed. After enable PSTORE_RAM in .config, we still need add ramoops node
>> Interesting, I knew about pstore but I never used it with the Exynos Chromebooks.
>>
>>> into file, like:
>>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>>> @@ -750,6 +750,15 @@
>>>                  iommu = <&sysmmu_gsc3>;
>>>          };
>>>
>>> +       ramoops: ramoops {
>>> +               compatible = "ramoops";
>>> +               name = "ramoops";
>>> +               reg = <0x41f00000 0x100000>;
>>> +               record-size = <0x20000>;
>>> +               dump-oops;
>>> +               status = "okay";
>>> +       };
>>> +
>> Are you using mainline? There isn't a "ramoops" compatible string documented
>> in the upstream DT bindings, platform_match() would match by driver name as
>> a fallback but I don't see code in fs/pstore/ram.c that parses the properties
>> in your device node. I wonder how this works for you or did I missunderstand?
> 
> Aha, I lost some things that I back port the pstore/ram.c from chrome
> v3.14 tree which driver would parsed the "ramoops" compatible.
>

Ah, that explains it then.

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v5 0/17] Add Analogix Core Display Port Driver
@ 2015-10-14  8:18                         ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-14  8:18 UTC (permalink / raw)
  To: linux-arm-kernel

Hello Yakir,

On 10/13/2015 03:50 PM, Yakir Yang wrote:
> On 10/13/2015 05:21 PM, Javier Martinez Canillas wrote:
> 

[snip]

>>> And it's better to enable pstore function on mainline kernel, so we can analysis the last log when
>>> the mainline kernel crashed. After enable PSTORE_RAM in .config, we still need add ramoops node
>> Interesting, I knew about pstore but I never used it with the Exynos Chromebooks.
>>
>>> into file, like:
>>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>>> @@ -750,6 +750,15 @@
>>>                  iommu = <&sysmmu_gsc3>;
>>>          };
>>>
>>> +       ramoops: ramoops {
>>> +               compatible = "ramoops";
>>> +               name = "ramoops";
>>> +               reg = <0x41f00000 0x100000>;
>>> +               record-size = <0x20000>;
>>> +               dump-oops;
>>> +               status = "okay";
>>> +       };
>>> +
>> Are you using mainline? There isn't a "ramoops" compatible string documented
>> in the upstream DT bindings, platform_match() would match by driver name as
>> a fallback but I don't see code in fs/pstore/ram.c that parses the properties
>> in your device node. I wonder how this works for you or did I missunderstand?
> 
> Aha, I lost some things that I back port the pstore/ram.c from chrome
> v3.14 tree which driver would parsed the "ramoops" compatible.
>

Ah, that explains it then.

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 0/17] Add Analogix Core Display Port Driver
@ 2015-10-19 10:40     ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-19 10:40 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	Andy Yan, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Hello Yakir,

On 10/10/2015 05:35 PM, Yakir Yang wrote:
> 
> Hi all,
> 
>    The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM :)
> 
> But  there are still three light registers setting differents bewteen
> exynos and rk3288.
> 1. RK3288 have five special pll resigters which not indicata in exynos
>    dp controller.
> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>    between rk3288 and exynos.
> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>    register).
> 
> This series have been well tested on Rockchip platform with eDP panel
> on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
> to Javier@Samsung help me to find a way to install mainline kernel to
> Samsung Exynos Chromebooks, so this series also have been tested on Samsung
> Snow and Peach Pit Chromebooks which borrowed from my friends.
> 
> Besides, This version was build on linux-next branch (tag next-20150918), and
> the above test experiments also base on that tag. But I know the latest tag is
> next-20151009, so i do rebase this series again on next-20151009, there were
> little conflicts(exynos_dp removed the suspend/resume).
> 
> But after I retest this series on next-20151009, I saw kernel crashed in mmc
> driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
> module(after all I boot with USB device), and I can see eDP light up normally
> in startup stage, but kernel keep crashed when it try to mount the filesystem.
> I thought this isn't related to dp driver directly, so i choice not to debug
> more depth.
> 
> That's to say if someone want to test this series, I suggest you applied this
> series on tag-20150918, just need to fix some light conflicts with the 01 & 02
> patches (or just email me, I can send you directly).
> 
> Thanks,

Do you have a branch that I can use to test this series?

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 0/17] Add Analogix Core Display Port Driver
@ 2015-10-19 10:40     ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-19 10:40 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Heiko Stuebner, Mark Yao
  Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, Russell King,
	Pawel Moll, Ian Campbell, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w,
	dianders-F7+t8E8rja9g9hUCZPvPmw, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	Kishon Vijay Abraham I,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kukjin Kim,
	Sean Paul, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	Kumar Gala, ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan, Gustavo Padovan,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Hello Yakir,

On 10/10/2015 05:35 PM, Yakir Yang wrote:
> 
> Hi all,
> 
>    The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM :)
> 
> But  there are still three light registers setting differents bewteen
> exynos and rk3288.
> 1. RK3288 have five special pll resigters which not indicata in exynos
>    dp controller.
> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>    between rk3288 and exynos.
> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>    register).
> 
> This series have been well tested on Rockchip platform with eDP panel
> on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
> to Javier@Samsung help me to find a way to install mainline kernel to
> Samsung Exynos Chromebooks, so this series also have been tested on Samsung
> Snow and Peach Pit Chromebooks which borrowed from my friends.
> 
> Besides, This version was build on linux-next branch (tag next-20150918), and
> the above test experiments also base on that tag. But I know the latest tag is
> next-20151009, so i do rebase this series again on next-20151009, there were
> little conflicts(exynos_dp removed the suspend/resume).
> 
> But after I retest this series on next-20151009, I saw kernel crashed in mmc
> driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
> module(after all I boot with USB device), and I can see eDP light up normally
> in startup stage, but kernel keep crashed when it try to mount the filesystem.
> I thought this isn't related to dp driver directly, so i choice not to debug
> more depth.
> 
> That's to say if someone want to test this series, I suggest you applied this
> series on tag-20150918, just need to fix some light conflicts with the 01 & 02
> patches (or just email me, I can send you directly).
> 
> Thanks,

Do you have a branch that I can use to test this series?

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 0/17] Add Analogix Core Display Port Driver
@ 2015-10-19 10:40     ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-19 10:40 UTC (permalink / raw)
  To: linux-arm-kernel

Hello Yakir,

On 10/10/2015 05:35 PM, Yakir Yang wrote:
> 
> Hi all,
> 
>    The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM :)
> 
> But  there are still three light registers setting differents bewteen
> exynos and rk3288.
> 1. RK3288 have five special pll resigters which not indicata in exynos
>    dp controller.
> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>    between rk3288 and exynos.
> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>    register).
> 
> This series have been well tested on Rockchip platform with eDP panel
> on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
> to Javier at Samsung help me to find a way to install mainline kernel to
> Samsung Exynos Chromebooks, so this series also have been tested on Samsung
> Snow and Peach Pit Chromebooks which borrowed from my friends.
> 
> Besides, This version was build on linux-next branch (tag next-20150918), and
> the above test experiments also base on that tag. But I know the latest tag is
> next-20151009, so i do rebase this series again on next-20151009, there were
> little conflicts(exynos_dp removed the suspend/resume).
> 
> But after I retest this series on next-20151009, I saw kernel crashed in mmc
> driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
> module(after all I boot with USB device), and I can see eDP light up normally
> in startup stage, but kernel keep crashed when it try to mount the filesystem.
> I thought this isn't related to dp driver directly, so i choice not to debug
> more depth.
> 
> That's to say if someone want to test this series, I suggest you applied this
> series on tag-20150918, just need to fix some light conflicts with the 01 & 02
> patches (or just email me, I can send you directly).
> 
> Thanks,

Do you have a branch that I can use to test this series?

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 0/17] Add Analogix Core Display Port Driver
  2015-10-19 10:40     ` Javier Martinez Canillas
@ 2015-10-20  2:10       ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-20  2:10 UTC (permalink / raw)
  To: Javier Martinez Canillas, Inki Dae, Andrzej Hajda,
	Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, Jingoo Han,
	Thierry Reding, Krzysztof Kozlowski, Rob Herring, joe,
	Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	Andy Yan, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Hi Javier,

On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/10/2015 05:35 PM, Yakir Yang wrote:
>> Hi all,
>>
>>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I split the common
>> code into bridge directory, then rk3288 and exynos only need to keep
>> some platform code. Cause I can't find the exact IP name of exynos dp
>> controller, so I decide to name dp core driver with "analogix" which I
>> find in rk3288 eDP TRM :)
>>
>> But  there are still three light registers setting differents bewteen
>> exynos and rk3288.
>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>     dp controller.
>> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>>     between rk3288 and exynos.
>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>>     register).
>>
>> This series have been well tested on Rockchip platform with eDP panel
>> on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
>> to Javier@Samsung help me to find a way to install mainline kernel to
>> Samsung Exynos Chromebooks, so this series also have been tested on Samsung
>> Snow and Peach Pit Chromebooks which borrowed from my friends.
>>
>> Besides, This version was build on linux-next branch (tag next-20150918), and
>> the above test experiments also base on that tag. But I know the latest tag is
>> next-20151009, so i do rebase this series again on next-20151009, there were
>> little conflicts(exynos_dp removed the suspend/resume).
>>
>> But after I retest this series on next-20151009, I saw kernel crashed in mmc
>> driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
>> module(after all I boot with USB device), and I can see eDP light up normally
>> in startup stage, but kernel keep crashed when it try to mount the filesystem.
>> I thought this isn't related to dp driver directly, so i choice not to debug
>> more depth.
>>
>> That's to say if someone want to test this series, I suggest you applied this
>> series on tag-20150918, just need to fix some light conflicts with the 01 & 02
>> patches (or just email me, I can send you directly).
>>
>> Thanks,
> Do you have a branch that I can use to test this series?

Thank you for your kind assistance, I have created a tree which checkout 
from the next-20151019. Surely there were some conflicts to applied this 
series on that tag, but things still works for me, here is the git 
address [https://github.com/yakir-Yang/linux/tree/analogix_dp]

Best regards,
- Yakir

>
> Best regards,



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 0/17] Add Analogix Core Display Port Driver
@ 2015-10-20  2:10       ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-20  2:10 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Javier,

On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/10/2015 05:35 PM, Yakir Yang wrote:
>> Hi all,
>>
>>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I split the common
>> code into bridge directory, then rk3288 and exynos only need to keep
>> some platform code. Cause I can't find the exact IP name of exynos dp
>> controller, so I decide to name dp core driver with "analogix" which I
>> find in rk3288 eDP TRM :)
>>
>> But  there are still three light registers setting differents bewteen
>> exynos and rk3288.
>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>     dp controller.
>> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>>     between rk3288 and exynos.
>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>>     register).
>>
>> This series have been well tested on Rockchip platform with eDP panel
>> on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
>> to Javier at Samsung help me to find a way to install mainline kernel to
>> Samsung Exynos Chromebooks, so this series also have been tested on Samsung
>> Snow and Peach Pit Chromebooks which borrowed from my friends.
>>
>> Besides, This version was build on linux-next branch (tag next-20150918), and
>> the above test experiments also base on that tag. But I know the latest tag is
>> next-20151009, so i do rebase this series again on next-20151009, there were
>> little conflicts(exynos_dp removed the suspend/resume).
>>
>> But after I retest this series on next-20151009, I saw kernel crashed in mmc
>> driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
>> module(after all I boot with USB device), and I can see eDP light up normally
>> in startup stage, but kernel keep crashed when it try to mount the filesystem.
>> I thought this isn't related to dp driver directly, so i choice not to debug
>> more depth.
>>
>> That's to say if someone want to test this series, I suggest you applied this
>> series on tag-20150918, just need to fix some light conflicts with the 01 & 02
>> patches (or just email me, I can send you directly).
>>
>> Thanks,
> Do you have a branch that I can use to test this series?

Thank you for your kind assistance, I have created a tree which checkout 
from the next-20151019. Surely there were some conflicts to applied this 
series on that tag, but things still works for me, here is the git 
address [https://github.com/yakir-Yang/linux/tree/analogix_dp]

Best regards,
- Yakir

>
> Best regards,

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 0/17] Add Analogix Core Display Port Driver
@ 2015-10-20  9:48         ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-20  9:48 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, joe, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	Andy Yan, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Hello Yakir,

On 10/20/2015 04:10 AM, Yakir Yang wrote:
> Hi Javier,
> 
> On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
>> Hello Yakir,
>>
>> On 10/10/2015 05:35 PM, Yakir Yang wrote:
>>> Hi all,
>>>
>>>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>>> share the same IP, so a lot of parts can be re-used. I split the common
>>> code into bridge directory, then rk3288 and exynos only need to keep
>>> some platform code. Cause I can't find the exact IP name of exynos dp
>>> controller, so I decide to name dp core driver with "analogix" which I
>>> find in rk3288 eDP TRM :)
>>>
>>> But  there are still three light registers setting differents bewteen
>>> exynos and rk3288.
>>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>>     dp controller.
>>> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>>>     between rk3288 and exynos.
>>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>>>     register).
>>>
>>> This series have been well tested on Rockchip platform with eDP panel
>>> on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
>>> to Javier@Samsung help me to find a way to install mainline kernel to
>>> Samsung Exynos Chromebooks, so this series also have been tested on Samsung
>>> Snow and Peach Pit Chromebooks which borrowed from my friends.
>>>
>>> Besides, This version was build on linux-next branch (tag next-20150918), and
>>> the above test experiments also base on that tag. But I know the latest tag is
>>> next-20151009, so i do rebase this series again on next-20151009, there were
>>> little conflicts(exynos_dp removed the suspend/resume).
>>>
>>> But after I retest this series on next-20151009, I saw kernel crashed in mmc
>>> driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
>>> module(after all I boot with USB device), and I can see eDP light up normally
>>> in startup stage, but kernel keep crashed when it try to mount the filesystem.
>>> I thought this isn't related to dp driver directly, so i choice not to debug
>>> more depth.
>>>
>>> That's to say if someone want to test this series, I suggest you applied this
>>> series on tag-20150918, just need to fix some light conflicts with the 01 & 02
>>> patches (or just email me, I can send you directly).
>>>
>>> Thanks,
>> Do you have a branch that I can use to test this series?
> 
> Thank you for your kind assistance, I have created a tree which checkout from the next-20151019. Surely there were some conflicts to applied this series on that tag, but things still works for me, here is the git address [https://github.com/yakir-Yang/linux/tree/analogix_dp]
>

I tested your branch on an Exynos5800 Peach Pi Chromebook and display is
working on boot. I also tested DPMS and S2R and things are still working
so for the whole series feel free to add:

Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>

> Best regards,
> - Yakir
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 0/17] Add Analogix Core Display Port Driver
@ 2015-10-20  9:48         ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-20  9:48 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, joe-6d6DIl74uiNBDgjK7y7TUQ,
	Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz-F7+t8E8rja9g9hUCZPvPmw,
	dianders-F7+t8E8rja9g9hUCZPvPmw, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll,
	ajaynumb-Re5JQEeQqe8AvxtiuMwx3w,
	robherring2-Re5JQEeQqe8AvxtiuMwx3w, Andy Yan,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Hello Yakir,

On 10/20/2015 04:10 AM, Yakir Yang wrote:
> Hi Javier,
> 
> On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
>> Hello Yakir,
>>
>> On 10/10/2015 05:35 PM, Yakir Yang wrote:
>>> Hi all,
>>>
>>>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>>> share the same IP, so a lot of parts can be re-used. I split the common
>>> code into bridge directory, then rk3288 and exynos only need to keep
>>> some platform code. Cause I can't find the exact IP name of exynos dp
>>> controller, so I decide to name dp core driver with "analogix" which I
>>> find in rk3288 eDP TRM :)
>>>
>>> But  there are still three light registers setting differents bewteen
>>> exynos and rk3288.
>>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>>     dp controller.
>>> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>>>     between rk3288 and exynos.
>>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>>>     register).
>>>
>>> This series have been well tested on Rockchip platform with eDP panel
>>> on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
>>> to Javier@Samsung help me to find a way to install mainline kernel to
>>> Samsung Exynos Chromebooks, so this series also have been tested on Samsung
>>> Snow and Peach Pit Chromebooks which borrowed from my friends.
>>>
>>> Besides, This version was build on linux-next branch (tag next-20150918), and
>>> the above test experiments also base on that tag. But I know the latest tag is
>>> next-20151009, so i do rebase this series again on next-20151009, there were
>>> little conflicts(exynos_dp removed the suspend/resume).
>>>
>>> But after I retest this series on next-20151009, I saw kernel crashed in mmc
>>> driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
>>> module(after all I boot with USB device), and I can see eDP light up normally
>>> in startup stage, but kernel keep crashed when it try to mount the filesystem.
>>> I thought this isn't related to dp driver directly, so i choice not to debug
>>> more depth.
>>>
>>> That's to say if someone want to test this series, I suggest you applied this
>>> series on tag-20150918, just need to fix some light conflicts with the 01 & 02
>>> patches (or just email me, I can send you directly).
>>>
>>> Thanks,
>> Do you have a branch that I can use to test this series?
> 
> Thank you for your kind assistance, I have created a tree which checkout from the next-20151019. Surely there were some conflicts to applied this series on that tag, but things still works for me, here is the git address [https://github.com/yakir-Yang/linux/tree/analogix_dp]
>

I tested your branch on an Exynos5800 Peach Pi Chromebook and display is
working on boot. I also tested DPMS and S2R and things are still working
so for the whole series feel free to add:

Tested-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>

> Best regards,
> - Yakir
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 0/17] Add Analogix Core Display Port Driver
@ 2015-10-20  9:48         ` Javier Martinez Canillas
  0 siblings, 0 replies; 370+ messages in thread
From: Javier Martinez Canillas @ 2015-10-20  9:48 UTC (permalink / raw)
  To: linux-arm-kernel

Hello Yakir,

On 10/20/2015 04:10 AM, Yakir Yang wrote:
> Hi Javier,
> 
> On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
>> Hello Yakir,
>>
>> On 10/10/2015 05:35 PM, Yakir Yang wrote:
>>> Hi all,
>>>
>>>     The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>>> share the same IP, so a lot of parts can be re-used. I split the common
>>> code into bridge directory, then rk3288 and exynos only need to keep
>>> some platform code. Cause I can't find the exact IP name of exynos dp
>>> controller, so I decide to name dp core driver with "analogix" which I
>>> find in rk3288 eDP TRM :)
>>>
>>> But  there are still three light registers setting differents bewteen
>>> exynos and rk3288.
>>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>>     dp controller.
>>> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>>>     between rk3288 and exynos.
>>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>>>     register).
>>>
>>> This series have been well tested on Rockchip platform with eDP panel
>>> on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
>>> to Javier at Samsung help me to find a way to install mainline kernel to
>>> Samsung Exynos Chromebooks, so this series also have been tested on Samsung
>>> Snow and Peach Pit Chromebooks which borrowed from my friends.
>>>
>>> Besides, This version was build on linux-next branch (tag next-20150918), and
>>> the above test experiments also base on that tag. But I know the latest tag is
>>> next-20151009, so i do rebase this series again on next-20151009, there were
>>> little conflicts(exynos_dp removed the suspend/resume).
>>>
>>> But after I retest this series on next-20151009, I saw kernel crashed in mmc
>>> driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
>>> module(after all I boot with USB device), and I can see eDP light up normally
>>> in startup stage, but kernel keep crashed when it try to mount the filesystem.
>>> I thought this isn't related to dp driver directly, so i choice not to debug
>>> more depth.
>>>
>>> That's to say if someone want to test this series, I suggest you applied this
>>> series on tag-20150918, just need to fix some light conflicts with the 01 & 02
>>> patches (or just email me, I can send you directly).
>>>
>>> Thanks,
>> Do you have a branch that I can use to test this series?
> 
> Thank you for your kind assistance, I have created a tree which checkout from the next-20151019. Surely there were some conflicts to applied this series on that tag, but things still works for me, here is the git address [https://github.com/yakir-Yang/linux/tree/analogix_dp]
>

I tested your branch on an Exynos5800 Peach Pi Chromebook and display is
working on boot. I also tested DPMS and S2R and things are still working
so for the whole series feel free to add:

Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>

> Best regards,
> - Yakir
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 370+ messages in thread
* Re: [PATCH v6 0/17] Add Analogix Core Display Port Driver
  2015-10-20  9:48         ` Javier Martinez Canillas
@ 2015-10-20 11:40           ` Yakir Yang
  -1 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-20 11:40 UTC (permalink / raw)
  To: Javier Martinez Canillas, Inki Dae, Andrzej Hajda,
	Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, Jingoo Han,
	Thierry Reding, Krzysztof Kozlowski, Rob Herring, joe,
	Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, dianders, Sean Paul, Kukjin Kim,
	Kumar Gala, emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	Andy Yan, dri-devel, devicetree, linux-kernel, linux-samsung-soc,
	linux-rockchip, linux-arm-kernel

Hi Javier,

On 10/20/2015 05:48 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/20/2015 04:10 AM, Yakir Yang wrote:
>> Hi Javier,
>>
>> On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
>>> Hello Yakir,
>>>
>>> On 10/10/2015 05:35 PM, Yakir Yang wrote:
>>>> Hi all,
>>>>
>>>>      The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>>>> share the same IP, so a lot of parts can be re-used. I split the common
>>>> code into bridge directory, then rk3288 and exynos only need to keep
>>>> some platform code. Cause I can't find the exact IP name of exynos dp
>>>> controller, so I decide to name dp core driver with "analogix" which I
>>>> find in rk3288 eDP TRM :)
>>>>
>>>> But  there are still three light registers setting differents bewteen
>>>> exynos and rk3288.
>>>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>>>      dp controller.
>>>> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>>>>      between rk3288 and exynos.
>>>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>>>>      register).
>>>>
>>>> This series have been well tested on Rockchip platform with eDP panel
>>>> on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
>>>> to Javier@Samsung help me to find a way to install mainline kernel to
>>>> Samsung Exynos Chromebooks, so this series also have been tested on Samsung
>>>> Snow and Peach Pit Chromebooks which borrowed from my friends.
>>>>
>>>> Besides, This version was build on linux-next branch (tag next-20150918), and
>>>> the above test experiments also base on that tag. But I know the latest tag is
>>>> next-20151009, so i do rebase this series again on next-20151009, there were
>>>> little conflicts(exynos_dp removed the suspend/resume).
>>>>
>>>> But after I retest this series on next-20151009, I saw kernel crashed in mmc
>>>> driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
>>>> module(after all I boot with USB device), and I can see eDP light up normally
>>>> in startup stage, but kernel keep crashed when it try to mount the filesystem.
>>>> I thought this isn't related to dp driver directly, so i choice not to debug
>>>> more depth.
>>>>
>>>> That's to say if someone want to test this series, I suggest you applied this
>>>> series on tag-20150918, just need to fix some light conflicts with the 01 & 02
>>>> patches (or just email me, I can send you directly).
>>>>
>>>> Thanks,
>>> Do you have a branch that I can use to test this series?
>> Thank you for your kind assistance, I have created a tree which checkout from the next-20151019. Surely there were some conflicts to applied this series on that tag, but things still works for me, here is the git address [https://github.com/yakir-Yang/linux/tree/analogix_dp]
>>
> I tested your branch on an Exynos5800 Peach Pi Chromebook and display is
> working on boot. I also tested DPMS and S2R and things are still working
> so for the whole series feel free to add:
>
> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>

Thanks a lot    ;)

- Yakir

>> Best regards,
>> - Yakir
>>
> Best regards,



^ permalink raw reply	[flat|nested] 370+ messages in thread
* [PATCH v6 0/17] Add Analogix Core Display Port Driver
@ 2015-10-20 11:40           ` Yakir Yang
  0 siblings, 0 replies; 370+ messages in thread
From: Yakir Yang @ 2015-10-20 11:40 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Javier,

On 10/20/2015 05:48 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/20/2015 04:10 AM, Yakir Yang wrote:
>> Hi Javier,
>>
>> On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
>>> Hello Yakir,
>>>
>>> On 10/10/2015 05:35 PM, Yakir Yang wrote:
>>>> Hi all,
>>>>
>>>>      The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>>>> share the same IP, so a lot of parts can be re-used. I split the common
>>>> code into bridge directory, then rk3288 and exynos only need to keep
>>>> some platform code. Cause I can't find the exact IP name of exynos dp
>>>> controller, so I decide to name dp core driver with "analogix" which I
>>>> find in rk3288 eDP TRM :)
>>>>
>>>> But  there are still three light registers setting differents bewteen
>>>> exynos and rk3288.
>>>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>>>      dp controller.
>>>> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>>>>      between rk3288 and exynos.
>>>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>>>>      register).
>>>>
>>>> This series have been well tested on Rockchip platform with eDP panel
>>>> on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
>>>> to Javier at Samsung help me to find a way to install mainline kernel to
>>>> Samsung Exynos Chromebooks, so this series also have been tested on Samsung
>>>> Snow and Peach Pit Chromebooks which borrowed from my friends.
>>>>
>>>> Besides, This version was build on linux-next branch (tag next-20150918), and
>>>> the above test experiments also base on that tag. But I know the latest tag is
>>>> next-20151009, so i do rebase this series again on next-20151009, there were
>>>> little conflicts(exynos_dp removed the suspend/resume).
>>>>
>>>> But after I retest this series on next-20151009, I saw kernel crashed in mmc
>>>> driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
>>>> module(after all I boot with USB device), and I can see eDP light up normally
>>>> in startup stage, but kernel keep crashed when it try to mount the filesystem.
>>>> I thought this isn't related to dp driver directly, so i choice not to debug
>>>> more depth.
>>>>
>>>> That's to say if someone want to test this series, I suggest you applied this
>>>> series on tag-20150918, just need to fix some light conflicts with the 01 & 02
>>>> patches (or just email me, I can send you directly).
>>>>
>>>> Thanks,
>>> Do you have a branch that I can use to test this series?
>> Thank you for your kind assistance, I have created a tree which checkout from the next-20151019. Surely there were some conflicts to applied this series on that tag, but things still works for me, here is the git address [https://github.com/yakir-Yang/linux/tree/analogix_dp]
>>
> I tested your branch on an Exynos5800 Peach Pi Chromebook and display is
> working on boot. I also tested DPMS and S2R and things are still working
> so for the whole series feel free to add:
>
> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>

Thanks a lot    ;)

- Yakir

>> Best regards,
>> - Yakir
>>
> Best regards,

^ permalink raw reply	[flat|nested] 370+ messages in thread
end of thread, other threads:[~2015-10-20 11:40 UTC | newest]

Thread overview: 370+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-09-01  5:46 [PATCH v4 0/16] Add Analogix Core Display Port Driver Yakir Yang
2015-09-01  5:46 ` Yakir Yang
2015-09-01  5:46 ` [PATCH v4 01/16] drm: exynos/dp: fix code style Yakir Yang
2015-09-01  5:46   ` Yakir Yang
2015-09-03  0:21   ` Krzysztof Kozlowski
2015-09-03  0:21     ` Krzysztof Kozlowski
2015-09-03  5:04     ` Yakir Yang
2015-09-03  5:04       ` Yakir Yang
2015-09-03  5:08       ` Krzysztof Kozlowski
2015-09-03  5:08         ` Krzysztof Kozlowski
2015-09-03  5:33         ` Yakir Yang
2015-09-03  5:33           ` Yakir Yang
2015-09-03  5:57           ` Joe Perches
2015-09-03  5:57             ` Joe Perches
2015-09-03  5:57             ` Joe Perches
2015-09-06  1:33             ` Yakir Yang
2015-09-06  1:33               ` Yakir Yang
2015-09-06  1:33               ` Yakir Yang
2015-09-01  5:49 ` [PATCH v4 02/16] drm: exynos/dp: convert to drm bridge mode Yakir Yang
2015-09-01  5:49   ` Yakir Yang
2015-09-01  5:49 ` [PATCH v4 03/16] drm: bridge: analogix/dp: split exynos dp driver to bridge dir Yakir Yang
2015-09-01  5:49   ` Yakir Yang
2015-09-01 20:46   ` Heiko Stuebner
2015-09-01 20:46     ` Heiko Stuebner
2015-09-01 20:46     ` Heiko Stuebner
2015-09-02  1:45     ` Yakir Yang
2015-09-02  1:45       ` Yakir Yang
2015-09-04 21:06     ` Rob Herring
2015-09-04 21:06       ` Rob Herring
2015-09-04 21:06       ` Rob Herring
2015-09-04 21:29       ` Heiko Stuebner
2015-09-04 21:29         ` Heiko Stuebner
2015-09-04 21:29         ` Heiko Stuebner
2015-09-07  8:11         ` Thierry Reding
2015-09-07  8:11           ` Thierry Reding
2015-09-07  8:11           ` Thierry Reding
2015-09-02 14:50   ` Emil Velikov
2015-09-02 14:50     ` Emil Velikov
2015-09-02 14:50     ` Emil Velikov
2015-09-03  3:55     ` Yakir Yang
2015-09-03  3:55       ` Yakir Yang
2015-09-03  3:55       ` Yakir Yang
2015-09-03  0:58   ` Krzysztof Kozlowski
2015-09-03  0:58     ` Krzysztof Kozlowski
2015-09-03  5:30     ` Yakir Yang
2015-09-03  5:30       ` Yakir Yang
2015-09-04  0:41       ` Krzysztof Kozlowski
2015-09-04  0:41         ` Krzysztof Kozlowski
2015-09-06  7:49         ` Yakir Yang
2015-09-06  7:49           ` Yakir Yang
2015-09-07  0:22           ` Krzysztof Kozlowski
2015-09-07  0:22             ` Krzysztof Kozlowski
2015-09-07  0:22             ` Krzysztof Kozlowski
2015-09-07  2:27             ` Yakir Yang
2015-09-07  2:27               ` Yakir Yang
2015-09-01  5:52 ` [PATCH v4 04/16] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
2015-09-01  5:52   ` Yakir Yang
2015-09-01  5:55 ` [PATCH v4 05/16] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & colorimetry Yakir Yang
2015-09-01  5:55   ` Yakir Yang
2015-09-03  8:04   ` Krzysztof Kozlowski
2015-09-03  8:04     ` Krzysztof Kozlowski
2015-09-06  2:00     ` Yakir Yang
2015-09-06  2:00       ` Yakir Yang
2015-09-06  2:00       ` Yakir Yang
2015-09-01  5:58 ` [PATCH v4 06/16] Documentation: drm/bridge: add document for analogix_dp Yakir Yang
2015-09-01  5:58   ` Yakir Yang
2015-09-01  6:01 ` [PATCH v4 07/16] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
2015-09-01  6:01   ` Yakir Yang
2015-09-03  0:01   ` Krzysztof Kozlowski
2015-09-03  0:01     ` Krzysztof Kozlowski
2015-09-03  4:51     ` Yakir Yang
2015-09-01  6:01 ` [PATCH v4 08/16] drm: rockchip/dp: add rockchip platform dp driver Yakir Yang
2015-09-01  6:01   ` Yakir Yang
2015-09-01  6:01   ` Yakir Yang
2015-09-01 14:24   ` Heiko Stuebner
2015-09-01 14:24     ` Heiko Stuebner
2015-09-01 14:24     ` Heiko Stuebner
2015-09-01 14:48     ` Yakir Yang
2015-09-01 14:48       ` Yakir Yang
2015-09-01 21:00   ` Heiko Stuebner
2015-09-01 21:00     ` Heiko Stuebner
2015-09-01 21:00     ` Heiko Stuebner
2015-09-02  1:52     ` Yakir Yang
2015-09-02  1:52       ` Yakir Yang
2015-09-01  6:01 ` [PATCH v4 09/16] drm: rockchip: add bpc and color mode setting Yakir Yang
2015-09-01  6:01   ` Yakir Yang
2015-09-01  6:01   ` Yakir Yang
2015-09-01 21:00   ` Heiko Stuebner
2015-09-01 21:00     ` Heiko Stuebner
2015-09-01 21:00     ` Heiko Stuebner
2015-09-02  2:06     ` Yakir Yang
2015-09-02  2:06       ` Yakir Yang
2015-09-02  8:34       ` Thierry Reding
2015-09-02  8:34         ` Thierry Reding
2015-09-02 10:02         ` Yakir Yang
2015-09-02 10:02           ` Yakir Yang
2015-09-03  8:38           ` Thierry Reding
2015-09-03  8:38             ` Thierry Reding
2015-09-06  2:06             ` Yakir Yang
2015-09-06  2:06               ` Yakir Yang
2015-09-01  6:04 ` [PATCH v4 10/16] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-09-01  6:04   ` Yakir Yang
2015-09-01  6:04   ` Yakir Yang
2015-09-01 16:51   ` Heiko Stuebner
2015-09-01 16:51     ` Heiko Stuebner
2015-09-01 16:51     ` Heiko Stuebner
2015-09-01 20:58     ` Heiko Stuebner
2015-09-01 20:58       ` Heiko Stuebner
2015-09-01 20:58       ` Heiko Stuebner
2015-09-02  1:46       ` Yakir Yang
2015-09-02  1:46         ` Yakir Yang
2015-09-02  1:02     ` Yakir Yang
2015-09-02  1:02       ` Yakir Yang
2015-09-02 13:27   ` Rob Herring
2015-09-02 13:27     ` Rob Herring
2015-09-02 13:27     ` Rob Herring
2015-09-03  3:25     ` Yakir Yang
2015-09-03  3:25       ` Yakir Yang
2015-09-03  3:25       ` Yakir Yang
2015-09-03 13:52       ` Heiko Stuebner
2015-09-03 13:52         ` Heiko Stuebner
2015-09-03 13:52         ` Heiko Stuebner
2015-09-06  4:09         ` Yakir Yang
2015-09-06  4:09           ` Yakir Yang
2015-09-01  6:07 ` [PATCH v4 11/16] drm: bridge: analogix/dp: add platform device type support Yakir Yang
2015-09-01  6:07   ` Yakir Yang
2015-09-04  0:36   ` Krzysztof Kozlowski
2015-09-04  0:36     ` Krzysztof Kozlowski
2015-09-06  4:07     ` Yakir Yang
2015-09-06  4:07       ` Yakir Yang
2015-09-06 23:55       ` Krzysztof Kozlowski
2015-09-06 23:55         ` Krzysztof Kozlowski
2015-09-07  1:47         ` Yakir Yang
2015-09-01  6:09 ` [PATCH v4 12/16] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
2015-09-01  6:09   ` Yakir Yang
2015-09-01  6:11 ` [PATCH v4 13/16] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
2015-09-01  6:11   ` Yakir Yang
2015-09-01  6:14 ` [PATCH v4 14/16] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
2015-09-01  6:14   ` Yakir Yang
2015-09-02 20:17   ` Rob Herring
2015-09-02 20:17     ` Rob Herring
2015-09-02 20:17     ` Rob Herring
2015-09-03  4:27     ` Yakir Yang
2015-09-03  4:27       ` Yakir Yang
2015-09-03  4:27       ` Yakir Yang
2015-09-03  9:04       ` Thierry Reding
2015-09-03  9:04         ` Thierry Reding
2015-09-03  9:04         ` Thierry Reding
2015-09-04 10:20         ` Russell King - ARM Linux
2015-09-04 10:20           ` Russell King - ARM Linux
2015-09-04 10:20           ` Russell King - ARM Linux
2015-09-07  9:01           ` Thierry Reding
2015-09-07  9:01             ` Thierry Reding
2015-09-07  9:01             ` Thierry Reding
2015-09-06  3:59         ` Yakir Yang
2015-09-06  3:59           ` Yakir Yang
2015-09-07  8:20           ` Thierry Reding
2015-09-07  8:20             ` Thierry Reding
2015-09-07  8:20             ` Thierry Reding
2015-09-21  9:10             ` Yakir Yang
2015-09-04 21:46       ` Rob Herring
2015-09-04 21:46         ` Rob Herring
2015-09-04 21:46         ` Rob Herring
2015-09-06  8:20         ` Yakir Yang
2015-09-06  8:20           ` Yakir Yang
2015-09-06  8:20           ` Yakir Yang
2015-09-07  8:39           ` Thierry Reding
2015-09-07  8:39             ` Thierry Reding
2015-09-07  8:39             ` Thierry Reding
2015-09-03  8:47     ` Thierry Reding
2015-09-03  8:47       ` Thierry Reding
2015-09-03  8:47       ` Thierry Reding
2015-09-03 21:55       ` Rob Herring
2015-09-03 21:55         ` Rob Herring
2015-09-03 21:55         ` Rob Herring
2015-09-04 10:01         ` Thierry Reding
2015-09-04 10:01           ` Thierry Reding
2015-09-04 10:01           ` Thierry Reding
2015-09-01  6:17 ` [PATCH v4 15/16] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
2015-09-01  6:17   ` Yakir Yang
2015-09-01  6:20 ` [PATCH v4 16/16] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
2015-09-01  6:20   ` Yakir Yang
2015-09-01  6:20   ` Yakir Yang
2015-09-01 21:47 ` [PATCH v4 0/16] Add Analogix Core Display Port Driver Heiko Stuebner
2015-09-01 21:47   ` Heiko Stuebner
2015-09-01 21:47   ` Heiko Stuebner
2015-09-02  2:15   ` Yakir Yang
2015-09-02  2:15     ` Yakir Yang
2015-09-21  8:45     ` Yakir Yang
2015-09-21  9:15       ` Thierry Reding
2015-09-21  9:15         ` Thierry Reding
2015-09-21 10:27         ` Yakir Yang
2015-09-21 10:27           ` Yakir Yang
2015-09-21 11:22           ` Thierry Reding
2015-09-21 11:22             ` Thierry Reding
2015-09-21 11:43             ` Yakir Yang
2015-09-22  7:20 ` [PATCH v5 0/17] " Yakir Yang
2015-09-22  7:20   ` Yakir Yang
2015-09-22  7:26   ` [PATCH v5 01/17] drm: exynos: dp: convert to drm bridge mode Yakir Yang
2015-09-22  7:26     ` Yakir Yang
2015-09-22  7:29   ` [PATCH v5 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang
2015-09-22  7:29     ` Yakir Yang
2015-09-30  5:17     ` Krzysztof Kozlowski
2015-09-30  5:17       ` Krzysztof Kozlowski
2015-09-30  6:48       ` Yakir Yang
2015-09-30  6:48         ` Yakir Yang
2015-09-30  6:48         ` Yakir Yang
2015-09-22  7:34   ` [PATCH v5 03/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
2015-09-22  7:34     ` Yakir Yang
2015-09-30  5:22     ` Krzysztof Kozlowski
2015-09-30  5:22       ` Krzysztof Kozlowski
2015-09-30  6:52       ` Yakir Yang
2015-09-30  6:52         ` Yakir Yang
2015-09-22  7:35   ` [PATCH v5 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
2015-09-22  7:35     ` Yakir Yang
2015-09-22  7:35     ` Yakir Yang
2015-09-22  7:37   ` [PATCH v5 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
2015-09-22  7:37     ` Yakir Yang
2015-09-22  7:37     ` Yakir Yang
2015-09-30  5:32     ` Krzysztof Kozlowski
2015-09-30  5:32       ` Krzysztof Kozlowski
2015-09-30  5:32       ` Krzysztof Kozlowski
2015-09-30  7:19       ` Yakir Yang
2015-09-30  7:34         ` Krzysztof Kozlowski
2015-09-30  7:34           ` Krzysztof Kozlowski
2015-09-30  8:20           ` Yakir Yang
2015-09-30  8:26             ` Krzysztof Kozlowski
2015-09-30  8:26               ` Krzysztof Kozlowski
2015-09-30  8:26               ` Krzysztof Kozlowski
2015-09-30  9:39               ` Yakir Yang
2015-09-30  9:39                 ` Yakir Yang
2015-09-22  7:40   ` [PATCH v5 06/17] Documentation: drm/bridge: add document for analogix_dp Yakir Yang
2015-09-22  7:40     ` Yakir Yang
2015-09-22  7:43   ` [PATCH v5 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
2015-09-22  7:43     ` Yakir Yang
2015-09-30  5:39     ` Krzysztof Kozlowski
2015-09-30  5:39       ` Krzysztof Kozlowski
2015-09-30  7:20       ` Yakir Yang
2015-09-30  7:20         ` Yakir Yang
2015-09-30  7:20         ` Yakir Yang
2015-09-22  7:45   ` [PATCH v5 08/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
2015-09-22  7:45     ` Yakir Yang
2015-09-22  7:48   ` [PATCH v5 09/17] Documentation: drm/bridge: add document for analogix_dp Yakir Yang
2015-09-22  7:48     ` Yakir Yang
2015-09-22  7:48   ` [PATCH v5 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-09-22  7:48     ` Yakir Yang
2015-09-22  7:51   ` [PATCH v5 11/17] Documentation: phy: add document for rockchip dp phy Yakir Yang
2015-09-22  7:51     ` Yakir Yang
2015-09-22  7:55   ` [PATCH v5 12/17] drm: rockchip: vop: add bpc and color mode setting Yakir Yang
2015-09-22  7:55     ` Yakir Yang
2015-09-22  7:55     ` Yakir Yang
2015-09-22  7:57   ` [PATCH v5 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
2015-09-22  7:57     ` Yakir Yang
2015-09-22  8:00   ` [PATCH v5 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
2015-09-22  8:00     ` Yakir Yang
2015-09-22  8:02   ` [PATCH v5 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
2015-09-22  8:02     ` Yakir Yang
2015-09-22  8:05   ` [PATCH v5 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
2015-09-22  8:05     ` Yakir Yang
2015-09-22  8:05     ` Yakir Yang
2015-09-22  8:07   ` [PATCH v5 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
2015-09-22  8:07     ` Yakir Yang
2015-09-22  8:07     ` Yakir Yang
2015-10-07  6:25   ` [PATCH v5 0/17] Add Analogix Core Display Port Driver Yakir Yang
2015-10-07  6:25     ` Yakir Yang
2015-10-07  8:46     ` Javier Martinez Canillas
2015-10-07  8:46       ` Javier Martinez Canillas
2015-10-07  9:02       ` Yakir Yang
2015-10-07  9:02         ` Yakir Yang
2015-10-07  9:26         ` Javier Martinez Canillas
2015-10-07  9:26           ` Javier Martinez Canillas
2015-10-07 11:05           ` Yakir Yang
2015-10-07 11:25             ` Javier Martinez Canillas
2015-10-07 11:25               ` Javier Martinez Canillas
2015-10-08  0:40               ` Yakir Yang
2015-10-08  0:40                 ` Yakir Yang
2015-10-10 14:31                 ` Yakir Yang
2015-10-10 14:31                   ` Yakir Yang
2015-10-10 14:31                   ` Yakir Yang
2015-10-13  9:21                   ` Javier Martinez Canillas
2015-10-13  9:21                     ` Javier Martinez Canillas
2015-10-13  9:21                     ` Javier Martinez Canillas
2015-10-13 13:50                     ` Yakir Yang
2015-10-13 13:50                       ` Yakir Yang
2015-10-14  8:18                       ` Javier Martinez Canillas
2015-10-14  8:18                         ` Javier Martinez Canillas
2015-10-14  8:18                         ` Javier Martinez Canillas
2015-10-10 15:35 ` [PATCH v6 " Yakir Yang
2015-10-10 15:35   ` Yakir Yang
2015-10-10 15:38   ` [PATCH v6 01/17] drm: exynos: dp: convert to drm bridge mode Yakir Yang
2015-10-10 15:38     ` Yakir Yang
2015-10-10 15:39   ` [PATCH v6 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang
2015-10-10 15:39     ` Yakir Yang
2015-10-10 15:41   ` [PATCH v6 03/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
2015-10-10 15:41     ` Yakir Yang
2015-10-10 15:43   ` [PATCH v6 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
2015-10-10 15:43     ` Yakir Yang
2015-10-10 15:43     ` Yakir Yang
2015-10-10 15:46   ` [PATCH v6 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
2015-10-10 15:46     ` Yakir Yang
2015-10-12  0:37     ` Yakir Yang
2015-10-12  0:37       ` Yakir Yang
2015-10-12  0:49       ` Krzysztof Kozlowski
2015-10-12  0:49         ` Krzysztof Kozlowski
2015-10-12  0:49         ` Krzysztof Kozlowski
2015-10-12  2:43         ` Yakir Yang
2015-10-12  2:43           ` Yakir Yang
2015-10-12  3:51           ` Krzysztof Kozlowski
2015-10-12  3:51             ` Krzysztof Kozlowski
2015-10-12  4:09             ` Yakir Yang
2015-10-12  4:09               ` Yakir Yang
2015-10-12  4:09               ` Yakir Yang
2015-10-12  4:16               ` Krzysztof Kozlowski
2015-10-12  4:16                 ` Krzysztof Kozlowski
2015-10-10 15:49   ` [PATCH v6 06/17] Documentation: drm/bridge: add document for analogix_dp Yakir Yang
2015-10-10 15:49     ` Yakir Yang
2015-10-10 15:49   ` [PATCH v6 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
2015-10-10 15:49     ` Yakir Yang
2015-10-10 15:51   ` [PATCH v6 08/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
2015-10-10 15:51     ` Yakir Yang
2015-10-10 15:53   ` [PATCH v6 09/17] Documentation: drm/bridge: add document for analogix_dp Yakir Yang
2015-10-10 15:53     ` Yakir Yang
2015-10-10 15:53     ` Yakir Yang
2015-10-10 15:55   ` [PATCH v6 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-10-10 15:55     ` Yakir Yang
2015-10-12 15:02     ` Kishon Vijay Abraham I
2015-10-12 15:02       ` Kishon Vijay Abraham I
2015-10-12 15:02       ` Kishon Vijay Abraham I
2015-10-12 16:18       ` Heiko Stübner
2015-10-12 16:18         ` Heiko Stübner
2015-10-12 16:18         ` Heiko Stübner
2015-10-13  1:20       ` Yakir Yang
2015-10-13  1:20         ` Yakir Yang
2015-10-10 15:58   ` [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy Yakir Yang
2015-10-10 15:58     ` Yakir Yang
2015-10-12 22:28     ` Kishon Vijay Abraham I
2015-10-12 22:28       ` Kishon Vijay Abraham I
2015-10-12 22:28       ` Kishon Vijay Abraham I
2015-10-13  1:21       ` Yakir Yang
2015-10-13  1:21         ` Yakir Yang
2015-10-10 16:00   ` [PATCH v6 12/17] drm: rockchip: vop: add bpc and color mode setting Yakir Yang
2015-10-10 16:00     ` Yakir Yang
2015-10-10 16:05   ` [PATCH v6 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
2015-10-10 16:05     ` Yakir Yang
2015-10-10 16:05     ` Yakir Yang
2015-10-10 16:05   ` [PATCH v6 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
2015-10-10 16:05     ` Yakir Yang
2015-10-10 16:05   ` [PATCH v6 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
2015-10-10 16:05     ` Yakir Yang
2015-10-10 16:05   ` [PATCH v6 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
2015-10-10 16:05     ` Yakir Yang
2015-10-10 16:06   ` [PATCH v6 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
2015-10-10 16:06     ` Yakir Yang
2015-10-12  4:29   ` [PATCH v7 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
2015-10-12  4:29     ` Yakir Yang
2015-10-12  6:54     ` Krzysztof Kozlowski
2015-10-12  6:54       ` Krzysztof Kozlowski
2015-10-12  7:20       ` Yakir Yang
2015-10-12  7:20         ` Yakir Yang
2015-10-12  7:20         ` Yakir Yang
2015-10-19 10:40   ` [PATCH v6 0/17] Add Analogix Core Display Port Driver Javier Martinez Canillas
2015-10-19 10:40     ` Javier Martinez Canillas
2015-10-19 10:40     ` Javier Martinez Canillas
2015-10-20  2:10     ` Yakir Yang
2015-10-20  2:10       ` Yakir Yang
2015-10-20  9:48       ` Javier Martinez Canillas
2015-10-20  9:48         ` Javier Martinez Canillas
2015-10-20  9:48         ` Javier Martinez Canillas
2015-10-20 11:40         ` Yakir Yang
2015-10-20 11:40           ` Yakir Yang

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