From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34360) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZXIE8-0001Gq-7t for qemu-devel@nongnu.org; Wed, 02 Sep 2015 20:18:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZXIE6-0006Nv-IL for qemu-devel@nongnu.org; Wed, 02 Sep 2015 20:18:04 -0400 Received: from mail-pa0-x229.google.com ([2607:f8b0:400e:c03::229]:33499) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZXIE5-0006MH-VW for qemu-devel@nongnu.org; Wed, 02 Sep 2015 20:18:02 -0400 Received: by pacex6 with SMTP id ex6so21958297pac.0 for ; Wed, 02 Sep 2015 17:18:00 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 2 Sep 2015 17:17:43 -0700 Message-Id: <1441239463-18981-18-git-send-email-rth@twiddle.net> In-Reply-To: <1441239463-18981-1-git-send-email-rth@twiddle.net> References: <1441239463-18981-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 17/17] target-openrisc: Implement lwa, swa List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, proljc@gmail.com Signed-off-by: Richard Henderson --- linux-user/main.c | 45 ++++++++++++++++++++++++ target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 9 +++++ target-openrisc/interrupt.c | 1 + target-openrisc/interrupt_helper.c | 1 + target-openrisc/mmu.c | 1 + target-openrisc/translate.c | 70 ++++++++++++++++++++++++++++++++++++++ 7 files changed, 128 insertions(+) diff --git a/linux-user/main.c b/linux-user/main.c index 2c9658e..77b301c 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2644,6 +2644,48 @@ error: #endif #ifdef TARGET_OPENRISC +static void do_store_exclusive(CPUOpenRISCState *env) +{ + target_ulong addr, val, tmp; + target_siginfo_t info; + int ret = 0; + + addr = env->lock_addr; + tmp = env->lock_st_addr; + env->lock_addr = -1; + env->lock_st_addr = 0; + + start_exclusive(); + mmap_lock(); + + if (addr == tmp) { + if (get_user_u32(val, addr)) { + goto do_sigsegv; + } + if (val == env->lock_value) { + if (put_user_u32(env->lock_st_value, addr)) { + goto do_sigsegv; + } + ret = 1; + } + } + env->sr_f = ret; + env->pc += 4; + + mmap_unlock(); + end_exclusive(); + return; + + do_sigsegv: + mmap_unlock(); + end_exclusive(); + + info.si_signo = TARGET_SIGSEGV; + info.si_errno = 0; + info.si_code = TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr = addr; + queue_signal(env, TARGET_SIGSEGV, &info); +} void cpu_loop(CPUOpenRISCState *env) { @@ -2713,6 +2755,9 @@ void cpu_loop(CPUOpenRISCState *env) case EXCP_NR: qemu_log("\nNR\n"); break; + case EXCP_SWA: + do_store_exclusive(env); + break; default: qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n", trapnr); diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index d97f3c0..56ceba4 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -52,6 +52,7 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.pc = 0x100; cpu->env.sr = SR_FO | SR_SM; + cpu->env.lock_addr = -1; s->exception_index = -1; cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 5ddf477..e3afe26 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -171,6 +171,8 @@ enum { EXCP_FPE = 0xd, EXCP_TRAP = 0xe, EXCP_NR, + /* For usermode emulation. */ + EXCP_SWA, }; /* Supervisor register */ @@ -297,6 +299,13 @@ typedef struct CPUOpenRISCState { uint32_t fpcsr; /* Float register */ float_status fp_status; + target_ulong lock_addr; + target_ulong lock_value; +#ifdef CONFIG_USER_ONLY + target_ulong lock_st_addr; + target_ulong lock_st_value; +#endif + uint32_t flags; /* cpu_flags, we only use it for exception in solt so far. */ diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index 2d89acb..428314f 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -53,6 +53,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr &= ~SR_TEE; env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; + env->lock_addr = -1; if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { env->pc = (cs->exception_index << 8); diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c index 8695fe7..70e64a3 100644 --- a/target-openrisc/interrupt_helper.c +++ b/target-openrisc/interrupt_helper.c @@ -32,6 +32,7 @@ void HELPER(rfe)(CPUOpenRISCState *env) cpu->env.pc = cpu->env.epcr; cpu->env.npc = cpu->env.epcr; cpu_set_sr(&cpu->env, cpu->env.esr); + cpu->env.lock_addr = -1; #ifndef CONFIG_USER_ONLY if (cpu->env.sr & SR_DME) { diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c index 750a936..a656232 100644 --- a/target-openrisc/mmu.c +++ b/target-openrisc/mmu.c @@ -172,6 +172,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, cs->exception_index = exception; cpu->env.eear = address; + cpu->env.lock_addr = -1; } #ifndef CONFIG_USER_ONLY diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 569f4ab..80d2b84 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -57,6 +57,8 @@ static TCGv cpu_ppc; static TCGv cpu_sr_f; /* bf/bnf, F flag taken */ static TCGv cpu_sr_cy; /* carry (unsigned overflow) */ static TCGv cpu_sr_ov; /* signed overflow */ +static TCGv cpu_lock_addr; +static TCGv cpu_lock_value; static TCGv_i32 fpcsr; static TCGv_i64 cpu_mac; /* MACHI:MACLO */ static TCGv_i32 env_flags; @@ -92,6 +94,12 @@ void openrisc_translate_init(void) offsetof(CPUOpenRISCState, sr_cy), "sr_cy"); cpu_sr_ov = tcg_global_mem_new(TCG_AREG0, offsetof(CPUOpenRISCState, sr_ov), "sr_ov"); + cpu_lock_addr = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUOpenRISCState, lock_addr), + "lock_addr"); + cpu_lock_value = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUOpenRISCState, lock_value), + "lock_value"); fpcsr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUOpenRISCState, fpcsr), "fpcsr"); @@ -467,6 +475,58 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) gen_ove_cy(dc); } +static void gen_lwa(DisasContext *dc, TCGv rd, TCGv ra, int32_t ofs) +{ + TCGv ea = tcg_temp_new(); + + tcg_gen_addi_tl(ea, ra, ofs); + tcg_gen_qemu_ld_tl(rd, ea, dc->mem_idx, MO_TEUL); + tcg_gen_mov_tl(cpu_lock_addr, ea); + tcg_gen_mov_tl(cpu_lock_value, rd); + tcg_temp_free(ea); +} + +static void gen_swa(DisasContext *dc, TCGv rb, TCGv ra, int32_t ofs) +{ +#ifdef CONFIG_USER_ONLY + TCGv ea = tcg_temp_new(); + tcg_gen_addi_tl(ea, ra, ofs); + tcg_gen_st_tl(ea, cpu_env, offsetof(CPUOpenRISCState, lock_st_addr)); + tcg_temp_free(ea); + + tcg_gen_st32_tl(rb, cpu_env, offsetof(CPUOpenRISCState, lock_st_value)); + + tcg_gen_movi_tl(cpu_pc, dc->pc); + gen_exception(dc, EXCP_SWA); + dc->is_jmp = DISAS_UPDATE; +#else + TCGv ea, val; + TCGLabel *lab_fail, *lab_done; + + ea = tcg_temp_new(); + tcg_gen_addi_tl(ea, ra, ofs); + + lab_fail = gen_new_label(); + lab_done = gen_new_label(); + tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); + tcg_temp_free(ea); + + val = tcg_temp_new(); + tcg_gen_qemu_ld_tl(val, cpu_lock_addr, dc->mem_idx, MO_TEUL); + tcg_gen_brcond_tl(TCG_COND_NE, val, cpu_lock_value, lab_fail); + + tcg_gen_qemu_st_tl(rb, cpu_lock_addr, dc->mem_idx, MO_TEUL); + tcg_gen_movi_tl(cpu_sr_f, 1); + tcg_gen_br(lab_done); + + gen_set_label(lab_fail); + tcg_gen_movi_tl(cpu_sr_f, 0); + + gen_set_label(lab_done); + tcg_gen_movi_tl(cpu_lock_addr, -1); +#endif +} + static void dec_calc(DisasContext *dc, uint32_t insn) { uint32_t op0, op1, op2; @@ -721,6 +781,11 @@ static void dec_misc(DisasContext *dc, uint32_t insn) } break; + case 0x1b: /* l.lwa */ + LOG_DIS("l.lwa r%d, r%d, %d\n", rd, ra, I16); + gen_lwa(dc, cpu_R[rd], cpu_R[ra], I16); + break; + case 0x1c: /* l.cust1 */ LOG_DIS("l.cust1\n"); break; @@ -847,6 +912,11 @@ static void dec_misc(DisasContext *dc, uint32_t insn) } break; + case 0x33: /* l.swa */ + LOG_DIS("l.swa r%d, r%d, %d\n", ra, rb, I5_11); + gen_swa(dc, cpu_R[rb], cpu_R[ra], I5_11); + break; + case 0x34: /* l.sd */ LOG_DIS("l.sd r%d, r%d, %d\n", ra, rb, I5_11); check_ob64s(dc); -- 2.4.3