From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34129) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZXIDv-0000yF-Ql for qemu-devel@nongnu.org; Wed, 02 Sep 2015 20:17:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZXIDs-0006GS-CY for qemu-devel@nongnu.org; Wed, 02 Sep 2015 20:17:51 -0400 Received: from mail-pa0-x232.google.com ([2607:f8b0:400e:c03::232]:33477) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZXIDr-0006GC-W8 for qemu-devel@nongnu.org; Wed, 02 Sep 2015 20:17:48 -0400 Received: by pacex6 with SMTP id ex6so21952776pac.0 for ; Wed, 02 Sep 2015 17:17:46 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 2 Sep 2015 17:17:27 -0700 Message-Id: <1441239463-18981-2-git-send-email-rth@twiddle.net> In-Reply-To: <1441239463-18981-1-git-send-email-rth@twiddle.net> References: <1441239463-18981-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 01/17] target-openrisc: Always enable OPENRISC_DISAS List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, proljc@gmail.com Avoids warnings from unused variables etc. Signed-off-by: Richard Henderson --- target-openrisc/translate.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index aca1242..9d04753 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -33,14 +33,9 @@ #include "trace-tcg.h" - -#define OPENRISC_DISAS - -#ifdef OPENRISC_DISAS -# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) -#else -# define LOG_DIS(...) do { } while (0) -#endif +/* Set to 0 to completely disable. */ +#define OPENRISC_DISAS CPU_LOG_TB_IN_ASM +#define LOG_DIS(...) qemu_log_mask(OPENRISC_DISAS, ## __VA_ARGS__) typedef struct DisasContext { TranslationBlock *tb; @@ -704,9 +699,7 @@ static void dec_misc(DisasContext *dc, uint32_t insn) { uint32_t op0, op1; uint32_t ra, rb, rd; -#ifdef OPENRISC_DISAS uint32_t L6, K5; -#endif uint32_t I16, I5, I11, N26, tmp; TCGMemOp mop; @@ -715,10 +708,8 @@ static void dec_misc(DisasContext *dc, uint32_t insn) ra = extract32(insn, 16, 5); rb = extract32(insn, 11, 5); rd = extract32(insn, 21, 5); -#ifdef OPENRISC_DISAS L6 = extract32(insn, 5, 6); K5 = extract32(insn, 0, 5); -#endif I16 = extract32(insn, 0, 16); I5 = extract32(insn, 21, 5); I11 = extract32(insn, 0, 11); @@ -1315,13 +1306,10 @@ static void dec_compi(DisasContext *dc, uint32_t insn) static void dec_sys(DisasContext *dc, uint32_t insn) { uint32_t op0; -#ifdef OPENRISC_DISAS uint32_t K16; -#endif + op0 = extract32(insn, 16, 10); -#ifdef OPENRISC_DISAS K16 = extract32(insn, 0, 16); -#endif switch (op0) { case 0x000: /* l.sys */ -- 2.4.3