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From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 01/11] x86: quark: Optimize MRC execution time
Date: Thu,  3 Sep 2015 04:43:37 -0700	[thread overview]
Message-ID: <1441280627-29714-2-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1441280627-29714-1-git-send-email-bmeng.cn@gmail.com>

Intel Quark SoC has a low end x86 processor with only 400MHz
frequency. Currently it takes about 15 seconds for U-Boot to
boot to shell and the most time consuming part is with MRC,
which is about 12 seconds. MRC programs lots of registers on
the SoC internal message bus indirectly accessed via pci bus.

To speed up the boot, create an optimized version of pci config
read/write dword routines which directly operate on PCI I/O ports.
These two routines are inlined to provide better performance too.
Now it only takes about 3 seconds to finish MRC, which is really
fast (4 times faster than before).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

---

Changes in v3: None
Changes in v2:
- Drop v1 patch: "x86: quark: Make host bridge (b.d.f=0.0.0) visible",
  as pci_skip_dev() is not needed with the conversion to dm pci.
- Drop v1 patch: "dm: pci: Allow skipping device configuration",
  as full PCIe root port support has been added and there is no need
  to add such feature at this point. We can still add such capability
  to dm pci in the future whenever needed.
- Reorder to put patch "Optimize MRC execution time" as the first one
  in v2, as this patch addressed the slow boot time issue which exists
  before dm pci conversion, although it significantly improves more
  after dm pci conversion :-)
- Move qrk_pci_write_config_dword() and qrk_pci_read_config_dword()
  to arch/x86/cpu/quark/quark.c
- Rewrite this commit's message (ie: not mentioning dm pci conversion)

 arch/x86/cpu/quark/msg_port.c           | 44 ++++++++++++++++-----------------
 arch/x86/include/asm/arch-quark/quark.h | 35 ++++++++++++++++++++++++++
 2 files changed, 57 insertions(+), 22 deletions(-)

diff --git a/arch/x86/cpu/quark/msg_port.c b/arch/x86/cpu/quark/msg_port.c
index 31713e3..cf828f2 100644
--- a/arch/x86/cpu/quark/msg_port.c
+++ b/arch/x86/cpu/quark/msg_port.c
@@ -5,34 +5,34 @@
  */
 
 #include <common.h>
-#include <pci.h>
 #include <asm/arch/device.h>
 #include <asm/arch/msg_port.h>
+#include <asm/arch/quark.h>
 
 void msg_port_setup(int op, int port, int reg)
 {
-	pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
-			       (((op) << 24) | ((port) << 16) |
-			       (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
+	qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
+				   (((op) << 24) | ((port) << 16) |
+				   (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
 }
 
 u32 msg_port_read(u8 port, u32 reg)
 {
 	u32 value;
 
-	pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
-			       reg & 0xffffff00);
+	qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+				   reg & 0xffffff00);
 	msg_port_setup(MSG_OP_READ, port, reg);
-	pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
+	qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
 
 	return value;
 }
 
 void msg_port_write(u8 port, u32 reg, u32 value)
 {
-	pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
-	pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
-			       reg & 0xffffff00);
+	qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
+	qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+				   reg & 0xffffff00);
 	msg_port_setup(MSG_OP_WRITE, port, reg);
 }
 
@@ -40,19 +40,19 @@ u32 msg_port_alt_read(u8 port, u32 reg)
 {
 	u32 value;
 
-	pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
-			       reg & 0xffffff00);
+	qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+				   reg & 0xffffff00);
 	msg_port_setup(MSG_OP_ALT_READ, port, reg);
-	pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
+	qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
 
 	return value;
 }
 
 void msg_port_alt_write(u8 port, u32 reg, u32 value)
 {
-	pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
-	pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
-			       reg & 0xffffff00);
+	qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
+	qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+				   reg & 0xffffff00);
 	msg_port_setup(MSG_OP_ALT_WRITE, port, reg);
 }
 
@@ -60,18 +60,18 @@ u32 msg_port_io_read(u8 port, u32 reg)
 {
 	u32 value;
 
-	pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
-			       reg & 0xffffff00);
+	qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+				   reg & 0xffffff00);
 	msg_port_setup(MSG_OP_IO_READ, port, reg);
-	pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
+	qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
 
 	return value;
 }
 
 void msg_port_io_write(u8 port, u32 reg, u32 value)
 {
-	pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
-	pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
-			       reg & 0xffffff00);
+	qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
+	qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+				   reg & 0xffffff00);
 	msg_port_setup(MSG_OP_IO_WRITE, port, reg);
 }
diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h
index c997928..1ce5693 100644
--- a/arch/x86/include/asm/arch-quark/quark.h
+++ b/arch/x86/include/asm/arch-quark/quark.h
@@ -89,6 +89,41 @@ struct quark_rcba {
 	u16	d20d21_ir;
 };
 
+#include <asm/io.h>
+#include <asm/pci.h>
+
+/**
+ * qrk_pci_read_config_dword() - Read a configuration value
+ *
+ * @dev:	PCI device address: bus, device and function
+ * @offset:	Dword offset within the device's configuration space
+ * @valuep:	Place to put the returned value
+ *
+ * Note: This routine is inlined to provide better performance on Quark
+ */
+static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset,
+					     u32 *valuep)
+{
+	outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
+	*valuep = inl(PCI_REG_DATA);
+}
+
+/**
+ * qrk_pci_write_config_dword() - Write a PCI configuration value
+ *
+ * @dev:	PCI device address: bus, device and function
+ * @offset:	Dword offset within the device's configuration space
+ * @value:	Value to write
+ *
+ * Note: This routine is inlined to provide better performance on Quark
+ */
+static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset,
+					      u32 value)
+{
+	outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
+	outl(value, PCI_REG_DATA);
+}
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _QUARK_H_ */
-- 
1.8.2.1

  reply	other threads:[~2015-09-03 11:43 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-03 11:43 [U-Boot] [PATCH v3 00/11] x86: quark: Convert to driver model Bin Meng
2015-09-03 11:43 ` Bin Meng [this message]
2015-09-03 11:43 ` [U-Boot] [PATCH v3 02/11] x86: quark: Avoid chicken and egg problem Bin Meng
2015-09-03 11:43 ` [U-Boot] [PATCH v3 03/11] x86: Enable PCIe controller on quark/galileo Bin Meng
2015-09-03 11:43 ` [U-Boot] [PATCH v3 04/11] x86: Convert to use driver model pci " Bin Meng
2015-09-03 11:43 ` [U-Boot] [PATCH v3 05/11] x86: quark: Add USB PHY initialization support Bin Meng
2015-09-03 11:43 ` [U-Boot] [PATCH v3 06/11] x86: galileo: Convert to use CONFIG_DM_USB Bin Meng
2015-09-03 11:43 ` [U-Boot] [PATCH v3 07/11] net: designware: Fix build warnings Bin Meng
2015-09-03 11:43 ` [U-Boot] [PATCH v3 08/11] dm: pci: Add an inline API to test if a device is on a PCI bus Bin Meng
2015-09-03 11:43 ` [U-Boot] [PATCH v3 09/11] net: designware: Add support to PCI designware devices Bin Meng
2015-09-03 11:43 ` [U-Boot] [PATCH v3 10/11] x86: Convert to use driver model eth on quark/galileo Bin Meng
2015-09-03 11:43 ` [U-Boot] [PATCH v3 11/11] x86: quark: Add PCIe/USB static register programming after memory init Bin Meng

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