From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex Williamson Subject: Re: [Qemu-devel] [PATCH 1/2] target-i386: disable LINT0 after reset Date: Tue, 15 Sep 2015 15:19:42 -0600 Message-ID: <1442351982.23936.157.camel@redhat.com> References: <1428881529-29459-1-git-send-email-namit@cs.technion.ac.il> <1428881529-29459-2-git-send-email-namit@cs.technion.ac.il> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Cc: pbonzini@redhat.com, kvm@vger.kernel.org, jan.kiszka@siemens.com, qemu-devel@nongnu.org, bsd@redhat.com, avi.kivity@gmail.com To: Nadav Amit Return-path: Received: from mx1.redhat.com ([209.132.183.28]:38172 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751540AbbIOVTo (ORCPT ); Tue, 15 Sep 2015 17:19:44 -0400 In-Reply-To: <1428881529-29459-2-git-send-email-namit@cs.technion.ac.il> Sender: kvm-owner@vger.kernel.org List-ID: On Mon, 2015-04-13 at 02:32 +0300, Nadav Amit wrote: > Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone > and therefore this hack is no longer needed. Since it violates the > specifications, it is removed. > > Signed-off-by: Nadav Amit > --- > hw/intc/apic_common.c | 9 --------- > 1 file changed, 9 deletions(-) Please see bug: https://bugs.launchpad.net/qemu/+bug/1488363 Is this bug perhaps not as long gone as we thought, or is there something else going on here? Thanks, Alex > diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c > index 042e960..d38d24b 100644 > --- a/hw/intc/apic_common.c > +++ b/hw/intc/apic_common.c > @@ -243,15 +243,6 @@ static void apic_reset_common(DeviceState *dev) > info->vapic_base_update(s); > > apic_init_reset(dev); > - > - if (bsp) { > - /* > - * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization > - * time typically by BIOS, so PIC interrupt can be delivered to the > - * processor when local APIC is enabled. > - */ > - s->lvt[APIC_LVT_LINT0] = 0x700; > - } > } > > /* This function is only used for old state version 1 and 2 */ From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57027) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zbxdm-0008Sl-1b for qemu-devel@nongnu.org; Tue, 15 Sep 2015 17:19:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zbxdh-0005eO-JO for qemu-devel@nongnu.org; Tue, 15 Sep 2015 17:19:49 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37780) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zbxdh-0005cK-EN for qemu-devel@nongnu.org; Tue, 15 Sep 2015 17:19:45 -0400 Message-ID: <1442351982.23936.157.camel@redhat.com> From: Alex Williamson Date: Tue, 15 Sep 2015 15:19:42 -0600 In-Reply-To: <1428881529-29459-2-git-send-email-namit@cs.technion.ac.il> References: <1428881529-29459-1-git-send-email-namit@cs.technion.ac.il> <1428881529-29459-2-git-send-email-namit@cs.technion.ac.il> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/2] target-i386: disable LINT0 after reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nadav Amit Cc: kvm@vger.kernel.org, jan.kiszka@siemens.com, qemu-devel@nongnu.org, bsd@redhat.com, avi.kivity@gmail.com, pbonzini@redhat.com On Mon, 2015-04-13 at 02:32 +0300, Nadav Amit wrote: > Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone > and therefore this hack is no longer needed. Since it violates the > specifications, it is removed. > > Signed-off-by: Nadav Amit > --- > hw/intc/apic_common.c | 9 --------- > 1 file changed, 9 deletions(-) Please see bug: https://bugs.launchpad.net/qemu/+bug/1488363 Is this bug perhaps not as long gone as we thought, or is there something else going on here? Thanks, Alex > diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c > index 042e960..d38d24b 100644 > --- a/hw/intc/apic_common.c > +++ b/hw/intc/apic_common.c > @@ -243,15 +243,6 @@ static void apic_reset_common(DeviceState *dev) > info->vapic_base_update(s); > > apic_init_reset(dev); > - > - if (bsp) { > - /* > - * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization > - * time typically by BIOS, so PIC interrupt can be delivered to the > - * processor when local APIC is enabled. > - */ > - s->lvt[APIC_LVT_LINT0] = 0x700; > - } > } > > /* This function is only used for old state version 1 and 2 */