From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932877AbbIVHj5 (ORCPT ); Tue, 22 Sep 2015 03:39:57 -0400 Received: from lucky1.263xmail.com ([211.157.147.130]:57719 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932115AbbIVHjz (ORCPT ); Tue, 22 Sep 2015 03:39:55 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: ykk@rock-chips.com X-FST-TO: inki.dae@samsung.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: ykk@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Yakir Yang To: Inki Dae , Andrzej Hajda , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Jingoo Han , Heiko Stuebner , Mark Yao , Thierry Reding , joe@perches.com, Krzysztof Kozlowski , Rob Herring Cc: David Airlie , Russell King , djkurtz@chromium.org, dianders@chromium.org, Sean Paul , Kukjin Kim , Kumar Gala , emil.l.velikov@gmail.com, Ian Campbell , Gustavo Padovan , Kishon Vijay Abraham I , Pawel Moll , ajaynumb@gmail.com, robherring2@gmail.com, Andy Yan , Yakir Yang , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Date: Tue, 22 Sep 2015 15:35:14 +0800 Message-Id: <1442907314-3065-1-git-send-email-ykk@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442906428-2609-1-git-send-email-ykk@rock-chips.com> References: <1442906428-2609-1-git-send-email-ykk@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org link_rate and lane_count already configured in analogix_dp_set_link_train(), so we don't need to config those repeatly after training finished, just remove them out. Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}. Signed-off-by: Yakir Yang --- Changes in v5: None Changes in v4: - Update commit message more readable. (Jingoo) - Adjust the order from 05 to 04 Changes in v3: - The link_rate and lane_count shouldn't config to the DT property value directly, but we can take those as hardware limite. For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would like "link-rate = 0x0a" "lane-count = 4". (Thierry) Changes in v2: None drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++---- drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++-- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index fa9eb19..1e3c8d3 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -624,6 +624,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, /* * For DP rev.1.1, Maximum link rate of Main Link lanes * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + * For DP rev.1.2, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps */ analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); *bandwidth = data; @@ -657,7 +659,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp, analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && - (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { + (dp->link_train.link_rate != LINK_RATE_2_70GBPS) && + (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) { dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", dp->link_train.link_rate); dp->link_train.link_rate = LINK_RATE_1_62GBPS; @@ -898,9 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) analogix_dp_enable_rx_to_enhanced_mode(dp, 1); analogix_dp_enable_enhanced_mode(dp, 1); - analogix_dp_set_lane_count(dp, dp->video_info->lane_count); - analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate); - analogix_dp_init_video(dp); ret = analogix_dp_config_video(dp); if (ret) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h index 14d20be..9a90a18 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h @@ -21,8 +21,9 @@ #define MAX_EQ_LOOP 5 enum link_rate_type { - LINK_RATE_1_62GBPS = 0x06, - LINK_RATE_2_70GBPS = 0x0a + LINK_RATE_1_62GBPS = DP_LINK_BW_1_62, + LINK_RATE_2_70GBPS = DP_LINK_BW_2_7, + LINK_RATE_5_40GBPS = DP_LINK_BW_5_4, }; enum link_lane_count_type { -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yakir Yang Subject: [PATCH v5 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Date: Tue, 22 Sep 2015 15:35:14 +0800 Message-ID: <1442907314-3065-1-git-send-email-ykk@rock-chips.com> References: <1442906428-2609-1-git-send-email-ykk@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1442906428-2609-1-git-send-email-ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Inki Dae , Andrzej Hajda , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Jingoo Han , Heiko Stuebner , Mark Yao , Thierry Reding , joe-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org, Krzysztof Kozlowski , Rob Herring Cc: David Airlie , djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, Yakir Yang , Gustavo Padovan , linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King , Kishon Vijay Abraham I , linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Kukjin Kim , robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Pawel Moll , Ian Campbell , Sean Paul , dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Kumar Gala , ajaynumb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, Andy Yan List-Id: devicetree@vger.kernel.org link_rate and lane_count already configured in analogix_dp_set_link_train(), so we don't need to config those repeatly after training finished, just remove them out. Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}. Signed-off-by: Yakir Yang --- Changes in v5: None Changes in v4: - Update commit message more readable. (Jingoo) - Adjust the order from 05 to 04 Changes in v3: - The link_rate and lane_count shouldn't config to the DT property value directly, but we can take those as hardware limite. For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would like "link-rate = 0x0a" "lane-count = 4". (Thierry) Changes in v2: None drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++---- drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++-- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index fa9eb19..1e3c8d3 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -624,6 +624,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, /* * For DP rev.1.1, Maximum link rate of Main Link lanes * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + * For DP rev.1.2, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps */ analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); *bandwidth = data; @@ -657,7 +659,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp, analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && - (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { + (dp->link_train.link_rate != LINK_RATE_2_70GBPS) && + (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) { dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", dp->link_train.link_rate); dp->link_train.link_rate = LINK_RATE_1_62GBPS; @@ -898,9 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) analogix_dp_enable_rx_to_enhanced_mode(dp, 1); analogix_dp_enable_enhanced_mode(dp, 1); - analogix_dp_set_lane_count(dp, dp->video_info->lane_count); - analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate); - analogix_dp_init_video(dp); ret = analogix_dp_config_video(dp); if (ret) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h index 14d20be..9a90a18 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h @@ -21,8 +21,9 @@ #define MAX_EQ_LOOP 5 enum link_rate_type { - LINK_RATE_1_62GBPS = 0x06, - LINK_RATE_2_70GBPS = 0x0a + LINK_RATE_1_62GBPS = DP_LINK_BW_1_62, + LINK_RATE_2_70GBPS = DP_LINK_BW_2_7, + LINK_RATE_5_40GBPS = DP_LINK_BW_5_4, }; enum link_lane_count_type { -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: ykk@rock-chips.com (Yakir Yang) Date: Tue, 22 Sep 2015 15:35:14 +0800 Subject: [PATCH v5 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count In-Reply-To: <1442906428-2609-1-git-send-email-ykk@rock-chips.com> References: <1442906428-2609-1-git-send-email-ykk@rock-chips.com> Message-ID: <1442907314-3065-1-git-send-email-ykk@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org link_rate and lane_count already configured in analogix_dp_set_link_train(), so we don't need to config those repeatly after training finished, just remove them out. Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}. Signed-off-by: Yakir Yang --- Changes in v5: None Changes in v4: - Update commit message more readable. (Jingoo) - Adjust the order from 05 to 04 Changes in v3: - The link_rate and lane_count shouldn't config to the DT property value directly, but we can take those as hardware limite. For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would like "link-rate = 0x0a" "lane-count = 4". (Thierry) Changes in v2: None drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++---- drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++-- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index fa9eb19..1e3c8d3 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -624,6 +624,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, /* * For DP rev.1.1, Maximum link rate of Main Link lanes * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + * For DP rev.1.2, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps */ analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); *bandwidth = data; @@ -657,7 +659,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp, analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && - (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { + (dp->link_train.link_rate != LINK_RATE_2_70GBPS) && + (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) { dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", dp->link_train.link_rate); dp->link_train.link_rate = LINK_RATE_1_62GBPS; @@ -898,9 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) analogix_dp_enable_rx_to_enhanced_mode(dp, 1); analogix_dp_enable_enhanced_mode(dp, 1); - analogix_dp_set_lane_count(dp, dp->video_info->lane_count); - analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate); - analogix_dp_init_video(dp); ret = analogix_dp_config_video(dp); if (ret) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h index 14d20be..9a90a18 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h @@ -21,8 +21,9 @@ #define MAX_EQ_LOOP 5 enum link_rate_type { - LINK_RATE_1_62GBPS = 0x06, - LINK_RATE_2_70GBPS = 0x0a + LINK_RATE_1_62GBPS = DP_LINK_BW_1_62, + LINK_RATE_2_70GBPS = DP_LINK_BW_2_7, + LINK_RATE_5_40GBPS = DP_LINK_BW_5_4, }; enum link_lane_count_type { -- 1.9.1