From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wenzhuo Lu Subject: [PATCH 1/6] lib/librte_ether: modify the structures for fdir new modes Date: Fri, 25 Sep 2015 14:05:20 +0800 Message-ID: <1443161125-1035-2-git-send-email-wenzhuo.lu@intel.com> References: <1443161125-1035-1-git-send-email-wenzhuo.lu@intel.com> To: dev@dpdk.org Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id BE5648E79 for ; Fri, 25 Sep 2015 08:05:35 +0200 (CEST) In-Reply-To: <1443161125-1035-1-git-send-email-wenzhuo.lu@intel.com> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Define the new modes and modify the filter and mask structure for the mac vlan and cloud modes. Signed-off-by: Wenzhuo Lu --- lib/librte_ether/rte_eth_ctrl.h | 68 ++++++++++++++++++++++++++++++----------- 1 file changed, 50 insertions(+), 18 deletions(-) diff --git a/lib/librte_ether/rte_eth_ctrl.h b/lib/librte_ether/rte_eth_ctrl.h index 26b7b33..66d6c1a 100644 --- a/lib/librte_ether/rte_eth_ctrl.h +++ b/lib/librte_ether/rte_eth_ctrl.h @@ -248,6 +248,17 @@ enum rte_eth_tunnel_type { }; /** + * Flow Director setting modes: none, signature or perfect. + */ +enum rte_fdir_mode { + RTE_FDIR_MODE_NONE = 0, /**< Disable FDIR support. */ + RTE_FDIR_MODE_SIGNATURE, /**< Enable FDIR signature filter mode. */ + RTE_FDIR_MODE_PERFECT, /**< Enable FDIR perfect filter mode for IP. */ + RTE_FDIR_MODE_PERFECT_MAC_VLAN, /**< Enable FDIR filter mode - MAC VLAN. */ + RTE_FDIR_MODE_PERFECT_CLOUD, /**< Enable FDIR filter mode - cloud. */ +}; + +/** * filter type of tunneling packet */ #define ETH_TUNNEL_FILTER_OMAC 0x01 /**< filter by outer MAC addr */ @@ -377,18 +388,45 @@ struct rte_eth_sctpv6_flow { }; /** + * A structure used to define the input for MAC VLAN flow + */ +struct rte_eth_mac_vlan_flow { + struct ether_addr mac_addr; /**< Mac address to match. */ +}; + +/** + * Tunnel type for flow director. + */ +enum rte_eth_fdir_tunnel_type { + RTE_FDIR_TUNNEL_TYPE_NVGRE = 0, + RTE_FDIR_TUNNEL_TYPE_VXLAN, + RTE_FDIR_TUNNEL_TYPE_UNKNOWN, +}; + +/** + * A structure used to define the input for VxLAN NVGRE flow + */ +struct rte_eth_cloud_flow { + enum rte_eth_fdir_tunnel_type tunnel_type; /**< Tunnel type to match. */ + uint32_t tni_vni; /**< TNI or VNI to match. */ + struct ether_addr mac_addr; /**< Mac address to match. */ +}; + +/** * An union contains the inputs for all types of flow */ union rte_eth_fdir_flow { - struct rte_eth_l2_flow l2_flow; - struct rte_eth_udpv4_flow udp4_flow; - struct rte_eth_tcpv4_flow tcp4_flow; - struct rte_eth_sctpv4_flow sctp4_flow; - struct rte_eth_ipv4_flow ip4_flow; - struct rte_eth_udpv6_flow udp6_flow; - struct rte_eth_tcpv6_flow tcp6_flow; - struct rte_eth_sctpv6_flow sctp6_flow; - struct rte_eth_ipv6_flow ipv6_flow; + struct rte_eth_l2_flow l2_flow; + struct rte_eth_udpv4_flow udp4_flow; + struct rte_eth_tcpv4_flow tcp4_flow; + struct rte_eth_sctpv4_flow sctp4_flow; + struct rte_eth_ipv4_flow ip4_flow; + struct rte_eth_udpv6_flow udp6_flow; + struct rte_eth_tcpv6_flow tcp6_flow; + struct rte_eth_sctpv6_flow sctp6_flow; + struct rte_eth_ipv6_flow ipv6_flow; + struct rte_eth_mac_vlan_flow mac_vlan_flow; + struct rte_eth_cloud_flow cloud_flow; }; /** @@ -465,6 +503,9 @@ struct rte_eth_fdir_masks { struct rte_eth_ipv6_flow ipv6_mask; uint16_t src_port_mask; uint16_t dst_port_mask; + uint8_t mac_addr_mask; /** Per byte MAC address mask */ + uint32_t tni_vni_mask; /** Per byte TNI or VNI mask */ + uint8_t tunnel_type_mask; }; /** @@ -515,15 +556,6 @@ struct rte_eth_fdir_flex_conf { /**< Flex mask configuration for each flow type */ }; -/** - * Flow Director setting modes: none, signature or perfect. - */ -enum rte_fdir_mode { - RTE_FDIR_MODE_NONE = 0, /**< Disable FDIR support. */ - RTE_FDIR_MODE_SIGNATURE, /**< Enable FDIR signature filter mode. */ - RTE_FDIR_MODE_PERFECT, /**< Enable FDIR perfect filter mode. */ -}; - #define UINT32_BIT (CHAR_BIT * sizeof(uint32_t)) #define RTE_FLOW_MASK_ARRAY_SIZE \ (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT) -- 1.9.3