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From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
To: <bp@suse.de>, <tglx@linutronix.de>, <mingo@redhat.com>, <hpa@zytor.com>
Cc: <x86@kernel.org>, <linux-kernel@vger.kernel.org>,
	Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Subject: [PATCH V2 3/3] RAS, mce_amd_inj: Inject errors on NBC for bank 4 errors
Date: Fri, 25 Sep 2015 09:20:51 -0500	[thread overview]
Message-ID: <1443190851-2172-4-git-send-email-Aravind.Gopalakrishnan@amd.com> (raw)
In-Reply-To: <1443190851-2172-1-git-send-email-Aravind.Gopalakrishnan@amd.com>

Bank 4 MCEs are logged and reported only on the node base core (NBC) in
a socket. Refer to the D18F3x44[NbMcaToMstCpuEn] field in Fam10h and
later BKDGs. The node base core (NBC) is the lowest numbered core in the
node.

This patch ensures that we inject the error on the NBC for bank 4
errors. Otherwise, triggering #MC or APIC interrupts on a core which is
not the NBC would not have any effect on the system, i.e we would not
see any relevant output on kernel logs for the error we just injected.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
 arch/x86/ras/mce_amd_inj.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/arch/x86/ras/mce_amd_inj.c b/arch/x86/ras/mce_amd_inj.c
index 794ca1f..42ab672 100644
--- a/arch/x86/ras/mce_amd_inj.c
+++ b/arch/x86/ras/mce_amd_inj.c
@@ -17,7 +17,9 @@
 #include <linux/cpu.h>
 #include <linux/string.h>
 #include <linux/uaccess.h>
+#include <linux/pci.h>
 #include <asm/mce.h>
+#include <asm/amd_nb.h>
 
 #include "../kernel/cpu/mcheck/mce-internal.h"
 
@@ -30,6 +32,7 @@ static struct dentry *dfs_inj;
 static u8 n_banks;
 
 #define MAX_FLAG_OPT_SIZE	3
+#define NBCFG			0x44
 
 enum injection_type {
 	SW_INJ = 0,	/* SW injection, simply decode the error */
@@ -196,6 +199,45 @@ static void trigger_thr_int(void *info)
 	asm volatile("int %0" :: "i" (THRESHOLD_APIC_VECTOR));
 }
 
+static u32 get_nbc_for_node(int node_id)
+{
+	struct cpuinfo_x86 *c = &boot_cpu_data;
+	u32 cores_per_node;
+
+	cores_per_node = c->x86_max_cores / amd_get_nodes_per_socket();
+
+	return cores_per_node * node_id;
+}
+
+static void toggle_nb_mca_mst_cpu(u16 nid)
+{
+	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
+	u32 val;
+	int err;
+
+	if (!F3)
+		return;
+
+	err = pci_read_config_dword(F3, NBCFG, &val);
+	if (err) {
+		pr_err("%s: Error reading F%dx%03x.\n",
+		       __func__, PCI_FUNC(F3->devfn), NBCFG);
+		return;
+	}
+
+	if (val & BIT(27))
+		return;
+
+	pr_err("%s: Set D18F3x44[NbMcaToMstCpuEn] which BIOS hasn't done.\n",
+	       __func__);
+
+	val |= BIT(27);
+	err = pci_write_config_dword(F3, NBCFG, val);
+	if (err)
+		pr_err("%s: Error writing F%dx%03x.\n",
+		       __func__, PCI_FUNC(F3->devfn), NBCFG);
+}
+
 static void do_inject(void)
 {
 	u64 mcg_status = 0;
@@ -230,6 +272,20 @@ static void do_inject(void)
 		i_mce.status |= (i_mce.status & ~MCI_STATUS_UC);
 	}
 
+	/*
+	 * For multi node CPUs, logging and reporting of bank 4 errors happens
+	 * only on the node base core. Refer to D18F3x44[NbMcaToMstCpuEn] for
+	 * Fam10h and later BKDGs.
+	 */
+	if (static_cpu_has(X86_FEATURE_AMD_DCM) && b == 4) {
+		/*
+		 * BIOS sets D18F3x44[NbMcaToMstCpuEn] by default. But make
+		 * sure of it here just in case.
+		 */
+		toggle_nb_mca_mst_cpu(amd_get_nb_id(cpu));
+		cpu = get_nbc_for_node(amd_get_nb_id(cpu));
+	}
+
 	get_online_cpus();
 	if (!cpu_online(cpu))
 		goto err;
-- 
2.4.0


  parent reply	other threads:[~2015-09-25 19:17 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-25 14:20 [PATCH V2 0/3] Updates to mce_amd_inj module Aravind Gopalakrishnan
2015-09-25 14:20 ` [PATCH V2 1/3] RAS, mce_amd_inj: Return early on invalid input Aravind Gopalakrishnan
2015-09-25 14:20 ` [PATCH V2 2/3] RAS, mce_amd_inj: Add capability to trigger apic interrupts Aravind Gopalakrishnan
2015-09-25 14:20 ` Aravind Gopalakrishnan [this message]
2015-09-28  9:06 ` [PATCH V2 0/3] Updates to mce_amd_inj module Borislav Petkov
2015-10-12  9:22 [PATCH 0/6] tip-queue 2015-10-12 Borislav Petkov
2015-10-12  9:22 ` [PATCH 1/6] x86/mce: Don't clear shared banks on Intel when offlining CPUs Borislav Petkov
2015-10-12  9:22 ` [PATCH 2/6] x86/ras/mce_amd_inj: Return early on invalid input Borislav Petkov
2015-10-12 14:31   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2015-10-12  9:22 ` [PATCH 3/6] x86/ras/mce_amd_inj: Trigger deferred and thresholding errors interrupts Borislav Petkov
2015-10-12 14:31   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2015-10-12  9:22 ` [PATCH 4/6] x86/ras/mce_amd_inj: Inject bank 4 errors on the NBC Borislav Petkov
2015-10-12 14:31   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2015-10-12  9:22 ` [PATCH 5/6] x86/microcode/amd: Extract current patch level read to a function Borislav Petkov
2015-10-12 14:32   ` [tip:ras/core] " tip-bot for Borislav Petkov
2015-10-12  9:22 ` [PATCH 6/6] x86/microcode/amd: Do not overwrite final patch levels Borislav Petkov
2015-10-12 14:32   ` [tip:ras/core] " tip-bot for Borislav Petkov

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