From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40015) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZgJVV-00052O-Ez for qemu-devel@nongnu.org; Sun, 27 Sep 2015 17:29:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZgJVT-0005ar-JH for qemu-devel@nongnu.org; Sun, 27 Sep 2015 17:29:17 -0400 Received: from relay-06.andrew.cmu.edu ([128.2.157.21]:60907 helo=relay.andrew.cmu.edu) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZgJVT-0005an-F3 for qemu-devel@nongnu.org; Sun, 27 Sep 2015 17:29:15 -0400 From: "Gabriel L. Somlo" Date: Sun, 27 Sep 2015 17:28:58 -0400 Message-Id: <1443389342-2186-2-git-send-email-somlo@cmu.edu> In-Reply-To: <1443389342-2186-1-git-send-email-somlo@cmu.edu> References: <1443389342-2186-1-git-send-email-somlo@cmu.edu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v4 1/5] fw_cfg: expose control register size in fw_cfg.h List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, drjones@redhat.com, matt.fleming@intel.com, ehabkost@redhat.com, mst@redhat.com, zhaoshenglong@huawei.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, kevin@koconnor.net, kraxel@redhat.com, pbonzini@redhat.com, imammedo@redhat.com, markmb@redhat.com, lersek@redhat.com, rth@twiddle.net Expose the size of the control register (FW_CFG_SIZE, renamed to FW_CFG_CTL_SIZE) in fw_cfg.h. Add comment to fw_cfg_io_realize() pointing out that since the 8-bit data register is always subsumed by the 16-bit control register in the port I/O case, we use the control register width as the *total* width of the port I/O region reserved for the device. Suggested-by: Marc Mar=C3=AD Signed-off-by: Gabriel Somlo --- hw/nvram/fw_cfg.c | 8 +++++--- include/hw/nvram/fw_cfg.h | 3 +++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 658f8c4..9dd95c7 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -30,7 +30,6 @@ #include "qemu/error-report.h" #include "qemu/config-file.h" =20 -#define FW_CFG_SIZE 2 #define FW_CFG_NAME "fw_cfg" #define FW_CFG_PATH "/machine/" FW_CFG_NAME =20 @@ -672,8 +671,11 @@ static void fw_cfg_io_realize(DeviceState *dev, Erro= r **errp) FWCfgIoState *s =3D FW_CFG_IO(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); =20 + /* when using port i/o, the 8-bit data register ALWAYS overlaps + * with half of the 16-bit control register. Hence, the total size + * of the i/o region used is FW_CFG_CTL_SIZE */ memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_op= s, - FW_CFG(s), "fwcfg", FW_CFG_SIZE); + FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE); sysbus_add_io(sbd, s->iobase, &s->comb_iomem); } =20 @@ -705,7 +707,7 @@ static void fw_cfg_mem_realize(DeviceState *dev, Erro= r **errp) const MemoryRegionOps *data_ops =3D &fw_cfg_data_mem_ops; =20 memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops, - FW_CFG(s), "fwcfg.ctl", FW_CFG_SIZE); + FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE); sysbus_init_mmio(sbd, &s->ctl_iomem); =20 if (s->data_width > data_ops->valid.max_access_size) { diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h index e60d3ca..5008270 100644 --- a/include/hw/nvram/fw_cfg.h +++ b/include/hw/nvram/fw_cfg.h @@ -46,6 +46,9 @@ =20 #define FW_CFG_INVALID 0xffff =20 +/* width in bytes of fw_cfg control port */ +#define FW_CFG_CTL_SIZE 0x02 + #define FW_CFG_MAX_FILE_PATH 56 =20 #ifndef NO_QEMU_PROTOS --=20 2.4.3