From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH v1 6/8] xen/arm: vgic: Optimize the way to store the target vCPU in the rank Date: Thu, 1 Oct 2015 09:30:37 +0100 Message-ID: <1443688237.16718.216.camel@citrix.com> References: <1443192698-16163-1-git-send-email-julien.grall@citrix.com> <1443192698-16163-7-git-send-email-julien.grall@citrix.com> <1443532034.16718.63.camel@citrix.com> <560A93DB.4090701@citrix.com> <1443536619.16718.104.camel@citrix.com> <560C25C9.8040207@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1ZhZGE-0004EG-2O for xen-devel@lists.xenproject.org; Thu, 01 Oct 2015 08:30:42 +0000 In-Reply-To: <560C25C9.8040207@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Julien Grall , xen-devel@lists.xenproject.org Cc: Vijaya.Kumar@caviumnetworks.com, stefano.stabellini@citrix.com, manish.jaggi@caviumnetworks.com, vijay.kilari@gmail.com List-Id: xen-devel@lists.xenproject.org On Wed, 2015-09-30 at 19:11 +0100, Julien Grall wrote: > On 29/09/15 15:23, Ian Campbell wrote: > > On Tue, 2015-09-29 at 14:36 +0100, Julien Grall wrote: > > > On 29/09/15 14:07, Ian Campbell wrote: > > > > On Fri, 2015-09-25 at 15:51 +0100, Julien Grall wrote: > > > > > Xen is currently directly storing the value of register > > > > > GICD_ITARGETSR > > > > > (for GICv2) and GICD_IROUTER (for GICv3) in the rank. This makes > > > > > the > > > > > emulation of the registers access very simple but makes the code > > > > > to > > > > > get > > > > > the target vCPU for a given IRQ more complex. > > > > > > > > > > While the target vCPU of an IRQ is retrieved everytime an IRQ is > > > > > injected to the guest, the access to the register occurs less > > > > > often. > > > > > > > > > > So the data structure should be optimized for the most common > > > > > case > > > > > rather than the inverse. > > > > > > > > > > This patch introduce the usage of an array to store the target > > > > > vCPU > > > > > for > > > > > every interrupt in the rank. This will make the code to get the > > > > > target > > > > > very quick. The emulation code will now have to generate the > > > > > GICD_ITARGETSR > > > > > and GICD_IROUTER register for read access and split it to store > > > > > in a > > > > > convenient way. > > > > > > > > > > Note that with these changes, any read to those registers will > > > > > list > > > > > only > > > > > the target vCPU used by Xen. This is fine because the GIC spec > > > > > doesn't > > > > > require to return exactly the value written and it can be seen as > > > > > if > > > > > we > > > > > decide to implement the register read-only. > > > > > > > > I think this is probably OK, but skirting round what the spec > > > > actually > > > > says > > > > a fair bit. > > > > > > Well, nothing in the spec clearly explain the behavior of a read > > > access > > > on the register. An implementation could decide to make some bits RO > > > or > > > even not store everything. > > > > > > FWIW, KVM is using the same trick. > > > > At least we'll both get screwed by a picky OS then ;-) > > I think our implementation could fold into 4.3.12 IHI 0048B: > > "It is IMPLEMENTATION DEFINED which, if any, SPIs are statically > configured in hardware. The CPU targets field for such an SPI is > read-only, and returns a value that indicates the CPU targets for the > interrupt." > > We are implementing a weird read-only but at least an OS should not > trust the written value. It's certainly a weird read-only, in that it isn't at all read-only, but I agree its likely to be tolerated by most OSes. Note though that an OS written by a pedant would be quite entitled to do: old_targets = readb(GICD_TARGETR+irq) writeb(GICD_TARGET+irq, new_targets) foo = readb(GICD_TARGETR+irq) ASSERT(foo==old_targets || foo==new_targets) That would be rather retentive though. Ian.