From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53320) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZiVSN-0004lZ-US for qemu-devel@nongnu.org; Sat, 03 Oct 2015 18:39:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZiVSI-0006J4-T4 for qemu-devel@nongnu.org; Sat, 03 Oct 2015 18:39:07 -0400 Received: from mail-pa0-x22e.google.com ([2607:f8b0:400e:c03::22e]:33010) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZiVSI-0006Iv-N1 for qemu-devel@nongnu.org; Sat, 03 Oct 2015 18:39:02 -0400 Received: by pacex6 with SMTP id ex6so139077800pac.0 for ; Sat, 03 Oct 2015 15:39:01 -0700 (PDT) From: "Edgar E. Iglesias" Date: Sat, 3 Oct 2015 15:38:50 -0700 Message-Id: <1443911939-2825-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v3 0/9] arm: Steps towards EL2 support round 5 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: laurent.desnogues@gmail.com, serge.fdrv@gmail.com, edgar.iglesias@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Hi, Another round of patches towards EL2 support. This one adds partial support for 2-stage MMU. The AArch32/ARMv7 support is untested. Some of the details of error reporting are intentionally missing, I was thinking to add those incrementally as they get quite involved (e.g the register target and memory access size). Comments welcome! Best regards, Edgar v2 -> v3: * Prettify comments for ARMMMUFaultInfo * Add S2 translation for 32bit S1 PTWs * Add more comments to S2 PTW starting level computation. v1 -> v2: * Fix HPFAR_EL2 access checks * Prettify computation of starting level for S2 PTW * Improve description of ap argument to get_S2prot * Fix EXEC protection in get_S2prot * Improve comments on S2 PTW attribute extraction * Add comment describing ARMMMUFaultInfo Edgar E. Iglesias (9): target-arm: Add HPFAR_EL2 target-arm: Add computation of starting level for S2 PTW target-arm: Add support for S2 page-table protection bits target-arm: Avoid inline for get_phys_addr target-arm: Add ARMMMUFaultInfo target-arm: Add S2 translation to 64bit S1 PTWs target-arm: Add S2 translation to 32bit S1 PTWs target-arm: Route S2 MMU faults to EL2 target-arm: Add support for S1 + S2 MMU translations target-arm/cpu.h | 1 + target-arm/helper.c | 252 +++++++++++++++++++++++++++++++++++++++---------- target-arm/internals.h | 15 ++- target-arm/op_helper.c | 17 +++- 4 files changed, 231 insertions(+), 54 deletions(-) -- 1.9.1