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From: Borislav Petkov <bp@alien8.de>
To: Ingo Molnar <mingo@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>
Subject: [PATCH 3/6] x86/ras/mce_amd_inj: Trigger deferred and thresholding errors interrupts
Date: Mon, 12 Oct 2015 11:22:39 +0200	[thread overview]
Message-ID: <1444641762-9437-4-git-send-email-bp@alien8.de> (raw)
In-Reply-To: <1444641762-9437-1-git-send-email-bp@alien8.de>

From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>

Add the capability to trigger deferred error interrupts and threshold
interrupts in order to test the APIC interrupt handler functionality for
these type of errors.

Update README section about the same too.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Reported by: kbuild test robot <fengguang.wu@intel.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1443190851-2172-3-git-send-email-Aravind.Gopalakrishnan@amd.com
[ Cleanup comments. ]
[ Include asm/irq_vectors.h directly so that misc randbuilds don't fail. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/ras/mce_amd_inj.c | 42 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/arch/x86/ras/mce_amd_inj.c b/arch/x86/ras/mce_amd_inj.c
index 4fd8bb9b90b9..4d3bafb540c2 100644
--- a/arch/x86/ras/mce_amd_inj.c
+++ b/arch/x86/ras/mce_amd_inj.c
@@ -17,7 +17,9 @@
 #include <linux/cpu.h>
 #include <linux/string.h>
 #include <linux/uaccess.h>
+
 #include <asm/mce.h>
+#include <asm/irq_vectors.h>
 
 #include "../kernel/cpu/mcheck/mce-internal.h"
 
@@ -34,12 +36,16 @@ static u8 n_banks;
 enum injection_type {
 	SW_INJ = 0,	/* SW injection, simply decode the error */
 	HW_INJ,		/* Trigger a #MC */
+	DFR_INT_INJ,    /* Trigger Deferred error interrupt */
+	THR_INT_INJ,    /* Trigger threshold interrupt */
 	N_INJ_TYPES,
 };
 
 static const char * const flags_options[] = {
 	[SW_INJ] = "sw",
 	[HW_INJ] = "hw",
+	[DFR_INT_INJ] = "df",
+	[THR_INT_INJ] = "th",
 	NULL
 };
 
@@ -182,6 +188,16 @@ static void trigger_mce(void *info)
 	asm volatile("int $18");
 }
 
+static void trigger_dfr_int(void *info)
+{
+	asm volatile("int %0" :: "i" (DEFERRED_ERROR_VECTOR));
+}
+
+static void trigger_thr_int(void *info)
+{
+	asm volatile("int %0" :: "i" (THRESHOLD_APIC_VECTOR));
+}
+
 static void do_inject(void)
 {
 	u64 mcg_status = 0;
@@ -202,6 +218,16 @@ static void do_inject(void)
 	if (!(i_mce.status & MCI_STATUS_PCC))
 		mcg_status |= MCG_STATUS_RIPV;
 
+	/*
+	 * Ensure necessary status bits for deferred errors:
+	 * - MCx_STATUS[Deferred]: make sure it is a deferred error
+	 * - MCx_STATUS[UC] cleared: deferred errors are _not_ UC
+	 */
+	if (inj_type == DFR_INT_INJ) {
+		i_mce.status |= MCI_STATUS_DEFERRED;
+		i_mce.status |= (i_mce.status & ~MCI_STATUS_UC);
+	}
+
 	get_online_cpus();
 	if (!cpu_online(cpu))
 		goto err;
@@ -222,7 +248,16 @@ static void do_inject(void)
 
 	toggle_hw_mce_inject(cpu, false);
 
-	smp_call_function_single(cpu, trigger_mce, NULL, 0);
+	switch (inj_type) {
+	case DFR_INT_INJ:
+		smp_call_function_single(cpu, trigger_dfr_int, NULL, 0);
+		break;
+	case THR_INT_INJ:
+		smp_call_function_single(cpu, trigger_thr_int, NULL, 0);
+		break;
+	default:
+		smp_call_function_single(cpu, trigger_mce, NULL, 0);
+	}
 
 err:
 	put_online_cpus();
@@ -287,6 +322,11 @@ static const char readme_msg[] =
 "\t    handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n"
 "\t    is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n"
 "\t    before injecting.\n"
+"\t  - \"df\": Trigger APIC interrupt for Deferred error. Causes deferred \n"
+"\t    error APIC interrupt handler to handle the error if the feature is \n"
+"\t    is present in hardware. \n"
+"\t  - \"th\": Trigger APIC interrupt for Threshold errors. Causes threshold \n"
+"\t    APIC interrupt handler to handle the error. \n"
 "\n";
 
 static ssize_t
-- 
2.3.5


  parent reply	other threads:[~2015-10-12  9:23 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-12  9:22 [PATCH 0/6] tip-queue 2015-10-12 Borislav Petkov
2015-10-12  9:22 ` [PATCH 1/6] x86/mce: Don't clear shared banks on Intel when offlining CPUs Borislav Petkov
2015-10-12  9:22 ` [PATCH 2/6] x86/ras/mce_amd_inj: Return early on invalid input Borislav Petkov
2015-10-12 14:31   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2015-10-12  9:22 ` Borislav Petkov [this message]
2015-10-12 14:31   ` [tip:ras/core] x86/ras/mce_amd_inj: Trigger deferred and thresholding errors interrupts tip-bot for Aravind Gopalakrishnan
2015-10-12  9:22 ` [PATCH 4/6] x86/ras/mce_amd_inj: Inject bank 4 errors on the NBC Borislav Petkov
2015-10-12 14:31   ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2015-10-12  9:22 ` [PATCH 5/6] x86/microcode/amd: Extract current patch level read to a function Borislav Petkov
2015-10-12 14:32   ` [tip:ras/core] " tip-bot for Borislav Petkov
2015-10-12  9:22 ` [PATCH 6/6] x86/microcode/amd: Do not overwrite final patch levels Borislav Petkov
2015-10-12 14:32   ` [tip:ras/core] " tip-bot for Borislav Petkov
  -- strict thread matches above, loose matches on Subject: below --
2015-09-25 14:20 [PATCH V2 0/3] Updates to mce_amd_inj module Aravind Gopalakrishnan
2015-09-25 14:20 ` [PATCH V2 1/3] RAS, mce_amd_inj: Return early on invalid input Aravind Gopalakrishnan
2015-09-25 14:20 ` [PATCH V2 2/3] RAS, mce_amd_inj: Add capability to trigger apic interrupts Aravind Gopalakrishnan
2015-09-25 14:20 ` [PATCH V2 3/3] RAS, mce_amd_inj: Inject errors on NBC for bank 4 errors Aravind Gopalakrishnan
2015-09-28  9:06 ` [PATCH V2 0/3] Updates to mce_amd_inj module Borislav Petkov

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