From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: [PATCH v4 0/5] xen/arm: vgic: Support 32-bit access for 64-bit register Date: Mon, 12 Oct 2015 15:22:35 +0100 Message-ID: <1444659760-24123-1-git-send-email-julien.grall@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Zle1X-00026B-66 for xen-devel@lists.xenproject.org; Mon, 12 Oct 2015 14:24:23 +0000 List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xenproject.org Cc: Julien Grall , ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Hi all, This series aims to fix the 32-bit access on 64-bit register. Some guest OS such as FreeBSD and Linux (ITS and recently 32-bit guest using GICv3) use 32-bit access and will crash at boot time. Major changes in v4: - Patch #1-#6 of the previous version has been applied - Split "Optimize the way to store the target vCPU in the rank" in 3 patchs to avoiding fixing a bug (byte access), changing behavior (handle zero write), and the actual optimizing in a single patch. Sincerely yours, Julien Grall (5): xen/arm: vgic-v2: Handle correctly byte write in ITARGETSR xen/arm: vgic-v2: Don't ignore a write in ITARGETSR if one field is 0 xen/arm: vgic: Optimize the way to store the target vCPU in the rank xen/arm: vgic: Introduce helpers to extract/update/clear/set vGIC register ... xen/arm: vgic-v3: Support 32-bit access for 64-bit registers xen/arch/arm/vgic-v2.c | 276 +++++++++++++++++++++++++++------------------ xen/arch/arm/vgic-v3.c | 264 +++++++++++++++++++++++++++---------------- xen/arch/arm/vgic.c | 45 ++++++-- xen/include/asm-arm/vgic.h | 129 +++++++++++++++++---- 4 files changed, 474 insertions(+), 240 deletions(-) -- 2.1.4