From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: [PATCH v4 5/5] xen/arm: vgic-v3: Support 32-bit access for 64-bit registers Date: Mon, 12 Oct 2015 15:22:40 +0100 Message-ID: <1444659760-24123-6-git-send-email-julien.grall@citrix.com> References: <1444659760-24123-1-git-send-email-julien.grall@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Zle1X-00026V-VT for xen-devel@lists.xenproject.org; Mon, 12 Oct 2015 14:24:24 +0000 In-Reply-To: <1444659760-24123-1-git-send-email-julien.grall@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xenproject.org Cc: Julien Grall , ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Based on 8.1.3 (IHI 0069A), unless stated otherwise, the 64-bit registers supports both 32-bit and 64-bits access. All the registers we properly emulate (i.e not RAZ/WI) supports 32-bit access. For RAZ/WI, it's also seems to be the case but I'm not 100% sure. Anyway, emulating 32-bit access for them doesn't hurt. Note that we would need some extra care when they will be implemented (for instance GICR_PROPBASER). Signed-off-by: Julien Grall Acked-by: Ian Campbell --- This is technically fixing boot of FreeBSD ARM64 guest with GICv3. The next version of Linux (4.4) will contain support of GICv3 for 32-bit OS. While we only support GICv3 on 64-bit host, the vGICv3 is not tight to 64-bit. This patch will allow 32-bit guest booting on platform which doesn't have a GICv3 compatible with GICv2. So this patch is a good candidate for Xen 4.6.1. Although this patch is heavily depend on previous patches. It may be possible to shuffle and move the "opmitization" patches towards the end. I haven't yet done that because I feel this series makes more sense in the current order. Also, I haven't move vgic_reg64_check_access in vgic.h because there is no usage in this series outside of vgic-v3.c and the helpers is GICv3 oriented. Changes in v2: - Add Ian's acked-by Changes in v1: - Support 32bit access on the most significant word of GICR_TYPER --- xen/arch/arm/vgic-v3.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 75db23d..659d784 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -157,6 +157,15 @@ static void vgic_store_irouter(struct domain *d, struct vgic_irq_rank *rank, rank->vcpu[offset] = new_vcpu->vcpu_id; } +static inline bool vgic_reg64_check_access(struct hsr_dabt dabt) +{ + /* + * 64 bits registers can be accessible using 32-bit and 64-bit unless + * stated otherwise (See 8.1.3 ARM IHI 0069A). + */ + return ( dabt.size == DABT_DOUBLE_WORD || dabt.size == DABT_WORD ); +} + static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, uint32_t gicr_reg, register_t *r) @@ -173,10 +182,11 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, *r = vgic_reg32_extract(GICV3_GICR_IIDR_VAL, info); return 1; case GICR_TYPER: + case GICR_TYPER + 4: { uint64_t typer, aff; - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width; + if ( !vgic_reg64_check_access(dabt) ) goto bad_width; /* TBD: Update processor id in [23:8] when ITS support is added */ aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 | MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 | @@ -262,7 +272,7 @@ bad_width: return 0; read_as_zero_64: - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width; + if ( !vgic_reg64_check_access(dabt) ) goto bad_width; *r = 0; return 1; @@ -338,7 +348,7 @@ bad_width: return 0; write_ignore_64: - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width; + if ( vgic_reg64_check_access(dabt) ) goto bad_width; return 1; write_ignore_32: @@ -803,7 +813,7 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info, { uint64_t irouter; - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width; + if ( !vgic_reg64_check_access(dabt) ) goto bad_width; rank = vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER, DABT_DOUBLE_WORD); if ( rank == NULL ) goto read_as_zero; @@ -878,7 +888,7 @@ bad_width: return 0; read_as_zero_64: - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width; + if ( vgic_reg64_check_access(dabt) ) goto bad_width; *r = 0; return 1; @@ -971,7 +981,7 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info, { uint64_t irouter; - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width; + if ( !vgic_reg64_check_access(dabt) ) goto bad_width; rank = vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER, DABT_DOUBLE_WORD); if ( rank == NULL ) goto write_ignore; @@ -1030,7 +1040,7 @@ write_ignore_32: return 1; write_ignore_64: - if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width; + if ( vgic_reg64_check_access(dabt) ) goto bad_width; return 1; write_ignore: -- 2.1.4