From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZmUyV-0008Df-29 for qemu-devel@nongnu.org; Wed, 14 Oct 2015 18:56:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZmUyT-0007AC-VU for qemu-devel@nongnu.org; Wed, 14 Oct 2015 18:56:46 -0400 Received: from mail-pa0-x233.google.com ([2607:f8b0:400e:c03::233]:35747) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZmUyT-0007A7-8s for qemu-devel@nongnu.org; Wed, 14 Oct 2015 18:56:45 -0400 Received: by pacao1 with SMTP id ao1so2063054pac.2 for ; Wed, 14 Oct 2015 15:56:44 -0700 (PDT) From: "Edgar E. Iglesias" Date: Thu, 15 Oct 2015 00:55:44 +0200 Message-Id: <1444863346-9711-12-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1444863346-9711-1-git-send-email-edgar.iglesias@gmail.com> References: <1444863346-9711-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v4 11/13] target-arm: Add S2 translation to 32bit S1 PTWs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: laurent.desnogues@gmail.com, serge.fdrv@gmail.com, edgar.iglesias@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Add support for applying S2 translation to 32bit S1 page-table walks. Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 784cd0b..69e24e1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6182,11 +6182,19 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, * was being done for a CPU load/store or an address translation instruction * (but not if it was for a debug access). */ -static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure) +static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, uint32_t *fsr, + ARMMMUFaultInfo *fi) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; MemTxAttrs attrs = {}; attrs.secure = is_secure; + addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); + if (fi->s1ptw) { + return 0; + } return address_space_ldl(cs->as, addr, attrs, NULL); } @@ -6230,7 +6238,8 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, code = 5; goto do_fault; } - desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx)); + desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fsr, fi); type = (desc & 3); domain = (desc >> 5) & 0x0f; if (regime_el(env, mmu_idx) == 1) { @@ -6266,7 +6275,8 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, /* Fine pagetable. */ table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); } - desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx)); + desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fsr, fi); switch (desc & 3) { case 0: /* Page translation fault. */ code = 7; @@ -6347,7 +6357,8 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, code = 5; goto do_fault; } - desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx)); + desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fsr, fi); type = (desc & 3); if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { /* Section translation fault, or attempt to use the encoding @@ -6398,7 +6409,8 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, ns = extract32(desc, 3, 1); /* Lookup l2 entry. */ table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx)); + desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fsr, fi); ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); switch (desc & 3) { case 0: /* Page translation fault. */ -- 1.9.1