From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55433) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZmUxs-0007jH-AQ for qemu-devel@nongnu.org; Wed, 14 Oct 2015 18:56:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZmUxr-00071i-EE for qemu-devel@nongnu.org; Wed, 14 Oct 2015 18:56:08 -0400 Received: from mail-pa0-x22f.google.com ([2607:f8b0:400e:c03::22f]:35891) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZmUxr-00071c-8g for qemu-devel@nongnu.org; Wed, 14 Oct 2015 18:56:07 -0400 Received: by pabws5 with SMTP id ws5so2842701pab.3 for ; Wed, 14 Oct 2015 15:56:06 -0700 (PDT) From: "Edgar E. Iglesias" Date: Thu, 15 Oct 2015 00:55:36 +0200 Message-Id: <1444863346-9711-4-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1444863346-9711-1-git-send-email-edgar.iglesias@gmail.com> References: <1444863346-9711-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v4 03/13] target-arm: Add support for AArch32 S2 negative t0sz List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: laurent.desnogues@gmail.com, serge.fdrv@gmail.com, edgar.iglesias@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Add support for AArch32 S2 negative t0sz. In preparation for using 40bit IPAs on AArch32. Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4e19838..a8a46db 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6475,6 +6475,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (va_size == 64) { t0sz = MIN(t0sz, 39); t0sz = MAX(t0sz, 16); + } else { + bool sext = extract32(t0sz, 4, 1); + bool sign = extract32(t0sz, 3, 1); + t0sz = sextract32(t0sz, 0, 4); + + /* If the sign-extend bit is not the same as t0sz[3], the result + * is unpredictable. Flag this as a guest error. */ + if (sign != sext) { + qemu_log_mask(LOG_GUEST_ERROR, + "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n"); + } } int32_t t1sz = extract32(tcr->raw_tcr, 16, 6); if (va_size == 64) { -- 1.9.1