From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55539) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZmUyB-0007rf-GD for qemu-devel@nongnu.org; Wed, 14 Oct 2015 18:56:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZmUyA-00075v-Fk for qemu-devel@nongnu.org; Wed, 14 Oct 2015 18:56:27 -0400 Received: from mail-pa0-x229.google.com ([2607:f8b0:400e:c03::229]:33791) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZmUyA-00075r-9m for qemu-devel@nongnu.org; Wed, 14 Oct 2015 18:56:26 -0400 Received: by pabrc13 with SMTP id rc13so66828520pab.0 for ; Wed, 14 Oct 2015 15:56:25 -0700 (PDT) From: "Edgar E. Iglesias" Date: Thu, 15 Oct 2015 00:55:40 +0200 Message-Id: <1444863346-9711-8-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1444863346-9711-1-git-send-email-edgar.iglesias@gmail.com> References: <1444863346-9711-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v4 07/13] target-arm: Add support for S2 page-table protection bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: laurent.desnogues@gmail.com, serge.fdrv@gmail.com, edgar.iglesias@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 41 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 8530f7e..d1ffcdf 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6015,6 +6015,28 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); } +/* Translate S2 section/page access permissions to protection flags + * + * @env: CPUARMState + * @s2ap: The 2-bit stage2 access permissions (S2AP) + * @xn: XN (execute-never) bit + */ +static int get_S2prot(CPUARMState *env, int s2ap, int xn) +{ + int prot = 0; + + if (s2ap & 1) { + prot |= PAGE_READ; + } + if (s2ap & 2) { + prot |= PAGE_WRITE; + } + if (!xn) { + prot |= PAGE_EXEC; + } + return prot; +} + /* Translate section/page access permissions to protection flags * * @env: CPUARMState @@ -6715,9 +6737,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, */ page_size = (1ULL << ((stride * (4 - level)) + 3)); descaddr |= (address & (page_size - 1)); - /* Extract attributes from the descriptor and merge with table attrs */ + /* Extract attributes from the descriptor */ attrs = extract64(descriptor, 2, 10) | (extract64(descriptor, 52, 12) << 10); + + if (mmu_idx == ARMMMUIdx_S2NS) { + /* Stage 2 table descriptors do not include any attribute fields */ + break; + } + /* Merge in attributes from table descriptors */ attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 @@ -6739,11 +6767,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, } ap = extract32(attrs, 4, 2); - ns = extract32(attrs, 3, 1); xn = extract32(attrs, 12, 1); - pxn = extract32(attrs, 11, 1); - *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn); + if (mmu_idx == ARMMMUIdx_S2NS) { + ns = true; + *prot = get_S2prot(env, ap, xn); + } else { + ns = extract32(attrs, 3, 1); + pxn = extract32(attrs, 11, 1); + *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn); + } fault_type = permission_fault; if (!(*prot & (1 << access_type))) { -- 1.9.1