From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrzej Hajda Subject: [PATCH 05/10] drm/exynos/decon5433: fix timing registers writes Date: Tue, 20 Oct 2015 11:22:36 +0200 Message-ID: <1445332961-25419-6-git-send-email-a.hajda@samsung.com> References: <1445332961-25419-1-git-send-email-a.hajda@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-reply-to: <1445332961-25419-1-git-send-email-a.hajda@samsung.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Inki Dae Cc: devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , dri-devel@lists.freedesktop.org, Andrzej Hajda , Kyungmin Park , Kukjin Kim , Sylwester Nawrocki , linux-clk@vger.kernel.org, Marek Szyprowski List-Id: devicetree@vger.kernel.org QWxsIHRpbWluZyByZWdpc3RlcnMgc2hvdWxkIGNvbnRhaW4gdmFsdWVzIGRlY3JlYXNlZCBieSBv bmUuCgpTaWduZWQtb2ZmLWJ5OiBBbmRyemVqIEhhamRhIDxhLmhhamRhQHNhbXN1bmcuY29tPgot LS0KIGRyaXZlcnMvZ3B1L2RybS9leHlub3MvZXh5bm9zNTQzM19kcm1fZGVjb24uYyB8IDE4ICsr KysrKysrKy0tLS0tLS0tLQogMSBmaWxlIGNoYW5nZWQsIDkgaW5zZXJ0aW9ucygrKSwgOSBkZWxl dGlvbnMoLSkKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vZXh5bm9zL2V4eW5vczU0MzNf ZHJtX2RlY29uLmMgYi9kcml2ZXJzL2dwdS9kcm0vZXh5bm9zL2V4eW5vczU0MzNfZHJtX2RlY29u LmMKaW5kZXggYjI1ZDc2NC4uODNlMDkzOSAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL2V4 eW5vcy9leHlub3M1NDMzX2RybV9kZWNvbi5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9leHlub3Mv ZXh5bm9zNTQzM19kcm1fZGVjb24uYwpAQCAtMTA0LDcgKzEwNCw3IEBAIHN0YXRpYyB2b2lkIGRl Y29uX3NldHVwX3RyaWdnZXIoc3RydWN0IGRlY29uX2NvbnRleHQgKmN0eCkKIHN0YXRpYyB2b2lk IGRlY29uX2NvbW1pdChzdHJ1Y3QgZXh5bm9zX2RybV9jcnRjICpjcnRjKQogewogCXN0cnVjdCBk ZWNvbl9jb250ZXh0ICpjdHggPSBjcnRjLT5jdHg7Ci0Jc3RydWN0IGRybV9kaXNwbGF5X21vZGUg Km1vZGUgPSAmY3J0Yy0+YmFzZS5tb2RlOworCXN0cnVjdCBkcm1fZGlzcGxheV9tb2RlICptID0g JmNydGMtPmJhc2UubW9kZTsKIAl1MzIgdmFsOwogCiAJaWYgKGN0eC0+c3VzcGVuZGVkKQpAQCAt MTIyLDI5ICsxMjIsMjkgQEAgc3RhdGljIHZvaWQgZGVjb25fY29tbWl0KHN0cnVjdCBleHlub3Nf ZHJtX2NydGMgKmNydGMpCiAJCXZhbCB8PSBWSURPVVRfUkdCX0lGOwogCXdyaXRlbCh2YWwsIGN0 eC0+YWRkciArIERFQ09OX1ZJRE9VVENPTjApOwogCi0JdmFsID0gVklEVENPTjJfTElORVZBTCht b2RlLT52ZGlzcGxheSAtIDEpIHwKLQkJVklEVENPTjJfSE9aVkFMKG1vZGUtPmhkaXNwbGF5IC0g MSk7CisJdmFsID0gVklEVENPTjJfTElORVZBTChtLT52ZGlzcGxheSAtIDEpIHwKKwkJVklEVENP TjJfSE9aVkFMKG0tPmhkaXNwbGF5IC0gMSk7CiAJd3JpdGVsKHZhbCwgY3R4LT5hZGRyICsgREVD T05fVklEVENPTjIpOwogCiAJaWYgKCFjdHgtPmk4MF9pZikgewogCQl2YWwgPSBWSURUQ09OMDBf VkJQRF9GKAotCQkJCW1vZGUtPmNydGNfdnRvdGFsIC0gbW9kZS0+Y3J0Y192c3luY19lbmQpIHwK KwkJCQltLT5jcnRjX3Z0b3RhbCAtIG0tPmNydGNfdnN5bmNfZW5kIC0gMSkgfAogCQkJVklEVENP TjAwX1ZGUERfRigKLQkJCQltb2RlLT5jcnRjX3ZzeW5jX3N0YXJ0IC0gbW9kZS0+Y3J0Y192ZGlz cGxheSk7CisJCQkJbS0+Y3J0Y192c3luY19zdGFydCAtIG0tPmNydGNfdmRpc3BsYXkgLSAxKTsK IAkJd3JpdGVsKHZhbCwgY3R4LT5hZGRyICsgREVDT05fVklEVENPTjAwKTsKIAogCQl2YWwgPSBW SURUQ09OMDFfVlNQV19GKAotCQkJCW1vZGUtPmNydGNfdnN5bmNfZW5kIC0gbW9kZS0+Y3J0Y192 c3luY19zdGFydCk7CisJCQkJbS0+Y3J0Y192c3luY19lbmQgLSBtLT5jcnRjX3ZzeW5jX3N0YXJ0 IC0gMSk7CiAJCXdyaXRlbCh2YWwsIGN0eC0+YWRkciArIERFQ09OX1ZJRFRDT04wMSk7CiAKIAkJ dmFsID0gVklEVENPTjEwX0hCUERfRigKLQkJCQltb2RlLT5jcnRjX2h0b3RhbCAtIG1vZGUtPmNy dGNfaHN5bmNfZW5kKSB8CisJCQkJbS0+Y3J0Y19odG90YWwgLSBtLT5jcnRjX2hzeW5jX2VuZCAt IDEpIHwKIAkJCVZJRFRDT04xMF9IRlBEX0YoCi0JCQkJbW9kZS0+Y3J0Y19oc3luY19zdGFydCAt IG1vZGUtPmNydGNfaGRpc3BsYXkpOworCQkJCW0tPmNydGNfaHN5bmNfc3RhcnQgLSBtLT5jcnRj X2hkaXNwbGF5IC0gMSk7CiAJCXdyaXRlbCh2YWwsIGN0eC0+YWRkciArIERFQ09OX1ZJRFRDT04x MCk7CiAKIAkJdmFsID0gVklEVENPTjExX0hTUFdfRigKLQkJCQltb2RlLT5jcnRjX2hzeW5jX2Vu ZCAtIG1vZGUtPmNydGNfaHN5bmNfc3RhcnQpOworCQkJCW0tPmNydGNfaHN5bmNfZW5kIC0gbS0+ Y3J0Y19oc3luY19zdGFydCAtIDEpOwogCQl3cml0ZWwodmFsLCBjdHgtPmFkZHIgKyBERUNPTl9W SURUQ09OMTEpOwogCX0KIAotLSAKMS45LjEKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3Rz LmZyZWVkZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlz dGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailout2.w1.samsung.com ([210.118.77.12]:29494 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752156AbbJTJX3 (ORCPT ); Tue, 20 Oct 2015 05:23:29 -0400 From: Andrzej Hajda To: Inki Dae Cc: Andrzej Hajda , Bartlomiej Zolnierkiewicz , Marek Szyprowski , Kyungmin Park , dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, Kukjin Kim , Krzysztof Kozlowski , Sylwester Nawrocki , Hyungwon Hwang Subject: [PATCH 05/10] drm/exynos/decon5433: fix timing registers writes Date: Tue, 20 Oct 2015 11:22:36 +0200 Message-id: <1445332961-25419-6-git-send-email-a.hajda@samsung.com> In-reply-to: <1445332961-25419-1-git-send-email-a.hajda@samsung.com> References: <1445332961-25419-1-git-send-email-a.hajda@samsung.com> Sender: linux-clk-owner@vger.kernel.org List-ID: All timing registers should contain values decreased by one. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index b25d764..83e0939 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -104,7 +104,7 @@ static void decon_setup_trigger(struct decon_context *ctx) static void decon_commit(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; - struct drm_display_mode *mode = &crtc->base.mode; + struct drm_display_mode *m = &crtc->base.mode; u32 val; if (ctx->suspended) @@ -122,29 +122,29 @@ static void decon_commit(struct exynos_drm_crtc *crtc) val |= VIDOUT_RGB_IF; writel(val, ctx->addr + DECON_VIDOUTCON0); - val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | - VIDTCON2_HOZVAL(mode->hdisplay - 1); + val = VIDTCON2_LINEVAL(m->vdisplay - 1) | + VIDTCON2_HOZVAL(m->hdisplay - 1); writel(val, ctx->addr + DECON_VIDTCON2); if (!ctx->i80_if) { val = VIDTCON00_VBPD_F( - mode->crtc_vtotal - mode->crtc_vsync_end) | + m->crtc_vtotal - m->crtc_vsync_end - 1) | VIDTCON00_VFPD_F( - mode->crtc_vsync_start - mode->crtc_vdisplay); + m->crtc_vsync_start - m->crtc_vdisplay - 1); writel(val, ctx->addr + DECON_VIDTCON00); val = VIDTCON01_VSPW_F( - mode->crtc_vsync_end - mode->crtc_vsync_start); + m->crtc_vsync_end - m->crtc_vsync_start - 1); writel(val, ctx->addr + DECON_VIDTCON01); val = VIDTCON10_HBPD_F( - mode->crtc_htotal - mode->crtc_hsync_end) | + m->crtc_htotal - m->crtc_hsync_end - 1) | VIDTCON10_HFPD_F( - mode->crtc_hsync_start - mode->crtc_hdisplay); + m->crtc_hsync_start - m->crtc_hdisplay - 1); writel(val, ctx->addr + DECON_VIDTCON10); val = VIDTCON11_HSPW_F( - mode->crtc_hsync_end - mode->crtc_hsync_start); + m->crtc_hsync_end - m->crtc_hsync_start - 1); writel(val, ctx->addr + DECON_VIDTCON11); } -- 1.9.1