From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH v4 2/5] xen/arm: vgic-v2: Don't ignore a write in ITARGETSR if one field is 0 Date: Fri, 23 Oct 2015 10:53:51 +0100 Message-ID: <1445594031.2374.97.camel@citrix.com> References: <1444659760-24123-1-git-send-email-julien.grall@citrix.com> <1444659760-24123-3-git-send-email-julien.grall@citrix.com> <1445530071.2374.40.camel@citrix.com> <56291414.8030007@citrix.com> <1445592615.2374.80.camel@citrix.com> <5629FFDE.6030506@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1ZpZ2r-0004Ri-3A for xen-devel@lists.xenproject.org; Fri, 23 Oct 2015 09:53:57 +0000 In-Reply-To: <5629FFDE.6030506@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Julien Grall , xen-devel@lists.xenproject.org Cc: stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org On Fri, 2015-10-23 at 10:37 +0100, Julien Grall wrote: > Hi Ian, > > On 23/10/15 10:30, Ian Campbell wrote: > > On Thu, 2015-10-22 at 17:51 +0100, Julien Grall wrote: > > > On 22/10/15 17:07, Ian Campbell wrote: > > > > > diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c > > > > > index 665afeb..6b7eab3 100644 > > > > > --- a/xen/arch/arm/vgic-v2.c > > > > > +++ b/xen/arch/arm/vgic-v2.c > > > > > @@ -50,6 +50,94 @@ void vgic_v2_setup_hw(paddr_t dbase, paddr_t > > > > > cbase, > > > > > paddr_t vbase) > > > > > vgic_v2_hw.vbase = vbase; > > > > > } > > > > > > > > > > +#define NR_TARGET_PER_REG 4U > > > > > +#define NR_BIT_PER_TARGET 8U > > > > > > > > NR_TARGETS_ and NR_BITS_... > > > > > > > > "REG" there is a bit generic, given this only works for registers > > > > with > > > > 8 > > > > -bit fields, _ITARGETSR instead? > > > > > > Well this is within the vgic-v2.c and only one register contains > > > target. > > > So I found pointless to add ITARGETSR to the name. > > > > It's the use of the generic "REG" when there is only one relevant > > register > > (which could be named) which I found confusing, since the current name > > implies it has wider relevance than it actually does. > > Ok. I guess you'd like to rename NR_BITS_PER_TARGET? If so, do you have > any suggestion? NR_BITS_PER_TARGET is OK here, since 8 is always correct for that in the gic v2 irrespective of whether it is used with any register. NR_TARGET_PER_REG was the thing I thought we were discussing above. I think that one should be NR_TARGETS_PER_ITARGETSR. Alternatively const unsigned long nr_targets_per_reg = 32/NR_BITS_PER_TARGET; in the context of the vgic_store_itargetsr function (and others which use it) would be ok too. Or maybe 32=>(sizeof(...)*8). And maybe in that context an even terser name would be ok too. Ian.