From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54130) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zr7uM-00056G-Mg for qemu-devel@nongnu.org; Tue, 27 Oct 2015 13:19:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zr7uI-0005Av-IT for qemu-devel@nongnu.org; Tue, 27 Oct 2015 13:19:38 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:51299) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zr7uI-0005Ab-D9 for qemu-devel@nongnu.org; Tue, 27 Oct 2015 13:19:34 -0400 From: Yongbok Kim Date: Tue, 27 Oct 2015 17:12:33 +0000 Message-ID: <1445965957-37888-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH for-2.5 v2 0/4] mips: add Global Interrupt Controller List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, james.hogan@imgtec.com, crosthwaitepeter@gmail.com, pbonzini@redhat.com, leon.alrae@imgtec.com, aurelien@aurel32.net This patchset implement MIPS Global Interrupt Controller. In order to bring GIC up a part of GCR has been implemented as well. The Global Interrupt Controller (GIC) is responsible for mapping each internal and external interrupt to the correct location for servicing. With the patchset Linux Kernel detects GIC and utilises it. # cat /proc/interrupts CPU0 0: 2 XT-PIC 0 timer 2: 0 XT-PIC 2 cascade 4: 264 XT-PIC 4 serial 8: 0 XT-PIC 8 rtc0 14: 956 XT-PIC 14 ata_piix 15: 5 XT-PIC 15 ata_piix 21: 0 MIPS 5 CoreHi 23: 1 MIPS 7 timer 25: 5209 MIPS GIC Local 1 timer 34: 1227 MIPS GIC 10 XT-PIC cascade ERR: 0 Limitation: Level triggering only GIC CounterHi not implemented (Countbits = 32bits) DINT not implemented Local WatchDog, Fast Debug Channel, Perf Counter not implemented It is based on the earlier un-merged GIC implementation. https://lists.gnu.org/archive/html/qemu-devel/2013-03/msg00194.html For more information, http://imgtec.com/mips/warrior/p-class-p5600-multiprocessor-core/ http://imgtec.com/mips/warrior/i-class-i6400-multiprocessor-core/ v2: * added user mode section (James) * moved mips_gic.c into hw/intc, mips_gcr.c into hw/misc (PeterM, PeterC) * renamed obvious duplications (Leon) * renamed gic_irqs into irq_state (Leon) * removed pointer to gic IRQs from env (Leon) * fixed loading target_ulong CMGCRBase (Leon) * removed unimplemented registers (Leon) * fixed writing to wedge register (Leon) * removed magic numbers * update usage of map_vp to indicate not mapped * cosmetic changes and other review comments Yongbok Kim (4): target-mips: add CMGCRBase register mips: add Global Config Register block (part) mips: add Global Interrupt Controller mips: add gic support to malta default-configs/mips-softmmu.mak | 1 + default-configs/mips64-softmmu.mak | 1 + default-configs/mips64el-softmmu.mak | 1 + default-configs/mipsel-softmmu.mak | 1 + hw/intc/Makefile.objs | 1 + hw/intc/mips_gic.c | 530 ++++++++++++++++++++++++++++++++++ hw/mips/mips_malta.c | 73 +++++- hw/misc/Makefile.objs | 1 + hw/misc/mips_gcr.c | 113 +++++++ include/hw/intc/mips_gic.h | 269 +++++++++++++++++ include/hw/misc/mips_gcr.h | 58 ++++ target-mips/cpu.h | 3 +- target-mips/translate.c | 18 ++ target-mips/translate_init.c | 3 +- 14 files changed, 1069 insertions(+), 4 deletions(-) create mode 100644 hw/intc/mips_gic.c create mode 100644 hw/misc/mips_gcr.c create mode 100644 include/hw/intc/mips_gic.h create mode 100644 include/hw/misc/mips_gcr.h