[PATCH v3 0/4] SMP support for Broadcom NSP

[PATCH v3 0/4] SMP support for Broadcom NSP

[Kapil Hali]

Change in v3:
* Fixed patch subject from RESEND PATCH to PATCH
* Deleted arch/arm/mach-bcm/bcm_nsp.h file
* Removed inclusion of header file bcm_nsp.h in platsmp.c
* Removed unused variable 'timeout' in nsp_boot_secondary()

Changes in v2:
Removed the pen_holding method of SMP bringup for NSP SoC and
replaced it with simple wakeup of secondary core using ARM IPI.


This series adds SMP support for Broadcom's Northstar Plus SoC.

There are similar SMP enablement methods for many ARMv7 bsed SoCs.
BCM NSP SoC, has a typical such mechanism - after power-on, the
secondary core is held in a standby state, primary core provides a
startup address for the secondary core and wakes it up. Booting of
the secondary core is serialized using pen_release global variable.

The startup address is programmed at a special register location
which is defined in the device tree using a "secondary-boot-reg"
property in a node whose "enable-method" property matches.

The first patch adds cpu-enable-method in the device tree bindings
documentation. It also updates ARM CPU device tree documentation
with Broadcom Northstar Plus CPU details.

The second patch adds SMP support to the BCM NSP device tree file.

The third patch, enables SMP on BCM NSP. It also consolidates
common SMP handling between BCM NSP and BCM Kona.

The final patch, enables SMP on BCM 4708 and this patch is pulled
in from Jon Mason's patch from the mailing list.

This patch series is constructed based on Linux v4.3-rc2.

The source code is available at GITHUB:
https://github.com/Broadcom/cygnus-linux/tree/nsp-smp-v1

Jon Mason (1):
  ARM: BCM: Add SMP support for Broadcom 4708

Kapil Hali (3):
  dt-bindings: add SMP enable-method for Broadcom NSP
  ARM: dts: add SMP support for Broadcom NSP
  ARM: BCM: Add SMP support for Broadcom NSP

 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 arch/arm/boot/dts/bcm-nsp.dtsi                     | 33 +++++----
 arch/arm/boot/dts/bcm4708.dtsi                     |  2 +
 arch/arm/mach-bcm/Kconfig                          |  3 +
 arch/arm/mach-bcm/Makefile                         | 11 ++-
 arch/arm/mach-bcm/{kona_smp.c => platsmp.c}        | 82 +++++++++++++++++++---
 7 files changed, 145 insertions(+), 23 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
 rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (75%)

-- 
2.1.0

[PATCH v3 0/4] SMP support for Broadcom NSP

[Kapil Hali]

Change in v3:
* Fixed patch subject from RESEND PATCH to PATCH
* Deleted arch/arm/mach-bcm/bcm_nsp.h file
* Removed inclusion of header file bcm_nsp.h in platsmp.c
* Removed unused variable 'timeout' in nsp_boot_secondary()

Changes in v2:
Removed the pen_holding method of SMP bringup for NSP SoC and
replaced it with simple wakeup of secondary core using ARM IPI.


This series adds SMP support for Broadcom's Northstar Plus SoC.

There are similar SMP enablement methods for many ARMv7 bsed SoCs.
BCM NSP SoC, has a typical such mechanism - after power-on, the
secondary core is held in a standby state, primary core provides a
startup address for the secondary core and wakes it up. Booting of
the secondary core is serialized using pen_release global variable.

The startup address is programmed at a special register location
which is defined in the device tree using a "secondary-boot-reg"
property in a node whose "enable-method" property matches.

The first patch adds cpu-enable-method in the device tree bindings
documentation. It also updates ARM CPU device tree documentation
with Broadcom Northstar Plus CPU details.

The second patch adds SMP support to the BCM NSP device tree file.

The third patch, enables SMP on BCM NSP. It also consolidates
common SMP handling between BCM NSP and BCM Kona.

The final patch, enables SMP on BCM 4708 and this patch is pulled
in from Jon Mason's patch from the mailing list.

This patch series is constructed based on Linux v4.3-rc2.

The source code is available at GITHUB:
https://github.com/Broadcom/cygnus-linux/tree/nsp-smp-v1

Jon Mason (1):
  ARM: BCM: Add SMP support for Broadcom 4708

Kapil Hali (3):
  dt-bindings: add SMP enable-method for Broadcom NSP
  ARM: dts: add SMP support for Broadcom NSP
  ARM: BCM: Add SMP support for Broadcom NSP

 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 arch/arm/boot/dts/bcm-nsp.dtsi                     | 33 +++++----
 arch/arm/boot/dts/bcm4708.dtsi                     |  2 +
 arch/arm/mach-bcm/Kconfig                          |  3 +
 arch/arm/mach-bcm/Makefile                         | 11 ++-
 arch/arm/mach-bcm/{kona_smp.c => platsmp.c}        | 82 +++++++++++++++++++---
 7 files changed, 145 insertions(+), 23 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
 rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (75%)

-- 
2.1.0

[PATCH v3 0/4] SMP support for Broadcom NSP

[Kapil Hali]

Change in v3:
* Fixed patch subject from RESEND PATCH to PATCH
* Deleted arch/arm/mach-bcm/bcm_nsp.h file
* Removed inclusion of header file bcm_nsp.h in platsmp.c
* Removed unused variable 'timeout' in nsp_boot_secondary()

Changes in v2:
Removed the pen_holding method of SMP bringup for NSP SoC and
replaced it with simple wakeup of secondary core using ARM IPI.


This series adds SMP support for Broadcom's Northstar Plus SoC.

There are similar SMP enablement methods for many ARMv7 bsed SoCs.
BCM NSP SoC, has a typical such mechanism - after power-on, the
secondary core is held in a standby state, primary core provides a
startup address for the secondary core and wakes it up. Booting of
the secondary core is serialized using pen_release global variable.

The startup address is programmed at a special register location
which is defined in the device tree using a "secondary-boot-reg"
property in a node whose "enable-method" property matches.

The first patch adds cpu-enable-method in the device tree bindings
documentation. It also updates ARM CPU device tree documentation
with Broadcom Northstar Plus CPU details.

The second patch adds SMP support to the BCM NSP device tree file.

The third patch, enables SMP on BCM NSP. It also consolidates
common SMP handling between BCM NSP and BCM Kona.

The final patch, enables SMP on BCM 4708 and this patch is pulled
in from Jon Mason's patch from the mailing list.

This patch series is constructed based on Linux v4.3-rc2.

The source code is available at GITHUB:
https://github.com/Broadcom/cygnus-linux/tree/nsp-smp-v1

Jon Mason (1):
  ARM: BCM: Add SMP support for Broadcom 4708

Kapil Hali (3):
  dt-bindings: add SMP enable-method for Broadcom NSP
  ARM: dts: add SMP support for Broadcom NSP
  ARM: BCM: Add SMP support for Broadcom NSP

 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 arch/arm/boot/dts/bcm-nsp.dtsi                     | 33 +++++----
 arch/arm/boot/dts/bcm4708.dtsi                     |  2 +
 arch/arm/mach-bcm/Kconfig                          |  3 +
 arch/arm/mach-bcm/Makefile                         | 11 ++-
 arch/arm/mach-bcm/{kona_smp.c => platsmp.c}        | 82 +++++++++++++++++++---
 7 files changed, 145 insertions(+), 23 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
 rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (75%)

-- 
2.1.0

[PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
Northstar Plus CPU to the 32-bit ARM CPU device tree binding
documentation file and create a new binding documentation for
Northstar Plus CPU.

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 2 files changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt

diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
new file mode 100644
index 0000000..8506da7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
@@ -0,0 +1,36 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:
+  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the "cpus" device tree node:
+  - enable-method = "brcm,bcm-nsp-smp";
+  - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register used to request the ROM holding pen
+code release a secondary CPU.
+
+Example:
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";
+		secondary-boot-reg = <0xffff042c>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <1>;
+		};
+	};
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 91e6e5c..6abe3f3 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
 			    "allwinner,sun8i-a23"
 			    "arm,psci"
 			    "brcm,brahma-b15"
+			    "brcm,bcm-nsp-smp"
 			    "marvell,armada-375-smp"
 			    "marvell,armada-380-smp"
 			    "marvell,armada-390-smp"
-- 
2.1.0

[PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
Northstar Plus CPU to the 32-bit ARM CPU device tree binding
documentation file and create a new binding documentation for
Northstar Plus CPU.

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 2 files changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt

diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
new file mode 100644
index 0000000..8506da7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
@@ -0,0 +1,36 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:
+  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the "cpus" device tree node:
+  - enable-method = "brcm,bcm-nsp-smp";
+  - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register used to request the ROM holding pen
+code release a secondary CPU.
+
+Example:
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";
+		secondary-boot-reg = <0xffff042c>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <1>;
+		};
+	};
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 91e6e5c..6abe3f3 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
 			    "allwinner,sun8i-a23"
 			    "arm,psci"
 			    "brcm,brahma-b15"
+			    "brcm,bcm-nsp-smp"
 			    "marvell,armada-375-smp"
 			    "marvell,armada-380-smp"
 			    "marvell,armada-390-smp"
-- 
2.1.0

[PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
Northstar Plus CPU to the 32-bit ARM CPU device tree binding
documentation file and create a new binding documentation for
Northstar Plus CPU.

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
 2 files changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt

diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
new file mode 100644
index 0000000..8506da7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
@@ -0,0 +1,36 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:
+  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the "cpus" device tree node:
+  - enable-method = "brcm,bcm-nsp-smp";
+  - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register used to request the ROM holding pen
+code release a secondary CPU.
+
+Example:
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";
+		secondary-boot-reg = <0xffff042c>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0>;
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <1>;
+		};
+	};
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 91e6e5c..6abe3f3 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
 			    "allwinner,sun8i-a23"
 			    "arm,psci"
 			    "brcm,brahma-b15"
+			    "brcm,bcm-nsp-smp"
 			    "marvell,armada-375-smp"
 			    "marvell,armada-380-smp"
 			    "marvell,armada-390-smp"
-- 
2.1.0

[PATCH v3 2/4] ARM: dts: add SMP support for Broadcom NSP

[Kapil Hali]

Add device tree changes required for providing SMP support
for Broadcom Northstar Plus SoC.

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 arch/arm/boot/dts/bcm-nsp.dtsi | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..d1875d9 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -40,24 +40,33 @@
 	model = "Broadcom Northstar Plus SoC";
 	interrupt-parent = <&gic>;
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";
+		secondary-boot-reg = <0xffff042c>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x1>;
+		};
+	};
+
 	mpcore {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0x19020000 0x00003000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpus {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			cpu@0 {
-				device_type = "cpu";
-				compatible = "arm,cortex-a9";
-				next-level-cache = <&L2>;
-				reg = <0x0>;
-			};
-		};
-
 		L2: l2-cache {
 			compatible = "arm,pl310-cache";
 			reg = <0x2000 0x1000>;
-- 
2.1.0

[PATCH v3 2/4] ARM: dts: add SMP support for Broadcom NSP

[Kapil Hali]

Add device tree changes required for providing SMP support
for Broadcom Northstar Plus SoC.

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 arch/arm/boot/dts/bcm-nsp.dtsi | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..d1875d9 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -40,24 +40,33 @@
 	model = "Broadcom Northstar Plus SoC";
 	interrupt-parent = <&gic>;
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";
+		secondary-boot-reg = <0xffff042c>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x1>;
+		};
+	};
+
 	mpcore {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0x19020000 0x00003000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpus {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			cpu@0 {
-				device_type = "cpu";
-				compatible = "arm,cortex-a9";
-				next-level-cache = <&L2>;
-				reg = <0x0>;
-			};
-		};
-
 		L2: l2-cache {
 			compatible = "arm,pl310-cache";
 			reg = <0x2000 0x1000>;
-- 
2.1.0

[PATCH v3 2/4] ARM: dts: add SMP support for Broadcom NSP

[Kapil Hali]

Add device tree changes required for providing SMP support
for Broadcom Northstar Plus SoC.

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 arch/arm/boot/dts/bcm-nsp.dtsi | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..d1875d9 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -40,24 +40,33 @@
 	model = "Broadcom Northstar Plus SoC";
 	interrupt-parent = <&gic>;
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";
+		secondary-boot-reg = <0xffff042c>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x0>;
+		};
+
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x1>;
+		};
+	};
+
 	mpcore {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0x19020000 0x00003000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpus {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			cpu at 0 {
-				device_type = "cpu";
-				compatible = "arm,cortex-a9";
-				next-level-cache = <&L2>;
-				reg = <0x0>;
-			};
-		};
-
 		L2: l2-cache {
 			compatible = "arm,pl310-cache";
 			reg = <0x2000 0x1000>;
-- 
2.1.0

[PATCH v3 3/4] ARM: BCM: Add SMP support for Broadcom NSP

[Kapil Hali]

Add SMP support for Broadcom's Northstar Plus SoC
cpu enable method. This changes also consolidates
iProc family's - BCM NSP and BCM Kona, platform
SMP handling in a common file.

Northstar Plus SoC is based on ARM Cortex-A9
revision r3p0 which requires configuration for ARM
Errata 764369 for SMP. This change adds the needed
configuration option.

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig                   |  2 +
 arch/arm/mach-bcm/Makefile                  |  8 ++-
 arch/arm/mach-bcm/{kona_smp.c => platsmp.c} | 82 +++++++++++++++++++++++++----
 3 files changed, 81 insertions(+), 11 deletions(-)
 rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (75%)

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 1679fa4..2e9dbb5 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -40,6 +40,8 @@ config ARCH_BCM_NSP
 	select ARCH_BCM_IPROC
 	select ARM_ERRATA_754322
 	select ARM_ERRATA_775420
+	select ARM_ERRATA_764369 if SMP
+	select HAVE_SMP
 	help
 	  Support for Broadcom Northstar Plus SoC.
 	  Broadcom Northstar Plus family of SoCs are used for switching control
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 892261f..5193a25 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -14,7 +14,11 @@
 obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
 
 # Northstar Plus
-obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
+obj-$(CONFIG_ARCH_BCM_NSP)	+= bcm_nsp.o
+
+ifeq ($(CONFIG_ARCH_BCM_NSP),y)
+obj-$(CONFIG_SMP)		+= platsmp.o
+endif
 
 # BCM281XX
 obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
@@ -23,7 +27,7 @@ obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
 obj-$(CONFIG_ARCH_BCM_21664)	+= board_bcm21664.o
 
 # BCM281XX and BCM21664 SMP support
-obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
+obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o
 
 # BCM281XX and BCM21664 L2 cache control
 obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/platsmp.c
similarity index 75%
rename from arch/arm/mach-bcm/kona_smp.c
rename to arch/arm/mach-bcm/platsmp.c
index 66a0465..dbf14fb 100644
--- a/arch/arm/mach-bcm/kona_smp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Broadcom Corporation
+ * Copyright (C) 2014-2015 Broadcom Corporation
  * Copyright 2014 Linaro Limited
  *
  * This program is free software; you can redistribute it and/or
@@ -12,12 +12,17 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/init.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
+#include <linux/init.h>
 #include <linux/io.h>
+#include <linux/jiffies.h>
 #include <linux/of.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 
+#include <asm/cacheflush.h>
 #include <asm/smp.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
@@ -75,6 +80,37 @@ static int __init scu_a9_enable(void)
 	return 0;
 }
 
+static int nsp_write_lut(void)
+{
+	void __iomem *sku_rom_lut;
+	phys_addr_t secondary_startup_phy;
+
+	if (!secondary_boot) {
+		pr_warn("required secondary boot register not specified\n");
+		return -EINVAL;
+	}
+
+	sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot,
+						sizeof(secondary_boot));
+	if (!sku_rom_lut) {
+		pr_warn("unable to ioremap SKU-ROM LUT register\n");
+		return -ENOMEM;
+	}
+
+	secondary_startup_phy = virt_to_phys(secondary_startup);
+	BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
+
+	writel_relaxed(secondary_startup_phy, sku_rom_lut);
+	/*
+	 * Ensure the write is visible to the secondary core.
+	 */
+	smp_wmb();
+
+	iounmap(sku_rom_lut);
+
+	return 0;
+}
+
 static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
 {
 	static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
@@ -95,11 +131,11 @@ static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
 	/*
 	 * Our secondary enable method requires a "secondary-boot-reg"
 	 * property to specify a register address used to request the
-	 * ROM code boot a secondary code.  If we have any trouble
+	 * ROM code boot a secondary core.  If we have any trouble
 	 * getting this we fall back to uniprocessor mode.
 	 */
 	if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
-		pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
+		pr_warn("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
 			node->name);
 		ret = -ENOENT;		/* Arrange to disable SMP */
 		goto out;
@@ -115,7 +151,6 @@ out:
 	of_node_put(node);
 	if (ret) {
 		/* Update the CPU present map to reflect uniprocessor mode */
-		BUG_ON(ret != -ENOENT);
 		pr_warn("disabling SMP\n");
 		init_cpu_present(&only_cpu_0);
 	}
@@ -139,7 +174,7 @@ out:
  * - Wait for the secondary boot register to be re-written, which
  *   indicates the secondary core has started.
  */
-static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	void __iomem *boot_reg;
 	phys_addr_t boot_func;
@@ -162,7 +197,7 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
 	if (!boot_reg) {
 		pr_err("unable to map boot register for cpu %u\n", cpu_id);
-		return -ENOSYS;
+		return -ENOMEM;
 	}
 
 	/*
@@ -191,12 +226,41 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 	pr_err("timeout waiting for cpu %u to start\n", cpu_id);
 
-	return -ENOSYS;
+	return -ENXIO;
+}
+
+static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	int ret;
+
+	/*
+	 * After wake up, secondary core branches to the startup
+	 * address programmed at SKU ROM LUT location.
+	 */
+	ret = nsp_write_lut();
+	if (ret) {
+		pr_err("unable to write startup addr to SKU ROM LUT\n");
+		goto out;
+	}
+
+	/*
+	 * Send a CPU wakeup interrupt to the secondary core.
+	 */
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+out:
+	return ret;
 }
 
 static struct smp_operations bcm_smp_ops __initdata = {
 	.smp_prepare_cpus	= bcm_smp_prepare_cpus,
-	.smp_boot_secondary	= bcm_boot_secondary,
+	.smp_boot_secondary	= kona_boot_secondary,
 };
 CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
 			&bcm_smp_ops);
+
+struct smp_operations nsp_smp_ops __initdata = {
+	.smp_prepare_cpus	= bcm_smp_prepare_cpus,
+	.smp_boot_secondary	= nsp_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
-- 
2.1.0

[PATCH v3 3/4] ARM: BCM: Add SMP support for Broadcom NSP

[Kapil Hali]

Add SMP support for Broadcom's Northstar Plus SoC
cpu enable method. This changes also consolidates
iProc family's - BCM NSP and BCM Kona, platform
SMP handling in a common file.

Northstar Plus SoC is based on ARM Cortex-A9
revision r3p0 which requires configuration for ARM
Errata 764369 for SMP. This change adds the needed
configuration option.

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig                   |  2 +
 arch/arm/mach-bcm/Makefile                  |  8 ++-
 arch/arm/mach-bcm/{kona_smp.c => platsmp.c} | 82 +++++++++++++++++++++++++----
 3 files changed, 81 insertions(+), 11 deletions(-)
 rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (75%)

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 1679fa4..2e9dbb5 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -40,6 +40,8 @@ config ARCH_BCM_NSP
 	select ARCH_BCM_IPROC
 	select ARM_ERRATA_754322
 	select ARM_ERRATA_775420
+	select ARM_ERRATA_764369 if SMP
+	select HAVE_SMP
 	help
 	  Support for Broadcom Northstar Plus SoC.
 	  Broadcom Northstar Plus family of SoCs are used for switching control
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 892261f..5193a25 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -14,7 +14,11 @@
 obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
 
 # Northstar Plus
-obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
+obj-$(CONFIG_ARCH_BCM_NSP)	+= bcm_nsp.o
+
+ifeq ($(CONFIG_ARCH_BCM_NSP),y)
+obj-$(CONFIG_SMP)		+= platsmp.o
+endif
 
 # BCM281XX
 obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
@@ -23,7 +27,7 @@ obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
 obj-$(CONFIG_ARCH_BCM_21664)	+= board_bcm21664.o
 
 # BCM281XX and BCM21664 SMP support
-obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
+obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o
 
 # BCM281XX and BCM21664 L2 cache control
 obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/platsmp.c
similarity index 75%
rename from arch/arm/mach-bcm/kona_smp.c
rename to arch/arm/mach-bcm/platsmp.c
index 66a0465..dbf14fb 100644
--- a/arch/arm/mach-bcm/kona_smp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Broadcom Corporation
+ * Copyright (C) 2014-2015 Broadcom Corporation
  * Copyright 2014 Linaro Limited
  *
  * This program is free software; you can redistribute it and/or
@@ -12,12 +12,17 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/init.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
+#include <linux/init.h>
 #include <linux/io.h>
+#include <linux/jiffies.h>
 #include <linux/of.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 
+#include <asm/cacheflush.h>
 #include <asm/smp.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
@@ -75,6 +80,37 @@ static int __init scu_a9_enable(void)
 	return 0;
 }
 
+static int nsp_write_lut(void)
+{
+	void __iomem *sku_rom_lut;
+	phys_addr_t secondary_startup_phy;
+
+	if (!secondary_boot) {
+		pr_warn("required secondary boot register not specified\n");
+		return -EINVAL;
+	}
+
+	sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot,
+						sizeof(secondary_boot));
+	if (!sku_rom_lut) {
+		pr_warn("unable to ioremap SKU-ROM LUT register\n");
+		return -ENOMEM;
+	}
+
+	secondary_startup_phy = virt_to_phys(secondary_startup);
+	BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
+
+	writel_relaxed(secondary_startup_phy, sku_rom_lut);
+	/*
+	 * Ensure the write is visible to the secondary core.
+	 */
+	smp_wmb();
+
+	iounmap(sku_rom_lut);
+
+	return 0;
+}
+
 static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
 {
 	static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
@@ -95,11 +131,11 @@ static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
 	/*
 	 * Our secondary enable method requires a "secondary-boot-reg"
 	 * property to specify a register address used to request the
-	 * ROM code boot a secondary code.  If we have any trouble
+	 * ROM code boot a secondary core.  If we have any trouble
 	 * getting this we fall back to uniprocessor mode.
 	 */
 	if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
-		pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
+		pr_warn("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
 			node->name);
 		ret = -ENOENT;		/* Arrange to disable SMP */
 		goto out;
@@ -115,7 +151,6 @@ out:
 	of_node_put(node);
 	if (ret) {
 		/* Update the CPU present map to reflect uniprocessor mode */
-		BUG_ON(ret != -ENOENT);
 		pr_warn("disabling SMP\n");
 		init_cpu_present(&only_cpu_0);
 	}
@@ -139,7 +174,7 @@ out:
  * - Wait for the secondary boot register to be re-written, which
  *   indicates the secondary core has started.
  */
-static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	void __iomem *boot_reg;
 	phys_addr_t boot_func;
@@ -162,7 +197,7 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
 	if (!boot_reg) {
 		pr_err("unable to map boot register for cpu %u\n", cpu_id);
-		return -ENOSYS;
+		return -ENOMEM;
 	}
 
 	/*
@@ -191,12 +226,41 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 	pr_err("timeout waiting for cpu %u to start\n", cpu_id);
 
-	return -ENOSYS;
+	return -ENXIO;
+}
+
+static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	int ret;
+
+	/*
+	 * After wake up, secondary core branches to the startup
+	 * address programmed at SKU ROM LUT location.
+	 */
+	ret = nsp_write_lut();
+	if (ret) {
+		pr_err("unable to write startup addr to SKU ROM LUT\n");
+		goto out;
+	}
+
+	/*
+	 * Send a CPU wakeup interrupt to the secondary core.
+	 */
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+out:
+	return ret;
 }
 
 static struct smp_operations bcm_smp_ops __initdata = {
 	.smp_prepare_cpus	= bcm_smp_prepare_cpus,
-	.smp_boot_secondary	= bcm_boot_secondary,
+	.smp_boot_secondary	= kona_boot_secondary,
 };
 CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
 			&bcm_smp_ops);
+
+struct smp_operations nsp_smp_ops __initdata = {
+	.smp_prepare_cpus	= bcm_smp_prepare_cpus,
+	.smp_boot_secondary	= nsp_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
-- 
2.1.0

[PATCH v3 3/4] ARM: BCM: Add SMP support for Broadcom NSP

[Kapil Hali]

Add SMP support for Broadcom's Northstar Plus SoC
cpu enable method. This changes also consolidates
iProc family's - BCM NSP and BCM Kona, platform
SMP handling in a common file.

Northstar Plus SoC is based on ARM Cortex-A9
revision r3p0 which requires configuration for ARM
Errata 764369 for SMP. This change adds the needed
configuration option.

Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig                   |  2 +
 arch/arm/mach-bcm/Makefile                  |  8 ++-
 arch/arm/mach-bcm/{kona_smp.c => platsmp.c} | 82 +++++++++++++++++++++++++----
 3 files changed, 81 insertions(+), 11 deletions(-)
 rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (75%)

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 1679fa4..2e9dbb5 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -40,6 +40,8 @@ config ARCH_BCM_NSP
 	select ARCH_BCM_IPROC
 	select ARM_ERRATA_754322
 	select ARM_ERRATA_775420
+	select ARM_ERRATA_764369 if SMP
+	select HAVE_SMP
 	help
 	  Support for Broadcom Northstar Plus SoC.
 	  Broadcom Northstar Plus family of SoCs are used for switching control
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 892261f..5193a25 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -14,7 +14,11 @@
 obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
 
 # Northstar Plus
-obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
+obj-$(CONFIG_ARCH_BCM_NSP)	+= bcm_nsp.o
+
+ifeq ($(CONFIG_ARCH_BCM_NSP),y)
+obj-$(CONFIG_SMP)		+= platsmp.o
+endif
 
 # BCM281XX
 obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
@@ -23,7 +27,7 @@ obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
 obj-$(CONFIG_ARCH_BCM_21664)	+= board_bcm21664.o
 
 # BCM281XX and BCM21664 SMP support
-obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
+obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o
 
 # BCM281XX and BCM21664 L2 cache control
 obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/platsmp.c
similarity index 75%
rename from arch/arm/mach-bcm/kona_smp.c
rename to arch/arm/mach-bcm/platsmp.c
index 66a0465..dbf14fb 100644
--- a/arch/arm/mach-bcm/kona_smp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Broadcom Corporation
+ * Copyright (C) 2014-2015 Broadcom Corporation
  * Copyright 2014 Linaro Limited
  *
  * This program is free software; you can redistribute it and/or
@@ -12,12 +12,17 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/init.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
+#include <linux/init.h>
 #include <linux/io.h>
+#include <linux/jiffies.h>
 #include <linux/of.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 
+#include <asm/cacheflush.h>
 #include <asm/smp.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
@@ -75,6 +80,37 @@ static int __init scu_a9_enable(void)
 	return 0;
 }
 
+static int nsp_write_lut(void)
+{
+	void __iomem *sku_rom_lut;
+	phys_addr_t secondary_startup_phy;
+
+	if (!secondary_boot) {
+		pr_warn("required secondary boot register not specified\n");
+		return -EINVAL;
+	}
+
+	sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot,
+						sizeof(secondary_boot));
+	if (!sku_rom_lut) {
+		pr_warn("unable to ioremap SKU-ROM LUT register\n");
+		return -ENOMEM;
+	}
+
+	secondary_startup_phy = virt_to_phys(secondary_startup);
+	BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
+
+	writel_relaxed(secondary_startup_phy, sku_rom_lut);
+	/*
+	 * Ensure the write is visible to the secondary core.
+	 */
+	smp_wmb();
+
+	iounmap(sku_rom_lut);
+
+	return 0;
+}
+
 static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
 {
 	static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
@@ -95,11 +131,11 @@ static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
 	/*
 	 * Our secondary enable method requires a "secondary-boot-reg"
 	 * property to specify a register address used to request the
-	 * ROM code boot a secondary code.  If we have any trouble
+	 * ROM code boot a secondary core.  If we have any trouble
 	 * getting this we fall back to uniprocessor mode.
 	 */
 	if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
-		pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
+		pr_warn("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
 			node->name);
 		ret = -ENOENT;		/* Arrange to disable SMP */
 		goto out;
@@ -115,7 +151,6 @@ out:
 	of_node_put(node);
 	if (ret) {
 		/* Update the CPU present map to reflect uniprocessor mode */
-		BUG_ON(ret != -ENOENT);
 		pr_warn("disabling SMP\n");
 		init_cpu_present(&only_cpu_0);
 	}
@@ -139,7 +174,7 @@ out:
  * - Wait for the secondary boot register to be re-written, which
  *   indicates the secondary core has started.
  */
-static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	void __iomem *boot_reg;
 	phys_addr_t boot_func;
@@ -162,7 +197,7 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
 	if (!boot_reg) {
 		pr_err("unable to map boot register for cpu %u\n", cpu_id);
-		return -ENOSYS;
+		return -ENOMEM;
 	}
 
 	/*
@@ -191,12 +226,41 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 	pr_err("timeout waiting for cpu %u to start\n", cpu_id);
 
-	return -ENOSYS;
+	return -ENXIO;
+}
+
+static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	int ret;
+
+	/*
+	 * After wake up, secondary core branches to the startup
+	 * address programmed at SKU ROM LUT location.
+	 */
+	ret = nsp_write_lut();
+	if (ret) {
+		pr_err("unable to write startup addr to SKU ROM LUT\n");
+		goto out;
+	}
+
+	/*
+	 * Send a CPU wakeup interrupt to the secondary core.
+	 */
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+out:
+	return ret;
 }
 
 static struct smp_operations bcm_smp_ops __initdata = {
 	.smp_prepare_cpus	= bcm_smp_prepare_cpus,
-	.smp_boot_secondary	= bcm_boot_secondary,
+	.smp_boot_secondary	= kona_boot_secondary,
 };
 CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
 			&bcm_smp_ops);
+
+struct smp_operations nsp_smp_ops __initdata = {
+	.smp_prepare_cpus	= bcm_smp_prepare_cpus,
+	.smp_boot_secondary	= nsp_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
-- 
2.1.0

[PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Kapil Hali]

From: Jon Mason <jonmason@broadcom.com>

Add SMP support for Broadcom's 4708 SoCs.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 arch/arm/boot/dts/bcm4708.dtsi | 2 ++
 arch/arm/mach-bcm/Kconfig      | 1 +
 arch/arm/mach-bcm/Makefile     | 3 +++
 3 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
index 31141e8..22a41df 100644
--- a/arch/arm/boot/dts/bcm4708.dtsi
+++ b/arch/arm/boot/dts/bcm4708.dtsi
@@ -15,6 +15,8 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";
+		secondary-boot-reg = <0xffff0400>;
 
 		cpu@0 {
 			device_type = "cpu";
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 2e9dbb5..4fc8fa3 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -54,6 +54,7 @@ config ARCH_BCM_NSP
 config ARCH_BCM_5301X
 	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
 	select ARCH_BCM_IPROC
+	select HAVE_SMP
 	help
 	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
 
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 5193a25..7d66515 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835)	+= board_bcm2835.o
 
 # BCM5301X
 obj-$(CONFIG_ARCH_BCM_5301X)	+= bcm_5301x.o
+ifeq ($(CONFIG_ARCH_BCM_5301X),y)
+obj-$(CONFIG_SMP)		+= platsmp.o
+endif
 
 # BCM63XXx
 ifeq ($(CONFIG_ARCH_BCM_63XX),y)
-- 
2.1.0

[PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Kapil Hali]

From: Jon Mason <jonmason@broadcom.com>

Add SMP support for Broadcom's 4708 SoCs.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 arch/arm/boot/dts/bcm4708.dtsi | 2 ++
 arch/arm/mach-bcm/Kconfig      | 1 +
 arch/arm/mach-bcm/Makefile     | 3 +++
 3 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
index 31141e8..22a41df 100644
--- a/arch/arm/boot/dts/bcm4708.dtsi
+++ b/arch/arm/boot/dts/bcm4708.dtsi
@@ -15,6 +15,8 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";
+		secondary-boot-reg = <0xffff0400>;
 
 		cpu@0 {
 			device_type = "cpu";
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 2e9dbb5..4fc8fa3 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -54,6 +54,7 @@ config ARCH_BCM_NSP
 config ARCH_BCM_5301X
 	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
 	select ARCH_BCM_IPROC
+	select HAVE_SMP
 	help
 	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
 
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 5193a25..7d66515 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835)	+= board_bcm2835.o
 
 # BCM5301X
 obj-$(CONFIG_ARCH_BCM_5301X)	+= bcm_5301x.o
+ifeq ($(CONFIG_ARCH_BCM_5301X),y)
+obj-$(CONFIG_SMP)		+= platsmp.o
+endif
 
 # BCM63XXx
 ifeq ($(CONFIG_ARCH_BCM_63XX),y)
-- 
2.1.0

[PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Kapil Hali]

From: Jon Mason <jonmason@broadcom.com>

Add SMP support for Broadcom's 4708 SoCs.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
 arch/arm/boot/dts/bcm4708.dtsi | 2 ++
 arch/arm/mach-bcm/Kconfig      | 1 +
 arch/arm/mach-bcm/Makefile     | 3 +++
 3 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
index 31141e8..22a41df 100644
--- a/arch/arm/boot/dts/bcm4708.dtsi
+++ b/arch/arm/boot/dts/bcm4708.dtsi
@@ -15,6 +15,8 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "brcm,bcm-nsp-smp";
+		secondary-boot-reg = <0xffff0400>;
 
 		cpu at 0 {
 			device_type = "cpu";
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 2e9dbb5..4fc8fa3 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -54,6 +54,7 @@ config ARCH_BCM_NSP
 config ARCH_BCM_5301X
 	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
 	select ARCH_BCM_IPROC
+	select HAVE_SMP
 	help
 	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
 
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 5193a25..7d66515 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835)	+= board_bcm2835.o
 
 # BCM5301X
 obj-$(CONFIG_ARCH_BCM_5301X)	+= bcm_5301x.o
+ifeq ($(CONFIG_ARCH_BCM_5301X),y)
+obj-$(CONFIG_SMP)		+= platsmp.o
+endif
 
 # BCM63XXx
 ifeq ($(CONFIG_ARCH_BCM_63XX),y)
-- 
2.1.0

Re: [PATCH v3 0/4] SMP support for Broadcom NSP

[Heiko Stuebner]

Hi,

Am Freitag, 6. November 2015, 16:11:09 schrieb Kapil Hali:
> Change in v3:
> * Fixed patch subject from RESEND PATCH to PATCH
> * Deleted arch/arm/mach-bcm/bcm_nsp.h file
> * Removed inclusion of header file bcm_nsp.h in platsmp.c
> * Removed unused variable 'timeout' in nsp_boot_secondary()

I'm still not sure why I'm getting this :-) . But with the number of patch 
(re-)sends it's crowding my inbox a bit to much for my liking, so please drop 
me of your recipient list


Thanks
Heiko

[PATCH v3 0/4] SMP support for Broadcom NSP

[Heiko Stuebner]

Hi,

Am Freitag, 6. November 2015, 16:11:09 schrieb Kapil Hali:
> Change in v3:
> * Fixed patch subject from RESEND PATCH to PATCH
> * Deleted arch/arm/mach-bcm/bcm_nsp.h file
> * Removed inclusion of header file bcm_nsp.h in platsmp.c
> * Removed unused variable 'timeout' in nsp_boot_secondary()

I'm still not sure why I'm getting this :-) . But with the number of patch 
(re-)sends it's crowding my inbox a bit to much for my liking, so please drop 
me of your recipient list


Thanks
Heiko

Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Hauke Mehrtens]

On 11/06/2015 10:11 PM, Kapil Hali wrote:
> From: Jon Mason <jonmason@broadcom.com>
> 
> Add SMP support for Broadcom's 4708 SoCs.
> 
> Signed-off-by: Jon Mason <jonmason@broadcom.com>
> Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
> Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>

I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.

> ---
>  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
>  arch/arm/mach-bcm/Kconfig      | 1 +
>  arch/arm/mach-bcm/Makefile     | 3 +++
>  3 files changed, 6 insertions(+)
> 

...

> --- a/arch/arm/mach-bcm/Kconfig
> +++ b/arch/arm/mach-bcm/Kconfig
> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
>  config ARCH_BCM_5301X
>  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
>  	select ARCH_BCM_IPROC

You activated ARM_ERRATA_764369 for NSP is this not needed for NS?


> +	select HAVE_SMP
>  	help
>  	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
>  

...

Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Hauke Mehrtens]

On 11/06/2015 10:11 PM, Kapil Hali wrote:
> From: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> 
> Add SMP support for Broadcom's 4708 SoCs.
> 
> Signed-off-by: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> Acked-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> Tested-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> Signed-off-by: Kapil Hali <kapilh-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>

I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.

> ---
>  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
>  arch/arm/mach-bcm/Kconfig      | 1 +
>  arch/arm/mach-bcm/Makefile     | 3 +++
>  3 files changed, 6 insertions(+)
> 

...

> --- a/arch/arm/mach-bcm/Kconfig
> +++ b/arch/arm/mach-bcm/Kconfig
> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
>  config ARCH_BCM_5301X
>  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
>  	select ARCH_BCM_IPROC

You activated ARM_ERRATA_764369 for NSP is this not needed for NS?


> +	select HAVE_SMP
>  	help
>  	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
>  

...
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[PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Hauke Mehrtens]

On 11/06/2015 10:11 PM, Kapil Hali wrote:
> From: Jon Mason <jonmason@broadcom.com>
> 
> Add SMP support for Broadcom's 4708 SoCs.
> 
> Signed-off-by: Jon Mason <jonmason@broadcom.com>
> Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
> Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>

I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.

> ---
>  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
>  arch/arm/mach-bcm/Kconfig      | 1 +
>  arch/arm/mach-bcm/Makefile     | 3 +++
>  3 files changed, 6 insertions(+)
> 

...

> --- a/arch/arm/mach-bcm/Kconfig
> +++ b/arch/arm/mach-bcm/Kconfig
> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
>  config ARCH_BCM_5301X
>  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
>  	select ARCH_BCM_IPROC

You activated ARM_ERRATA_764369 for NSP is this not needed for NS?


> +	select HAVE_SMP
>  	help
>  	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
>  

...

Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Jon Mason]

On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
> On 11/06/2015 10:11 PM, Kapil Hali wrote:
> > From: Jon Mason <jonmason@broadcom.com>
> > 
> > Add SMP support for Broadcom's 4708 SoCs.
> > 
> > Signed-off-by: Jon Mason <jonmason@broadcom.com>
> > Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
> > Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
> > Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> 
> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
> 
> > ---
> >  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
> >  arch/arm/mach-bcm/Kconfig      | 1 +
> >  arch/arm/mach-bcm/Makefile     | 3 +++
> >  3 files changed, 6 insertions(+)
> > 
> 
> ...
> 
> > --- a/arch/arm/mach-bcm/Kconfig
> > +++ b/arch/arm/mach-bcm/Kconfig
> > @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
> >  config ARCH_BCM_5301X
> >  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
> >  	select ARCH_BCM_IPROC
> 
> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?

I'm not certain the CPU version, and without that it is difficult to
know what errata's are present in the underlying hardware.  My guess
is that all present in NSP are present in NS (for UP and SMP).  This
would put it as:
        select ARM_ERRATA_754322
        select ARM_ERRATA_775420
        select ARM_ERRATA_764369 if SMP

Would you like me to have them added?

Thanks,
Jon

> 
> 
> > +	select HAVE_SMP
> >  	help
> >  	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
> >  
> 
> ...

Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Jon Mason]

On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
> On 11/06/2015 10:11 PM, Kapil Hali wrote:
> > From: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> > 
> > Add SMP support for Broadcom's 4708 SoCs.
> > 
> > Signed-off-by: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> > Acked-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> > Tested-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> > Signed-off-by: Kapil Hali <kapilh-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> 
> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
> 
> > ---
> >  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
> >  arch/arm/mach-bcm/Kconfig      | 1 +
> >  arch/arm/mach-bcm/Makefile     | 3 +++
> >  3 files changed, 6 insertions(+)
> > 
> 
> ...
> 
> > --- a/arch/arm/mach-bcm/Kconfig
> > +++ b/arch/arm/mach-bcm/Kconfig
> > @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
> >  config ARCH_BCM_5301X
> >  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
> >  	select ARCH_BCM_IPROC
> 
> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?

I'm not certain the CPU version, and without that it is difficult to
know what errata's are present in the underlying hardware.  My guess
is that all present in NSP are present in NS (for UP and SMP).  This
would put it as:
        select ARM_ERRATA_754322
        select ARM_ERRATA_775420
        select ARM_ERRATA_764369 if SMP

Would you like me to have them added?

Thanks,
Jon

> 
> 
> > +	select HAVE_SMP
> >  	help
> >  	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
> >  
> 
> ...
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[PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Jon Mason]

On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
> On 11/06/2015 10:11 PM, Kapil Hali wrote:
> > From: Jon Mason <jonmason@broadcom.com>
> > 
> > Add SMP support for Broadcom's 4708 SoCs.
> > 
> > Signed-off-by: Jon Mason <jonmason@broadcom.com>
> > Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
> > Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
> > Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> 
> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
> 
> > ---
> >  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
> >  arch/arm/mach-bcm/Kconfig      | 1 +
> >  arch/arm/mach-bcm/Makefile     | 3 +++
> >  3 files changed, 6 insertions(+)
> > 
> 
> ...
> 
> > --- a/arch/arm/mach-bcm/Kconfig
> > +++ b/arch/arm/mach-bcm/Kconfig
> > @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
> >  config ARCH_BCM_5301X
> >  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
> >  	select ARCH_BCM_IPROC
> 
> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?

I'm not certain the CPU version, and without that it is difficult to
know what errata's are present in the underlying hardware.  My guess
is that all present in NSP are present in NS (for UP and SMP).  This
would put it as:
        select ARM_ERRATA_754322
        select ARM_ERRATA_775420
        select ARM_ERRATA_764369 if SMP

Would you like me to have them added?

Thanks,
Jon

> 
> 
> > +	select HAVE_SMP
> >  	help
> >  	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
> >  
> 
> ...

Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Scott Branden]

Hi Hauke,

On 15-11-06 01:42 PM, Hauke Mehrtens wrote:
> On 11/06/2015 10:11 PM, Kapil Hali wrote:
>> From: Jon Mason <jonmason@broadcom.com>
>>
>> Add SMP support for Broadcom's 4708 SoCs.
>>
>> Signed-off-by: Jon Mason <jonmason@broadcom.com>
>> Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
>> Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>
> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
>
>> ---
>>   arch/arm/boot/dts/bcm4708.dtsi | 2 ++
>>   arch/arm/mach-bcm/Kconfig      | 1 +
>>   arch/arm/mach-bcm/Makefile     | 3 +++
>>   3 files changed, 6 insertions(+)
>>
>
> ...
>
>> --- a/arch/arm/mach-bcm/Kconfig
>> +++ b/arch/arm/mach-bcm/Kconfig
>> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
>>   config ARCH_BCM_5301X
>>   	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
>>   	select ARCH_BCM_IPROC
>
> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?
>
You would have to read the ARM CPU register and then compare to ARM 
Errata to see whether the Errata affects NS or not.
>
>> +	select HAVE_SMP
>>   	help
>>   	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
>>
>
> ...
>

Regards,
Scott

Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Scott Branden]

Hi Hauke,

On 15-11-06 01:42 PM, Hauke Mehrtens wrote:
> On 11/06/2015 10:11 PM, Kapil Hali wrote:
>> From: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>>
>> Add SMP support for Broadcom's 4708 SoCs.
>>
>> Signed-off-by: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>> Acked-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>> Tested-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>> Signed-off-by: Kapil Hali <kapilh-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>
> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
>
>> ---
>>   arch/arm/boot/dts/bcm4708.dtsi | 2 ++
>>   arch/arm/mach-bcm/Kconfig      | 1 +
>>   arch/arm/mach-bcm/Makefile     | 3 +++
>>   3 files changed, 6 insertions(+)
>>
>
> ...
>
>> --- a/arch/arm/mach-bcm/Kconfig
>> +++ b/arch/arm/mach-bcm/Kconfig
>> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
>>   config ARCH_BCM_5301X
>>   	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
>>   	select ARCH_BCM_IPROC
>
> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?
>
You would have to read the ARM CPU register and then compare to ARM 
Errata to see whether the Errata affects NS or not.
>
>> +	select HAVE_SMP
>>   	help
>>   	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
>>
>
> ...
>

Regards,
Scott

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[PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Scott Branden]

Hi Hauke,

On 15-11-06 01:42 PM, Hauke Mehrtens wrote:
> On 11/06/2015 10:11 PM, Kapil Hali wrote:
>> From: Jon Mason <jonmason@broadcom.com>
>>
>> Add SMP support for Broadcom's 4708 SoCs.
>>
>> Signed-off-by: Jon Mason <jonmason@broadcom.com>
>> Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
>> Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>
> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
>
>> ---
>>   arch/arm/boot/dts/bcm4708.dtsi | 2 ++
>>   arch/arm/mach-bcm/Kconfig      | 1 +
>>   arch/arm/mach-bcm/Makefile     | 3 +++
>>   3 files changed, 6 insertions(+)
>>
>
> ...
>
>> --- a/arch/arm/mach-bcm/Kconfig
>> +++ b/arch/arm/mach-bcm/Kconfig
>> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
>>   config ARCH_BCM_5301X
>>   	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
>>   	select ARCH_BCM_IPROC
>
> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?
>
You would have to read the ARM CPU register and then compare to ARM 
Errata to see whether the Errata affects NS or not.
>
>> +	select HAVE_SMP
>>   	help
>>   	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
>>
>
> ...
>

Regards,
Scott

Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Hauke Mehrtens]

On 11/06/2015 11:54 PM, Jon Mason wrote:
> On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
>> On 11/06/2015 10:11 PM, Kapil Hali wrote:
>>> From: Jon Mason <jonmason@broadcom.com>
>>>
>>> Add SMP support for Broadcom's 4708 SoCs.
>>>
>>> Signed-off-by: Jon Mason <jonmason@broadcom.com>
>>> Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
>>> Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
>>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>>
>> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
>>
>>> ---
>>>  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
>>>  arch/arm/mach-bcm/Kconfig      | 1 +
>>>  arch/arm/mach-bcm/Makefile     | 3 +++
>>>  3 files changed, 6 insertions(+)
>>>
>>
>> ...
>>
>>> --- a/arch/arm/mach-bcm/Kconfig
>>> +++ b/arch/arm/mach-bcm/Kconfig
>>> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
>>>  config ARCH_BCM_5301X
>>>  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
>>>  	select ARCH_BCM_IPROC
>>
>> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?
> 
> I'm not certain the CPU version, and without that it is difficult to
> know what errata's are present in the underlying hardware.  My guess
> is that all present in NSP are present in NS (for UP and SMP).  This
> would put it as:
>         select ARM_ERRATA_754322
>         select ARM_ERRATA_775420
>         select ARM_ERRATA_764369 if SMP
> 
> Would you like me to have them added?
> 

I will send a separate patch adding all the workarounds for erratas in
the CPU core and the cache controller.

Hauke

Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Hauke Mehrtens]

On 11/06/2015 11:54 PM, Jon Mason wrote:
> On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
>> On 11/06/2015 10:11 PM, Kapil Hali wrote:
>>> From: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>>>
>>> Add SMP support for Broadcom's 4708 SoCs.
>>>
>>> Signed-off-by: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>>> Acked-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>>> Tested-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>>> Signed-off-by: Kapil Hali <kapilh-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>>
>> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
>>
>>> ---
>>>  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
>>>  arch/arm/mach-bcm/Kconfig      | 1 +
>>>  arch/arm/mach-bcm/Makefile     | 3 +++
>>>  3 files changed, 6 insertions(+)
>>>
>>
>> ...
>>
>>> --- a/arch/arm/mach-bcm/Kconfig
>>> +++ b/arch/arm/mach-bcm/Kconfig
>>> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
>>>  config ARCH_BCM_5301X
>>>  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
>>>  	select ARCH_BCM_IPROC
>>
>> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?
> 
> I'm not certain the CPU version, and without that it is difficult to
> know what errata's are present in the underlying hardware.  My guess
> is that all present in NSP are present in NS (for UP and SMP).  This
> would put it as:
>         select ARM_ERRATA_754322
>         select ARM_ERRATA_775420
>         select ARM_ERRATA_764369 if SMP
> 
> Would you like me to have them added?
> 

I will send a separate patch adding all the workarounds for erratas in
the CPU core and the cache controller.

Hauke


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[PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Hauke Mehrtens]

On 11/06/2015 11:54 PM, Jon Mason wrote:
> On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
>> On 11/06/2015 10:11 PM, Kapil Hali wrote:
>>> From: Jon Mason <jonmason@broadcom.com>
>>>
>>> Add SMP support for Broadcom's 4708 SoCs.
>>>
>>> Signed-off-by: Jon Mason <jonmason@broadcom.com>
>>> Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
>>> Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
>>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>>
>> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
>>
>>> ---
>>>  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
>>>  arch/arm/mach-bcm/Kconfig      | 1 +
>>>  arch/arm/mach-bcm/Makefile     | 3 +++
>>>  3 files changed, 6 insertions(+)
>>>
>>
>> ...
>>
>>> --- a/arch/arm/mach-bcm/Kconfig
>>> +++ b/arch/arm/mach-bcm/Kconfig
>>> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
>>>  config ARCH_BCM_5301X
>>>  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
>>>  	select ARCH_BCM_IPROC
>>
>> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?
> 
> I'm not certain the CPU version, and without that it is difficult to
> know what errata's are present in the underlying hardware.  My guess
> is that all present in NSP are present in NS (for UP and SMP).  This
> would put it as:
>         select ARM_ERRATA_754322
>         select ARM_ERRATA_775420
>         select ARM_ERRATA_764369 if SMP
> 
> Would you like me to have them added?
> 

I will send a separate patch adding all the workarounds for erratas in
the CPU core and the cache controller.

Hauke

Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Hauke Mehrtens]

On 11/07/2015 12:27 AM, Hauke Mehrtens wrote:
> On 11/06/2015 11:54 PM, Jon Mason wrote:
>> On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
>>> On 11/06/2015 10:11 PM, Kapil Hali wrote:
>>>> From: Jon Mason <jonmason@broadcom.com>
>>>>
>>>> Add SMP support for Broadcom's 4708 SoCs.
>>>>
>>>> Signed-off-by: Jon Mason <jonmason@broadcom.com>
>>>> Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
>>>> Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
>>>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>>>
>>> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
>>>
>>>> ---
>>>>  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
>>>>  arch/arm/mach-bcm/Kconfig      | 1 +
>>>>  arch/arm/mach-bcm/Makefile     | 3 +++
>>>>  3 files changed, 6 insertions(+)
>>>>
>>>
>>> ...
>>>
>>>> --- a/arch/arm/mach-bcm/Kconfig
>>>> +++ b/arch/arm/mach-bcm/Kconfig
>>>> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
>>>>  config ARCH_BCM_5301X
>>>>  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
>>>>  	select ARCH_BCM_IPROC
>>>
>>> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?
>>
>> I'm not certain the CPU version, and without that it is difficult to
>> know what errata's are present in the underlying hardware.  My guess
>> is that all present in NSP are present in NS (for UP and SMP).  This
>> would put it as:
>>         select ARM_ERRATA_754322
>>         select ARM_ERRATA_775420
>>         select ARM_ERRATA_764369 if SMP
>>
>> Would you like me to have them added?
>>
> 
> I will send a separate patch adding all the workarounds for erratas in
> the CPU core and the cache controller.
> 
> Hauke
> 
> 
Hi,

BCM4708 uses a Cortex-A9 rev r3p0 and a L2C-310 rev r3p2. For this CPU
and cache controller the same workaround are needed as for NSP, if you
will resend this patch, please add all of them.

Hauke

[PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Hauke Mehrtens]

On 11/07/2015 12:27 AM, Hauke Mehrtens wrote:
> On 11/06/2015 11:54 PM, Jon Mason wrote:
>> On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
>>> On 11/06/2015 10:11 PM, Kapil Hali wrote:
>>>> From: Jon Mason <jonmason@broadcom.com>
>>>>
>>>> Add SMP support for Broadcom's 4708 SoCs.
>>>>
>>>> Signed-off-by: Jon Mason <jonmason@broadcom.com>
>>>> Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
>>>> Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
>>>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>>>
>>> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
>>>
>>>> ---
>>>>  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
>>>>  arch/arm/mach-bcm/Kconfig      | 1 +
>>>>  arch/arm/mach-bcm/Makefile     | 3 +++
>>>>  3 files changed, 6 insertions(+)
>>>>
>>>
>>> ...
>>>
>>>> --- a/arch/arm/mach-bcm/Kconfig
>>>> +++ b/arch/arm/mach-bcm/Kconfig
>>>> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
>>>>  config ARCH_BCM_5301X
>>>>  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
>>>>  	select ARCH_BCM_IPROC
>>>
>>> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?
>>
>> I'm not certain the CPU version, and without that it is difficult to
>> know what errata's are present in the underlying hardware.  My guess
>> is that all present in NSP are present in NS (for UP and SMP).  This
>> would put it as:
>>         select ARM_ERRATA_754322
>>         select ARM_ERRATA_775420
>>         select ARM_ERRATA_764369 if SMP
>>
>> Would you like me to have them added?
>>
> 
> I will send a separate patch adding all the workarounds for erratas in
> the CPU core and the cache controller.
> 
> Hauke
> 
> 
Hi,

BCM4708 uses a Cortex-A9 rev r3p0 and a L2C-310 rev r3p2. For this CPU
and cache controller the same workaround are needed as for NSP, if you
will resend this patch, please add all of them.

Hauke

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Rob Herring]

On Fri, Nov 6, 2015 at 3:11 PM, Kapil Hali <kapilh@broadcom.com> wrote:
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU.
>
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> ---
>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>  2 files changed, 37 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> new file mode 100644
> index 0000000..8506da7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> @@ -0,0 +1,36 @@
> +Broadcom Northstar Plus SoC CPU Enable Method
> +---------------------------------------------
> +This binding defines the enable method used for starting secondary
> +CPUs in the following Broadcom SoCs:
> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
> +
> +The enable method is specified by defining the following required
> +properties in the "cpus" device tree node:
> +  - enable-method = "brcm,bcm-nsp-smp";

As I said already, this is supposed to be per cpu.

> +  - secondary-boot-reg = <...>;

And then you might as well move this too.

> +
> +The secondary-boot-reg property is a u32 value that specifies the
> +physical address of the register used to request the ROM holding pen
> +code release a secondary CPU.
> +
> +Example:
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               enable-method = "brcm,bcm-nsp-smp";
> +               secondary-boot-reg = <0xffff042c>;
> +
> +               cpu0: cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       next-level-cache = <&L2>;
> +                       reg = <0>;
> +               };
> +
> +               cpu1: cpu@1 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       next-level-cache = <&L2>;
> +                       reg = <1>;
> +               };
> +       };
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 91e6e5c..6abe3f3 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>                             "allwinner,sun8i-a23"
>                             "arm,psci"
>                             "brcm,brahma-b15"
> +                           "brcm,bcm-nsp-smp"
>                             "marvell,armada-375-smp"
>                             "marvell,armada-380-smp"
>                             "marvell,armada-390-smp"
> --
> 2.1.0
>

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Rob Herring]

On Fri, Nov 6, 2015 at 3:11 PM, Kapil Hali <kapilh@broadcom.com> wrote:
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU.
>
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> ---
>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>  2 files changed, 37 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> new file mode 100644
> index 0000000..8506da7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> @@ -0,0 +1,36 @@
> +Broadcom Northstar Plus SoC CPU Enable Method
> +---------------------------------------------
> +This binding defines the enable method used for starting secondary
> +CPUs in the following Broadcom SoCs:
> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
> +
> +The enable method is specified by defining the following required
> +properties in the "cpus" device tree node:
> +  - enable-method = "brcm,bcm-nsp-smp";

As I said already, this is supposed to be per cpu.

> +  - secondary-boot-reg = <...>;

And then you might as well move this too.

> +
> +The secondary-boot-reg property is a u32 value that specifies the
> +physical address of the register used to request the ROM holding pen
> +code release a secondary CPU.
> +
> +Example:
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               enable-method = "brcm,bcm-nsp-smp";
> +               secondary-boot-reg = <0xffff042c>;
> +
> +               cpu0: cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       next-level-cache = <&L2>;
> +                       reg = <0>;
> +               };
> +
> +               cpu1: cpu@1 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       next-level-cache = <&L2>;
> +                       reg = <1>;
> +               };
> +       };
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 91e6e5c..6abe3f3 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>                             "allwinner,sun8i-a23"
>                             "arm,psci"
>                             "brcm,brahma-b15"
> +                           "brcm,bcm-nsp-smp"
>                             "marvell,armada-375-smp"
>                             "marvell,armada-380-smp"
>                             "marvell,armada-390-smp"
> --
> 2.1.0
>

[PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Rob Herring]

On Fri, Nov 6, 2015 at 3:11 PM, Kapil Hali <kapilh@broadcom.com> wrote:
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU.
>
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> ---
>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>  2 files changed, 37 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> new file mode 100644
> index 0000000..8506da7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> @@ -0,0 +1,36 @@
> +Broadcom Northstar Plus SoC CPU Enable Method
> +---------------------------------------------
> +This binding defines the enable method used for starting secondary
> +CPUs in the following Broadcom SoCs:
> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
> +
> +The enable method is specified by defining the following required
> +properties in the "cpus" device tree node:
> +  - enable-method = "brcm,bcm-nsp-smp";

As I said already, this is supposed to be per cpu.

> +  - secondary-boot-reg = <...>;

And then you might as well move this too.

> +
> +The secondary-boot-reg property is a u32 value that specifies the
> +physical address of the register used to request the ROM holding pen
> +code release a secondary CPU.
> +
> +Example:
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               enable-method = "brcm,bcm-nsp-smp";
> +               secondary-boot-reg = <0xffff042c>;
> +
> +               cpu0: cpu at 0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       next-level-cache = <&L2>;
> +                       reg = <0>;
> +               };
> +
> +               cpu1: cpu at 1 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       next-level-cache = <&L2>;
> +                       reg = <1>;
> +               };
> +       };
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 91e6e5c..6abe3f3 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>                             "allwinner,sun8i-a23"
>                             "arm,psci"
>                             "brcm,brahma-b15"
> +                           "brcm,bcm-nsp-smp"
>                             "marvell,armada-375-smp"
>                             "marvell,armada-380-smp"
>                             "marvell,armada-390-smp"
> --
> 2.1.0
>

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Florian Fainelli]

Le 06/11/2015 13:11, Kapil Hali a écrit :
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU.
> 
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> ---
>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>  2 files changed, 37 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> new file mode 100644
> index 0000000..8506da7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> @@ -0,0 +1,36 @@
> +Broadcom Northstar Plus SoC CPU Enable Method
> +---------------------------------------------
> +This binding defines the enable method used for starting secondary
> +CPUs in the following Broadcom SoCs:
> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
> +
> +The enable method is specified by defining the following required
> +properties in the "cpus" device tree node:
> +  - enable-method = "brcm,bcm-nsp-smp";
> +  - secondary-boot-reg = <...>;
> +
> +The secondary-boot-reg property is a u32 value that specifies the
> +physical address of the register used to request the ROM holding pen
> +code release a secondary CPU.

Is it really how the ROM code is implemented, as a pen holding/release
mechanism (which sounds like how this was implemented previously in the
kernel actually) or should this be described in a more generic way as
the physical address of the register where the secondary CPUs reset
vector address must be written to? Or something along these lines.

> +
> +Example:
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		enable-method = "brcm,bcm-nsp-smp";

Just a nit, but if NSP and NS are sharing the same mechanism, would not
a more "NS-centric" property be more appropriate because NS came before NSP?

> +		secondary-boot-reg = <0xffff042c>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			next-level-cache = <&L2>;
> +			reg = <0>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			next-level-cache = <&L2>;
> +			reg = <1>;
> +		};
> +	};
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 91e6e5c..6abe3f3 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>  			    "allwinner,sun8i-a23"
>  			    "arm,psci"
>  			    "brcm,brahma-b15"
> +			    "brcm,bcm-nsp-smp"
>  			    "marvell,armada-375-smp"
>  			    "marvell,armada-380-smp"
>  			    "marvell,armada-390-smp"
> 


-- 
Florian

[PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Florian Fainelli]

Le 06/11/2015 13:11, Kapil Hali a ?crit :
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU.
> 
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> ---
>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>  2 files changed, 37 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> new file mode 100644
> index 0000000..8506da7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> @@ -0,0 +1,36 @@
> +Broadcom Northstar Plus SoC CPU Enable Method
> +---------------------------------------------
> +This binding defines the enable method used for starting secondary
> +CPUs in the following Broadcom SoCs:
> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
> +
> +The enable method is specified by defining the following required
> +properties in the "cpus" device tree node:
> +  - enable-method = "brcm,bcm-nsp-smp";
> +  - secondary-boot-reg = <...>;
> +
> +The secondary-boot-reg property is a u32 value that specifies the
> +physical address of the register used to request the ROM holding pen
> +code release a secondary CPU.

Is it really how the ROM code is implemented, as a pen holding/release
mechanism (which sounds like how this was implemented previously in the
kernel actually) or should this be described in a more generic way as
the physical address of the register where the secondary CPUs reset
vector address must be written to? Or something along these lines.

> +
> +Example:
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		enable-method = "brcm,bcm-nsp-smp";

Just a nit, but if NSP and NS are sharing the same mechanism, would not
a more "NS-centric" property be more appropriate because NS came before NSP?

> +		secondary-boot-reg = <0xffff042c>;
> +
> +		cpu0: cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			next-level-cache = <&L2>;
> +			reg = <0>;
> +		};
> +
> +		cpu1: cpu at 1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			next-level-cache = <&L2>;
> +			reg = <1>;
> +		};
> +	};
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 91e6e5c..6abe3f3 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>  			    "allwinner,sun8i-a23"
>  			    "arm,psci"
>  			    "brcm,brahma-b15"
> +			    "brcm,bcm-nsp-smp"
>  			    "marvell,armada-375-smp"
>  			    "marvell,armada-380-smp"
>  			    "marvell,armada-390-smp"
> 


-- 
Florian

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Russell King - ARM Linux]

On Sat, Nov 07, 2015 at 01:40:23PM -0800, Florian Fainelli wrote:
> Le 06/11/2015 13:11, Kapil Hali a écrit :
> > Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> > Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> > documentation file and create a new binding documentation for
> > Northstar Plus CPU.
> > 
> > Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> > ---
> >  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
> >  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
> >  2 files changed, 37 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> > new file mode 100644
> > index 0000000..8506da7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> > @@ -0,0 +1,36 @@
> > +Broadcom Northstar Plus SoC CPU Enable Method
> > +---------------------------------------------
> > +This binding defines the enable method used for starting secondary
> > +CPUs in the following Broadcom SoCs:
> > +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
> > +
> > +The enable method is specified by defining the following required
> > +properties in the "cpus" device tree node:
> > +  - enable-method = "brcm,bcm-nsp-smp";
> > +  - secondary-boot-reg = <...>;
> > +
> > +The secondary-boot-reg property is a u32 value that specifies the
> > +physical address of the register used to request the ROM holding pen
> > +code release a secondary CPU.
> 
> Is it really how the ROM code is implemented, as a pen holding/release
> mechanism (which sounds like how this was implemented previously in the
> kernel actually) or should this be described in a more generic way as
> the physical address of the register where the secondary CPUs reset
> vector address must be written to? Or something along these lines.

Why do people insist on using holding pens to bring their secondary CPUs
into existence?  I hope the hardware people aren't being dumb and have no
way to hold in reset or power down their secondary CPUs, either of which
is a vital feature for things like kexec and the like.  If they do have
a way to hold secondary CPUs in reset or powered down, why aren't they
using that at boot instead of implementing the stupid Versatile scheme,
which exists because Versatile _can't_ hold its CPUs in reset or power
them down...

It's times like this that I wonder what kind of drugs the hardware SoC
people are on, but I'm well aware that people contributing SMP bringup
solutions are also dumb idiots who copy the Versatile scheme with very
little thought... (as you can see, I'm not mincing my words here - if
people want to be lazy in this regard despite this having been brought
up multiple times, and the lead developers having said that the versatile
pen_release stuff should not be used, they earn themselves the right to
be called dumb idiots.  Simple solution to avoid that title: don't be a
dumb idiot by copy the Versatile SMP bring up code!  It's not a sane
model for any SoC sane SoC to follow.)

Is this clear enough?

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

[PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Russell King - ARM Linux]

On Sat, Nov 07, 2015 at 01:40:23PM -0800, Florian Fainelli wrote:
> Le 06/11/2015 13:11, Kapil Hali a ?crit :
> > Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> > Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> > documentation file and create a new binding documentation for
> > Northstar Plus CPU.
> > 
> > Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> > ---
> >  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
> >  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
> >  2 files changed, 37 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> > new file mode 100644
> > index 0000000..8506da7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> > @@ -0,0 +1,36 @@
> > +Broadcom Northstar Plus SoC CPU Enable Method
> > +---------------------------------------------
> > +This binding defines the enable method used for starting secondary
> > +CPUs in the following Broadcom SoCs:
> > +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
> > +
> > +The enable method is specified by defining the following required
> > +properties in the "cpus" device tree node:
> > +  - enable-method = "brcm,bcm-nsp-smp";
> > +  - secondary-boot-reg = <...>;
> > +
> > +The secondary-boot-reg property is a u32 value that specifies the
> > +physical address of the register used to request the ROM holding pen
> > +code release a secondary CPU.
> 
> Is it really how the ROM code is implemented, as a pen holding/release
> mechanism (which sounds like how this was implemented previously in the
> kernel actually) or should this be described in a more generic way as
> the physical address of the register where the secondary CPUs reset
> vector address must be written to? Or something along these lines.

Why do people insist on using holding pens to bring their secondary CPUs
into existence?  I hope the hardware people aren't being dumb and have no
way to hold in reset or power down their secondary CPUs, either of which
is a vital feature for things like kexec and the like.  If they do have
a way to hold secondary CPUs in reset or powered down, why aren't they
using that at boot instead of implementing the stupid Versatile scheme,
which exists because Versatile _can't_ hold its CPUs in reset or power
them down...

It's times like this that I wonder what kind of drugs the hardware SoC
people are on, but I'm well aware that people contributing SMP bringup
solutions are also dumb idiots who copy the Versatile scheme with very
little thought... (as you can see, I'm not mincing my words here - if
people want to be lazy in this regard despite this having been brought
up multiple times, and the lead developers having said that the versatile
pen_release stuff should not be used, they earn themselves the right to
be called dumb idiots.  Simple solution to avoid that title: don't be a
dumb idiot by copy the Versatile SMP bring up code!  It's not a sane
model for any SoC sane SoC to follow.)

Is this clear enough?

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Florian Fainelli]

2015-11-08 9:31 GMT-08:00 Russell King - ARM Linux <linux@arm.linux.org.uk>:

>> Is it really how the ROM code is implemented, as a pen holding/release
>> mechanism (which sounds like how this was implemented previously in the
>> kernel actually) or should this be described in a more generic way as
>> the physical address of the register where the secondary CPUs reset
>> vector address must be written to? Or something along these lines.
>
> Why do people insist on using holding pens to bring their secondary CPUs
> into existence?  I hope the hardware people aren't being dumb and have no
> way to hold in reset or power down their secondary CPUs, either of which
> is a vital feature for things like kexec and the like.  If they do have
> a way to hold secondary CPUs in reset or powered down, why aren't they
> using that at boot instead of implementing the stupid Versatile scheme,
> which exists because Versatile _can't_ hold its CPUs in reset or power
> them down...

There are few implementations out there which suffer from this same
mistake (mostly MIPS implementations) but that is not really relevant
here. Most of the time this comes from not understanding software
models and/or not properly taking into account a complex (too complex)
reset model.

>
> It's times like this that I wonder what kind of drugs the hardware SoC
> people are on, but I'm well aware that people contributing SMP bringup
> solutions are also dumb idiots who copy the Versatile scheme with very
> little thought... (as you can see, I'm not mincing my words here - if
> people want to be lazy in this regard despite this having been brought
> up multiple times, and the lead developers having said that the versatile
> pen_release stuff should not be used, they earn themselves the right to
> be called dumb idiots.  Simple solution to avoid that title: don't be a
> dumb idiot by copy the Versatile SMP bring up code!  It's not a sane
> model for any SoC sane SoC to follow.)
>
> Is this clear enough?

The actual implementation of the SMP code in the next patches do not
use a pen holding/release mechanism anymore as it used in the previous
iterations of these same patches, so I would say, lesson learned. My
question was whether the binding was documenting the hardware
implementation (which it should) or the software implementation (which
it should not).
-- 
Florian

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Florian Fainelli]

2015-11-08 9:31 GMT-08:00 Russell King - ARM Linux <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>:

>> Is it really how the ROM code is implemented, as a pen holding/release
>> mechanism (which sounds like how this was implemented previously in the
>> kernel actually) or should this be described in a more generic way as
>> the physical address of the register where the secondary CPUs reset
>> vector address must be written to? Or something along these lines.
>
> Why do people insist on using holding pens to bring their secondary CPUs
> into existence?  I hope the hardware people aren't being dumb and have no
> way to hold in reset or power down their secondary CPUs, either of which
> is a vital feature for things like kexec and the like.  If they do have
> a way to hold secondary CPUs in reset or powered down, why aren't they
> using that at boot instead of implementing the stupid Versatile scheme,
> which exists because Versatile _can't_ hold its CPUs in reset or power
> them down...

There are few implementations out there which suffer from this same
mistake (mostly MIPS implementations) but that is not really relevant
here. Most of the time this comes from not understanding software
models and/or not properly taking into account a complex (too complex)
reset model.

>
> It's times like this that I wonder what kind of drugs the hardware SoC
> people are on, but I'm well aware that people contributing SMP bringup
> solutions are also dumb idiots who copy the Versatile scheme with very
> little thought... (as you can see, I'm not mincing my words here - if
> people want to be lazy in this regard despite this having been brought
> up multiple times, and the lead developers having said that the versatile
> pen_release stuff should not be used, they earn themselves the right to
> be called dumb idiots.  Simple solution to avoid that title: don't be a
> dumb idiot by copy the Versatile SMP bring up code!  It's not a sane
> model for any SoC sane SoC to follow.)
>
> Is this clear enough?

The actual implementation of the SMP code in the next patches do not
use a pen holding/release mechanism anymore as it used in the previous
iterations of these same patches, so I would say, lesson learned. My
question was whether the binding was documenting the hardware
implementation (which it should) or the software implementation (which
it should not).
-- 
Florian
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[PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Florian Fainelli]

2015-11-08 9:31 GMT-08:00 Russell King - ARM Linux <linux@arm.linux.org.uk>:

>> Is it really how the ROM code is implemented, as a pen holding/release
>> mechanism (which sounds like how this was implemented previously in the
>> kernel actually) or should this be described in a more generic way as
>> the physical address of the register where the secondary CPUs reset
>> vector address must be written to? Or something along these lines.
>
> Why do people insist on using holding pens to bring their secondary CPUs
> into existence?  I hope the hardware people aren't being dumb and have no
> way to hold in reset or power down their secondary CPUs, either of which
> is a vital feature for things like kexec and the like.  If they do have
> a way to hold secondary CPUs in reset or powered down, why aren't they
> using that at boot instead of implementing the stupid Versatile scheme,
> which exists because Versatile _can't_ hold its CPUs in reset or power
> them down...

There are few implementations out there which suffer from this same
mistake (mostly MIPS implementations) but that is not really relevant
here. Most of the time this comes from not understanding software
models and/or not properly taking into account a complex (too complex)
reset model.

>
> It's times like this that I wonder what kind of drugs the hardware SoC
> people are on, but I'm well aware that people contributing SMP bringup
> solutions are also dumb idiots who copy the Versatile scheme with very
> little thought... (as you can see, I'm not mincing my words here - if
> people want to be lazy in this regard despite this having been brought
> up multiple times, and the lead developers having said that the versatile
> pen_release stuff should not be used, they earn themselves the right to
> be called dumb idiots.  Simple solution to avoid that title: don't be a
> dumb idiot by copy the Versatile SMP bring up code!  It's not a sane
> model for any SoC sane SoC to follow.)
>
> Is this clear enough?

The actual implementation of the SMP code in the next patches do not
use a pen holding/release mechanism anymore as it used in the previous
iterations of these same patches, so I would say, lesson learned. My
question was whether the binding was documenting the hardware
implementation (which it should) or the software implementation (which
it should not).
-- 
Florian

Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Jon Mason]

On Sat, Nov 07, 2015 at 12:41:21AM +0100, Hauke Mehrtens wrote:
> On 11/07/2015 12:27 AM, Hauke Mehrtens wrote:
> > On 11/06/2015 11:54 PM, Jon Mason wrote:
> >> On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
> >>> On 11/06/2015 10:11 PM, Kapil Hali wrote:
> >>>> From: Jon Mason <jonmason@broadcom.com>
> >>>>
> >>>> Add SMP support for Broadcom's 4708 SoCs.
> >>>>
> >>>> Signed-off-by: Jon Mason <jonmason@broadcom.com>
> >>>> Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
> >>>> Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
> >>>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> >>>
> >>> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
> >>>
> >>>> ---
> >>>>  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
> >>>>  arch/arm/mach-bcm/Kconfig      | 1 +
> >>>>  arch/arm/mach-bcm/Makefile     | 3 +++
> >>>>  3 files changed, 6 insertions(+)
> >>>>
> >>>
> >>> ...
> >>>
> >>>> --- a/arch/arm/mach-bcm/Kconfig
> >>>> +++ b/arch/arm/mach-bcm/Kconfig
> >>>> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
> >>>>  config ARCH_BCM_5301X
> >>>>  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
> >>>>  	select ARCH_BCM_IPROC
> >>>
> >>> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?
> >>
> >> I'm not certain the CPU version, and without that it is difficult to
> >> know what errata's are present in the underlying hardware.  My guess
> >> is that all present in NSP are present in NS (for UP and SMP).  This
> >> would put it as:
> >>         select ARM_ERRATA_754322
> >>         select ARM_ERRATA_775420
> >>         select ARM_ERRATA_764369 if SMP
> >>
> >> Would you like me to have them added?
> >>
> > 
> > I will send a separate patch adding all the workarounds for erratas in
> > the CPU core and the cache controller.
> > 
> > Hauke
> > 
> > 
> Hi,
> 
> BCM4708 uses a Cortex-A9 rev r3p0 and a L2C-310 rev r3p2. For this CPU
> and cache controller the same workaround are needed as for NSP, if you
> will resend this patch, please add all of them.

Agreed.  Kapil or I will mod the patch.

Thanks,
Jon

> 
> Hauke

Re: [PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Jon Mason]

On Sat, Nov 07, 2015 at 12:41:21AM +0100, Hauke Mehrtens wrote:
> On 11/07/2015 12:27 AM, Hauke Mehrtens wrote:
> > On 11/06/2015 11:54 PM, Jon Mason wrote:
> >> On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
> >>> On 11/06/2015 10:11 PM, Kapil Hali wrote:
> >>>> From: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> >>>>
> >>>> Add SMP support for Broadcom's 4708 SoCs.
> >>>>
> >>>> Signed-off-by: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> >>>> Acked-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> >>>> Tested-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> >>>> Signed-off-by: Kapil Hali <kapilh-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
> >>>
> >>> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
> >>>
> >>>> ---
> >>>>  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
> >>>>  arch/arm/mach-bcm/Kconfig      | 1 +
> >>>>  arch/arm/mach-bcm/Makefile     | 3 +++
> >>>>  3 files changed, 6 insertions(+)
> >>>>
> >>>
> >>> ...
> >>>
> >>>> --- a/arch/arm/mach-bcm/Kconfig
> >>>> +++ b/arch/arm/mach-bcm/Kconfig
> >>>> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
> >>>>  config ARCH_BCM_5301X
> >>>>  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
> >>>>  	select ARCH_BCM_IPROC
> >>>
> >>> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?
> >>
> >> I'm not certain the CPU version, and without that it is difficult to
> >> know what errata's are present in the underlying hardware.  My guess
> >> is that all present in NSP are present in NS (for UP and SMP).  This
> >> would put it as:
> >>         select ARM_ERRATA_754322
> >>         select ARM_ERRATA_775420
> >>         select ARM_ERRATA_764369 if SMP
> >>
> >> Would you like me to have them added?
> >>
> > 
> > I will send a separate patch adding all the workarounds for erratas in
> > the CPU core and the cache controller.
> > 
> > Hauke
> > 
> > 
> Hi,
> 
> BCM4708 uses a Cortex-A9 rev r3p0 and a L2C-310 rev r3p2. For this CPU
> and cache controller the same workaround are needed as for NSP, if you
> will resend this patch, please add all of them.

Agreed.  Kapil or I will mod the patch.

Thanks,
Jon

> 
> Hauke
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[PATCH v3 4/4] ARM: BCM: Add SMP support for Broadcom 4708

[Jon Mason]

On Sat, Nov 07, 2015 at 12:41:21AM +0100, Hauke Mehrtens wrote:
> On 11/07/2015 12:27 AM, Hauke Mehrtens wrote:
> > On 11/06/2015 11:54 PM, Jon Mason wrote:
> >> On Fri, Nov 06, 2015 at 10:42:41PM +0100, Hauke Mehrtens wrote:
> >>> On 11/06/2015 10:11 PM, Kapil Hali wrote:
> >>>> From: Jon Mason <jonmason@broadcom.com>
> >>>>
> >>>> Add SMP support for Broadcom's 4708 SoCs.
> >>>>
> >>>> Signed-off-by: Jon Mason <jonmason@broadcom.com>
> >>>> Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
> >>>> Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
> >>>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> >>>
> >>> I tested this on a Netgear R6250 V1 (BCM4708) and SMP worked.
> >>>
> >>>> ---
> >>>>  arch/arm/boot/dts/bcm4708.dtsi | 2 ++
> >>>>  arch/arm/mach-bcm/Kconfig      | 1 +
> >>>>  arch/arm/mach-bcm/Makefile     | 3 +++
> >>>>  3 files changed, 6 insertions(+)
> >>>>
> >>>
> >>> ...
> >>>
> >>>> --- a/arch/arm/mach-bcm/Kconfig
> >>>> +++ b/arch/arm/mach-bcm/Kconfig
> >>>> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
> >>>>  config ARCH_BCM_5301X
> >>>>  	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
> >>>>  	select ARCH_BCM_IPROC
> >>>
> >>> You activated ARM_ERRATA_764369 for NSP is this not needed for NS?
> >>
> >> I'm not certain the CPU version, and without that it is difficult to
> >> know what errata's are present in the underlying hardware.  My guess
> >> is that all present in NSP are present in NS (for UP and SMP).  This
> >> would put it as:
> >>         select ARM_ERRATA_754322
> >>         select ARM_ERRATA_775420
> >>         select ARM_ERRATA_764369 if SMP
> >>
> >> Would you like me to have them added?
> >>
> > 
> > I will send a separate patch adding all the workarounds for erratas in
> > the CPU core and the cache controller.
> > 
> > Hauke
> > 
> > 
> Hi,
> 
> BCM4708 uses a Cortex-A9 rev r3p0 and a L2C-310 rev r3p2. For this CPU
> and cache controller the same workaround are needed as for NSP, if you
> will resend this patch, please add all of them.

Agreed.  Kapil or I will mod the patch.

Thanks,
Jon

> 
> Hauke

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Hi Russel,

On 11/8/2015 11:01 PM, Russell King - ARM Linux wrote:
> On Sat, Nov 07, 2015 at 01:40:23PM -0800, Florian Fainelli wrote:
>> Le 06/11/2015 13:11, Kapil Hali a écrit :
>>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>>> documentation file and create a new binding documentation for
>>> Northstar Plus CPU.
>>>
>>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>>> ---
>>>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>>>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>>>  2 files changed, 37 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>> new file mode 100644
>>> index 0000000..8506da7
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>> @@ -0,0 +1,36 @@
>>> +Broadcom Northstar Plus SoC CPU Enable Method
>>> +---------------------------------------------
>>> +This binding defines the enable method used for starting secondary
>>> +CPUs in the following Broadcom SoCs:
>>> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>>> +
>>> +The enable method is specified by defining the following required
>>> +properties in the "cpus" device tree node:
>>> +  - enable-method = "brcm,bcm-nsp-smp";
>>> +  - secondary-boot-reg = <...>;
>>> +
>>> +The secondary-boot-reg property is a u32 value that specifies the
>>> +physical address of the register used to request the ROM holding pen
>>> +code release a secondary CPU.
>>
>> Is it really how the ROM code is implemented, as a pen holding/release
>> mechanism (which sounds like how this was implemented previously in the
>> kernel actually) or should this be described in a more generic way as
>> the physical address of the register where the secondary CPUs reset
>> vector address must be written to? Or something along these lines.
> 
> Why do people insist on using holding pens to bring their secondary CPUs
> into existence?  I hope the hardware people aren't being dumb and have no
> way to hold in reset or power down their secondary CPUs, either of which
> is a vital feature for things like kexec and the like.  If they do have
> a way to hold secondary CPUs in reset or powered down, why aren't they
> using that at boot instead of implementing the stupid Versatile scheme,
> which exists because Versatile _can't_ hold its CPUs in reset or power
> them down...
> 
> It's times like this that I wonder what kind of drugs the hardware SoC
> people are on, but I'm well aware that people contributing SMP bringup
> solutions are also dumb idiots who copy the Versatile scheme with very
> little thought... (as you can see, I'm not mincing my words here - if
> people want to be lazy in this regard despite this having been brought
> up multiple times, and the lead developers having said that the versatile
> pen_release stuff should not be used, they earn themselves the right to
> be called dumb idiots.  Simple solution to avoid that title: don't be a
> dumb idiot by copy the Versatile SMP bring up code!  It's not a sane
> model for any SoC sane SoC to follow.)
> 
> Is this clear enough?
> 
It was clear the very first time itself as pointed out by you and the 
lead developers and hence the change was readily sent in the very next
patch set. I didn't change a comment in this patch, which is misleading 
about the SMP enable-method used in the patch set, it is my mistake and   
I apologies for the same. I will change it and send the next patch set.

Also, before sending out the patch set, I had asked for a clarification 
about the method: https://lkml.org/lkml/2015/11/6/234
For my understanding, I am repeating my query- In case of simple method of 
waking up secondary core, smp_boot_secondary() will always return success 
indicating secondary core successfully started. I understand that in 
__cpu_up(), primary core waits for completion till secondary core comes 
online or time outs. However, is it appropriate to return successful start 
of secondary core without knowing if it really did?

Thanks,
Kapil Hali

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Hi Russel,

On 11/8/2015 11:01 PM, Russell King - ARM Linux wrote:
> On Sat, Nov 07, 2015 at 01:40:23PM -0800, Florian Fainelli wrote:
>> Le 06/11/2015 13:11, Kapil Hali a écrit :
>>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>>> documentation file and create a new binding documentation for
>>> Northstar Plus CPU.
>>>
>>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>>> ---
>>>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>>>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>>>  2 files changed, 37 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>> new file mode 100644
>>> index 0000000..8506da7
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>> @@ -0,0 +1,36 @@
>>> +Broadcom Northstar Plus SoC CPU Enable Method
>>> +---------------------------------------------
>>> +This binding defines the enable method used for starting secondary
>>> +CPUs in the following Broadcom SoCs:
>>> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>>> +
>>> +The enable method is specified by defining the following required
>>> +properties in the "cpus" device tree node:
>>> +  - enable-method = "brcm,bcm-nsp-smp";
>>> +  - secondary-boot-reg = <...>;
>>> +
>>> +The secondary-boot-reg property is a u32 value that specifies the
>>> +physical address of the register used to request the ROM holding pen
>>> +code release a secondary CPU.
>>
>> Is it really how the ROM code is implemented, as a pen holding/release
>> mechanism (which sounds like how this was implemented previously in the
>> kernel actually) or should this be described in a more generic way as
>> the physical address of the register where the secondary CPUs reset
>> vector address must be written to? Or something along these lines.
> 
> Why do people insist on using holding pens to bring their secondary CPUs
> into existence?  I hope the hardware people aren't being dumb and have no
> way to hold in reset or power down their secondary CPUs, either of which
> is a vital feature for things like kexec and the like.  If they do have
> a way to hold secondary CPUs in reset or powered down, why aren't they
> using that at boot instead of implementing the stupid Versatile scheme,
> which exists because Versatile _can't_ hold its CPUs in reset or power
> them down...
> 
> It's times like this that I wonder what kind of drugs the hardware SoC
> people are on, but I'm well aware that people contributing SMP bringup
> solutions are also dumb idiots who copy the Versatile scheme with very
> little thought... (as you can see, I'm not mincing my words here - if
> people want to be lazy in this regard despite this having been brought
> up multiple times, and the lead developers having said that the versatile
> pen_release stuff should not be used, they earn themselves the right to
> be called dumb idiots.  Simple solution to avoid that title: don't be a
> dumb idiot by copy the Versatile SMP bring up code!  It's not a sane
> model for any SoC sane SoC to follow.)
> 
> Is this clear enough?
> 
It was clear the very first time itself as pointed out by you and the 
lead developers and hence the change was readily sent in the very next
patch set. I didn't change a comment in this patch, which is misleading 
about the SMP enable-method used in the patch set, it is my mistake and   
I apologies for the same. I will change it and send the next patch set.

Also, before sending out the patch set, I had asked for a clarification 
about the method: https://lkml.org/lkml/2015/11/6/234
For my understanding, I am repeating my query- In case of simple method of 
waking up secondary core, smp_boot_secondary() will always return success 
indicating secondary core successfully started. I understand that in 
__cpu_up(), primary core waits for completion till secondary core comes 
online or time outs. However, is it appropriate to return successful start 
of secondary core without knowing if it really did?

Thanks,
Kapil Hali

[PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Hi Russel,

On 11/8/2015 11:01 PM, Russell King - ARM Linux wrote:
> On Sat, Nov 07, 2015 at 01:40:23PM -0800, Florian Fainelli wrote:
>> Le 06/11/2015 13:11, Kapil Hali a ?crit :
>>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>>> documentation file and create a new binding documentation for
>>> Northstar Plus CPU.
>>>
>>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>>> ---
>>>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>>>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>>>  2 files changed, 37 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>> new file mode 100644
>>> index 0000000..8506da7
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>> @@ -0,0 +1,36 @@
>>> +Broadcom Northstar Plus SoC CPU Enable Method
>>> +---------------------------------------------
>>> +This binding defines the enable method used for starting secondary
>>> +CPUs in the following Broadcom SoCs:
>>> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>>> +
>>> +The enable method is specified by defining the following required
>>> +properties in the "cpus" device tree node:
>>> +  - enable-method = "brcm,bcm-nsp-smp";
>>> +  - secondary-boot-reg = <...>;
>>> +
>>> +The secondary-boot-reg property is a u32 value that specifies the
>>> +physical address of the register used to request the ROM holding pen
>>> +code release a secondary CPU.
>>
>> Is it really how the ROM code is implemented, as a pen holding/release
>> mechanism (which sounds like how this was implemented previously in the
>> kernel actually) or should this be described in a more generic way as
>> the physical address of the register where the secondary CPUs reset
>> vector address must be written to? Or something along these lines.
> 
> Why do people insist on using holding pens to bring their secondary CPUs
> into existence?  I hope the hardware people aren't being dumb and have no
> way to hold in reset or power down their secondary CPUs, either of which
> is a vital feature for things like kexec and the like.  If they do have
> a way to hold secondary CPUs in reset or powered down, why aren't they
> using that at boot instead of implementing the stupid Versatile scheme,
> which exists because Versatile _can't_ hold its CPUs in reset or power
> them down...
> 
> It's times like this that I wonder what kind of drugs the hardware SoC
> people are on, but I'm well aware that people contributing SMP bringup
> solutions are also dumb idiots who copy the Versatile scheme with very
> little thought... (as you can see, I'm not mincing my words here - if
> people want to be lazy in this regard despite this having been brought
> up multiple times, and the lead developers having said that the versatile
> pen_release stuff should not be used, they earn themselves the right to
> be called dumb idiots.  Simple solution to avoid that title: don't be a
> dumb idiot by copy the Versatile SMP bring up code!  It's not a sane
> model for any SoC sane SoC to follow.)
> 
> Is this clear enough?
> 
It was clear the very first time itself as pointed out by you and the 
lead developers and hence the change was readily sent in the very next
patch set. I didn't change a comment in this patch, which is misleading 
about the SMP enable-method used in the patch set, it is my mistake and   
I apologies for the same. I will change it and send the next patch set.

Also, before sending out the patch set, I had asked for a clarification 
about the method: https://lkml.org/lkml/2015/11/6/234
For my understanding, I am repeating my query- In case of simple method of 
waking up secondary core, smp_boot_secondary() will always return success 
indicating secondary core successfully started. I understand that in 
__cpu_up(), primary core waits for completion till secondary core comes 
online or time outs. However, is it appropriate to return successful start 
of secondary core without knowing if it really did?

Thanks,
Kapil Hali

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Hi Florian,

On 11/8/2015 3:10 AM, Florian Fainelli wrote:
> Le 06/11/2015 13:11, Kapil Hali a écrit :
>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>> documentation file and create a new binding documentation for
>> Northstar Plus CPU.
>>
>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>> ---
>>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>>  2 files changed, 37 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> new file mode 100644
>> index 0000000..8506da7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> @@ -0,0 +1,36 @@
>> +Broadcom Northstar Plus SoC CPU Enable Method
>> +---------------------------------------------
>> +This binding defines the enable method used for starting secondary
>> +CPUs in the following Broadcom SoCs:
>> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>> +
>> +The enable method is specified by defining the following required
>> +properties in the "cpus" device tree node:
>> +  - enable-method = "brcm,bcm-nsp-smp";
>> +  - secondary-boot-reg = <...>;
>> +
>> +The secondary-boot-reg property is a u32 value that specifies the
>> +physical address of the register used to request the ROM holding pen
>> +code release a secondary CPU.
> 
> Is it really how the ROM code is implemented, as a pen holding/release
> mechanism (which sounds like how this was implemented previously in the
> kernel actually) or should this be described in a more generic way as
> the physical address of the register where the secondary CPUs reset
> vector address must be written to? Or something along these lines.
> 
I overlooked this patch and didn't change the description. It is a physical
address of a register which holds the address of the secondary core's entry 
point.

>> +
>> +Example:
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		enable-method = "brcm,bcm-nsp-smp";
> 
> Just a nit, but if NSP and NS are sharing the same mechanism, would not
> a more "NS-centric" property be more appropriate because NS came before NSP?
> 
>> +		secondary-boot-reg = <0xffff042c>;
>> +
>> +		cpu0: cpu@0 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a9";
>> +			next-level-cache = <&L2>;
>> +			reg = <0>;
>> +		};
>> +
>> +		cpu1: cpu@1 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a9";
>> +			next-level-cache = <&L2>;
>> +			reg = <1>;
>> +		};
>> +	};
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 91e6e5c..6abe3f3 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>>  			    "allwinner,sun8i-a23"
>>  			    "arm,psci"
>>  			    "brcm,brahma-b15"
>> +			    "brcm,bcm-nsp-smp"
>>  			    "marvell,armada-375-smp"
>>  			    "marvell,armada-380-smp"
>>  			    "marvell,armada-390-smp"
>>
> 
> 

Thanks,
Kapil Hali

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Hi Florian,

On 11/8/2015 3:10 AM, Florian Fainelli wrote:
> Le 06/11/2015 13:11, Kapil Hali a écrit :
>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>> documentation file and create a new binding documentation for
>> Northstar Plus CPU.
>>
>> Signed-off-by: Kapil Hali <kapilh-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>> ---
>>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>>  2 files changed, 37 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> new file mode 100644
>> index 0000000..8506da7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> @@ -0,0 +1,36 @@
>> +Broadcom Northstar Plus SoC CPU Enable Method
>> +---------------------------------------------
>> +This binding defines the enable method used for starting secondary
>> +CPUs in the following Broadcom SoCs:
>> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>> +
>> +The enable method is specified by defining the following required
>> +properties in the "cpus" device tree node:
>> +  - enable-method = "brcm,bcm-nsp-smp";
>> +  - secondary-boot-reg = <...>;
>> +
>> +The secondary-boot-reg property is a u32 value that specifies the
>> +physical address of the register used to request the ROM holding pen
>> +code release a secondary CPU.
> 
> Is it really how the ROM code is implemented, as a pen holding/release
> mechanism (which sounds like how this was implemented previously in the
> kernel actually) or should this be described in a more generic way as
> the physical address of the register where the secondary CPUs reset
> vector address must be written to? Or something along these lines.
> 
I overlooked this patch and didn't change the description. It is a physical
address of a register which holds the address of the secondary core's entry 
point.

>> +
>> +Example:
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		enable-method = "brcm,bcm-nsp-smp";
> 
> Just a nit, but if NSP and NS are sharing the same mechanism, would not
> a more "NS-centric" property be more appropriate because NS came before NSP?
> 
>> +		secondary-boot-reg = <0xffff042c>;
>> +
>> +		cpu0: cpu@0 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a9";
>> +			next-level-cache = <&L2>;
>> +			reg = <0>;
>> +		};
>> +
>> +		cpu1: cpu@1 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a9";
>> +			next-level-cache = <&L2>;
>> +			reg = <1>;
>> +		};
>> +	};
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 91e6e5c..6abe3f3 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>>  			    "allwinner,sun8i-a23"
>>  			    "arm,psci"
>>  			    "brcm,brahma-b15"
>> +			    "brcm,bcm-nsp-smp"
>>  			    "marvell,armada-375-smp"
>>  			    "marvell,armada-380-smp"
>>  			    "marvell,armada-390-smp"
>>
> 
> 

Thanks,
Kapil Hali

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[PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Hi Florian,

On 11/8/2015 3:10 AM, Florian Fainelli wrote:
> Le 06/11/2015 13:11, Kapil Hali a ?crit :
>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>> documentation file and create a new binding documentation for
>> Northstar Plus CPU.
>>
>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>> ---
>>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>>  2 files changed, 37 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> new file mode 100644
>> index 0000000..8506da7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> @@ -0,0 +1,36 @@
>> +Broadcom Northstar Plus SoC CPU Enable Method
>> +---------------------------------------------
>> +This binding defines the enable method used for starting secondary
>> +CPUs in the following Broadcom SoCs:
>> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>> +
>> +The enable method is specified by defining the following required
>> +properties in the "cpus" device tree node:
>> +  - enable-method = "brcm,bcm-nsp-smp";
>> +  - secondary-boot-reg = <...>;
>> +
>> +The secondary-boot-reg property is a u32 value that specifies the
>> +physical address of the register used to request the ROM holding pen
>> +code release a secondary CPU.
> 
> Is it really how the ROM code is implemented, as a pen holding/release
> mechanism (which sounds like how this was implemented previously in the
> kernel actually) or should this be described in a more generic way as
> the physical address of the register where the secondary CPUs reset
> vector address must be written to? Or something along these lines.
> 
I overlooked this patch and didn't change the description. It is a physical
address of a register which holds the address of the secondary core's entry 
point.

>> +
>> +Example:
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		enable-method = "brcm,bcm-nsp-smp";
> 
> Just a nit, but if NSP and NS are sharing the same mechanism, would not
> a more "NS-centric" property be more appropriate because NS came before NSP?
> 
>> +		secondary-boot-reg = <0xffff042c>;
>> +
>> +		cpu0: cpu at 0 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a9";
>> +			next-level-cache = <&L2>;
>> +			reg = <0>;
>> +		};
>> +
>> +		cpu1: cpu at 1 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a9";
>> +			next-level-cache = <&L2>;
>> +			reg = <1>;
>> +		};
>> +	};
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 91e6e5c..6abe3f3 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>>  			    "allwinner,sun8i-a23"
>>  			    "arm,psci"
>>  			    "brcm,brahma-b15"
>> +			    "brcm,bcm-nsp-smp"
>>  			    "marvell,armada-375-smp"
>>  			    "marvell,armada-380-smp"
>>  			    "marvell,armada-390-smp"
>>
> 
> 

Thanks,
Kapil Hali

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Russell King - ARM Linux]

On Tue, Nov 10, 2015 at 09:33:12PM +0530, Kapil Hali wrote:
> Hi Russel,

Wrong.  Look at my name as sent in the From: and as quoted in the very
next line.  As far as I'm concerned (and I don't care what other people
say) it's disrespectful to spell people's names incorrectly.

> It was clear the very first time itself as pointed out by you and the 
> lead developers and hence the change was readily sent in the very next
> patch set. I didn't change a comment in this patch, which is misleading 
> about the SMP enable-method used in the patch set, it is my mistake and   
> I apologies for the same. I will change it and send the next patch set.

Thanks.

> Also, before sending out the patch set, I had asked for a clarification 
> about the method: https://lkml.org/lkml/2015/11/6/234

Sorry, I don't read every single email irrespective of how it's marked.
There's way too much email, and way too much mail with improperly
classified recipient lists to be able to usefully sort this mail.
(If you do the math, the email rate during a 12 hour working day from
just linux-arm-kernel is one email every 2.5 minutes, assuming 300 emails
a day.  It takes way longer than that to compose a proper reply to an
email - I've spent around 15 minutes on this one alone.  Hence, if I'm
busy, I more or less totally ignore email now, and rarely bother to
"catch up" with missed emails.)

> For my understanding, I am repeating my query- In case of simple method of 
> waking up secondary core, smp_boot_secondary() will always return success 
> indicating secondary core successfully started. I understand that in 
> __cpu_up(), primary core waits for completion till secondary core comes 
> online or time outs. However, is it appropriate to return successful start 
> of secondary core without knowing if it really did?

Yes, because all that your smp_boot_secondary() should be doing is
trying to start the core.  If you encounter an error trying to do so,
that's what the error return is for.

If you just set a bit somewhere to tell the hardware to release the
secondary core's reset, then if you set the bit and return success,
that's prefectly acceptable.  The core ARM SMP code will then wait
up to one second for the secondary core to become known to the kernel
before declaring that the CPU failed to come online.

If it fails to appear, we assume that it will never appear - and
actually at that point the system is in an unknown state: if the
secondary CPU crashed during its boot, it could start scribbling
into memory or touching devices in an unpredictable way: the only
sane answer is to reboot the whole system to ensure that it's back
to a known good state.  Hence why we don't provide any cleanup at
the point of a failed secondary CPU (I've been debating about
tainting the kernel at that point, so we know when things have
gone bad.)

Hope this helps.

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

[PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Russell King - ARM Linux]

On Tue, Nov 10, 2015 at 09:33:12PM +0530, Kapil Hali wrote:
> Hi Russel,

Wrong.  Look at my name as sent in the From: and as quoted in the very
next line.  As far as I'm concerned (and I don't care what other people
say) it's disrespectful to spell people's names incorrectly.

> It was clear the very first time itself as pointed out by you and the 
> lead developers and hence the change was readily sent in the very next
> patch set. I didn't change a comment in this patch, which is misleading 
> about the SMP enable-method used in the patch set, it is my mistake and   
> I apologies for the same. I will change it and send the next patch set.

Thanks.

> Also, before sending out the patch set, I had asked for a clarification 
> about the method: https://lkml.org/lkml/2015/11/6/234

Sorry, I don't read every single email irrespective of how it's marked.
There's way too much email, and way too much mail with improperly
classified recipient lists to be able to usefully sort this mail.
(If you do the math, the email rate during a 12 hour working day from
just linux-arm-kernel is one email every 2.5 minutes, assuming 300 emails
a day.  It takes way longer than that to compose a proper reply to an
email - I've spent around 15 minutes on this one alone.  Hence, if I'm
busy, I more or less totally ignore email now, and rarely bother to
"catch up" with missed emails.)

> For my understanding, I am repeating my query- In case of simple method of 
> waking up secondary core, smp_boot_secondary() will always return success 
> indicating secondary core successfully started. I understand that in 
> __cpu_up(), primary core waits for completion till secondary core comes 
> online or time outs. However, is it appropriate to return successful start 
> of secondary core without knowing if it really did?

Yes, because all that your smp_boot_secondary() should be doing is
trying to start the core.  If you encounter an error trying to do so,
that's what the error return is for.

If you just set a bit somewhere to tell the hardware to release the
secondary core's reset, then if you set the bit and return success,
that's prefectly acceptable.  The core ARM SMP code will then wait
up to one second for the secondary core to become known to the kernel
before declaring that the CPU failed to come online.

If it fails to appear, we assume that it will never appear - and
actually at that point the system is in an unknown state: if the
secondary CPU crashed during its boot, it could start scribbling
into memory or touching devices in an unpredictable way: the only
sane answer is to reboot the whole system to ensure that it's back
to a known good state.  Hence why we don't provide any cleanup at
the point of a failed secondary CPU (I've been debating about
tainting the kernel at that point, so we know when things have
gone bad.)

Hope this helps.

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Hi Rob,

On 11/7/2015 11:33 PM, Rob Herring wrote:
> On Fri, Nov 6, 2015 at 3:11 PM, Kapil Hali <kapilh@broadcom.com> wrote:
>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>> documentation file and create a new binding documentation for
>> Northstar Plus CPU.
>>
>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>> ---
>>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>>  2 files changed, 37 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> new file mode 100644
>> index 0000000..8506da7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> @@ -0,0 +1,36 @@
>> +Broadcom Northstar Plus SoC CPU Enable Method
>> +---------------------------------------------
>> +This binding defines the enable method used for starting secondary
>> +CPUs in the following Broadcom SoCs:
>> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>> +
>> +The enable method is specified by defining the following required
>> +properties in the "cpus" device tree node:
>> +  - enable-method = "brcm,bcm-nsp-smp";
> 
> As I said already, this is supposed to be per cpu.
> 
>> +  - secondary-boot-reg = <...>;
> 
> And then you might as well move this too.
> 
NS/NSP family of SoCs have maximum of two cores. There would not be a
need for another boot-reg in this family of SoCs. However, I agree, it 
should go to individual CPU nodes. I will do the change in the next patch.
>> +
>> +The secondary-boot-reg property is a u32 value that specifies the
>> +physical address of the register used to request the ROM holding pen
>> +code release a secondary CPU.
>> +
>> +Example:
>> +       cpus {
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +               enable-method = "brcm,bcm-nsp-smp";
>> +               secondary-boot-reg = <0xffff042c>;
>> +
>> +               cpu0: cpu@0 {
>> +                       device_type = "cpu";
>> +                       compatible = "arm,cortex-a9";
>> +                       next-level-cache = <&L2>;
>> +                       reg = <0>;
>> +               };
>> +
>> +               cpu1: cpu@1 {
>> +                       device_type = "cpu";
>> +                       compatible = "arm,cortex-a9";
>> +                       next-level-cache = <&L2>;
>> +                       reg = <1>;
>> +               };
>> +       };
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 91e6e5c..6abe3f3 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>>                             "allwinner,sun8i-a23"
>>                             "arm,psci"
>>                             "brcm,brahma-b15"
>> +                           "brcm,bcm-nsp-smp"
>>                             "marvell,armada-375-smp"
>>                             "marvell,armada-380-smp"
>>                             "marvell,armada-390-smp"
>> --
>> 2.1.0
>>
Thanks,
Kapil Hali

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Hi Rob,

On 11/7/2015 11:33 PM, Rob Herring wrote:
> On Fri, Nov 6, 2015 at 3:11 PM, Kapil Hali <kapilh-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:
>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>> documentation file and create a new binding documentation for
>> Northstar Plus CPU.
>>
>> Signed-off-by: Kapil Hali <kapilh-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
>> ---
>>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>>  2 files changed, 37 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> new file mode 100644
>> index 0000000..8506da7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> @@ -0,0 +1,36 @@
>> +Broadcom Northstar Plus SoC CPU Enable Method
>> +---------------------------------------------
>> +This binding defines the enable method used for starting secondary
>> +CPUs in the following Broadcom SoCs:
>> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>> +
>> +The enable method is specified by defining the following required
>> +properties in the "cpus" device tree node:
>> +  - enable-method = "brcm,bcm-nsp-smp";
> 
> As I said already, this is supposed to be per cpu.
> 
>> +  - secondary-boot-reg = <...>;
> 
> And then you might as well move this too.
> 
NS/NSP family of SoCs have maximum of two cores. There would not be a
need for another boot-reg in this family of SoCs. However, I agree, it 
should go to individual CPU nodes. I will do the change in the next patch.
>> +
>> +The secondary-boot-reg property is a u32 value that specifies the
>> +physical address of the register used to request the ROM holding pen
>> +code release a secondary CPU.
>> +
>> +Example:
>> +       cpus {
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +               enable-method = "brcm,bcm-nsp-smp";
>> +               secondary-boot-reg = <0xffff042c>;
>> +
>> +               cpu0: cpu@0 {
>> +                       device_type = "cpu";
>> +                       compatible = "arm,cortex-a9";
>> +                       next-level-cache = <&L2>;
>> +                       reg = <0>;
>> +               };
>> +
>> +               cpu1: cpu@1 {
>> +                       device_type = "cpu";
>> +                       compatible = "arm,cortex-a9";
>> +                       next-level-cache = <&L2>;
>> +                       reg = <1>;
>> +               };
>> +       };
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 91e6e5c..6abe3f3 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>>                             "allwinner,sun8i-a23"
>>                             "arm,psci"
>>                             "brcm,brahma-b15"
>> +                           "brcm,bcm-nsp-smp"
>>                             "marvell,armada-375-smp"
>>                             "marvell,armada-380-smp"
>>                             "marvell,armada-390-smp"
>> --
>> 2.1.0
>>
Thanks,
Kapil Hali
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[PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Hi Rob,

On 11/7/2015 11:33 PM, Rob Herring wrote:
> On Fri, Nov 6, 2015 at 3:11 PM, Kapil Hali <kapilh@broadcom.com> wrote:
>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>> documentation file and create a new binding documentation for
>> Northstar Plus CPU.
>>
>> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
>> ---
>>  .../bindings/arm/bcm/brcm,nsp-cpu-method.txt       | 36 ++++++++++++++++++++++
>>  Documentation/devicetree/bindings/arm/cpus.txt     |  1 +
>>  2 files changed, 37 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> new file mode 100644
>> index 0000000..8506da7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> @@ -0,0 +1,36 @@
>> +Broadcom Northstar Plus SoC CPU Enable Method
>> +---------------------------------------------
>> +This binding defines the enable method used for starting secondary
>> +CPUs in the following Broadcom SoCs:
>> +  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>> +
>> +The enable method is specified by defining the following required
>> +properties in the "cpus" device tree node:
>> +  - enable-method = "brcm,bcm-nsp-smp";
> 
> As I said already, this is supposed to be per cpu.
> 
>> +  - secondary-boot-reg = <...>;
> 
> And then you might as well move this too.
> 
NS/NSP family of SoCs have maximum of two cores. There would not be a
need for another boot-reg in this family of SoCs. However, I agree, it 
should go to individual CPU nodes. I will do the change in the next patch.
>> +
>> +The secondary-boot-reg property is a u32 value that specifies the
>> +physical address of the register used to request the ROM holding pen
>> +code release a secondary CPU.
>> +
>> +Example:
>> +       cpus {
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +               enable-method = "brcm,bcm-nsp-smp";
>> +               secondary-boot-reg = <0xffff042c>;
>> +
>> +               cpu0: cpu at 0 {
>> +                       device_type = "cpu";
>> +                       compatible = "arm,cortex-a9";
>> +                       next-level-cache = <&L2>;
>> +                       reg = <0>;
>> +               };
>> +
>> +               cpu1: cpu at 1 {
>> +                       device_type = "cpu";
>> +                       compatible = "arm,cortex-a9";
>> +                       next-level-cache = <&L2>;
>> +                       reg = <1>;
>> +               };
>> +       };
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 91e6e5c..6abe3f3 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
>>                             "allwinner,sun8i-a23"
>>                             "arm,psci"
>>                             "brcm,brahma-b15"
>> +                           "brcm,bcm-nsp-smp"
>>                             "marvell,armada-375-smp"
>>                             "marvell,armada-380-smp"
>>                             "marvell,armada-390-smp"
>> --
>> 2.1.0
>>
Thanks,
Kapil Hali

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Hi Russell,

On 11/10/2015 9:55 PM, Russell King - ARM Linux wrote:
> On Tue, Nov 10, 2015 at 09:33:12PM +0530, Kapil Hali wrote:
>> Hi Russel,
> 
> Wrong.  Look at my name as sent in the From: and as quoted in the very
> next line.  As far as I'm concerned (and I don't care what other people
> say) it's disrespectful to spell people's names incorrectly.
> 
I am sincerely apologetic about it. It was a deviation that will not 
repeat again. 
>> It was clear the very first time itself as pointed out by you and the 
>> lead developers and hence the change was readily sent in the very next
>> patch set. I didn't change a comment in this patch, which is misleading 
>> about the SMP enable-method used in the patch set, it is my mistake and   
>> I apologies for the same. I will change it and send the next patch set.
> 
> Thanks.
> 
>> Also, before sending out the patch set, I had asked for a clarification 
>> about the method: https://lkml.org/lkml/2015/11/6/234
> 
> Sorry, I don't read every single email irrespective of how it's marked.
> There's way too much email, and way too much mail with improperly
> classified recipient lists to be able to usefully sort this mail.
> (If you do the math, the email rate during a 12 hour working day from
> just linux-arm-kernel is one email every 2.5 minutes, assuming 300 emails
> a day.  It takes way longer than that to compose a proper reply to an
> email - I've spent around 15 minutes on this one alone.  Hence, if I'm
> busy, I more or less totally ignore email now, and rarely bother to
> "catch up" with missed emails.)
> 
>> For my understanding, I am repeating my query- In case of simple method of 
>> waking up secondary core, smp_boot_secondary() will always return success 
>> indicating secondary core successfully started. I understand that in 
>> __cpu_up(), primary core waits for completion till secondary core comes 
>> online or time outs. However, is it appropriate to return successful start 
>> of secondary core without knowing if it really did?
> 
> Yes, because all that your smp_boot_secondary() should be doing is
> trying to start the core.  If you encounter an error trying to do so,
> that's what the error return is for.
> 
> If you just set a bit somewhere to tell the hardware to release the
> secondary core's reset, then if you set the bit and return success,
> that's prefectly acceptable.  The core ARM SMP code will then wait
> up to one second for the secondary core to become known to the kernel
> before declaring that the CPU failed to come online.
> 
> If it fails to appear, we assume that it will never appear - and
> actually at that point the system is in an unknown state: if the
> secondary CPU crashed during its boot, it could start scribbling
> into memory or touching devices in an unpredictable way: the only
> sane answer is to reboot the whole system to ensure that it's back
> to a known good state.  Hence why we don't provide any cleanup at
> the point of a failed secondary CPU (I've been debating about
> tainting the kernel at that point, so we know when things have
> gone bad.)
> 
> Hope this helps.
> 
Surely it has helped and many thanks for your detailed explanation.

Thanks,
Kapil Hali

Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Hi Russell,

On 11/10/2015 9:55 PM, Russell King - ARM Linux wrote:
> On Tue, Nov 10, 2015 at 09:33:12PM +0530, Kapil Hali wrote:
>> Hi Russel,
> 
> Wrong.  Look at my name as sent in the From: and as quoted in the very
> next line.  As far as I'm concerned (and I don't care what other people
> say) it's disrespectful to spell people's names incorrectly.
> 
I am sincerely apologetic about it. It was a deviation that will not 
repeat again. 
>> It was clear the very first time itself as pointed out by you and the 
>> lead developers and hence the change was readily sent in the very next
>> patch set. I didn't change a comment in this patch, which is misleading 
>> about the SMP enable-method used in the patch set, it is my mistake and   
>> I apologies for the same. I will change it and send the next patch set.
> 
> Thanks.
> 
>> Also, before sending out the patch set, I had asked for a clarification 
>> about the method: https://lkml.org/lkml/2015/11/6/234
> 
> Sorry, I don't read every single email irrespective of how it's marked.
> There's way too much email, and way too much mail with improperly
> classified recipient lists to be able to usefully sort this mail.
> (If you do the math, the email rate during a 12 hour working day from
> just linux-arm-kernel is one email every 2.5 minutes, assuming 300 emails
> a day.  It takes way longer than that to compose a proper reply to an
> email - I've spent around 15 minutes on this one alone.  Hence, if I'm
> busy, I more or less totally ignore email now, and rarely bother to
> "catch up" with missed emails.)
> 
>> For my understanding, I am repeating my query- In case of simple method of 
>> waking up secondary core, smp_boot_secondary() will always return success 
>> indicating secondary core successfully started. I understand that in 
>> __cpu_up(), primary core waits for completion till secondary core comes 
>> online or time outs. However, is it appropriate to return successful start 
>> of secondary core without knowing if it really did?
> 
> Yes, because all that your smp_boot_secondary() should be doing is
> trying to start the core.  If you encounter an error trying to do so,
> that's what the error return is for.
> 
> If you just set a bit somewhere to tell the hardware to release the
> secondary core's reset, then if you set the bit and return success,
> that's prefectly acceptable.  The core ARM SMP code will then wait
> up to one second for the secondary core to become known to the kernel
> before declaring that the CPU failed to come online.
> 
> If it fails to appear, we assume that it will never appear - and
> actually at that point the system is in an unknown state: if the
> secondary CPU crashed during its boot, it could start scribbling
> into memory or touching devices in an unpredictable way: the only
> sane answer is to reboot the whole system to ensure that it's back
> to a known good state.  Hence why we don't provide any cleanup at
> the point of a failed secondary CPU (I've been debating about
> tainting the kernel at that point, so we know when things have
> gone bad.)
> 
> Hope this helps.
> 
Surely it has helped and many thanks for your detailed explanation.

Thanks,
Kapil Hali
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[PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP

[Kapil Hali]

Hi Russell,

On 11/10/2015 9:55 PM, Russell King - ARM Linux wrote:
> On Tue, Nov 10, 2015 at 09:33:12PM +0530, Kapil Hali wrote:
>> Hi Russel,
> 
> Wrong.  Look at my name as sent in the From: and as quoted in the very
> next line.  As far as I'm concerned (and I don't care what other people
> say) it's disrespectful to spell people's names incorrectly.
> 
I am sincerely apologetic about it. It was a deviation that will not 
repeat again. 
>> It was clear the very first time itself as pointed out by you and the 
>> lead developers and hence the change was readily sent in the very next
>> patch set. I didn't change a comment in this patch, which is misleading 
>> about the SMP enable-method used in the patch set, it is my mistake and   
>> I apologies for the same. I will change it and send the next patch set.
> 
> Thanks.
> 
>> Also, before sending out the patch set, I had asked for a clarification 
>> about the method: https://lkml.org/lkml/2015/11/6/234
> 
> Sorry, I don't read every single email irrespective of how it's marked.
> There's way too much email, and way too much mail with improperly
> classified recipient lists to be able to usefully sort this mail.
> (If you do the math, the email rate during a 12 hour working day from
> just linux-arm-kernel is one email every 2.5 minutes, assuming 300 emails
> a day.  It takes way longer than that to compose a proper reply to an
> email - I've spent around 15 minutes on this one alone.  Hence, if I'm
> busy, I more or less totally ignore email now, and rarely bother to
> "catch up" with missed emails.)
> 
>> For my understanding, I am repeating my query- In case of simple method of 
>> waking up secondary core, smp_boot_secondary() will always return success 
>> indicating secondary core successfully started. I understand that in 
>> __cpu_up(), primary core waits for completion till secondary core comes 
>> online or time outs. However, is it appropriate to return successful start 
>> of secondary core without knowing if it really did?
> 
> Yes, because all that your smp_boot_secondary() should be doing is
> trying to start the core.  If you encounter an error trying to do so,
> that's what the error return is for.
> 
> If you just set a bit somewhere to tell the hardware to release the
> secondary core's reset, then if you set the bit and return success,
> that's prefectly acceptable.  The core ARM SMP code will then wait
> up to one second for the secondary core to become known to the kernel
> before declaring that the CPU failed to come online.
> 
> If it fails to appear, we assume that it will never appear - and
> actually at that point the system is in an unknown state: if the
> secondary CPU crashed during its boot, it could start scribbling
> into memory or touching devices in an unpredictable way: the only
> sane answer is to reboot the whole system to ensure that it's back
> to a known good state.  Hence why we don't provide any cleanup at
> the point of a failed secondary CPU (I've been debating about
> tainting the kernel at that point, so we know when things have
> gone bad.)
> 
> Hope this helps.
> 
Surely it has helped and many thanks for your detailed explanation.

Thanks,
Kapil Hali