From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38942) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZwJKI-0004vI-WF for qemu-devel@nongnu.org; Tue, 10 Nov 2015 19:31:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZwJKH-00056j-Ik for qemu-devel@nongnu.org; Tue, 10 Nov 2015 19:31:50 -0500 From: Benjamin Herrenschmidt Date: Wed, 11 Nov 2015 11:28:19 +1100 Message-Id: <1447201710-10229-67-git-send-email-benh@kernel.crashing.org> In-Reply-To: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> Subject: [Qemu-devel] [PATCH 66/77] ppc: Add a few more P8 PMU SPRs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org Signed-off-by: Benjamin Herrenschmidt --- target-ppc/cpu.h | 7 +++++++ target-ppc/translate_init.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 756a66f..f7e653b 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1591,6 +1591,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch) #define SPR_PERF0 (0x300) #define SPR_RCPU_MI_RBA0 (0x300) #define SPR_MPC_MI_CTR (0x300) +#define SPR_POWER_USIER (0x300) #define SPR_PERF1 (0x301) #define SPR_RCPU_MI_RBA1 (0x301) #define SPR_POWER_UMMCR2 (0x301) @@ -1640,6 +1641,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch) #define SPR_PERFF (0x30F) #define SPR_MPC_MD_TW (0x30F) #define SPR_UPERF0 (0x310) +#define SPR_POWER_SIER (0x310) #define SPR_UPERF1 (0x311) #define SPR_POWER_MMCR2 (0x311) #define SPR_UPERF2 (0x312) @@ -1703,7 +1705,12 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch) #define SPR_440_ITV2 (0x376) #define SPR_440_ITV3 (0x377) #define SPR_440_CCR1 (0x378) +#define SPR_TACR (0x378) +#define SPR_TCSCR (0x379) +#define SPR_CSIGR (0x37a) #define SPR_DCRIPR (0x37B) +#define SPR_POWER_SPMC1 (0x37C) +#define SPR_POWER_SPMC2 (0x37D) #define SPR_POWER_MMCRS (0x37E) #define SPR_PPR (0x380) #define SPR_750_GQR0 (0x390) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index eaa2ac5..08730b6 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7764,6 +7764,30 @@ static void gen_spr_power8_pmu_sup(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, KVM_REG_PPC_MMCRS, 0x00000000); + spr_register_kvm(env, SPR_POWER_SIER, "SIER", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_SIER, 0x00000000); + spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_SPMC1, 0x00000000); + spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_SPMC2, 0x00000000); + spr_register_kvm(env, SPR_TACR, "TACR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_TACR, 0x00000000); + spr_register_kvm(env, SPR_TCSCR, "TCSCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_TCSCR, 0x00000000); + spr_register_kvm(env, SPR_CSIGR, "CSIGR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_CSIGR, 0x00000000); } static void gen_spr_power8_pmu_user(CPUPPCState *env) @@ -7772,6 +7796,10 @@ static void gen_spr_power8_pmu_user(CPUPPCState *env) &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, 0x00000000); + spr_register(env, SPR_POWER_USIER, "USIER", + &spr_read_generic, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); } static void gen_spr_power5p_ear(CPUPPCState *env) -- 2.5.0