From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benjamin Herrenschmidt Subject: Re: [PATCH v7 39/50] powerpc/powernv: Fundamental reset in pnv_pci_reset_secondary_bus() Date: Fri, 13 Nov 2015 11:23:23 +1100 Message-ID: <1447374203.3081.12.camel@kernel.crashing.org> References: <1446642770-4681-1-git-send-email-gwshan@linux.vnet.ibm.com> <1446642770-4681-40-git-send-email-gwshan@linux.vnet.ibm.com> <87fv0azrpe.fsf@gamma.ozlabs.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <87fv0azrpe.fsf-lvn/ZZ/ogF85kJ7NmlRacFaTQe2KTcn/@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Daniel Axtens , Gavin Shan , linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, mpe-Gsx/Oe8HsFggBc27wqDAHg@public.gmane.org, aik-sLpHqDYs0B2HXe+LvDLADg@public.gmane.org, bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, panto-wVdstyuyKrO8r51toPun2/C9HSW9iNxf@public.gmane.org, frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org List-Id: devicetree@vger.kernel.org On Fri, 2015-11-13 at 11:08 +1100, Daniel Axtens wrote: > Gavin Shan writes: >=20 > > =C2=A0void pnv_pci_reset_secondary_bus(struct pci_dev *dev) > > =C2=A0{ > > -> > > > pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); > > +> > > > int option, freset =3D 0; > > + > > +> > > > if (dev->subordinate) > > +> > > > > > pci_walk_bus(dev->subordinate, > > +> > > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pnv_pci_dev_reset= _type, &freset); > > + > > +> > > > option =3D freset ? EEH_RESET_FUNDAMENTAL : EEH_RESET_HOT= ; > > +> > > > pnv_eeh_bridge_reset(dev, option); >=20 > According to the skiboot sources, fundamental reset isn't supported o= n > p5ioc2. As far as I can tell from your corresponding skiboot patches, > this is still the case after they are applied. Do we need a fallback = to > EEH_RESET_HOT in this case? Otherwise there will be no reset performe= d > at all. We don't really care that much about what happens on p5ioc2 :-) > Likewise, if the FUNDAMENTAL reset fails for any reason, should we fa= ll > back to a HOT reset? Probably. Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe devicetree" i= n the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org ([63.228.1.57]:39395 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754465AbbKMAX6 (ORCPT ); Thu, 12 Nov 2015 19:23:58 -0500 Message-ID: <1447374203.3081.12.camel@kernel.crashing.org> Subject: Re: [PATCH v7 39/50] powerpc/powernv: Fundamental reset in pnv_pci_reset_secondary_bus() From: Benjamin Herrenschmidt To: Daniel Axtens , Gavin Shan , linuxppc-dev@lists.ozlabs.org Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, mpe@ellerman.id.au, aik@ozlabs.ru, bhelgaas@google.com, grant.likely@linaro.org, robherring2@gmail.com, panto@antoniou-consulting.com, frowand.list@gmail.com Date: Fri, 13 Nov 2015 11:23:23 +1100 In-Reply-To: <87fv0azrpe.fsf@gamma.ozlabs.ibm.com> References: <1446642770-4681-1-git-send-email-gwshan@linux.vnet.ibm.com> <1446642770-4681-40-git-send-email-gwshan@linux.vnet.ibm.com> <87fv0azrpe.fsf@gamma.ozlabs.ibm.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org List-ID: On Fri, 2015-11-13 at 11:08 +1100, Daniel Axtens wrote: > Gavin Shan writes: > > >  void pnv_pci_reset_secondary_bus(struct pci_dev *dev) > >  { > > -> > > > pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); > > +> > > > int option, freset = 0; > > + > > +> > > > if (dev->subordinate) > > +> > > > > > pci_walk_bus(dev->subordinate, > > +> > > > > > > >      pnv_pci_dev_reset_type, &freset); > > + > > +> > > > option = freset ? EEH_RESET_FUNDAMENTAL : EEH_RESET_HOT; > > +> > > > pnv_eeh_bridge_reset(dev, option); > > According to the skiboot sources, fundamental reset isn't supported on > p5ioc2. As far as I can tell from your corresponding skiboot patches, > this is still the case after they are applied. Do we need a fallback to > EEH_RESET_HOT in this case? Otherwise there will be no reset performed > at all. We don't really care that much about what happens on p5ioc2 :-) > Likewise, if the FUNDAMENTAL reset fails for any reason, should we fall > back to a HOT reset? Probably. Cheers, Ben.