* [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign
@ 2015-11-09 15:48 Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 01/12] drm/i915: Don't trust CSR program memory contents Patrik Jakobsson
` (12 more replies)
0 siblings, 13 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
This v2 of the series is rebased on top of a new series from Imre [1]
and contains a few new patches and reordering.
These patches should sit on top of the DMC redesign patches from
Animesh/Imre [2] which in turn depends on Mika's FW debug patches [3].
First couple of patches are from Ville and is included since they
otherwise might be forgotten. The third from Ville helps with handling
DC off when doing Aux A communication.
[1]
http://lists.freedesktop.org/archives/intel-gfx/2015-November/079412.html
[2]
http://lists.freedesktop.org/archives/intel-gfx/2015-October/079041.html
[3]
http://lists.freedesktop.org/archives/intel-gfx/2015-October/078898.html
Patrik Jakobsson (9):
drm/i915: Don't trust CSR program memory contents
drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6
drm/i915: Remove distinction between DDI 2 vs 4 lanes
drm/i915: Add a modeset power domain
drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()
drm/i915: Explain usage of power well IDs vs bit groups
drm/i915/gen9: Turn DC handling into a power well
drm/i915/gen9: Add boot parameter for disabling DC6
drm/i915/skl: Remove unused suspend and resume callbacks
Ville Syrjälä (3):
drm/i915: Clean up AUX power domain handling
drm/i915: Introduce a gmbus power domain
drm/i915: Remove DDI power domain exclusion
SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS
drivers/gpu/drm/i915/i915_debugfs.c | 32 ++--
drivers/gpu/drm/i915/i915_drv.c | 23 ---
drivers/gpu/drm/i915/i915_drv.h | 17 +--
drivers/gpu/drm/i915/i915_params.c | 6 +
drivers/gpu/drm/i915/i915_reg.h | 3 +
drivers/gpu/drm/i915/intel_csr.c | 10 +-
drivers/gpu/drm/i915/intel_display.c | 56 ++++++-
drivers/gpu/drm/i915/intel_dp.c | 48 ++----
drivers/gpu/drm/i915/intel_drv.h | 4 +-
drivers/gpu/drm/i915/intel_hdmi.c | 8 +-
drivers/gpu/drm/i915/intel_i2c.c | 6 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 255 ++++++++++++++++----------------
12 files changed, 233 insertions(+), 235 deletions(-)
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH 01/12] drm/i915: Don't trust CSR program memory contents
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
@ 2015-11-09 15:48 ` Patrik Jakobsson
2015-11-11 19:05 ` Imre Deak
2015-11-09 15:48 ` [PATCH 02/12] drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6 Patrik Jakobsson
` (11 subsequent siblings)
12 siblings, 1 reply; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
Replaces "drm/i915: Force loading of csr program at boot" in the old
series.
Previously we called blindly into intel_csr_load_program() and depended
on a check of whether the CSR program memory was cleared or not.
This check is not reliable and no longer needed since we fixed the
call-sites of intel_csr_load_program().
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/intel_csr.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index ecb7c70..ad8bc7a 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -220,14 +220,10 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
return;
}
- /*
- * FIXME: Firmware gets lost on S3/S4, but not when entering system
- * standby or suspend-to-idle (which is just like forced runtime pm).
- * Unfortunately the ACPI subsystem doesn't yet give us a way to
- * differentiate this, hence figure it out with this hack.
- */
- if ((!dev_priv->csr.dmc_payload) || I915_READ(CSR_PROGRAM(0)))
+ if (!dev_priv->csr.dmc_payload) {
+ DRM_ERROR("Tried to program CSR with empty payload\n");
return;
+ }
fw_size = dev_priv->csr.dmc_fw_size;
for (i = 0; i < fw_size; i++)
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 02/12] drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 01/12] drm/i915: Don't trust CSR program memory contents Patrik Jakobsson
@ 2015-11-09 15:48 ` Patrik Jakobsson
2015-11-11 19:08 ` Imre Deak
2015-11-09 15:48 ` [PATCH 03/12] drm/i915: Clean up AUX power domain handling Patrik Jakobsson
` (10 subsequent siblings)
12 siblings, 1 reply; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
Move call to gen9_set_dc_state_debugmask_memory_up() into
gen9_set_dc_state() to prevent us missing it somewhere.
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 35 ++++++++++++++++-----------------
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5a36dd5..4b9ee60 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -395,6 +395,20 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
*/
}
+static void gen9_set_dc_state_debugmask_memory_up(
+ struct drm_i915_private *dev_priv)
+{
+ uint32_t val;
+
+ /* The below bit doesn't need to be cleared ever afterwards */
+ val = I915_READ(DC_STATE_DEBUG);
+ if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
+ val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
+ I915_WRITE(DC_STATE_DEBUG, val);
+ POSTING_READ(DC_STATE_DEBUG);
+ }
+}
+
static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
{
uint32_t val;
@@ -408,6 +422,9 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
WARN_ON_ONCE(state & ~mask);
+ if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
+ gen9_set_dc_state_debugmask_memory_up(dev_priv);
+
val = I915_READ(DC_STATE_EN);
DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", val & mask, state);
val &= ~mask;
@@ -434,20 +451,6 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
}
-static void gen9_set_dc_state_debugmask_memory_up(
- struct drm_i915_private *dev_priv)
-{
- uint32_t val;
-
- /* The below bit doesn't need to be cleared ever afterwards */
- val = I915_READ(DC_STATE_DEBUG);
- if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
- val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
- I915_WRITE(DC_STATE_DEBUG, val);
- POSTING_READ(DC_STATE_DEBUG);
- }
-}
-
void assert_csr_loaded(struct drm_i915_private *dev_priv)
{
WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
@@ -496,8 +499,6 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
DRM_DEBUG_KMS("Enabling DC5\n");
- gen9_set_dc_state_debugmask_memory_up(dev_priv);
-
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
}
@@ -543,8 +544,6 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv)
DRM_DEBUG_KMS("Enabling DC6\n");
- gen9_set_dc_state_debugmask_memory_up(dev_priv);
-
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
}
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 03/12] drm/i915: Clean up AUX power domain handling
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 01/12] drm/i915: Don't trust CSR program memory contents Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 02/12] drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6 Patrik Jakobsson
@ 2015-11-09 15:48 ` Patrik Jakobsson
2015-11-11 18:22 ` Imre Deak
2015-11-16 14:01 ` [PATCH v2 " Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 04/12] drm/i915: Introduce a gmbus power domain Patrik Jakobsson
` (9 subsequent siblings)
12 siblings, 2 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Introduce intel_display_port_aux_power_domain() which simply returns
the appropriate AUX power domain for a specific port, and then replace
the intel_display_port_power_domain() with calls to the new function
in the DP code. As long as we're not actually enabling the port we don't
need the lane power domains, and those are handled now purely from
modeset_update_crtc_power_domains().
My initial motivation for this was to see if I could keep the DPIO power
wells powered down while doing AUX on CHV, but turns out I can't so this
doesn't change anything for CHV at least. But I think it's still a
worthwile change.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 40 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dp.c | 48 +++++++++++-------------------------
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 56 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d0fec07..c2578d9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5143,6 +5143,23 @@ static enum intel_display_power_domain port_to_power_domain(enum port port)
}
}
+static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
+{
+ switch (port) {
+ case PORT_A:
+ return POWER_DOMAIN_AUX_A;
+ case PORT_B:
+ return POWER_DOMAIN_AUX_B;
+ case PORT_C:
+ return POWER_DOMAIN_AUX_C;
+ case PORT_D:
+ return POWER_DOMAIN_AUX_D;
+ default:
+ WARN_ON_ONCE(1);
+ return POWER_DOMAIN_AUX_A;
+ }
+}
+
#define for_each_power_domain(domain, mask) \
for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
if ((1 << (domain)) & (mask))
@@ -5174,6 +5191,29 @@ intel_display_port_power_domain(struct intel_encoder *intel_encoder)
}
}
+enum intel_display_power_domain
+intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
+{
+ struct drm_device *dev = intel_encoder->base.dev;
+ struct intel_digital_port *intel_dig_port;
+
+ switch (intel_encoder->type) {
+ case INTEL_OUTPUT_UNKNOWN:
+ /* Only DDI platforms should ever use this output type */
+ WARN_ON_ONCE(!HAS_DDI(dev));
+ case INTEL_OUTPUT_DISPLAYPORT:
+ case INTEL_OUTPUT_EDP:
+ intel_dig_port = enc_to_dig_port(&intel_encoder->base);
+ return port_to_aux_power_domain(intel_dig_port->port);
+ case INTEL_OUTPUT_DP_MST:
+ intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
+ return port_to_aux_power_domain(intel_dig_port->port);
+ default:
+ WARN_ON_ONCE(1);
+ return POWER_DOMAIN_AUX_A;
+ }
+}
+
static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4655af0..3978540 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -277,7 +277,7 @@ static void pps_lock(struct intel_dp *intel_dp)
* See vlv_power_sequencer_reset() why we need
* a power domain reference here.
*/
- power_domain = intel_display_port_power_domain(encoder);
+ power_domain = intel_display_port_aux_power_domain(encoder);
intel_display_power_get(dev_priv, power_domain);
mutex_lock(&dev_priv->pps_mutex);
@@ -293,7 +293,7 @@ static void pps_unlock(struct intel_dp *intel_dp)
mutex_unlock(&dev_priv->pps_mutex);
- power_domain = intel_display_port_power_domain(encoder);
+ power_domain = intel_display_port_aux_power_domain(encoder);
intel_display_power_put(dev_priv, power_domain);
}
@@ -816,8 +816,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
intel_dp_check_edp(intel_dp);
- intel_aux_display_runtime_get(dev_priv);
-
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
status = I915_READ_NOTRACE(ch_ctl);
@@ -926,7 +924,6 @@ done:
ret = recv_bytes;
out:
pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
- intel_aux_display_runtime_put(dev_priv);
if (vdd)
edp_panel_vdd_off(intel_dp, false);
@@ -1784,7 +1781,7 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
if (edp_have_panel_vdd(intel_dp))
return need_to_disable;
- power_domain = intel_display_port_power_domain(intel_encoder);
+ power_domain = intel_display_port_aux_power_domain(intel_encoder);
intel_display_power_get(dev_priv, power_domain);
DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
@@ -1874,7 +1871,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
if ((pp & POWER_TARGET_ON) == 0)
intel_dp->last_power_cycle = jiffies;
- power_domain = intel_display_port_power_domain(intel_encoder);
+ power_domain = intel_display_port_aux_power_domain(intel_encoder);
intel_display_power_put(dev_priv, power_domain);
}
@@ -2025,7 +2022,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
wait_panel_off(intel_dp);
/* We got a reference when we enabled the VDD. */
- power_domain = intel_display_port_power_domain(intel_encoder);
+ power_domain = intel_display_port_aux_power_domain(intel_encoder);
intel_display_power_put(dev_priv, power_domain);
}
@@ -4765,26 +4762,6 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
intel_dp->has_audio = false;
}
-static enum intel_display_power_domain
-intel_dp_power_get(struct intel_dp *dp)
-{
- struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
- enum intel_display_power_domain power_domain;
-
- power_domain = intel_display_port_power_domain(encoder);
- intel_display_power_get(to_i915(encoder->base.dev), power_domain);
-
- return power_domain;
-}
-
-static void
-intel_dp_power_put(struct intel_dp *dp,
- enum intel_display_power_domain power_domain)
-{
- struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
- intel_display_power_put(to_i915(encoder->base.dev), power_domain);
-}
-
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
@@ -4808,7 +4785,8 @@ intel_dp_detect(struct drm_connector *connector, bool force)
return connector_status_disconnected;
}
- power_domain = intel_dp_power_get(intel_dp);
+ power_domain = intel_display_port_aux_power_domain(intel_encoder);
+ intel_display_power_get(to_i915(dev), power_domain);
/* Can't disconnect eDP, but you can close the lid... */
if (is_edp(intel_dp))
@@ -4853,7 +4831,7 @@ intel_dp_detect(struct drm_connector *connector, bool force)
}
out:
- intel_dp_power_put(intel_dp, power_domain);
+ intel_display_power_put(to_i915(dev), power_domain);
return status;
}
@@ -4862,6 +4840,7 @@ intel_dp_force(struct drm_connector *connector)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
enum intel_display_power_domain power_domain;
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
@@ -4871,11 +4850,12 @@ intel_dp_force(struct drm_connector *connector)
if (connector->status != connector_status_connected)
return;
- power_domain = intel_dp_power_get(intel_dp);
+ power_domain = intel_display_port_aux_power_domain(intel_encoder);
+ intel_display_power_get(dev_priv, power_domain);
intel_dp_set_edid(intel_dp);
- intel_dp_power_put(intel_dp, power_domain);
+ intel_display_power_put(dev_priv, power_domain);
if (intel_encoder->type != INTEL_OUTPUT_EDP)
intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
@@ -5091,7 +5071,7 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
* indefinitely.
*/
DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
- power_domain = intel_display_port_power_domain(&intel_dig_port->base);
+ power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
intel_display_power_get(dev_priv, power_domain);
edp_panel_vdd_schedule_off(intel_dp);
@@ -5172,7 +5152,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
port_name(intel_dig_port->port),
long_hpd ? "long" : "short");
- power_domain = intel_display_port_power_domain(intel_encoder);
+ power_domain = intel_display_port_aux_power_domain(intel_encoder);
intel_display_power_get(dev_priv, power_domain);
if (long_hpd) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a68b6cd..7d11aa0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1188,6 +1188,8 @@ void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
enum intel_display_power_domain
intel_display_port_power_domain(struct intel_encoder *intel_encoder);
+enum intel_display_power_domain
+intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_state *pipe_config);
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
--
2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 04/12] drm/i915: Introduce a gmbus power domain
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
` (2 preceding siblings ...)
2015-11-09 15:48 ` [PATCH 03/12] drm/i915: Clean up AUX power domain handling Patrik Jakobsson
@ 2015-11-09 15:48 ` Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 05/12] drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS Patrik Jakobsson
` (8 subsequent siblings)
12 siblings, 0 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently the gmbus code uses intel_aux_display_runtime_get/put in an
effort to make sure the hardware is powered up sufficiently for gmbus.
That function only takes the runtime PM reference which on VLV/CHV/BXT
is not enough. We need the disp2d/pipe-a well on VLV/CHV and power well
2 on BXT. So add a new power domnain for gmbus and kill off the now
unused intel_aux_display_runtime_get/put. And change
intel_hdmi_set_edid() to use the gmbus power domain too since that's all
we need there.
Also toss in a BUILD_BUG_ON() to catch problems if we run out of
bits for power domains. We're already really close to the limit...
[Patrik: Add gmbus string to debugfs output]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 2 --
drivers/gpu/drm/i915/intel_hdmi.c | 8 ++------
drivers/gpu/drm/i915/intel_i2c.c | 6 ++++--
drivers/gpu/drm/i915/intel_runtime_pm.c | 34 ++++-----------------------------
6 files changed, 13 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a0307fc..40ec895 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2744,6 +2744,8 @@ static const char *power_domain_str(enum intel_display_power_domain domain)
return "AUX_C";
case POWER_DOMAIN_AUX_D:
return "AUX_D";
+ case POWER_DOMAIN_GMBUS:
+ return "GMBUS";
case POWER_DOMAIN_INIT:
return "INIT";
default:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 71bd1dc..cef0588 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -199,6 +199,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_GMBUS,
POWER_DOMAIN_INIT,
POWER_DOMAIN_NUM,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7d11aa0..483f591 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1395,8 +1395,6 @@ void intel_display_power_get(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
void intel_display_power_put(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
-void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
-void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 013bd7d..cea05b8 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1335,21 +1335,17 @@ intel_hdmi_set_edid(struct drm_connector *connector, bool force)
{
struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
- struct intel_encoder *intel_encoder =
- &hdmi_to_dig_port(intel_hdmi)->base;
- enum intel_display_power_domain power_domain;
struct edid *edid = NULL;
bool connected = false;
- power_domain = intel_display_port_power_domain(intel_encoder);
- intel_display_power_get(dev_priv, power_domain);
+ intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
if (force)
edid = drm_get_edid(connector,
intel_gmbus_get_adapter(dev_priv,
intel_hdmi->ddc_bus));
- intel_display_power_put(dev_priv, power_domain);
+ intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
to_intel_connector(connector)->detect_edid = edid;
if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index bd58da0..fe69623 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -483,7 +483,7 @@ gmbus_xfer(struct i2c_adapter *adapter,
int i = 0, inc, try = 0;
int ret = 0;
- intel_aux_display_runtime_get(dev_priv);
+ intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
mutex_lock(&dev_priv->gmbus_mutex);
if (bus->force_bit) {
@@ -595,7 +595,9 @@ timeout:
out:
mutex_unlock(&dev_priv->gmbus_mutex);
- intel_aux_display_runtime_put(dev_priv);
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
+
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4b9ee60..c11522f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -341,6 +341,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_AUDIO) | \
BIT(POWER_DOMAIN_VGA) | \
+ BIT(POWER_DOMAIN_GMBUS) | \
BIT(POWER_DOMAIN_INIT))
#define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
@@ -1437,6 +1438,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_AUX_B) | \
BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_AUX_D) | \
+ BIT(POWER_DOMAIN_GMBUS) | \
BIT(POWER_DOMAIN_INIT))
#define HSW_DISPLAY_POWER_DOMAINS ( \
(POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
@@ -1814,6 +1816,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
+
mutex_init(&power_domains->lock);
/*
@@ -2088,36 +2092,6 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
}
/**
- * intel_aux_display_runtime_get - grab an auxiliary power domain reference
- * @dev_priv: i915 device instance
- *
- * This function grabs a power domain reference for the auxiliary power domain
- * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
- * parents are powered up. Therefore users should only grab a reference to the
- * innermost power domain they need.
- *
- * Any power domain reference obtained by this function must have a symmetric
- * call to intel_aux_display_runtime_put() to release the reference again.
- */
-void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
-{
- intel_runtime_pm_get(dev_priv);
-}
-
-/**
- * intel_aux_display_runtime_put - release an auxiliary power domain reference
- * @dev_priv: i915 device instance
- *
- * This function drops the auxiliary power domain reference obtained by
- * intel_aux_display_runtime_get() and might power down the corresponding
- * hardware block right away if this is the last reference.
- */
-void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
-{
- intel_runtime_pm_put(dev_priv);
-}
-
-/**
* intel_runtime_pm_get - grab a runtime pm reference
* @dev_priv: i915 device instance
*
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 05/12] drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
` (3 preceding siblings ...)
2015-11-09 15:48 ` [PATCH 04/12] drm/i915: Introduce a gmbus power domain Patrik Jakobsson
@ 2015-11-09 15:48 ` Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 06/12] drm/i915: Remove distinction between DDI 2 vs 4 lanes Patrik Jakobsson
` (7 subsequent siblings)
12 siblings, 0 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
All the DDI power domains are already excluded from
SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS on account of
excluding SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS and
SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, no need to spell them out again.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index c11522f..c9cb94d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -318,11 +318,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
(POWER_DOMAIN_MASK & ~( \
- SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \
- SKL_DISPLAY_DDI_B_POWER_DOMAINS | \
- SKL_DISPLAY_DDI_C_POWER_DOMAINS | \
- SKL_DISPLAY_DDI_D_POWER_DOMAINS)) | \
+ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
BIT(POWER_DOMAIN_INIT))
#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 06/12] drm/i915: Remove distinction between DDI 2 vs 4 lanes
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
` (4 preceding siblings ...)
2015-11-09 15:48 ` [PATCH 05/12] drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS Patrik Jakobsson
@ 2015-11-09 15:48 ` Patrik Jakobsson
2015-11-11 19:10 ` Imre Deak
2015-11-09 15:48 ` [PATCH 07/12] drm/i915: Add a modeset power domain Patrik Jakobsson
` (6 subsequent siblings)
12 siblings, 1 reply; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
We never make use of the distinction between 2 vs 4 lanes so combine
them into a per port domain instead. This saves us a few bits in the
power domain mask. Change suggested by Ville.
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 28 +++++--------
drivers/gpu/drm/i915/i915_drv.h | 14 +++----
drivers/gpu/drm/i915/intel_display.c | 10 ++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 71 ++++++++++++---------------------
4 files changed, 45 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 40ec895..2fad0a9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2706,24 +2706,16 @@ static const char *power_domain_str(enum intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
- case POWER_DOMAIN_PORT_DDI_A_2_LANES:
- return "PORT_DDI_A_2_LANES";
- case POWER_DOMAIN_PORT_DDI_A_4_LANES:
- return "PORT_DDI_A_4_LANES";
- case POWER_DOMAIN_PORT_DDI_B_2_LANES:
- return "PORT_DDI_B_2_LANES";
- case POWER_DOMAIN_PORT_DDI_B_4_LANES:
- return "PORT_DDI_B_4_LANES";
- case POWER_DOMAIN_PORT_DDI_C_2_LANES:
- return "PORT_DDI_C_2_LANES";
- case POWER_DOMAIN_PORT_DDI_C_4_LANES:
- return "PORT_DDI_C_4_LANES";
- case POWER_DOMAIN_PORT_DDI_D_2_LANES:
- return "PORT_DDI_D_2_LANES";
- case POWER_DOMAIN_PORT_DDI_D_4_LANES:
- return "PORT_DDI_D_4_LANES";
- case POWER_DOMAIN_PORT_DDI_E_2_LANES:
- return "PORT_DDI_E_2_LANES";
+ case POWER_DOMAIN_PORT_DDI_A_LANES:
+ return "PORT_DDI_A_LANES";
+ case POWER_DOMAIN_PORT_DDI_B_LANES:
+ return "PORT_DDI_B_LANES";
+ case POWER_DOMAIN_PORT_DDI_C_LANES:
+ return "PORT_DDI_C_LANES";
+ case POWER_DOMAIN_PORT_DDI_D_LANES:
+ return "PORT_DDI_D_LANES";
+ case POWER_DOMAIN_PORT_DDI_E_LANES:
+ return "PORT_DDI_E_LANES";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cef0588..fff7f63 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -180,15 +180,11 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
- POWER_DOMAIN_PORT_DDI_A_2_LANES,
- POWER_DOMAIN_PORT_DDI_A_4_LANES,
- POWER_DOMAIN_PORT_DDI_B_2_LANES,
- POWER_DOMAIN_PORT_DDI_B_4_LANES,
- POWER_DOMAIN_PORT_DDI_C_2_LANES,
- POWER_DOMAIN_PORT_DDI_C_4_LANES,
- POWER_DOMAIN_PORT_DDI_D_2_LANES,
- POWER_DOMAIN_PORT_DDI_D_4_LANES,
- POWER_DOMAIN_PORT_DDI_E_2_LANES,
+ POWER_DOMAIN_PORT_DDI_A_LANES,
+ POWER_DOMAIN_PORT_DDI_B_LANES,
+ POWER_DOMAIN_PORT_DDI_C_LANES,
+ POWER_DOMAIN_PORT_DDI_D_LANES,
+ POWER_DOMAIN_PORT_DDI_E_LANES,
POWER_DOMAIN_PORT_DSI,
POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_PORT_OTHER,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c2578d9..649ac34 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5128,15 +5128,15 @@ static enum intel_display_power_domain port_to_power_domain(enum port port)
{
switch (port) {
case PORT_A:
- return POWER_DOMAIN_PORT_DDI_A_4_LANES;
+ return POWER_DOMAIN_PORT_DDI_A_LANES;
case PORT_B:
- return POWER_DOMAIN_PORT_DDI_B_4_LANES;
+ return POWER_DOMAIN_PORT_DDI_B_LANES;
case PORT_C:
- return POWER_DOMAIN_PORT_DDI_C_4_LANES;
+ return POWER_DOMAIN_PORT_DDI_C_LANES;
case PORT_D:
- return POWER_DOMAIN_PORT_DDI_D_4_LANES;
+ return POWER_DOMAIN_PORT_DDI_D_LANES;
case PORT_E:
- return POWER_DOMAIN_PORT_DDI_E_2_LANES;
+ return POWER_DOMAIN_PORT_DDI_E_LANES;
default:
WARN_ON_ONCE(1);
return POWER_DOMAIN_PORT_OTHER;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index c9cb94d..fc206bb 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -286,13 +286,10 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_TRANSCODER_C) | \
BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
BIT(POWER_DOMAIN_AUX_B) | \
BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_AUX_D) | \
@@ -300,21 +297,17 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_VGA) | \
BIT(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
- BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
BIT(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
- BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
BIT(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
- BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
BIT(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
- BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
BIT(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
(POWER_DOMAIN_MASK & ~( \
@@ -329,10 +322,8 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_TRANSCODER_C) | \
BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
BIT(POWER_DOMAIN_AUX_B) | \
BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_AUDIO) | \
@@ -344,8 +335,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_PIPE_A) | \
BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
BIT(POWER_DOMAIN_AUX_A) | \
BIT(POWER_DOMAIN_PLLS) | \
BIT(POWER_DOMAIN_INIT))
@@ -1420,14 +1410,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PIPE_A) | \
BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
- BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
BIT(POWER_DOMAIN_PORT_CRT) | \
BIT(POWER_DOMAIN_PLLS) | \
BIT(POWER_DOMAIN_AUX_A) | \
@@ -1451,49 +1437,42 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
BIT(POWER_DOMAIN_PORT_CRT) | \
BIT(POWER_DOMAIN_AUX_B) | \
BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
- BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
BIT(POWER_DOMAIN_AUX_B) | \
BIT(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
- BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
BIT(POWER_DOMAIN_AUX_B) | \
BIT(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
- BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
- BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_INIT))
#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
BIT(POWER_DOMAIN_AUX_B) | \
BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_INIT))
#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
- BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
- BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
BIT(POWER_DOMAIN_AUX_D) | \
BIT(POWER_DOMAIN_INIT))
--
2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 07/12] drm/i915: Add a modeset power domain
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
` (5 preceding siblings ...)
2015-11-09 15:48 ` [PATCH 06/12] drm/i915: Remove distinction between DDI 2 vs 4 lanes Patrik Jakobsson
@ 2015-11-09 15:48 ` Patrik Jakobsson
2015-11-11 19:11 ` Imre Deak
2015-11-09 15:48 ` [PATCH 08/12] drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5() Patrik Jakobsson
` (5 subsequent siblings)
12 siblings, 1 reply; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
We need a power domain for disabling DC5/DC6 around modesets to prevent
confusing the DMC.
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2fad0a9..0b06192 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2738,6 +2738,8 @@ static const char *power_domain_str(enum intel_display_power_domain domain)
return "AUX_D";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
+ case POWER_DOMAIN_MODESET:
+ return "MODESET";
case POWER_DOMAIN_INIT:
return "INIT";
default:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fff7f63..c0252ef 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -196,6 +196,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D,
POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_MODESET,
POWER_DOMAIN_INIT,
POWER_DOMAIN_NUM,
--
2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 08/12] drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
` (6 preceding siblings ...)
2015-11-09 15:48 ` [PATCH 07/12] drm/i915: Add a modeset power domain Patrik Jakobsson
@ 2015-11-09 15:48 ` Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 09/12] drm/i915: Explain usage of power well IDs vs bit groups Patrik Jakobsson
` (4 subsequent siblings)
12 siblings, 0 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
PG2 enabled is not a requirement for disabling DC5. It's just one
of the reasons why the DMC wouldn't enter DC5. During modeset we don't
care about PG2 from a DC perspective, only the fact that DC5/DC6 is not
allowed.
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index fc206bb..edf753e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -466,8 +466,6 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
{
- bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
- SKL_DISP_PW_2);
/*
* During initialization, the firmware may not be loaded yet.
* We still want to make sure that the DC enabling flag is cleared.
@@ -475,7 +473,6 @@ static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
if (dev_priv->power_domains.initializing)
return;
- WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
WARN_ONCE(dev_priv->pm.suspended,
"Disabling of DC5 while platform is runtime-suspended should never happen.\n");
}
--
2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 09/12] drm/i915: Explain usage of power well IDs vs bit groups
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
` (7 preceding siblings ...)
2015-11-09 15:48 ` [PATCH 08/12] drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5() Patrik Jakobsson
@ 2015-11-09 15:48 ` Patrik Jakobsson
2015-11-11 19:13 ` Imre Deak
2015-11-16 14:01 ` [PATCH v2 " Patrik Jakobsson
2015-11-09 15:48 ` [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well Patrik Jakobsson
` (3 subsequent siblings)
12 siblings, 2 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e6d88f5..31b3a84 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -621,6 +621,7 @@ enum punit_power_well {
PUNIT_POWER_WELL_DPIO_RX1 = 11,
PUNIT_POWER_WELL_DPIO_CMN_D = 12,
+ /* Not actual bit groups. Used as IDs for lookup_power_well() */
PUNIT_POWER_WELL_ALWAYS_ON,
};
@@ -633,6 +634,7 @@ enum skl_disp_power_wells {
SKL_DISP_PW_1 = 14,
SKL_DISP_PW_2,
+ /* Not actual bit groups. Used as IDs for lookup_power_well() */
SKL_DISP_PW_ALWAYS_ON,
};
--
2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
` (8 preceding siblings ...)
2015-11-09 15:48 ` [PATCH 09/12] drm/i915: Explain usage of power well IDs vs bit groups Patrik Jakobsson
@ 2015-11-09 15:48 ` Patrik Jakobsson
2015-11-11 18:57 ` Imre Deak
` (2 more replies)
2015-11-09 15:48 ` [PATCH v2 11/12] drm/i915/gen9: Add boot parameter for disabling DC6 Patrik Jakobsson
` (2 subsequent siblings)
12 siblings, 3 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
Handle DC off as a power well where enabling the power well will prevent
the DMC to enter selected DC states (required around modesets and Aux
A). Disabling the power well will allow DC states again. For now the
highest DC state is DC6 for Skylake and DC5 for Broxton but will be
configurable for Skylake in a later patch.
v2: Check both DC5 and DC6 bits in power well enabled function (Ville)
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 6 --
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 6 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 110 +++++++++++++++++++++++---------
4 files changed, 88 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5a63f9a..0c7f435 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
static int skl_suspend_complete(struct drm_i915_private *dev_priv)
{
- if (dev_priv->csr.dmc_payload)
- skl_enable_dc6(dev_priv);
-
return 0;
}
@@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
static int skl_resume_prepare(struct drm_i915_private *dev_priv)
{
- if (dev_priv->csr.dmc_payload)
- skl_disable_dc6(dev_priv);
-
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31b3a84..df445ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -636,6 +636,7 @@ enum skl_disp_power_wells {
/* Not actual bit groups. Used as IDs for lookup_power_well() */
SKL_DISP_PW_ALWAYS_ON,
+ SKL_DISP_PW_DC_OFF,
};
#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 649ac34..856d801 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13320,6 +13320,9 @@ static int intel_atomic_commit(struct drm_device *dev,
to_intel_crtc_state(crtc->state)->update_pipe;
unsigned long put_domains = 0;
+ if (modeset)
+ intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
+
if (modeset && crtc->state->active) {
update_scanline_offset(to_intel_crtc(crtc));
dev_priv->display.crtc_enable(crtc);
@@ -13343,6 +13346,9 @@ static int intel_atomic_commit(struct drm_device *dev,
modeset_put_power_domains(dev_priv, put_domains);
intel_post_plane_update(intel_crtc);
+
+ if (modeset)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
}
/* FIXME: add subpixel order */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index edf753e..95c3fcc 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -49,9 +49,6 @@
* present for a given platform.
*/
-#define GEN9_ENABLE_DC5(dev) 0
-#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
-
#define for_each_power_well(i, power_well, domain_mask, power_domains) \
for (i = 0; \
i < (power_domains)->power_well_count && \
@@ -309,9 +306,14 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
BIT(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_MODESET) | \
+ BIT(POWER_DOMAIN_AUX_A) | \
+ BIT(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
(POWER_DOMAIN_MASK & ~( \
- SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
+ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
BIT(POWER_DOMAIN_INIT))
#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
@@ -339,6 +341,10 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_AUX_A) | \
BIT(POWER_DOMAIN_PLLS) | \
BIT(POWER_DOMAIN_INIT))
+#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_MODESET) | \
+ BIT(POWER_DOMAIN_AUX_A) | \
+ BIT(POWER_DOMAIN_INIT))
#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
(POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
@@ -486,15 +492,6 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
}
-static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
-{
- assert_can_disable_dc5(dev_priv);
-
- DRM_DEBUG_KMS("Disabling DC5\n");
-
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
-}
-
static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
@@ -522,6 +519,14 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
"DC6 already programmed to be disabled.\n");
}
+static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
+{
+ assert_can_disable_dc5(dev_priv);
+ assert_can_disable_dc6(dev_priv);
+
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+}
+
void skl_enable_dc6(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc6(dev_priv);
@@ -571,6 +576,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
case SKL_DISP_PW_DDI_C:
case SKL_DISP_PW_DDI_D:
case SKL_DISP_PW_MISC_IO:
+ case SKL_DISP_PW_DC_OFF:
break;
default:
WARN(1, "Unknown power well %lu\n", power_well->data);
@@ -589,17 +595,13 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
"Invalid for power well status to be enabled, unless done by the BIOS, \
when request is to disable!\n");
if (power_well->data == SKL_DISP_PW_2) {
- if (GEN9_ENABLE_DC5(dev))
- gen9_disable_dc5(dev_priv);
- if (SKL_ENABLE_DC6(dev)) {
- /*
- * DDI buffer programming unnecessary during driver-load/resume
- * as it's already done during modeset initialization then.
- * It's also invalid here as encoder list is still uninitialized.
- */
- if (!dev_priv->power_domains.initializing)
- intel_prepare_ddi(dev);
- }
+ /*
+ * DDI buffer programming unnecessary during driver-load/resume
+ * as it's already done during modeset initialization then.
+ * It's also invalid here as encoder list is still uninitialized.
+ */
+ if (!dev_priv->power_domains.initializing)
+ intel_prepare_ddi(dev);
}
I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
}
@@ -617,10 +619,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
POSTING_READ(HSW_PWR_WELL_DRIVER);
DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
-
- if (GEN9_ENABLE_DC5(dev) &&
- power_well->data == SKL_DISP_PW_2)
- gen9_enable_dc5(dev_priv);
}
}
@@ -695,6 +693,40 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
skl_set_power_well(dev_priv, power_well, false);
}
+static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
+}
+
+static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ gen9_disable_dc5_dc6(dev_priv);
+}
+
+static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if (IS_SKYLAKE(dev_priv))
+ skl_enable_dc6(dev_priv);
+ else
+ gen9_enable_dc5(dev_priv);
+}
+
+static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if (power_well->count > 0) {
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ } else {
+ if (IS_SKYLAKE(dev_priv))
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
+ else
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
+ }
+}
+
static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -1517,6 +1549,13 @@ static const struct i915_power_well_ops skl_power_well_ops = {
.is_enabled = skl_power_well_enabled,
};
+static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
+ .sync_hw = gen9_dc_off_power_well_sync_hw,
+ .enable = gen9_dc_off_power_well_enable,
+ .disable = gen9_dc_off_power_well_disable,
+ .is_enabled = gen9_dc_off_power_well_enabled,
+};
+
static struct i915_power_well hsw_power_wells[] = {
{
.name = "always-on",
@@ -1697,6 +1736,12 @@ static struct i915_power_well skl_power_wells[] = {
.data = SKL_DISP_PW_2,
},
{
+ .name = "DC off",
+ .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .data = SKL_DISP_PW_DC_OFF,
+ },
+ {
.name = "DDI A/E power well",
.domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
.ops = &skl_power_well_ops,
@@ -1769,7 +1814,14 @@ static struct i915_power_well bxt_power_wells[] = {
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &skl_power_well_ops,
.data = SKL_DISP_PW_2,
- }
+ },
+ {
+ .name = "DC off",
+ .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .data = SKL_DISP_PW_DC_OFF,
+ },
+
};
#define set_power_wells(power_domains, __power_wells) ({ \
--
2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 11/12] drm/i915/gen9: Add boot parameter for disabling DC6
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
` (9 preceding siblings ...)
2015-11-09 15:48 ` [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well Patrik Jakobsson
@ 2015-11-09 15:48 ` Patrik Jakobsson
2015-11-11 19:04 ` Imre Deak
2015-11-16 14:01 ` [PATCH v3 " Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 12/12] drm/i915/skl: Remove unused suspend and resume callbacks Patrik Jakobsson
2015-11-17 19:54 ` [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Imre Deak
12 siblings, 2 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
v2: Use _unsafe (Jani)
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 6 ++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0252ef..5628c5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2639,6 +2639,7 @@ struct i915_params {
int panel_use_ssc;
int vbt_sdvo_panel_type;
int enable_rc6;
+ int enable_dc6;
int enable_fbc;
int enable_ppgtt;
int enable_execlists;
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 368df67..6457f3a 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -32,6 +32,7 @@ struct i915_params i915 __read_mostly = {
.panel_use_ssc = -1,
.vbt_sdvo_panel_type = -1,
.enable_rc6 = -1,
+ .enable_dc6 = 1,
.enable_fbc = -1,
.enable_execlists = -1,
.enable_hangcheck = true,
@@ -79,6 +80,11 @@ MODULE_PARM_DESC(enable_rc6,
"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
"default: -1 (use per-chip default)");
+module_param_named_unsafe(enable_dc6, i915.enable_dc6, int, 0400);
+MODULE_PARM_DESC(enable_dc6,
+ "Enable power-saving display C-state 6. "
+ "(0 = disable; 1 = enable [default])");
+
module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600);
MODULE_PARM_DESC(enable_fbc,
"Enable frame buffer compression for power savings "
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 95c3fcc..62c1273 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -708,7 +708,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- if (IS_SKYLAKE(dev_priv))
+ if (IS_SKYLAKE(dev_priv) && i915.enable_dc6)
skl_enable_dc6(dev_priv);
else
gen9_enable_dc5(dev_priv);
@@ -720,7 +720,7 @@ static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
if (power_well->count > 0) {
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
} else {
- if (IS_SKYLAKE(dev_priv))
+ if (IS_SKYLAKE(dev_priv) && i915.enable_dc6)
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
else
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
--
2.5.0
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH 12/12] drm/i915/skl: Remove unused suspend and resume callbacks
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
` (10 preceding siblings ...)
2015-11-09 15:48 ` [PATCH v2 11/12] drm/i915/gen9: Add boot parameter for disabling DC6 Patrik Jakobsson
@ 2015-11-09 15:48 ` Patrik Jakobsson
2015-11-17 18:28 ` Imre Deak
2015-11-17 19:54 ` [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Imre Deak
12 siblings, 1 reply; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-09 15:48 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0c7f435..77d183d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -622,7 +622,6 @@ static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
static int intel_suspend_complete(struct drm_i915_private *dev_priv);
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
bool rpm_resume);
-static int skl_resume_prepare(struct drm_i915_private *dev_priv);
static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
@@ -857,8 +856,6 @@ static int i915_drm_resume_early(struct drm_device *dev)
if (IS_BROXTON(dev))
ret = bxt_resume_prepare(dev_priv);
- else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
- ret = skl_resume_prepare(dev_priv);
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
hsw_disable_pc8(dev_priv);
@@ -1070,11 +1067,6 @@ static int i915_pm_resume(struct device *dev)
return i915_drm_resume(drm_dev);
}
-static int skl_suspend_complete(struct drm_i915_private *dev_priv)
-{
- return 0;
-}
-
static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
{
hsw_enable_pc8(dev_priv);
@@ -1114,11 +1106,6 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
return 0;
}
-static int skl_resume_prepare(struct drm_i915_private *dev_priv)
-{
- return 0;
-}
-
/*
* Save all Gunit registers that may be lost after a D3 and a subsequent
* S0i[R123] transition. The list of registers needing a save/restore is
@@ -1582,8 +1569,6 @@ static int intel_runtime_resume(struct device *device)
if (IS_BROXTON(dev))
ret = bxt_resume_prepare(dev_priv);
- else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
- ret = skl_resume_prepare(dev_priv);
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
hsw_disable_pc8(dev_priv);
else if (IS_VALLEYVIEW(dev_priv))
@@ -1626,8 +1611,6 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv)
if (IS_BROXTON(dev_priv))
ret = bxt_suspend_complete(dev_priv);
- else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
- ret = skl_suspend_complete(dev_priv);
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ret = hsw_suspend_complete(dev_priv);
else if (IS_VALLEYVIEW(dev_priv))
--
2.5.0
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH 03/12] drm/i915: Clean up AUX power domain handling
2015-11-09 15:48 ` [PATCH 03/12] drm/i915: Clean up AUX power domain handling Patrik Jakobsson
@ 2015-11-11 18:22 ` Imre Deak
2015-11-11 18:37 ` Ville Syrjälä
2015-11-16 14:01 ` [PATCH v2 " Patrik Jakobsson
1 sibling, 1 reply; 47+ messages in thread
From: Imre Deak @ 2015-11-11 18:22 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Introduce intel_display_port_aux_power_domain() which simply returns
> the appropriate AUX power domain for a specific port, and then
> replace
> the intel_display_port_power_domain() with calls to the new function
> in the DP code. As long as we're not actually enabling the port we
> don't
> need the lane power domains, and those are handled now purely from
> modeset_update_crtc_power_domains().
>
> My initial motivation for this was to see if I could keep the DPIO
> power
> wells powered down while doing AUX on CHV, but turns out I can't so
> this
> doesn't change anything for CHV at least. But I think it's still a
> worthwile change.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 40
> ++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_dp.c | 48 +++++++++++---------------
> ----------
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 56 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index d0fec07..c2578d9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5143,6 +5143,23 @@ static enum intel_display_power_domain
> port_to_power_domain(enum port port)
> }
> }
>
> +static enum intel_display_power_domain port_to_aux_power_domain(enum
> port port)
> +{
> + switch (port) {
> + case PORT_A:
> + return POWER_DOMAIN_AUX_A;
> + case PORT_B:
> + return POWER_DOMAIN_AUX_B;
> + case PORT_C:
> + return POWER_DOMAIN_AUX_C;
> + case PORT_D:
> + return POWER_DOMAIN_AUX_D;
> + default:
> + WARN_ON_ONCE(1);
> + return POWER_DOMAIN_AUX_A;
> + }
> +}
Looks like port E is missing. I chatted with Ville he has some idea to
fix this.
> +
> #define for_each_power_domain(domain, mask)
> \
> for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)
> \
> if ((1 << (domain)) & (mask))
> @@ -5174,6 +5191,29 @@ intel_display_port_power_domain(struct
> intel_encoder *intel_encoder)
> }
> }
>
> +enum intel_display_power_domain
> +intel_display_port_aux_power_domain(struct intel_encoder
> *intel_encoder)
> +{
> + struct drm_device *dev = intel_encoder->base.dev;
> + struct intel_digital_port *intel_dig_port;
> +
> + switch (intel_encoder->type) {
> + case INTEL_OUTPUT_UNKNOWN:
> + /* Only DDI platforms should ever use this output
> type */
> + WARN_ON_ONCE(!HAS_DDI(dev));
> + case INTEL_OUTPUT_DISPLAYPORT:
> + case INTEL_OUTPUT_EDP:
> + intel_dig_port = enc_to_dig_port(&intel_encoder
> ->base);
> + return port_to_aux_power_domain(intel_dig_port
> ->port);
> + case INTEL_OUTPUT_DP_MST:
> + intel_dig_port = enc_to_mst(&intel_encoder->base)
> ->primary;
> + return port_to_aux_power_domain(intel_dig_port
> ->port);
> + default:
> + WARN_ON_ONCE(1);
> + return POWER_DOMAIN_AUX_A;
> + }
> +}
> +
> static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index 4655af0..3978540 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -277,7 +277,7 @@ static void pps_lock(struct intel_dp *intel_dp)
> * See vlv_power_sequencer_reset() why we need
> * a power domain reference here.
> */
> - power_domain = intel_display_port_power_domain(encoder);
> + power_domain = intel_display_port_aux_power_domain(encoder);
> intel_display_power_get(dev_priv, power_domain);
>
> mutex_lock(&dev_priv->pps_mutex);
> @@ -293,7 +293,7 @@ static void pps_unlock(struct intel_dp *intel_dp)
>
> mutex_unlock(&dev_priv->pps_mutex);
>
> - power_domain = intel_display_port_power_domain(encoder);
> + power_domain = intel_display_port_aux_power_domain(encoder);
> intel_display_power_put(dev_priv, power_domain);
> }
>
> @@ -816,8 +816,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>
> intel_dp_check_edp(intel_dp);
>
> - intel_aux_display_runtime_get(dev_priv);
> -
> /* Try to wait for any previous AUX channel activity */
> for (try = 0; try < 3; try++) {
> status = I915_READ_NOTRACE(ch_ctl);
> @@ -926,7 +924,6 @@ done:
> ret = recv_bytes;
> out:
> pm_qos_update_request(&dev_priv->pm_qos,
> PM_QOS_DEFAULT_VALUE);
> - intel_aux_display_runtime_put(dev_priv);
>
> if (vdd)
> edp_panel_vdd_off(intel_dp, false);
> @@ -1784,7 +1781,7 @@ static bool edp_panel_vdd_on(struct intel_dp
> *intel_dp)
> if (edp_have_panel_vdd(intel_dp))
> return need_to_disable;
>
> - power_domain =
> intel_display_port_power_domain(intel_encoder);
> + power_domain =
> intel_display_port_aux_power_domain(intel_encoder);
> intel_display_power_get(dev_priv, power_domain);
>
> DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
> @@ -1874,7 +1871,7 @@ static void edp_panel_vdd_off_sync(struct
> intel_dp *intel_dp)
> if ((pp & POWER_TARGET_ON) == 0)
> intel_dp->last_power_cycle = jiffies;
>
> - power_domain =
> intel_display_port_power_domain(intel_encoder);
> + power_domain =
> intel_display_port_aux_power_domain(intel_encoder);
> intel_display_power_put(dev_priv, power_domain);
> }
>
> @@ -2025,7 +2022,7 @@ static void edp_panel_off(struct intel_dp
> *intel_dp)
> wait_panel_off(intel_dp);
>
> /* We got a reference when we enabled the VDD. */
> - power_domain =
> intel_display_port_power_domain(intel_encoder);
> + power_domain =
> intel_display_port_aux_power_domain(intel_encoder);
> intel_display_power_put(dev_priv, power_domain);
> }
>
> @@ -4765,26 +4762,6 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> intel_dp->has_audio = false;
> }
>
> -static enum intel_display_power_domain
> -intel_dp_power_get(struct intel_dp *dp)
> -{
> - struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
> - enum intel_display_power_domain power_domain;
> -
> - power_domain = intel_display_port_power_domain(encoder);
> - intel_display_power_get(to_i915(encoder->base.dev),
> power_domain);
> -
> - return power_domain;
> -}
> -
> -static void
> -intel_dp_power_put(struct intel_dp *dp,
> - enum intel_display_power_domain power_domain)
> -{
> - struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
> - intel_display_power_put(to_i915(encoder->base.dev),
> power_domain);
> -}
> -
> static enum drm_connector_status
> intel_dp_detect(struct drm_connector *connector, bool force)
> {
> @@ -4808,7 +4785,8 @@ intel_dp_detect(struct drm_connector
> *connector, bool force)
> return connector_status_disconnected;
> }
>
> - power_domain = intel_dp_power_get(intel_dp);
> + power_domain =
> intel_display_port_aux_power_domain(intel_encoder);
> + intel_display_power_get(to_i915(dev), power_domain);
>
> /* Can't disconnect eDP, but you can close the lid... */
> if (is_edp(intel_dp))
> @@ -4853,7 +4831,7 @@ intel_dp_detect(struct drm_connector
> *connector, bool force)
> }
>
> out:
> - intel_dp_power_put(intel_dp, power_domain);
> + intel_display_power_put(to_i915(dev), power_domain);
> return status;
> }
>
> @@ -4862,6 +4840,7 @@ intel_dp_force(struct drm_connector *connector)
> {
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct intel_encoder *intel_encoder =
> &dp_to_dig_port(intel_dp)->base;
> + struct drm_i915_private *dev_priv = to_i915(intel_encoder
> ->base.dev);
> enum intel_display_power_domain power_domain;
>
> DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
> @@ -4871,11 +4850,12 @@ intel_dp_force(struct drm_connector
> *connector)
> if (connector->status != connector_status_connected)
> return;
>
> - power_domain = intel_dp_power_get(intel_dp);
> + power_domain =
> intel_display_port_aux_power_domain(intel_encoder);
> + intel_display_power_get(dev_priv, power_domain);
>
> intel_dp_set_edid(intel_dp);
>
> - intel_dp_power_put(intel_dp, power_domain);
> + intel_display_power_put(dev_priv, power_domain);
>
> if (intel_encoder->type != INTEL_OUTPUT_EDP)
> intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
> @@ -5091,7 +5071,7 @@ static void intel_edp_panel_vdd_sanitize(struct
> intel_dp *intel_dp)
> * indefinitely.
> */
> DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state
> tracking\n");
> - power_domain =
> intel_display_port_power_domain(&intel_dig_port->base);
> + power_domain =
> intel_display_port_aux_power_domain(&intel_dig_port->base);
> intel_display_power_get(dev_priv, power_domain);
>
> edp_panel_vdd_schedule_off(intel_dp);
> @@ -5172,7 +5152,7 @@ intel_dp_hpd_pulse(struct intel_digital_port
> *intel_dig_port, bool long_hpd)
> port_name(intel_dig_port->port),
> long_hpd ? "long" : "short");
>
> - power_domain =
> intel_display_port_power_domain(intel_encoder);
> + power_domain =
> intel_display_port_aux_power_domain(intel_encoder);
> intel_display_power_get(dev_priv, power_domain);
>
> if (long_hpd) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index a68b6cd..7d11aa0 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1188,6 +1188,8 @@ void hsw_enable_ips(struct intel_crtc *crtc);
> void hsw_disable_ips(struct intel_crtc *crtc);
> enum intel_display_power_domain
> intel_display_port_power_domain(struct intel_encoder
> *intel_encoder);
> +enum intel_display_power_domain
> +intel_display_port_aux_power_domain(struct intel_encoder
> *intel_encoder);
> void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> struct intel_crtc_state
> *pipe_config);
> void intel_modeset_preclose(struct drm_device *dev, struct drm_file
> *file);
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 03/12] drm/i915: Clean up AUX power domain handling
2015-11-11 18:22 ` Imre Deak
@ 2015-11-11 18:37 ` Ville Syrjälä
2015-11-12 9:02 ` Patrik Jakobsson
0 siblings, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2015-11-11 18:37 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Nov 11, 2015 at 08:22:03PM +0200, Imre Deak wrote:
> On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Introduce intel_display_port_aux_power_domain() which simply returns
> > the appropriate AUX power domain for a specific port, and then
> > replace
> > the intel_display_port_power_domain() with calls to the new function
> > in the DP code. As long as we're not actually enabling the port we
> > don't
> > need the lane power domains, and those are handled now purely from
> > modeset_update_crtc_power_domains().
> >
> > My initial motivation for this was to see if I could keep the DPIO
> > power
> > wells powered down while doing AUX on CHV, but turns out I can't so
> > this
> > doesn't change anything for CHV at least. But I think it's still a
> > worthwile change.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 40
> > ++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_dp.c | 48 +++++++++++---------------
> > ----------
> > drivers/gpu/drm/i915/intel_drv.h | 2 ++
> > 3 files changed, 56 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index d0fec07..c2578d9 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5143,6 +5143,23 @@ static enum intel_display_power_domain
> > port_to_power_domain(enum port port)
> > }
> > }
> >
> > +static enum intel_display_power_domain port_to_aux_power_domain(enum
> > port port)
> > +{
> > + switch (port) {
> > + case PORT_A:
> > + return POWER_DOMAIN_AUX_A;
> > + case PORT_B:
> > + return POWER_DOMAIN_AUX_B;
> > + case PORT_C:
> > + return POWER_DOMAIN_AUX_C;
> > + case PORT_D:
> > + return POWER_DOMAIN_AUX_D;
> > + default:
> > + WARN_ON_ONCE(1);
> > + return POWER_DOMAIN_AUX_A;
> > + }
> > +}
>
> Looks like port E is missing. I chatted with Ville he has some idea to
> fix this.
Yeah, so there's no dedicated AUX block for port E, and instead VBT
tells us which AUX block to use. The current code doin that is rather
messy, but I have a cleaned it up during my register type-safety
journey. I just reposted the remaining AUX related patches [1] from
that series.
So I was thinking that we could include an 'enum port aux_port' inside
intel_dp, and use that to pick the right power domain.
[1] http://lists.freedesktop.org/archives/intel-gfx/2015-November/079918.html
>
> > +
> > #define for_each_power_domain(domain, mask)
> > \
> > for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)
> > \
> > if ((1 << (domain)) & (mask))
> > @@ -5174,6 +5191,29 @@ intel_display_port_power_domain(struct
> > intel_encoder *intel_encoder)
> > }
> > }
> >
> > +enum intel_display_power_domain
> > +intel_display_port_aux_power_domain(struct intel_encoder
> > *intel_encoder)
> > +{
> > + struct drm_device *dev = intel_encoder->base.dev;
> > + struct intel_digital_port *intel_dig_port;
> > +
> > + switch (intel_encoder->type) {
> > + case INTEL_OUTPUT_UNKNOWN:
> > + /* Only DDI platforms should ever use this output
> > type */
> > + WARN_ON_ONCE(!HAS_DDI(dev));
> > + case INTEL_OUTPUT_DISPLAYPORT:
> > + case INTEL_OUTPUT_EDP:
> > + intel_dig_port = enc_to_dig_port(&intel_encoder
> > ->base);
> > + return port_to_aux_power_domain(intel_dig_port
> > ->port);
> > + case INTEL_OUTPUT_DP_MST:
> > + intel_dig_port = enc_to_mst(&intel_encoder->base)
> > ->primary;
> > + return port_to_aux_power_domain(intel_dig_port
> > ->port);
> > + default:
> > + WARN_ON_ONCE(1);
> > + return POWER_DOMAIN_AUX_A;
> > + }
> > +}
> > +
> > static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
> > {
> > struct drm_device *dev = crtc->dev;
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 4655af0..3978540 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -277,7 +277,7 @@ static void pps_lock(struct intel_dp *intel_dp)
> > * See vlv_power_sequencer_reset() why we need
> > * a power domain reference here.
> > */
> > - power_domain = intel_display_port_power_domain(encoder);
> > + power_domain = intel_display_port_aux_power_domain(encoder);
> > intel_display_power_get(dev_priv, power_domain);
> >
> > mutex_lock(&dev_priv->pps_mutex);
> > @@ -293,7 +293,7 @@ static void pps_unlock(struct intel_dp *intel_dp)
> >
> > mutex_unlock(&dev_priv->pps_mutex);
> >
> > - power_domain = intel_display_port_power_domain(encoder);
> > + power_domain = intel_display_port_aux_power_domain(encoder);
> > intel_display_power_put(dev_priv, power_domain);
> > }
> >
> > @@ -816,8 +816,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> >
> > intel_dp_check_edp(intel_dp);
> >
> > - intel_aux_display_runtime_get(dev_priv);
> > -
> > /* Try to wait for any previous AUX channel activity */
> > for (try = 0; try < 3; try++) {
> > status = I915_READ_NOTRACE(ch_ctl);
> > @@ -926,7 +924,6 @@ done:
> > ret = recv_bytes;
> > out:
> > pm_qos_update_request(&dev_priv->pm_qos,
> > PM_QOS_DEFAULT_VALUE);
> > - intel_aux_display_runtime_put(dev_priv);
> >
> > if (vdd)
> > edp_panel_vdd_off(intel_dp, false);
> > @@ -1784,7 +1781,7 @@ static bool edp_panel_vdd_on(struct intel_dp
> > *intel_dp)
> > if (edp_have_panel_vdd(intel_dp))
> > return need_to_disable;
> >
> > - power_domain =
> > intel_display_port_power_domain(intel_encoder);
> > + power_domain =
> > intel_display_port_aux_power_domain(intel_encoder);
> > intel_display_power_get(dev_priv, power_domain);
> >
> > DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
> > @@ -1874,7 +1871,7 @@ static void edp_panel_vdd_off_sync(struct
> > intel_dp *intel_dp)
> > if ((pp & POWER_TARGET_ON) == 0)
> > intel_dp->last_power_cycle = jiffies;
> >
> > - power_domain =
> > intel_display_port_power_domain(intel_encoder);
> > + power_domain =
> > intel_display_port_aux_power_domain(intel_encoder);
> > intel_display_power_put(dev_priv, power_domain);
> > }
> >
> > @@ -2025,7 +2022,7 @@ static void edp_panel_off(struct intel_dp
> > *intel_dp)
> > wait_panel_off(intel_dp);
> >
> > /* We got a reference when we enabled the VDD. */
> > - power_domain =
> > intel_display_port_power_domain(intel_encoder);
> > + power_domain =
> > intel_display_port_aux_power_domain(intel_encoder);
> > intel_display_power_put(dev_priv, power_domain);
> > }
> >
> > @@ -4765,26 +4762,6 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> > intel_dp->has_audio = false;
> > }
> >
> > -static enum intel_display_power_domain
> > -intel_dp_power_get(struct intel_dp *dp)
> > -{
> > - struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
> > - enum intel_display_power_domain power_domain;
> > -
> > - power_domain = intel_display_port_power_domain(encoder);
> > - intel_display_power_get(to_i915(encoder->base.dev),
> > power_domain);
> > -
> > - return power_domain;
> > -}
> > -
> > -static void
> > -intel_dp_power_put(struct intel_dp *dp,
> > - enum intel_display_power_domain power_domain)
> > -{
> > - struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
> > - intel_display_power_put(to_i915(encoder->base.dev),
> > power_domain);
> > -}
> > -
> > static enum drm_connector_status
> > intel_dp_detect(struct drm_connector *connector, bool force)
> > {
> > @@ -4808,7 +4785,8 @@ intel_dp_detect(struct drm_connector
> > *connector, bool force)
> > return connector_status_disconnected;
> > }
> >
> > - power_domain = intel_dp_power_get(intel_dp);
> > + power_domain =
> > intel_display_port_aux_power_domain(intel_encoder);
> > + intel_display_power_get(to_i915(dev), power_domain);
> >
> > /* Can't disconnect eDP, but you can close the lid... */
> > if (is_edp(intel_dp))
> > @@ -4853,7 +4831,7 @@ intel_dp_detect(struct drm_connector
> > *connector, bool force)
> > }
> >
> > out:
> > - intel_dp_power_put(intel_dp, power_domain);
> > + intel_display_power_put(to_i915(dev), power_domain);
> > return status;
> > }
> >
> > @@ -4862,6 +4840,7 @@ intel_dp_force(struct drm_connector *connector)
> > {
> > struct intel_dp *intel_dp = intel_attached_dp(connector);
> > struct intel_encoder *intel_encoder =
> > &dp_to_dig_port(intel_dp)->base;
> > + struct drm_i915_private *dev_priv = to_i915(intel_encoder
> > ->base.dev);
> > enum intel_display_power_domain power_domain;
> >
> > DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
> > @@ -4871,11 +4850,12 @@ intel_dp_force(struct drm_connector
> > *connector)
> > if (connector->status != connector_status_connected)
> > return;
> >
> > - power_domain = intel_dp_power_get(intel_dp);
> > + power_domain =
> > intel_display_port_aux_power_domain(intel_encoder);
> > + intel_display_power_get(dev_priv, power_domain);
> >
> > intel_dp_set_edid(intel_dp);
> >
> > - intel_dp_power_put(intel_dp, power_domain);
> > + intel_display_power_put(dev_priv, power_domain);
> >
> > if (intel_encoder->type != INTEL_OUTPUT_EDP)
> > intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
> > @@ -5091,7 +5071,7 @@ static void intel_edp_panel_vdd_sanitize(struct
> > intel_dp *intel_dp)
> > * indefinitely.
> > */
> > DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state
> > tracking\n");
> > - power_domain =
> > intel_display_port_power_domain(&intel_dig_port->base);
> > + power_domain =
> > intel_display_port_aux_power_domain(&intel_dig_port->base);
> > intel_display_power_get(dev_priv, power_domain);
> >
> > edp_panel_vdd_schedule_off(intel_dp);
> > @@ -5172,7 +5152,7 @@ intel_dp_hpd_pulse(struct intel_digital_port
> > *intel_dig_port, bool long_hpd)
> > port_name(intel_dig_port->port),
> > long_hpd ? "long" : "short");
> >
> > - power_domain =
> > intel_display_port_power_domain(intel_encoder);
> > + power_domain =
> > intel_display_port_aux_power_domain(intel_encoder);
> > intel_display_power_get(dev_priv, power_domain);
> >
> > if (long_hpd) {
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index a68b6cd..7d11aa0 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1188,6 +1188,8 @@ void hsw_enable_ips(struct intel_crtc *crtc);
> > void hsw_disable_ips(struct intel_crtc *crtc);
> > enum intel_display_power_domain
> > intel_display_port_power_domain(struct intel_encoder
> > *intel_encoder);
> > +enum intel_display_power_domain
> > +intel_display_port_aux_power_domain(struct intel_encoder
> > *intel_encoder);
> > void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> > struct intel_crtc_state
> > *pipe_config);
> > void intel_modeset_preclose(struct drm_device *dev, struct drm_file
> > *file);
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-09 15:48 ` [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well Patrik Jakobsson
@ 2015-11-11 18:57 ` Imre Deak
2015-11-12 12:24 ` Patrik Jakobsson
2015-11-11 19:23 ` Imre Deak
2015-11-16 14:01 ` [PATCH v3 " Patrik Jakobsson
2 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2015-11-11 18:57 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> Handle DC off as a power well where enabling the power well will
> prevent
> the DMC to enter selected DC states (required around modesets and Aux
> A). Disabling the power well will allow DC states again. For now the
> highest DC state is DC6 for Skylake and DC5 for Broxton but will be
> configurable for Skylake in a later patch.
>
> v2: Check both DC5 and DC6 bits in power well enabled function
> (Ville)
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 6 --
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 6 ++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 110
> +++++++++++++++++++++++---------
> 4 files changed, 88 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 5a63f9a..0c7f435 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
>
> static int skl_suspend_complete(struct drm_i915_private *dev_priv)
> {
> - if (dev_priv->csr.dmc_payload)
> - skl_enable_dc6(dev_priv);
> -
> return 0;
> }
>
> @@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct
> drm_i915_private *dev_priv)
>
> static int skl_resume_prepare(struct drm_i915_private *dev_priv)
> {
> - if (dev_priv->csr.dmc_payload)
> - skl_disable_dc6(dev_priv);
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 31b3a84..df445ba 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -636,6 +636,7 @@ enum skl_disp_power_wells {
>
> /* Not actual bit groups. Used as IDs for
> lookup_power_well() */
> SKL_DISP_PW_ALWAYS_ON,
> + SKL_DISP_PW_DC_OFF,
Imo it would be less confusing to call it DC3 power well. Looking at th
e DC spec, DC4 is only a transitory state to DC5/6, so what we expect
when we disable DC6/5 is DC3 or shallower power states (DC2/1/0).
> };
>
> #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 649ac34..856d801 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13320,6 +13320,9 @@ static int intel_atomic_commit(struct
> drm_device *dev,
> to_intel_crtc_state(crtc->state)
> ->update_pipe;
> unsigned long put_domains = 0;
>
> + if (modeset)
> + intel_display_power_get(dev_priv,
> POWER_DOMAIN_MODESET);
> +
> if (modeset && crtc->state->active) {
> update_scanline_offset(to_intel_crtc(crtc));
> dev_priv->display.crtc_enable(crtc);
> @@ -13343,6 +13346,9 @@ static int intel_atomic_commit(struct
> drm_device *dev,
> modeset_put_power_domains(dev_priv,
> put_domains);
>
> intel_post_plane_update(intel_crtc);
> +
> + if (modeset)
> + intel_display_power_put(dev_priv,
> POWER_DOMAIN_MODESET);
> }
>
> /* FIXME: add subpixel order */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index edf753e..95c3fcc 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -49,9 +49,6 @@
> * present for a given platform.
> */
>
> -#define GEN9_ENABLE_DC5(dev) 0
> -#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
> -
> #define for_each_power_well(i, power_well, domain_mask,
> power_domains) \
> for (i = 0;
> \
> i < (power_domains)->power_well_count &&
> \
> @@ -309,9 +306,14 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~( \
> - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> @@ -339,6 +341,10 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_AUX_A) | \
> BIT(POWER_DOMAIN_PLLS) | \
> BIT(POWER_DOMAIN_INIT))
> +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS
> | \
> BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> @@ -486,15 +492,6 @@ static void gen9_enable_dc5(struct
> drm_i915_private *dev_priv)
> gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> }
>
> -static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
> -{
> - assert_can_disable_dc5(dev_priv);
> -
> - DRM_DEBUG_KMS("Disabling DC5\n");
> -
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> -}
> -
> static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> {
> struct drm_device *dev = dev_priv->dev;
> @@ -522,6 +519,14 @@ static void assert_can_disable_dc6(struct
> drm_i915_private *dev_priv)
> "DC6 already programmed to be disabled.\n");
> }
>
> +static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
> +{
> + assert_can_disable_dc5(dev_priv);
> + assert_can_disable_dc6(dev_priv);
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +}
> +
> void skl_enable_dc6(struct drm_i915_private *dev_priv)
> {
> assert_can_enable_dc6(dev_priv);
> @@ -571,6 +576,7 @@ static void skl_set_power_well(struct
> drm_i915_private *dev_priv,
> case SKL_DISP_PW_DDI_C:
> case SKL_DISP_PW_DDI_D:
> case SKL_DISP_PW_MISC_IO:
> + case SKL_DISP_PW_DC_OFF:
> break;
> default:
> WARN(1, "Unknown power well %lu\n", power_well
> ->data);
> @@ -589,17 +595,13 @@ static void skl_set_power_well(struct
> drm_i915_private *dev_priv,
> "Invalid for power well status to be
> enabled, unless done by the BIOS, \
> when request is to disable!\n");
> if (power_well->data == SKL_DISP_PW_2) {
> - if (GEN9_ENABLE_DC5(dev))
> - gen9_disable_dc5(dev_priv);
> - if (SKL_ENABLE_DC6(dev)) {
> - /*
> - * DDI buffer programming
> unnecessary during driver-load/resume
> - * as it's already done
> during modeset initialization then.
> - * It's also invalid here as
> encoder list is still uninitialized.
> - */
> - if (!dev_priv
> ->power_domains.initializing)
> - intel_prepare_ddi(de
> v);
> - }
> + /*
> + * DDI buffer programming
> unnecessary during driver-load/resume
> + * as it's already done during
> modeset initialization then.
> + * It's also invalid here as encoder
> list is still uninitialized.
> + */
> + if (!dev_priv
> ->power_domains.initializing)
> + intel_prepare_ddi(dev);
> }
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp |
> req_mask);
> }
> @@ -617,10 +619,6 @@ static void skl_set_power_well(struct
> drm_i915_private *dev_priv,
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp &
> ~req_mask);
> POSTING_READ(HSW_PWR_WELL_DRIVER);
> DRM_DEBUG_KMS("Disabling %s\n", power_well
> ->name);
> -
> - if (GEN9_ENABLE_DC5(dev) &&
> - power_well->data == SKL_DISP_PW_2)
> - gen9_enable_dc5(dev_priv);
> }
> }
>
> @@ -695,6 +693,40 @@ static void skl_power_well_disable(struct
> drm_i915_private *dev_priv,
> skl_set_power_well(dev_priv, power_well, false);
> }
>
> +static bool gen9_dc_off_power_well_enabled(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + return (I915_READ(DC_STATE_EN) &
> DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> +}
> +
> +static void gen9_dc_off_power_well_enable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + gen9_disable_dc5_dc6(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + if (IS_SKYLAKE(dev_priv))
> + skl_enable_dc6(dev_priv);
> + else
> + gen9_enable_dc5(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + if (power_well->count > 0) {
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + } else {
> + if (IS_SKYLAKE(dev_priv))
> + gen9_set_dc_state(dev_priv,
> DC_STATE_EN_UPTO_DC6);
> + else
> + gen9_set_dc_state(dev_priv,
> DC_STATE_EN_UPTO_DC5);
> + }
> +}
> +
> static void i9xx_always_on_power_well_noop(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> @@ -1517,6 +1549,13 @@ static const struct i915_power_well_ops
> skl_power_well_ops = {
> .is_enabled = skl_power_well_enabled,
> };
>
> +static const struct i915_power_well_ops gen9_dc_off_power_well_ops =
> {
> + .sync_hw = gen9_dc_off_power_well_sync_hw,
> + .enable = gen9_dc_off_power_well_enable,
> + .disable = gen9_dc_off_power_well_disable,
> + .is_enabled = gen9_dc_off_power_well_enabled,
> +};
> +
> static struct i915_power_well hsw_power_wells[] = {
> {
> .name = "always-on",
> @@ -1697,6 +1736,12 @@ static struct i915_power_well
> skl_power_wells[] = {
> .data = SKL_DISP_PW_2,
> },
> {
> + .name = "DC off",
> + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .data = SKL_DISP_PW_DC_OFF,
> + },
> + {
> .name = "DDI A/E power well",
> .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> @@ -1769,7 +1814,14 @@ static struct i915_power_well
> bxt_power_wells[] = {
> .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> .data = SKL_DISP_PW_2,
> - }
> + },
> + {
> + .name = "DC off",
> + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .data = SKL_DISP_PW_DC_OFF,
> + },
> +
> };
>
> #define set_power_wells(power_domains, __power_wells) ({
> \
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 11/12] drm/i915/gen9: Add boot parameter for disabling DC6
2015-11-09 15:48 ` [PATCH v2 11/12] drm/i915/gen9: Add boot parameter for disabling DC6 Patrik Jakobsson
@ 2015-11-11 19:04 ` Imre Deak
2015-11-12 12:51 ` Patrik Jakobsson
2015-11-16 14:01 ` [PATCH v3 " Patrik Jakobsson
1 sibling, 1 reply; 47+ messages in thread
From: Imre Deak @ 2015-11-11 19:04 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> v2: Use _unsafe (Jani)
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_params.c | 6 ++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
> 3 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index c0252ef..5628c5a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2639,6 +2639,7 @@ struct i915_params {
> int panel_use_ssc;
> int vbt_sdvo_panel_type;
> int enable_rc6;
> + int enable_dc6;
> int enable_fbc;
> int enable_ppgtt;
> int enable_execlists;
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 368df67..6457f3a 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -32,6 +32,7 @@ struct i915_params i915 __read_mostly = {
> .panel_use_ssc = -1,
> .vbt_sdvo_panel_type = -1,
> .enable_rc6 = -1,
> + .enable_dc6 = 1,
> .enable_fbc = -1,
> .enable_execlists = -1,
> .enable_hangcheck = true,
> @@ -79,6 +80,11 @@ MODULE_PARM_DESC(enable_rc6,
> "For example, 3 would enable rc6 and deep rc6, and 7 would
> enable everything. "
> "default: -1 (use per-chip default)");
>
> +module_param_named_unsafe(enable_dc6, i915.enable_dc6, int, 0400);
> +MODULE_PARM_DESC(enable_dc6,
> + "Enable power-saving display C-state 6. "
> + "(0 = disable; 1 = enable [default])");
> +
It would be more generic to have something like enable_dc, -1=per-chip
default, 0=disable, 1=up to dc5, 2=up to dc6.
> module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600);
> MODULE_PARM_DESC(enable_fbc,
> "Enable frame buffer compression for power savings "
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 95c3fcc..62c1273 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -708,7 +708,7 @@ static void gen9_dc_off_power_well_enable(struct
> drm_i915_private *dev_priv,
> static void gen9_dc_off_power_well_disable(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> - if (IS_SKYLAKE(dev_priv))
> + if (IS_SKYLAKE(dev_priv) && i915.enable_dc6)
> skl_enable_dc6(dev_priv);
> else
> gen9_enable_dc5(dev_priv);
> @@ -720,7 +720,7 @@ static void gen9_dc_off_power_well_sync_hw(struct
> drm_i915_private *dev_priv,
> if (power_well->count > 0) {
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> } else {
> - if (IS_SKYLAKE(dev_priv))
> + if (IS_SKYLAKE(dev_priv) && i915.enable_dc6)
> gen9_set_dc_state(dev_priv,
> DC_STATE_EN_UPTO_DC6);
> else
> gen9_set_dc_state(dev_priv,
> DC_STATE_EN_UPTO_DC5);
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 01/12] drm/i915: Don't trust CSR program memory contents
2015-11-09 15:48 ` [PATCH 01/12] drm/i915: Don't trust CSR program memory contents Patrik Jakobsson
@ 2015-11-11 19:05 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2015-11-11 19:05 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> Replaces "drm/i915: Force loading of csr program at boot" in the old
> series.
>
> Previously we called blindly into intel_csr_load_program() and
> depended
> on a check of whether the CSR program memory was cleared or not.
> This check is not reliable and no longer needed since we fixed the
> call-sites of intel_csr_load_program().
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_csr.c | 10 +++-------
> 1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index ecb7c70..ad8bc7a 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -220,14 +220,10 @@ void intel_csr_load_program(struct
> drm_i915_private *dev_priv)
> return;
> }
>
> - /*
> - * FIXME: Firmware gets lost on S3/S4, but not when entering
> system
> - * standby or suspend-to-idle (which is just like forced
> runtime pm).
> - * Unfortunately the ACPI subsystem doesn't yet give us a
> way to
> - * differentiate this, hence figure it out with this hack.
> - */
> - if ((!dev_priv->csr.dmc_payload) ||
> I915_READ(CSR_PROGRAM(0)))
> + if (!dev_priv->csr.dmc_payload) {
> + DRM_ERROR("Tried to program CSR with empty
> payload\n");
> return;
> + }
>
> fw_size = dev_priv->csr.dmc_fw_size;
> for (i = 0; i < fw_size; i++)
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 02/12] drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6
2015-11-09 15:48 ` [PATCH 02/12] drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6 Patrik Jakobsson
@ 2015-11-11 19:08 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2015-11-11 19:08 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> Move call to gen9_set_dc_state_debugmask_memory_up() into
> gen9_set_dc_state() to prevent us missing it somewhere.
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 35 ++++++++++++++++-------
> ----------
> 1 file changed, 17 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 5a36dd5..4b9ee60 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -395,6 +395,20 @@ static void assert_can_disable_dc9(struct
> drm_i915_private *dev_priv)
> */
> }
>
> +static void gen9_set_dc_state_debugmask_memory_up(
> + struct drm_i915_private *dev_priv)
> +{
> + uint32_t val;
> +
> + /* The below bit doesn't need to be cleared ever afterwards
> */
> + val = I915_READ(DC_STATE_DEBUG);
> + if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
> + val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
> + I915_WRITE(DC_STATE_DEBUG, val);
> + POSTING_READ(DC_STATE_DEBUG);
> + }
> +}
> +
> static void gen9_set_dc_state(struct drm_i915_private *dev_priv,
> uint32_t state)
> {
> uint32_t val;
> @@ -408,6 +422,9 @@ static void gen9_set_dc_state(struct
> drm_i915_private *dev_priv, uint32_t state)
>
> WARN_ON_ONCE(state & ~mask);
>
> + if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
> + gen9_set_dc_state_debugmask_memory_up(dev_priv);
> +
> val = I915_READ(DC_STATE_EN);
> DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", val &
> mask, state);
> val &= ~mask;
> @@ -434,20 +451,6 @@ void bxt_disable_dc9(struct drm_i915_private
> *dev_priv)
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> }
>
> -static void gen9_set_dc_state_debugmask_memory_up(
> - struct drm_i915_private *dev_priv)
> -{
> - uint32_t val;
> -
> - /* The below bit doesn't need to be cleared ever afterwards
> */
> - val = I915_READ(DC_STATE_DEBUG);
> - if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
> - val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
> - I915_WRITE(DC_STATE_DEBUG, val);
> - POSTING_READ(DC_STATE_DEBUG);
> - }
> -}
> -
> void assert_csr_loaded(struct drm_i915_private *dev_priv)
> {
> WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
> @@ -496,8 +499,6 @@ static void gen9_enable_dc5(struct
> drm_i915_private *dev_priv)
>
> DRM_DEBUG_KMS("Enabling DC5\n");
>
> - gen9_set_dc_state_debugmask_memory_up(dev_priv);
> -
> gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> }
>
> @@ -543,8 +544,6 @@ void skl_enable_dc6(struct drm_i915_private
> *dev_priv)
>
> DRM_DEBUG_KMS("Enabling DC6\n");
>
> - gen9_set_dc_state_debugmask_memory_up(dev_priv);
> -
> gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
>
> }
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 06/12] drm/i915: Remove distinction between DDI 2 vs 4 lanes
2015-11-09 15:48 ` [PATCH 06/12] drm/i915: Remove distinction between DDI 2 vs 4 lanes Patrik Jakobsson
@ 2015-11-11 19:10 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2015-11-11 19:10 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> We never make use of the distinction between 2 vs 4 lanes so combine
> them into a per port domain instead. This saves us a few bits in the
> power domain mask. Change suggested by Ville.
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 28 +++++--------
> drivers/gpu/drm/i915/i915_drv.h | 14 +++----
> drivers/gpu/drm/i915/intel_display.c | 10 ++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 71 ++++++++++++-----------
> ----------
> 4 files changed, 45 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 40ec895..2fad0a9 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2706,24 +2706,16 @@ static const char *power_domain_str(enum
> intel_display_power_domain domain)
> return "TRANSCODER_C";
> case POWER_DOMAIN_TRANSCODER_EDP:
> return "TRANSCODER_EDP";
> - case POWER_DOMAIN_PORT_DDI_A_2_LANES:
> - return "PORT_DDI_A_2_LANES";
> - case POWER_DOMAIN_PORT_DDI_A_4_LANES:
> - return "PORT_DDI_A_4_LANES";
> - case POWER_DOMAIN_PORT_DDI_B_2_LANES:
> - return "PORT_DDI_B_2_LANES";
> - case POWER_DOMAIN_PORT_DDI_B_4_LANES:
> - return "PORT_DDI_B_4_LANES";
> - case POWER_DOMAIN_PORT_DDI_C_2_LANES:
> - return "PORT_DDI_C_2_LANES";
> - case POWER_DOMAIN_PORT_DDI_C_4_LANES:
> - return "PORT_DDI_C_4_LANES";
> - case POWER_DOMAIN_PORT_DDI_D_2_LANES:
> - return "PORT_DDI_D_2_LANES";
> - case POWER_DOMAIN_PORT_DDI_D_4_LANES:
> - return "PORT_DDI_D_4_LANES";
> - case POWER_DOMAIN_PORT_DDI_E_2_LANES:
> - return "PORT_DDI_E_2_LANES";
> + case POWER_DOMAIN_PORT_DDI_A_LANES:
> + return "PORT_DDI_A_LANES";
> + case POWER_DOMAIN_PORT_DDI_B_LANES:
> + return "PORT_DDI_B_LANES";
> + case POWER_DOMAIN_PORT_DDI_C_LANES:
> + return "PORT_DDI_C_LANES";
> + case POWER_DOMAIN_PORT_DDI_D_LANES:
> + return "PORT_DDI_D_LANES";
> + case POWER_DOMAIN_PORT_DDI_E_LANES:
> + return "PORT_DDI_E_LANES";
> case POWER_DOMAIN_PORT_DSI:
> return "PORT_DSI";
> case POWER_DOMAIN_PORT_CRT:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index cef0588..fff7f63 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -180,15 +180,11 @@ enum intel_display_power_domain {
> POWER_DOMAIN_TRANSCODER_B,
> POWER_DOMAIN_TRANSCODER_C,
> POWER_DOMAIN_TRANSCODER_EDP,
> - POWER_DOMAIN_PORT_DDI_A_2_LANES,
> - POWER_DOMAIN_PORT_DDI_A_4_LANES,
> - POWER_DOMAIN_PORT_DDI_B_2_LANES,
> - POWER_DOMAIN_PORT_DDI_B_4_LANES,
> - POWER_DOMAIN_PORT_DDI_C_2_LANES,
> - POWER_DOMAIN_PORT_DDI_C_4_LANES,
> - POWER_DOMAIN_PORT_DDI_D_2_LANES,
> - POWER_DOMAIN_PORT_DDI_D_4_LANES,
> - POWER_DOMAIN_PORT_DDI_E_2_LANES,
> + POWER_DOMAIN_PORT_DDI_A_LANES,
> + POWER_DOMAIN_PORT_DDI_B_LANES,
> + POWER_DOMAIN_PORT_DDI_C_LANES,
> + POWER_DOMAIN_PORT_DDI_D_LANES,
> + POWER_DOMAIN_PORT_DDI_E_LANES,
> POWER_DOMAIN_PORT_DSI,
> POWER_DOMAIN_PORT_CRT,
> POWER_DOMAIN_PORT_OTHER,
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index c2578d9..649ac34 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5128,15 +5128,15 @@ static enum intel_display_power_domain
> port_to_power_domain(enum port port)
> {
> switch (port) {
> case PORT_A:
> - return POWER_DOMAIN_PORT_DDI_A_4_LANES;
> + return POWER_DOMAIN_PORT_DDI_A_LANES;
> case PORT_B:
> - return POWER_DOMAIN_PORT_DDI_B_4_LANES;
> + return POWER_DOMAIN_PORT_DDI_B_LANES;
> case PORT_C:
> - return POWER_DOMAIN_PORT_DDI_C_4_LANES;
> + return POWER_DOMAIN_PORT_DDI_C_LANES;
> case PORT_D:
> - return POWER_DOMAIN_PORT_DDI_D_4_LANES;
> + return POWER_DOMAIN_PORT_DDI_D_LANES;
> case PORT_E:
> - return POWER_DOMAIN_PORT_DDI_E_2_LANES;
> + return POWER_DOMAIN_PORT_DDI_E_LANES;
> default:
> WARN_ON_ONCE(1);
> return POWER_DOMAIN_PORT_OTHER;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index c9cb94d..fc206bb 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -286,13 +286,10 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_TRANSCODER_C) | \
> BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> BIT(POWER_DOMAIN_AUX_B) | \
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_AUX_D) | \
> @@ -300,21 +297,17 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_VGA) | \
> BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~( \
> @@ -329,10 +322,8 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_TRANSCODER_C) | \
> BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_AUX_B) | \
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_AUDIO) | \
> @@ -344,8 +335,7 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_PIPE_A) | \
> BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
> BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> BIT(POWER_DOMAIN_AUX_A) | \
> BIT(POWER_DOMAIN_PLLS) | \
> BIT(POWER_DOMAIN_INIT))
> @@ -1420,14 +1410,10 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
> BIT(POWER_DOMAIN_PIPE_A) | \
> BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
> - BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT(POWER_DOMAIN_PORT_CRT) | \
> BIT(POWER_DOMAIN_PLLS) | \
> BIT(POWER_DOMAIN_AUX_A) | \
> @@ -1451,49 +1437,42 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
>
> #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_PORT_CRT) | \
> BIT(POWER_DOMAIN_AUX_B) | \
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> BIT(POWER_DOMAIN_AUX_B) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> BIT(POWER_DOMAIN_AUX_B) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_AUX_B) | \
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT(POWER_DOMAIN_AUX_D) | \
> BIT(POWER_DOMAIN_INIT))
>
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 07/12] drm/i915: Add a modeset power domain
2015-11-09 15:48 ` [PATCH 07/12] drm/i915: Add a modeset power domain Patrik Jakobsson
@ 2015-11-11 19:11 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2015-11-11 19:11 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> We need a power domain for disabling DC5/DC6 around modesets to
> prevent
> confusing the DMC.
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 2fad0a9..0b06192 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2738,6 +2738,8 @@ static const char *power_domain_str(enum
> intel_display_power_domain domain)
> return "AUX_D";
> case POWER_DOMAIN_GMBUS:
> return "GMBUS";
> + case POWER_DOMAIN_MODESET:
> + return "MODESET";
> case POWER_DOMAIN_INIT:
> return "INIT";
> default:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index fff7f63..c0252ef 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -196,6 +196,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_AUX_C,
> POWER_DOMAIN_AUX_D,
> POWER_DOMAIN_GMBUS,
> + POWER_DOMAIN_MODESET,
> POWER_DOMAIN_INIT,
>
> POWER_DOMAIN_NUM,
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 09/12] drm/i915: Explain usage of power well IDs vs bit groups
2015-11-09 15:48 ` [PATCH 09/12] drm/i915: Explain usage of power well IDs vs bit groups Patrik Jakobsson
@ 2015-11-11 19:13 ` Imre Deak
2015-11-12 13:15 ` Patrik Jakobsson
2015-11-16 14:01 ` [PATCH v2 " Patrik Jakobsson
1 sibling, 1 reply; 47+ messages in thread
From: Imre Deak @ 2015-11-11 19:13 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index e6d88f5..31b3a84 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -621,6 +621,7 @@ enum punit_power_well {
> PUNIT_POWER_WELL_DPIO_RX1 = 11,
> PUNIT_POWER_WELL_DPIO_CMN_D = 12,
>
> + /* Not actual bit groups. Used as IDs for
> lookup_power_well() */
> PUNIT_POWER_WELL_ALWAYS_ON,
> };
>
> @@ -633,6 +634,7 @@ enum skl_disp_power_wells {
> SKL_DISP_PW_1 = 14,
> SKL_DISP_PW_2,
>
> + /* Not actual bit groups. Used as IDs for
> lookup_power_well() */
It would be good to mention that these IDs are fixed since they are
also used to index HW flags. With that fixed:
Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> SKL_DISP_PW_ALWAYS_ON,
> };
>
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-09 15:48 ` [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well Patrik Jakobsson
2015-11-11 18:57 ` Imre Deak
@ 2015-11-11 19:23 ` Imre Deak
2015-11-12 12:55 ` Patrik Jakobsson
2015-11-16 14:01 ` [PATCH v3 " Patrik Jakobsson
2 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2015-11-11 19:23 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> Handle DC off as a power well where enabling the power well will
> prevent
> the DMC to enter selected DC states (required around modesets and Aux
> A). Disabling the power well will allow DC states again. For now the
> highest DC state is DC6 for Skylake and DC5 for Broxton but will be
> configurable for Skylake in a later patch.
>
> v2: Check both DC5 and DC6 bits in power well enabled function
> (Ville)
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 6 --
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 6 ++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 110
> +++++++++++++++++++++++---------
> 4 files changed, 88 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 5a63f9a..0c7f435 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
>
> static int skl_suspend_complete(struct drm_i915_private *dev_priv)
> {
> - if (dev_priv->csr.dmc_payload)
> - skl_enable_dc6(dev_priv);
> -
> return 0;
> }
>
> @@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct
> drm_i915_private *dev_priv)
>
> static int skl_resume_prepare(struct drm_i915_private *dev_priv)
> {
> - if (dev_priv->csr.dmc_payload)
> - skl_disable_dc6(dev_priv);
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 31b3a84..df445ba 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -636,6 +636,7 @@ enum skl_disp_power_wells {
>
> /* Not actual bit groups. Used as IDs for
> lookup_power_well() */
> SKL_DISP_PW_ALWAYS_ON,
> + SKL_DISP_PW_DC_OFF,
> };
>
> #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 649ac34..856d801 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13320,6 +13320,9 @@ static int intel_atomic_commit(struct
> drm_device *dev,
> to_intel_crtc_state(crtc->state)
> ->update_pipe;
> unsigned long put_domains = 0;
>
> + if (modeset)
> + intel_display_power_get(dev_priv,
> POWER_DOMAIN_MODESET);
> +
> if (modeset && crtc->state->active) {
> update_scanline_offset(to_intel_crtc(crtc));
> dev_priv->display.crtc_enable(crtc);
> @@ -13343,6 +13346,9 @@ static int intel_atomic_commit(struct
> drm_device *dev,
> modeset_put_power_domains(dev_priv,
> put_domains);
>
> intel_post_plane_update(intel_crtc);
> +
> + if (modeset)
> + intel_display_power_put(dev_priv,
> POWER_DOMAIN_MODESET);
> }
>
> /* FIXME: add subpixel order */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index edf753e..95c3fcc 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -49,9 +49,6 @@
> * present for a given platform.
> */
>
> -#define GEN9_ENABLE_DC5(dev) 0
> -#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
> -
> #define for_each_power_well(i, power_well, domain_mask,
> power_domains) \
> for (i = 0;
> \
> i < (power_domains)->power_well_count &&
> \
> @@ -309,9 +306,14 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~( \
> - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> @@ -339,6 +341,10 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_AUX_A) | \
> BIT(POWER_DOMAIN_PLLS) | \
> BIT(POWER_DOMAIN_INIT))
> +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS
> | \
> BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> @@ -486,15 +492,6 @@ static void gen9_enable_dc5(struct
> drm_i915_private *dev_priv)
> gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> }
>
> -static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
> -{
> - assert_can_disable_dc5(dev_priv);
> -
> - DRM_DEBUG_KMS("Disabling DC5\n");
> -
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> -}
> -
> static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> {
> struct drm_device *dev = dev_priv->dev;
> @@ -522,6 +519,14 @@ static void assert_can_disable_dc6(struct
> drm_i915_private *dev_priv)
> "DC6 already programmed to be disabled.\n");
> }
>
> +static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
> +{
> + assert_can_disable_dc5(dev_priv);
> + assert_can_disable_dc6(dev_priv);
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +}
> +
> void skl_enable_dc6(struct drm_i915_private *dev_priv)
> {
> assert_can_enable_dc6(dev_priv);
> @@ -571,6 +576,7 @@ static void skl_set_power_well(struct
> drm_i915_private *dev_priv,
> case SKL_DISP_PW_DDI_C:
> case SKL_DISP_PW_DDI_D:
> case SKL_DISP_PW_MISC_IO:
> + case SKL_DISP_PW_DC_OFF:
Why is this needed? I think this function won't be called for DC5/6.
> break;
> default:
> WARN(1, "Unknown power well %lu\n", power_well
> ->data);
> @@ -589,17 +595,13 @@ static void skl_set_power_well(struct
> drm_i915_private *dev_priv,
> "Invalid for power well status to be
> enabled, unless done by the BIOS, \
> when request is to disable!\n");
> if (power_well->data == SKL_DISP_PW_2) {
> - if (GEN9_ENABLE_DC5(dev))
> - gen9_disable_dc5(dev_priv);
> - if (SKL_ENABLE_DC6(dev)) {
> - /*
> - * DDI buffer programming
> unnecessary during driver-load/resume
> - * as it's already done
> during modeset initialization then.
> - * It's also invalid here as
> encoder list is still uninitialized.
> - */
> - if (!dev_priv
> ->power_domains.initializing)
> - intel_prepare_ddi(de
> v);
> - }
> + /*
> + * DDI buffer programming
> unnecessary during driver-load/resume
> + * as it's already done during
> modeset initialization then.
> + * It's also invalid here as encoder
> list is still uninitialized.
> + */
> + if (!dev_priv
> ->power_domains.initializing)
> + intel_prepare_ddi(dev);
> }
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp |
> req_mask);
> }
> @@ -617,10 +619,6 @@ static void skl_set_power_well(struct
> drm_i915_private *dev_priv,
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp &
> ~req_mask);
> POSTING_READ(HSW_PWR_WELL_DRIVER);
> DRM_DEBUG_KMS("Disabling %s\n", power_well
> ->name);
> -
> - if (GEN9_ENABLE_DC5(dev) &&
> - power_well->data == SKL_DISP_PW_2)
> - gen9_enable_dc5(dev_priv);
> }
> }
>
> @@ -695,6 +693,40 @@ static void skl_power_well_disable(struct
> drm_i915_private *dev_priv,
> skl_set_power_well(dev_priv, power_well, false);
> }
>
> +static bool gen9_dc_off_power_well_enabled(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + return (I915_READ(DC_STATE_EN) &
> DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> +}
> +
> +static void gen9_dc_off_power_well_enable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + gen9_disable_dc5_dc6(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + if (IS_SKYLAKE(dev_priv))
> + skl_enable_dc6(dev_priv);
> + else
> + gen9_enable_dc5(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + if (power_well->count > 0) {
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + } else {
> + if (IS_SKYLAKE(dev_priv))
> + gen9_set_dc_state(dev_priv,
> DC_STATE_EN_UPTO_DC6);
> + else
> + gen9_set_dc_state(dev_priv,
> DC_STATE_EN_UPTO_DC5);
> + }
> +}
> +
> static void i9xx_always_on_power_well_noop(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> @@ -1517,6 +1549,13 @@ static const struct i915_power_well_ops
> skl_power_well_ops = {
> .is_enabled = skl_power_well_enabled,
> };
>
> +static const struct i915_power_well_ops gen9_dc_off_power_well_ops =
> {
> + .sync_hw = gen9_dc_off_power_well_sync_hw,
> + .enable = gen9_dc_off_power_well_enable,
> + .disable = gen9_dc_off_power_well_disable,
> + .is_enabled = gen9_dc_off_power_well_enabled,
> +};
> +
> static struct i915_power_well hsw_power_wells[] = {
> {
> .name = "always-on",
> @@ -1697,6 +1736,12 @@ static struct i915_power_well
> skl_power_wells[] = {
> .data = SKL_DISP_PW_2,
> },
> {
> + .name = "DC off",
> + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .data = SKL_DISP_PW_DC_OFF,
> + },
> + {
> .name = "DDI A/E power well",
> .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> @@ -1769,7 +1814,14 @@ static struct i915_power_well
> bxt_power_wells[] = {
> .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> .data = SKL_DISP_PW_2,
> - }
> + },
> + {
> + .name = "DC off",
> + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .data = SKL_DISP_PW_DC_OFF,
> + },
> +
> };
>
> #define set_power_wells(power_domains, __power_wells) ({
> \
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 03/12] drm/i915: Clean up AUX power domain handling
2015-11-11 18:37 ` Ville Syrjälä
@ 2015-11-12 9:02 ` Patrik Jakobsson
2015-11-12 10:15 ` Ville Syrjälä
0 siblings, 1 reply; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-12 9:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Nov 11, 2015 at 08:37:36PM +0200, Ville Syrjälä wrote:
> On Wed, Nov 11, 2015 at 08:22:03PM +0200, Imre Deak wrote:
> > On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Introduce intel_display_port_aux_power_domain() which simply returns
> > > the appropriate AUX power domain for a specific port, and then
> > > replace
> > > the intel_display_port_power_domain() with calls to the new function
> > > in the DP code. As long as we're not actually enabling the port we
> > > don't
> > > need the lane power domains, and those are handled now purely from
> > > modeset_update_crtc_power_domains().
> > >
> > > My initial motivation for this was to see if I could keep the DPIO
> > > power
> > > wells powered down while doing AUX on CHV, but turns out I can't so
> > > this
> > > doesn't change anything for CHV at least. But I think it's still a
> > > worthwile change.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 40
> > > ++++++++++++++++++++++++++++++
> > > drivers/gpu/drm/i915/intel_dp.c | 48 +++++++++++---------------
> > > ----------
> > > drivers/gpu/drm/i915/intel_drv.h | 2 ++
> > > 3 files changed, 56 insertions(+), 34 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index d0fec07..c2578d9 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -5143,6 +5143,23 @@ static enum intel_display_power_domain
> > > port_to_power_domain(enum port port)
> > > }
> > > }
> > >
> > > +static enum intel_display_power_domain port_to_aux_power_domain(enum
> > > port port)
> > > +{
> > > + switch (port) {
> > > + case PORT_A:
> > > + return POWER_DOMAIN_AUX_A;
> > > + case PORT_B:
> > > + return POWER_DOMAIN_AUX_B;
> > > + case PORT_C:
> > > + return POWER_DOMAIN_AUX_C;
> > > + case PORT_D:
> > > + return POWER_DOMAIN_AUX_D;
> > > + default:
> > > + WARN_ON_ONCE(1);
> > > + return POWER_DOMAIN_AUX_A;
> > > + }
> > > +}
> >
> > Looks like port E is missing. I chatted with Ville he has some idea to
> > fix this.
>
> Yeah, so there's no dedicated AUX block for port E, and instead VBT
> tells us which AUX block to use. The current code doin that is rather
> messy, but I have a cleaned it up during my register type-safety
> journey. I just reposted the remaining AUX related patches [1] from
> that series.
>
> So I was thinking that we could include an 'enum port aux_port' inside
> intel_dp, and use that to pick the right power domain.
>
> [1] http://lists.freedesktop.org/archives/intel-gfx/2015-November/079918.html
Ok so one of Aux A-D is hardwired to port E and only VBT can tell us which? Do
we need to change anything in this patch or can we add the aux_port enum later
on?
>
> >
> > > +
> > > #define for_each_power_domain(domain, mask)
> > > \
> > > for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)
> > > \
> > > if ((1 << (domain)) & (mask))
> > > @@ -5174,6 +5191,29 @@ intel_display_port_power_domain(struct
> > > intel_encoder *intel_encoder)
> > > }
> > > }
> > >
> > > +enum intel_display_power_domain
> > > +intel_display_port_aux_power_domain(struct intel_encoder
> > > *intel_encoder)
> > > +{
> > > + struct drm_device *dev = intel_encoder->base.dev;
> > > + struct intel_digital_port *intel_dig_port;
> > > +
> > > + switch (intel_encoder->type) {
> > > + case INTEL_OUTPUT_UNKNOWN:
> > > + /* Only DDI platforms should ever use this output
> > > type */
> > > + WARN_ON_ONCE(!HAS_DDI(dev));
> > > + case INTEL_OUTPUT_DISPLAYPORT:
> > > + case INTEL_OUTPUT_EDP:
> > > + intel_dig_port = enc_to_dig_port(&intel_encoder
> > > ->base);
> > > + return port_to_aux_power_domain(intel_dig_port
> > > ->port);
> > > + case INTEL_OUTPUT_DP_MST:
> > > + intel_dig_port = enc_to_mst(&intel_encoder->base)
> > > ->primary;
> > > + return port_to_aux_power_domain(intel_dig_port
> > > ->port);
> > > + default:
> > > + WARN_ON_ONCE(1);
> > > + return POWER_DOMAIN_AUX_A;
> > > + }
> > > +}
> > > +
> > > static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
> > > {
> > > struct drm_device *dev = crtc->dev;
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 4655af0..3978540 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -277,7 +277,7 @@ static void pps_lock(struct intel_dp *intel_dp)
> > > * See vlv_power_sequencer_reset() why we need
> > > * a power domain reference here.
> > > */
> > > - power_domain = intel_display_port_power_domain(encoder);
> > > + power_domain = intel_display_port_aux_power_domain(encoder);
> > > intel_display_power_get(dev_priv, power_domain);
> > >
> > > mutex_lock(&dev_priv->pps_mutex);
> > > @@ -293,7 +293,7 @@ static void pps_unlock(struct intel_dp *intel_dp)
> > >
> > > mutex_unlock(&dev_priv->pps_mutex);
> > >
> > > - power_domain = intel_display_port_power_domain(encoder);
> > > + power_domain = intel_display_port_aux_power_domain(encoder);
> > > intel_display_power_put(dev_priv, power_domain);
> > > }
> > >
> > > @@ -816,8 +816,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> > >
> > > intel_dp_check_edp(intel_dp);
> > >
> > > - intel_aux_display_runtime_get(dev_priv);
> > > -
> > > /* Try to wait for any previous AUX channel activity */
> > > for (try = 0; try < 3; try++) {
> > > status = I915_READ_NOTRACE(ch_ctl);
> > > @@ -926,7 +924,6 @@ done:
> > > ret = recv_bytes;
> > > out:
> > > pm_qos_update_request(&dev_priv->pm_qos,
> > > PM_QOS_DEFAULT_VALUE);
> > > - intel_aux_display_runtime_put(dev_priv);
> > >
> > > if (vdd)
> > > edp_panel_vdd_off(intel_dp, false);
> > > @@ -1784,7 +1781,7 @@ static bool edp_panel_vdd_on(struct intel_dp
> > > *intel_dp)
> > > if (edp_have_panel_vdd(intel_dp))
> > > return need_to_disable;
> > >
> > > - power_domain =
> > > intel_display_port_power_domain(intel_encoder);
> > > + power_domain =
> > > intel_display_port_aux_power_domain(intel_encoder);
> > > intel_display_power_get(dev_priv, power_domain);
> > >
> > > DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
> > > @@ -1874,7 +1871,7 @@ static void edp_panel_vdd_off_sync(struct
> > > intel_dp *intel_dp)
> > > if ((pp & POWER_TARGET_ON) == 0)
> > > intel_dp->last_power_cycle = jiffies;
> > >
> > > - power_domain =
> > > intel_display_port_power_domain(intel_encoder);
> > > + power_domain =
> > > intel_display_port_aux_power_domain(intel_encoder);
> > > intel_display_power_put(dev_priv, power_domain);
> > > }
> > >
> > > @@ -2025,7 +2022,7 @@ static void edp_panel_off(struct intel_dp
> > > *intel_dp)
> > > wait_panel_off(intel_dp);
> > >
> > > /* We got a reference when we enabled the VDD. */
> > > - power_domain =
> > > intel_display_port_power_domain(intel_encoder);
> > > + power_domain =
> > > intel_display_port_aux_power_domain(intel_encoder);
> > > intel_display_power_put(dev_priv, power_domain);
> > > }
> > >
> > > @@ -4765,26 +4762,6 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> > > intel_dp->has_audio = false;
> > > }
> > >
> > > -static enum intel_display_power_domain
> > > -intel_dp_power_get(struct intel_dp *dp)
> > > -{
> > > - struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
> > > - enum intel_display_power_domain power_domain;
> > > -
> > > - power_domain = intel_display_port_power_domain(encoder);
> > > - intel_display_power_get(to_i915(encoder->base.dev),
> > > power_domain);
> > > -
> > > - return power_domain;
> > > -}
> > > -
> > > -static void
> > > -intel_dp_power_put(struct intel_dp *dp,
> > > - enum intel_display_power_domain power_domain)
> > > -{
> > > - struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
> > > - intel_display_power_put(to_i915(encoder->base.dev),
> > > power_domain);
> > > -}
> > > -
> > > static enum drm_connector_status
> > > intel_dp_detect(struct drm_connector *connector, bool force)
> > > {
> > > @@ -4808,7 +4785,8 @@ intel_dp_detect(struct drm_connector
> > > *connector, bool force)
> > > return connector_status_disconnected;
> > > }
> > >
> > > - power_domain = intel_dp_power_get(intel_dp);
> > > + power_domain =
> > > intel_display_port_aux_power_domain(intel_encoder);
> > > + intel_display_power_get(to_i915(dev), power_domain);
> > >
> > > /* Can't disconnect eDP, but you can close the lid... */
> > > if (is_edp(intel_dp))
> > > @@ -4853,7 +4831,7 @@ intel_dp_detect(struct drm_connector
> > > *connector, bool force)
> > > }
> > >
> > > out:
> > > - intel_dp_power_put(intel_dp, power_domain);
> > > + intel_display_power_put(to_i915(dev), power_domain);
> > > return status;
> > > }
> > >
> > > @@ -4862,6 +4840,7 @@ intel_dp_force(struct drm_connector *connector)
> > > {
> > > struct intel_dp *intel_dp = intel_attached_dp(connector);
> > > struct intel_encoder *intel_encoder =
> > > &dp_to_dig_port(intel_dp)->base;
> > > + struct drm_i915_private *dev_priv = to_i915(intel_encoder
> > > ->base.dev);
> > > enum intel_display_power_domain power_domain;
> > >
> > > DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
> > > @@ -4871,11 +4850,12 @@ intel_dp_force(struct drm_connector
> > > *connector)
> > > if (connector->status != connector_status_connected)
> > > return;
> > >
> > > - power_domain = intel_dp_power_get(intel_dp);
> > > + power_domain =
> > > intel_display_port_aux_power_domain(intel_encoder);
> > > + intel_display_power_get(dev_priv, power_domain);
> > >
> > > intel_dp_set_edid(intel_dp);
> > >
> > > - intel_dp_power_put(intel_dp, power_domain);
> > > + intel_display_power_put(dev_priv, power_domain);
> > >
> > > if (intel_encoder->type != INTEL_OUTPUT_EDP)
> > > intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
> > > @@ -5091,7 +5071,7 @@ static void intel_edp_panel_vdd_sanitize(struct
> > > intel_dp *intel_dp)
> > > * indefinitely.
> > > */
> > > DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state
> > > tracking\n");
> > > - power_domain =
> > > intel_display_port_power_domain(&intel_dig_port->base);
> > > + power_domain =
> > > intel_display_port_aux_power_domain(&intel_dig_port->base);
> > > intel_display_power_get(dev_priv, power_domain);
> > >
> > > edp_panel_vdd_schedule_off(intel_dp);
> > > @@ -5172,7 +5152,7 @@ intel_dp_hpd_pulse(struct intel_digital_port
> > > *intel_dig_port, bool long_hpd)
> > > port_name(intel_dig_port->port),
> > > long_hpd ? "long" : "short");
> > >
> > > - power_domain =
> > > intel_display_port_power_domain(intel_encoder);
> > > + power_domain =
> > > intel_display_port_aux_power_domain(intel_encoder);
> > > intel_display_power_get(dev_priv, power_domain);
> > >
> > > if (long_hpd) {
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index a68b6cd..7d11aa0 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1188,6 +1188,8 @@ void hsw_enable_ips(struct intel_crtc *crtc);
> > > void hsw_disable_ips(struct intel_crtc *crtc);
> > > enum intel_display_power_domain
> > > intel_display_port_power_domain(struct intel_encoder
> > > *intel_encoder);
> > > +enum intel_display_power_domain
> > > +intel_display_port_aux_power_domain(struct intel_encoder
> > > *intel_encoder);
> > > void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> > > struct intel_crtc_state
> > > *pipe_config);
> > > void intel_modeset_preclose(struct drm_device *dev, struct drm_file
> > > *file);
>
> --
> Ville Syrjälä
> Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 03/12] drm/i915: Clean up AUX power domain handling
2015-11-12 9:02 ` Patrik Jakobsson
@ 2015-11-12 10:15 ` Ville Syrjälä
0 siblings, 0 replies; 47+ messages in thread
From: Ville Syrjälä @ 2015-11-12 10:15 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On Thu, Nov 12, 2015 at 10:02:36AM +0100, Patrik Jakobsson wrote:
> On Wed, Nov 11, 2015 at 08:37:36PM +0200, Ville Syrjälä wrote:
> > On Wed, Nov 11, 2015 at 08:22:03PM +0200, Imre Deak wrote:
> > > On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > Introduce intel_display_port_aux_power_domain() which simply returns
> > > > the appropriate AUX power domain for a specific port, and then
> > > > replace
> > > > the intel_display_port_power_domain() with calls to the new function
> > > > in the DP code. As long as we're not actually enabling the port we
> > > > don't
> > > > need the lane power domains, and those are handled now purely from
> > > > modeset_update_crtc_power_domains().
> > > >
> > > > My initial motivation for this was to see if I could keep the DPIO
> > > > power
> > > > wells powered down while doing AUX on CHV, but turns out I can't so
> > > > this
> > > > doesn't change anything for CHV at least. But I think it's still a
> > > > worthwile change.
> > > >
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_display.c | 40
> > > > ++++++++++++++++++++++++++++++
> > > > drivers/gpu/drm/i915/intel_dp.c | 48 +++++++++++---------------
> > > > ----------
> > > > drivers/gpu/drm/i915/intel_drv.h | 2 ++
> > > > 3 files changed, 56 insertions(+), 34 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > index d0fec07..c2578d9 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -5143,6 +5143,23 @@ static enum intel_display_power_domain
> > > > port_to_power_domain(enum port port)
> > > > }
> > > > }
> > > >
> > > > +static enum intel_display_power_domain port_to_aux_power_domain(enum
> > > > port port)
> > > > +{
> > > > + switch (port) {
> > > > + case PORT_A:
> > > > + return POWER_DOMAIN_AUX_A;
> > > > + case PORT_B:
> > > > + return POWER_DOMAIN_AUX_B;
> > > > + case PORT_C:
> > > > + return POWER_DOMAIN_AUX_C;
> > > > + case PORT_D:
> > > > + return POWER_DOMAIN_AUX_D;
> > > > + default:
> > > > + WARN_ON_ONCE(1);
> > > > + return POWER_DOMAIN_AUX_A;
> > > > + }
> > > > +}
> > >
> > > Looks like port E is missing. I chatted with Ville he has some idea to
> > > fix this.
> >
> > Yeah, so there's no dedicated AUX block for port E, and instead VBT
> > tells us which AUX block to use. The current code doin that is rather
> > messy, but I have a cleaned it up during my register type-safety
> > journey. I just reposted the remaining AUX related patches [1] from
> > that series.
> >
> > So I was thinking that we could include an 'enum port aux_port' inside
> > intel_dp, and use that to pick the right power domain.
> >
> > [1] http://lists.freedesktop.org/archives/intel-gfx/2015-November/079918.html
>
> Ok so one of Aux A-D is hardwired to port E and only VBT can tell us which?
Yep.
> Do
> we need to change anything in this patch or can we add the aux_port enum later
> on?
Hmm. Lemme think. Before, we too the port power domain, so DDI_E, and
after the patch we would hit the default: case and get the WARN.
So that would be a regression of sorts. I guess as a quick hack you
could return eg. POWER_DOMAIN_AUX_D for port E, and add a FIXME that it
needs to be fixed, if you don't want to tackle the aux_port idea (or
something silimar right now).
On a side note maybe we should add MISSING_CASE_ONCE() to get some
better debug output from these kinds of cases...
>
> >
> > >
> > > > +
> > > > #define for_each_power_domain(domain, mask)
> > > > \
> > > > for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)
> > > > \
> > > > if ((1 << (domain)) & (mask))
> > > > @@ -5174,6 +5191,29 @@ intel_display_port_power_domain(struct
> > > > intel_encoder *intel_encoder)
> > > > }
> > > > }
> > > >
> > > > +enum intel_display_power_domain
> > > > +intel_display_port_aux_power_domain(struct intel_encoder
> > > > *intel_encoder)
> > > > +{
> > > > + struct drm_device *dev = intel_encoder->base.dev;
> > > > + struct intel_digital_port *intel_dig_port;
> > > > +
> > > > + switch (intel_encoder->type) {
> > > > + case INTEL_OUTPUT_UNKNOWN:
> > > > + /* Only DDI platforms should ever use this output
> > > > type */
> > > > + WARN_ON_ONCE(!HAS_DDI(dev));
> > > > + case INTEL_OUTPUT_DISPLAYPORT:
> > > > + case INTEL_OUTPUT_EDP:
> > > > + intel_dig_port = enc_to_dig_port(&intel_encoder
> > > > ->base);
> > > > + return port_to_aux_power_domain(intel_dig_port
> > > > ->port);
> > > > + case INTEL_OUTPUT_DP_MST:
> > > > + intel_dig_port = enc_to_mst(&intel_encoder->base)
> > > > ->primary;
> > > > + return port_to_aux_power_domain(intel_dig_port
> > > > ->port);
> > > > + default:
> > > > + WARN_ON_ONCE(1);
> > > > + return POWER_DOMAIN_AUX_A;
> > > > + }
> > > > +}
> > > > +
> > > > static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
> > > > {
> > > > struct drm_device *dev = crtc->dev;
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > index 4655af0..3978540 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -277,7 +277,7 @@ static void pps_lock(struct intel_dp *intel_dp)
> > > > * See vlv_power_sequencer_reset() why we need
> > > > * a power domain reference here.
> > > > */
> > > > - power_domain = intel_display_port_power_domain(encoder);
> > > > + power_domain = intel_display_port_aux_power_domain(encoder);
> > > > intel_display_power_get(dev_priv, power_domain);
> > > >
> > > > mutex_lock(&dev_priv->pps_mutex);
> > > > @@ -293,7 +293,7 @@ static void pps_unlock(struct intel_dp *intel_dp)
> > > >
> > > > mutex_unlock(&dev_priv->pps_mutex);
> > > >
> > > > - power_domain = intel_display_port_power_domain(encoder);
> > > > + power_domain = intel_display_port_aux_power_domain(encoder);
> > > > intel_display_power_put(dev_priv, power_domain);
> > > > }
> > > >
> > > > @@ -816,8 +816,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> > > >
> > > > intel_dp_check_edp(intel_dp);
> > > >
> > > > - intel_aux_display_runtime_get(dev_priv);
> > > > -
> > > > /* Try to wait for any previous AUX channel activity */
> > > > for (try = 0; try < 3; try++) {
> > > > status = I915_READ_NOTRACE(ch_ctl);
> > > > @@ -926,7 +924,6 @@ done:
> > > > ret = recv_bytes;
> > > > out:
> > > > pm_qos_update_request(&dev_priv->pm_qos,
> > > > PM_QOS_DEFAULT_VALUE);
> > > > - intel_aux_display_runtime_put(dev_priv);
> > > >
> > > > if (vdd)
> > > > edp_panel_vdd_off(intel_dp, false);
> > > > @@ -1784,7 +1781,7 @@ static bool edp_panel_vdd_on(struct intel_dp
> > > > *intel_dp)
> > > > if (edp_have_panel_vdd(intel_dp))
> > > > return need_to_disable;
> > > >
> > > > - power_domain =
> > > > intel_display_port_power_domain(intel_encoder);
> > > > + power_domain =
> > > > intel_display_port_aux_power_domain(intel_encoder);
> > > > intel_display_power_get(dev_priv, power_domain);
> > > >
> > > > DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
> > > > @@ -1874,7 +1871,7 @@ static void edp_panel_vdd_off_sync(struct
> > > > intel_dp *intel_dp)
> > > > if ((pp & POWER_TARGET_ON) == 0)
> > > > intel_dp->last_power_cycle = jiffies;
> > > >
> > > > - power_domain =
> > > > intel_display_port_power_domain(intel_encoder);
> > > > + power_domain =
> > > > intel_display_port_aux_power_domain(intel_encoder);
> > > > intel_display_power_put(dev_priv, power_domain);
> > > > }
> > > >
> > > > @@ -2025,7 +2022,7 @@ static void edp_panel_off(struct intel_dp
> > > > *intel_dp)
> > > > wait_panel_off(intel_dp);
> > > >
> > > > /* We got a reference when we enabled the VDD. */
> > > > - power_domain =
> > > > intel_display_port_power_domain(intel_encoder);
> > > > + power_domain =
> > > > intel_display_port_aux_power_domain(intel_encoder);
> > > > intel_display_power_put(dev_priv, power_domain);
> > > > }
> > > >
> > > > @@ -4765,26 +4762,6 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> > > > intel_dp->has_audio = false;
> > > > }
> > > >
> > > > -static enum intel_display_power_domain
> > > > -intel_dp_power_get(struct intel_dp *dp)
> > > > -{
> > > > - struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
> > > > - enum intel_display_power_domain power_domain;
> > > > -
> > > > - power_domain = intel_display_port_power_domain(encoder);
> > > > - intel_display_power_get(to_i915(encoder->base.dev),
> > > > power_domain);
> > > > -
> > > > - return power_domain;
> > > > -}
> > > > -
> > > > -static void
> > > > -intel_dp_power_put(struct intel_dp *dp,
> > > > - enum intel_display_power_domain power_domain)
> > > > -{
> > > > - struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
> > > > - intel_display_power_put(to_i915(encoder->base.dev),
> > > > power_domain);
> > > > -}
> > > > -
> > > > static enum drm_connector_status
> > > > intel_dp_detect(struct drm_connector *connector, bool force)
> > > > {
> > > > @@ -4808,7 +4785,8 @@ intel_dp_detect(struct drm_connector
> > > > *connector, bool force)
> > > > return connector_status_disconnected;
> > > > }
> > > >
> > > > - power_domain = intel_dp_power_get(intel_dp);
> > > > + power_domain =
> > > > intel_display_port_aux_power_domain(intel_encoder);
> > > > + intel_display_power_get(to_i915(dev), power_domain);
> > > >
> > > > /* Can't disconnect eDP, but you can close the lid... */
> > > > if (is_edp(intel_dp))
> > > > @@ -4853,7 +4831,7 @@ intel_dp_detect(struct drm_connector
> > > > *connector, bool force)
> > > > }
> > > >
> > > > out:
> > > > - intel_dp_power_put(intel_dp, power_domain);
> > > > + intel_display_power_put(to_i915(dev), power_domain);
> > > > return status;
> > > > }
> > > >
> > > > @@ -4862,6 +4840,7 @@ intel_dp_force(struct drm_connector *connector)
> > > > {
> > > > struct intel_dp *intel_dp = intel_attached_dp(connector);
> > > > struct intel_encoder *intel_encoder =
> > > > &dp_to_dig_port(intel_dp)->base;
> > > > + struct drm_i915_private *dev_priv = to_i915(intel_encoder
> > > > ->base.dev);
> > > > enum intel_display_power_domain power_domain;
> > > >
> > > > DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
> > > > @@ -4871,11 +4850,12 @@ intel_dp_force(struct drm_connector
> > > > *connector)
> > > > if (connector->status != connector_status_connected)
> > > > return;
> > > >
> > > > - power_domain = intel_dp_power_get(intel_dp);
> > > > + power_domain =
> > > > intel_display_port_aux_power_domain(intel_encoder);
> > > > + intel_display_power_get(dev_priv, power_domain);
> > > >
> > > > intel_dp_set_edid(intel_dp);
> > > >
> > > > - intel_dp_power_put(intel_dp, power_domain);
> > > > + intel_display_power_put(dev_priv, power_domain);
> > > >
> > > > if (intel_encoder->type != INTEL_OUTPUT_EDP)
> > > > intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
> > > > @@ -5091,7 +5071,7 @@ static void intel_edp_panel_vdd_sanitize(struct
> > > > intel_dp *intel_dp)
> > > > * indefinitely.
> > > > */
> > > > DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state
> > > > tracking\n");
> > > > - power_domain =
> > > > intel_display_port_power_domain(&intel_dig_port->base);
> > > > + power_domain =
> > > > intel_display_port_aux_power_domain(&intel_dig_port->base);
> > > > intel_display_power_get(dev_priv, power_domain);
> > > >
> > > > edp_panel_vdd_schedule_off(intel_dp);
> > > > @@ -5172,7 +5152,7 @@ intel_dp_hpd_pulse(struct intel_digital_port
> > > > *intel_dig_port, bool long_hpd)
> > > > port_name(intel_dig_port->port),
> > > > long_hpd ? "long" : "short");
> > > >
> > > > - power_domain =
> > > > intel_display_port_power_domain(intel_encoder);
> > > > + power_domain =
> > > > intel_display_port_aux_power_domain(intel_encoder);
> > > > intel_display_power_get(dev_priv, power_domain);
> > > >
> > > > if (long_hpd) {
> > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > index a68b6cd..7d11aa0 100644
> > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > @@ -1188,6 +1188,8 @@ void hsw_enable_ips(struct intel_crtc *crtc);
> > > > void hsw_disable_ips(struct intel_crtc *crtc);
> > > > enum intel_display_power_domain
> > > > intel_display_port_power_domain(struct intel_encoder
> > > > *intel_encoder);
> > > > +enum intel_display_power_domain
> > > > +intel_display_port_aux_power_domain(struct intel_encoder
> > > > *intel_encoder);
> > > > void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> > > > struct intel_crtc_state
> > > > *pipe_config);
> > > > void intel_modeset_preclose(struct drm_device *dev, struct drm_file
> > > > *file);
> >
> > --
> > Ville Syrjälä
> > Intel OTC
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-11 18:57 ` Imre Deak
@ 2015-11-12 12:24 ` Patrik Jakobsson
2015-11-12 13:30 ` Imre Deak
0 siblings, 1 reply; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-12 12:24 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Nov 11, 2015 at 08:57:19PM +0200, Imre Deak wrote:
> On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> > Handle DC off as a power well where enabling the power well will
> > prevent
> > the DMC to enter selected DC states (required around modesets and Aux
> > A). Disabling the power well will allow DC states again. For now the
> > highest DC state is DC6 for Skylake and DC5 for Broxton but will be
> > configurable for Skylake in a later patch.
> >
> > v2: Check both DC5 and DC6 bits in power well enabled function
> > (Ville)
> >
> > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 6 --
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_display.c | 6 ++
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 110
> > +++++++++++++++++++++++---------
> > 4 files changed, 88 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 5a63f9a..0c7f435 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
> >
> > static int skl_suspend_complete(struct drm_i915_private *dev_priv)
> > {
> > - if (dev_priv->csr.dmc_payload)
> > - skl_enable_dc6(dev_priv);
> > -
> > return 0;
> > }
> >
> > @@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct
> > drm_i915_private *dev_priv)
> >
> > static int skl_resume_prepare(struct drm_i915_private *dev_priv)
> > {
> > - if (dev_priv->csr.dmc_payload)
> > - skl_disable_dc6(dev_priv);
> > -
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 31b3a84..df445ba 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -636,6 +636,7 @@ enum skl_disp_power_wells {
> >
> > /* Not actual bit groups. Used as IDs for
> > lookup_power_well() */
> > SKL_DISP_PW_ALWAYS_ON,
> > + SKL_DISP_PW_DC_OFF,
>
> Imo it would be less confusing to call it DC3 power well. Looking at th
> e DC spec, DC4 is only a transitory state to DC5/6, so what we expect
> when we disable DC6/5 is DC3 or shallower power states (DC2/1/0).
I've been changing the name quite a few times but settled on "DC off" to keep it
generic. The main mechanism for the power well is to prevent any DC states that
can cause us problems during certain operations (i.e. modeset). The DC states we
need to block could change or be different between platforms. For that reason I
would prefer not to be as specific with the naming.
>
> > };
> >
> > #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 649ac34..856d801 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -13320,6 +13320,9 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> > to_intel_crtc_state(crtc->state)
> > ->update_pipe;
> > unsigned long put_domains = 0;
> >
> > + if (modeset)
> > + intel_display_power_get(dev_priv,
> > POWER_DOMAIN_MODESET);
> > +
> > if (modeset && crtc->state->active) {
> > update_scanline_offset(to_intel_crtc(crtc));
> > dev_priv->display.crtc_enable(crtc);
> > @@ -13343,6 +13346,9 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> > modeset_put_power_domains(dev_priv,
> > put_domains);
> >
> > intel_post_plane_update(intel_crtc);
> > +
> > + if (modeset)
> > + intel_display_power_put(dev_priv,
> > POWER_DOMAIN_MODESET);
> > }
> >
> > /* FIXME: add subpixel order */
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index edf753e..95c3fcc 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -49,9 +49,6 @@
> > * present for a given platform.
> > */
> >
> > -#define GEN9_ENABLE_DC5(dev) 0
> > -#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
> > -
> > #define for_each_power_well(i, power_well, domain_mask,
> > power_domains) \
> > for (i = 0;
> > \
> > i < (power_domains)->power_well_count &&
> > \
> > @@ -309,9 +306,14 @@ static void hsw_set_power_well(struct
> > drm_i915_private *dev_priv,
> > #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> > BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> > BIT(POWER_DOMAIN_INIT))
> > +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > + BIT(POWER_DOMAIN_MODESET) | \
> > + BIT(POWER_DOMAIN_AUX_A) | \
> > + BIT(POWER_DOMAIN_INIT))
> > #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> > (POWER_DOMAIN_MASK & ~( \
> > - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> > + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > + SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
> > BIT(POWER_DOMAIN_INIT))
> >
> > #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> > @@ -339,6 +341,10 @@ static void hsw_set_power_well(struct
> > drm_i915_private *dev_priv,
> > BIT(POWER_DOMAIN_AUX_A) | \
> > BIT(POWER_DOMAIN_PLLS) | \
> > BIT(POWER_DOMAIN_INIT))
> > +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > + BIT(POWER_DOMAIN_MODESET) | \
> > + BIT(POWER_DOMAIN_AUX_A) | \
> > + BIT(POWER_DOMAIN_INIT))
> > #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> > (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS
> > | \
> > BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> > @@ -486,15 +492,6 @@ static void gen9_enable_dc5(struct
> > drm_i915_private *dev_priv)
> > gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> > }
> >
> > -static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
> > -{
> > - assert_can_disable_dc5(dev_priv);
> > -
> > - DRM_DEBUG_KMS("Disabling DC5\n");
> > -
> > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > -}
> > -
> > static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> > {
> > struct drm_device *dev = dev_priv->dev;
> > @@ -522,6 +519,14 @@ static void assert_can_disable_dc6(struct
> > drm_i915_private *dev_priv)
> > "DC6 already programmed to be disabled.\n");
> > }
> >
> > +static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
> > +{
> > + assert_can_disable_dc5(dev_priv);
> > + assert_can_disable_dc6(dev_priv);
> > +
> > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > +}
> > +
> > void skl_enable_dc6(struct drm_i915_private *dev_priv)
> > {
> > assert_can_enable_dc6(dev_priv);
> > @@ -571,6 +576,7 @@ static void skl_set_power_well(struct
> > drm_i915_private *dev_priv,
> > case SKL_DISP_PW_DDI_C:
> > case SKL_DISP_PW_DDI_D:
> > case SKL_DISP_PW_MISC_IO:
> > + case SKL_DISP_PW_DC_OFF:
> > break;
> > default:
> > WARN(1, "Unknown power well %lu\n", power_well
> > ->data);
> > @@ -589,17 +595,13 @@ static void skl_set_power_well(struct
> > drm_i915_private *dev_priv,
> > "Invalid for power well status to be
> > enabled, unless done by the BIOS, \
> > when request is to disable!\n");
> > if (power_well->data == SKL_DISP_PW_2) {
> > - if (GEN9_ENABLE_DC5(dev))
> > - gen9_disable_dc5(dev_priv);
> > - if (SKL_ENABLE_DC6(dev)) {
> > - /*
> > - * DDI buffer programming
> > unnecessary during driver-load/resume
> > - * as it's already done
> > during modeset initialization then.
> > - * It's also invalid here as
> > encoder list is still uninitialized.
> > - */
> > - if (!dev_priv
> > ->power_domains.initializing)
> > - intel_prepare_ddi(de
> > v);
> > - }
> > + /*
> > + * DDI buffer programming
> > unnecessary during driver-load/resume
> > + * as it's already done during
> > modeset initialization then.
> > + * It's also invalid here as encoder
> > list is still uninitialized.
> > + */
> > + if (!dev_priv
> > ->power_domains.initializing)
> > + intel_prepare_ddi(dev);
> > }
> > I915_WRITE(HSW_PWR_WELL_DRIVER, tmp |
> > req_mask);
> > }
> > @@ -617,10 +619,6 @@ static void skl_set_power_well(struct
> > drm_i915_private *dev_priv,
> > I915_WRITE(HSW_PWR_WELL_DRIVER, tmp &
> > ~req_mask);
> > POSTING_READ(HSW_PWR_WELL_DRIVER);
> > DRM_DEBUG_KMS("Disabling %s\n", power_well
> > ->name);
> > -
> > - if (GEN9_ENABLE_DC5(dev) &&
> > - power_well->data == SKL_DISP_PW_2)
> > - gen9_enable_dc5(dev_priv);
> > }
> > }
> >
> > @@ -695,6 +693,40 @@ static void skl_power_well_disable(struct
> > drm_i915_private *dev_priv,
> > skl_set_power_well(dev_priv, power_well, false);
> > }
> >
> > +static bool gen9_dc_off_power_well_enabled(struct drm_i915_private
> > *dev_priv,
> > + struct i915_power_well
> > *power_well)
> > +{
> > + return (I915_READ(DC_STATE_EN) &
> > DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> > +}
> > +
> > +static void gen9_dc_off_power_well_enable(struct drm_i915_private
> > *dev_priv,
> > + struct i915_power_well
> > *power_well)
> > +{
> > + gen9_disable_dc5_dc6(dev_priv);
> > +}
> > +
> > +static void gen9_dc_off_power_well_disable(struct drm_i915_private
> > *dev_priv,
> > + struct i915_power_well
> > *power_well)
> > +{
> > + if (IS_SKYLAKE(dev_priv))
> > + skl_enable_dc6(dev_priv);
> > + else
> > + gen9_enable_dc5(dev_priv);
> > +}
> > +
> > +static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private
> > *dev_priv,
> > + struct i915_power_well
> > *power_well)
> > +{
> > + if (power_well->count > 0) {
> > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > + } else {
> > + if (IS_SKYLAKE(dev_priv))
> > + gen9_set_dc_state(dev_priv,
> > DC_STATE_EN_UPTO_DC6);
> > + else
> > + gen9_set_dc_state(dev_priv,
> > DC_STATE_EN_UPTO_DC5);
> > + }
> > +}
> > +
> > static void i9xx_always_on_power_well_noop(struct drm_i915_private
> > *dev_priv,
> > struct i915_power_well
> > *power_well)
> > {
> > @@ -1517,6 +1549,13 @@ static const struct i915_power_well_ops
> > skl_power_well_ops = {
> > .is_enabled = skl_power_well_enabled,
> > };
> >
> > +static const struct i915_power_well_ops gen9_dc_off_power_well_ops =
> > {
> > + .sync_hw = gen9_dc_off_power_well_sync_hw,
> > + .enable = gen9_dc_off_power_well_enable,
> > + .disable = gen9_dc_off_power_well_disable,
> > + .is_enabled = gen9_dc_off_power_well_enabled,
> > +};
> > +
> > static struct i915_power_well hsw_power_wells[] = {
> > {
> > .name = "always-on",
> > @@ -1697,6 +1736,12 @@ static struct i915_power_well
> > skl_power_wells[] = {
> > .data = SKL_DISP_PW_2,
> > },
> > {
> > + .name = "DC off",
> > + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .ops = &gen9_dc_off_power_well_ops,
> > + .data = SKL_DISP_PW_DC_OFF,
> > + },
> > + {
> > .name = "DDI A/E power well",
> > .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
> > .ops = &skl_power_well_ops,
> > @@ -1769,7 +1814,14 @@ static struct i915_power_well
> > bxt_power_wells[] = {
> > .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> > .ops = &skl_power_well_ops,
> > .data = SKL_DISP_PW_2,
> > - }
> > + },
> > + {
> > + .name = "DC off",
> > + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .ops = &gen9_dc_off_power_well_ops,
> > + .data = SKL_DISP_PW_DC_OFF,
> > + },
> > +
> > };
> >
> > #define set_power_wells(power_domains, __power_wells) ({
> > \
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 11/12] drm/i915/gen9: Add boot parameter for disabling DC6
2015-11-11 19:04 ` Imre Deak
@ 2015-11-12 12:51 ` Patrik Jakobsson
2015-11-12 13:52 ` Imre Deak
0 siblings, 1 reply; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-12 12:51 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Nov 11, 2015 at 09:04:09PM +0200, Imre Deak wrote:
> On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> > v2: Use _unsafe (Jani)
> >
> > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_params.c | 6 ++++++
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
> > 3 files changed, 9 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index c0252ef..5628c5a 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2639,6 +2639,7 @@ struct i915_params {
> > int panel_use_ssc;
> > int vbt_sdvo_panel_type;
> > int enable_rc6;
> > + int enable_dc6;
> > int enable_fbc;
> > int enable_ppgtt;
> > int enable_execlists;
> > diff --git a/drivers/gpu/drm/i915/i915_params.c
> > b/drivers/gpu/drm/i915/i915_params.c
> > index 368df67..6457f3a 100644
> > --- a/drivers/gpu/drm/i915/i915_params.c
> > +++ b/drivers/gpu/drm/i915/i915_params.c
> > @@ -32,6 +32,7 @@ struct i915_params i915 __read_mostly = {
> > .panel_use_ssc = -1,
> > .vbt_sdvo_panel_type = -1,
> > .enable_rc6 = -1,
> > + .enable_dc6 = 1,
> > .enable_fbc = -1,
> > .enable_execlists = -1,
> > .enable_hangcheck = true,
> > @@ -79,6 +80,11 @@ MODULE_PARM_DESC(enable_rc6,
> > "For example, 3 would enable rc6 and deep rc6, and 7 would
> > enable everything. "
> > "default: -1 (use per-chip default)");
> >
> > +module_param_named_unsafe(enable_dc6, i915.enable_dc6, int, 0400);
> > +MODULE_PARM_DESC(enable_dc6,
> > + "Enable power-saving display C-state 6. "
> > + "(0 = disable; 1 = enable [default])");
> > +
>
> It would be more generic to have something like enable_dc, -1=per-chip
> default, 0=disable, 1=up to dc5, 2=up to dc6.
I'm not sure if this parameter is going to stay for long but if it does I
suppose we should have DC9 as well. But do we really need this level of control?
My intention was to work around the DC6 corner case. Do you think we could make
good use of a more generic interface? Perhaps useful for testing? If so, I
definitely think we should go with your more generic solution. Otherwise I'd
rather keep it simple. Feel free to override my decision here.
Also, what would 0=disable be? Not starting the DMC at all or DC3/4?
>
> > module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600);
> > MODULE_PARM_DESC(enable_fbc,
> > "Enable frame buffer compression for power savings "
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 95c3fcc..62c1273 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -708,7 +708,7 @@ static void gen9_dc_off_power_well_enable(struct
> > drm_i915_private *dev_priv,
> > static void gen9_dc_off_power_well_disable(struct drm_i915_private
> > *dev_priv,
> > struct i915_power_well
> > *power_well)
> > {
> > - if (IS_SKYLAKE(dev_priv))
> > + if (IS_SKYLAKE(dev_priv) && i915.enable_dc6)
> > skl_enable_dc6(dev_priv);
> > else
> > gen9_enable_dc5(dev_priv);
> > @@ -720,7 +720,7 @@ static void gen9_dc_off_power_well_sync_hw(struct
> > drm_i915_private *dev_priv,
> > if (power_well->count > 0) {
> > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > } else {
> > - if (IS_SKYLAKE(dev_priv))
> > + if (IS_SKYLAKE(dev_priv) && i915.enable_dc6)
> > gen9_set_dc_state(dev_priv,
> > DC_STATE_EN_UPTO_DC6);
> > else
> > gen9_set_dc_state(dev_priv,
> > DC_STATE_EN_UPTO_DC5);
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-11 19:23 ` Imre Deak
@ 2015-11-12 12:55 ` Patrik Jakobsson
0 siblings, 0 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-12 12:55 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Nov 11, 2015 at 09:23:32PM +0200, Imre Deak wrote:
> On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> > Handle DC off as a power well where enabling the power well will
> > prevent
> > the DMC to enter selected DC states (required around modesets and Aux
> > A). Disabling the power well will allow DC states again. For now the
> > highest DC state is DC6 for Skylake and DC5 for Broxton but will be
> > configurable for Skylake in a later patch.
> >
> > v2: Check both DC5 and DC6 bits in power well enabled function
> > (Ville)
> >
> > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 6 --
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_display.c | 6 ++
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 110
> > +++++++++++++++++++++++---------
> > 4 files changed, 88 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 5a63f9a..0c7f435 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
> >
> > static int skl_suspend_complete(struct drm_i915_private *dev_priv)
> > {
> > - if (dev_priv->csr.dmc_payload)
> > - skl_enable_dc6(dev_priv);
> > -
> > return 0;
> > }
> >
> > @@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct
> > drm_i915_private *dev_priv)
> >
> > static int skl_resume_prepare(struct drm_i915_private *dev_priv)
> > {
> > - if (dev_priv->csr.dmc_payload)
> > - skl_disable_dc6(dev_priv);
> > -
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 31b3a84..df445ba 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -636,6 +636,7 @@ enum skl_disp_power_wells {
> >
> > /* Not actual bit groups. Used as IDs for
> > lookup_power_well() */
> > SKL_DISP_PW_ALWAYS_ON,
> > + SKL_DISP_PW_DC_OFF,
> > };
> >
> > #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 649ac34..856d801 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -13320,6 +13320,9 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> > to_intel_crtc_state(crtc->state)
> > ->update_pipe;
> > unsigned long put_domains = 0;
> >
> > + if (modeset)
> > + intel_display_power_get(dev_priv,
> > POWER_DOMAIN_MODESET);
> > +
> > if (modeset && crtc->state->active) {
> > update_scanline_offset(to_intel_crtc(crtc));
> > dev_priv->display.crtc_enable(crtc);
> > @@ -13343,6 +13346,9 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> > modeset_put_power_domains(dev_priv,
> > put_domains);
> >
> > intel_post_plane_update(intel_crtc);
> > +
> > + if (modeset)
> > + intel_display_power_put(dev_priv,
> > POWER_DOMAIN_MODESET);
> > }
> >
> > /* FIXME: add subpixel order */
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index edf753e..95c3fcc 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -49,9 +49,6 @@
> > * present for a given platform.
> > */
> >
> > -#define GEN9_ENABLE_DC5(dev) 0
> > -#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
> > -
> > #define for_each_power_well(i, power_well, domain_mask,
> > power_domains) \
> > for (i = 0;
> > \
> > i < (power_domains)->power_well_count &&
> > \
> > @@ -309,9 +306,14 @@ static void hsw_set_power_well(struct
> > drm_i915_private *dev_priv,
> > #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> > BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> > BIT(POWER_DOMAIN_INIT))
> > +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > + BIT(POWER_DOMAIN_MODESET) | \
> > + BIT(POWER_DOMAIN_AUX_A) | \
> > + BIT(POWER_DOMAIN_INIT))
> > #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> > (POWER_DOMAIN_MASK & ~( \
> > - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> > + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > + SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
> > BIT(POWER_DOMAIN_INIT))
> >
> > #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> > @@ -339,6 +341,10 @@ static void hsw_set_power_well(struct
> > drm_i915_private *dev_priv,
> > BIT(POWER_DOMAIN_AUX_A) | \
> > BIT(POWER_DOMAIN_PLLS) | \
> > BIT(POWER_DOMAIN_INIT))
> > +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > + BIT(POWER_DOMAIN_MODESET) | \
> > + BIT(POWER_DOMAIN_AUX_A) | \
> > + BIT(POWER_DOMAIN_INIT))
> > #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> > (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS
> > | \
> > BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> > @@ -486,15 +492,6 @@ static void gen9_enable_dc5(struct
> > drm_i915_private *dev_priv)
> > gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> > }
> >
> > -static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
> > -{
> > - assert_can_disable_dc5(dev_priv);
> > -
> > - DRM_DEBUG_KMS("Disabling DC5\n");
> > -
> > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > -}
> > -
> > static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> > {
> > struct drm_device *dev = dev_priv->dev;
> > @@ -522,6 +519,14 @@ static void assert_can_disable_dc6(struct
> > drm_i915_private *dev_priv)
> > "DC6 already programmed to be disabled.\n");
> > }
> >
> > +static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
> > +{
> > + assert_can_disable_dc5(dev_priv);
> > + assert_can_disable_dc6(dev_priv);
> > +
> > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > +}
> > +
> > void skl_enable_dc6(struct drm_i915_private *dev_priv)
> > {
> > assert_can_enable_dc6(dev_priv);
> > @@ -571,6 +576,7 @@ static void skl_set_power_well(struct
> > drm_i915_private *dev_priv,
> > case SKL_DISP_PW_DDI_C:
> > case SKL_DISP_PW_DDI_D:
> > case SKL_DISP_PW_MISC_IO:
> > + case SKL_DISP_PW_DC_OFF:
>
> Why is this needed? I think this function won't be called for DC5/6.
You're right, it's not needed. I'll remove it.
>
> > break;
> > default:
> > WARN(1, "Unknown power well %lu\n", power_well
> > ->data);
> > @@ -589,17 +595,13 @@ static void skl_set_power_well(struct
> > drm_i915_private *dev_priv,
> > "Invalid for power well status to be
> > enabled, unless done by the BIOS, \
> > when request is to disable!\n");
> > if (power_well->data == SKL_DISP_PW_2) {
> > - if (GEN9_ENABLE_DC5(dev))
> > - gen9_disable_dc5(dev_priv);
> > - if (SKL_ENABLE_DC6(dev)) {
> > - /*
> > - * DDI buffer programming
> > unnecessary during driver-load/resume
> > - * as it's already done
> > during modeset initialization then.
> > - * It's also invalid here as
> > encoder list is still uninitialized.
> > - */
> > - if (!dev_priv
> > ->power_domains.initializing)
> > - intel_prepare_ddi(de
> > v);
> > - }
> > + /*
> > + * DDI buffer programming
> > unnecessary during driver-load/resume
> > + * as it's already done during
> > modeset initialization then.
> > + * It's also invalid here as encoder
> > list is still uninitialized.
> > + */
> > + if (!dev_priv
> > ->power_domains.initializing)
> > + intel_prepare_ddi(dev);
> > }
> > I915_WRITE(HSW_PWR_WELL_DRIVER, tmp |
> > req_mask);
> > }
> > @@ -617,10 +619,6 @@ static void skl_set_power_well(struct
> > drm_i915_private *dev_priv,
> > I915_WRITE(HSW_PWR_WELL_DRIVER, tmp &
> > ~req_mask);
> > POSTING_READ(HSW_PWR_WELL_DRIVER);
> > DRM_DEBUG_KMS("Disabling %s\n", power_well
> > ->name);
> > -
> > - if (GEN9_ENABLE_DC5(dev) &&
> > - power_well->data == SKL_DISP_PW_2)
> > - gen9_enable_dc5(dev_priv);
> > }
> > }
> >
> > @@ -695,6 +693,40 @@ static void skl_power_well_disable(struct
> > drm_i915_private *dev_priv,
> > skl_set_power_well(dev_priv, power_well, false);
> > }
> >
> > +static bool gen9_dc_off_power_well_enabled(struct drm_i915_private
> > *dev_priv,
> > + struct i915_power_well
> > *power_well)
> > +{
> > + return (I915_READ(DC_STATE_EN) &
> > DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> > +}
> > +
> > +static void gen9_dc_off_power_well_enable(struct drm_i915_private
> > *dev_priv,
> > + struct i915_power_well
> > *power_well)
> > +{
> > + gen9_disable_dc5_dc6(dev_priv);
> > +}
> > +
> > +static void gen9_dc_off_power_well_disable(struct drm_i915_private
> > *dev_priv,
> > + struct i915_power_well
> > *power_well)
> > +{
> > + if (IS_SKYLAKE(dev_priv))
> > + skl_enable_dc6(dev_priv);
> > + else
> > + gen9_enable_dc5(dev_priv);
> > +}
> > +
> > +static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private
> > *dev_priv,
> > + struct i915_power_well
> > *power_well)
> > +{
> > + if (power_well->count > 0) {
> > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > + } else {
> > + if (IS_SKYLAKE(dev_priv))
> > + gen9_set_dc_state(dev_priv,
> > DC_STATE_EN_UPTO_DC6);
> > + else
> > + gen9_set_dc_state(dev_priv,
> > DC_STATE_EN_UPTO_DC5);
> > + }
> > +}
> > +
> > static void i9xx_always_on_power_well_noop(struct drm_i915_private
> > *dev_priv,
> > struct i915_power_well
> > *power_well)
> > {
> > @@ -1517,6 +1549,13 @@ static const struct i915_power_well_ops
> > skl_power_well_ops = {
> > .is_enabled = skl_power_well_enabled,
> > };
> >
> > +static const struct i915_power_well_ops gen9_dc_off_power_well_ops =
> > {
> > + .sync_hw = gen9_dc_off_power_well_sync_hw,
> > + .enable = gen9_dc_off_power_well_enable,
> > + .disable = gen9_dc_off_power_well_disable,
> > + .is_enabled = gen9_dc_off_power_well_enabled,
> > +};
> > +
> > static struct i915_power_well hsw_power_wells[] = {
> > {
> > .name = "always-on",
> > @@ -1697,6 +1736,12 @@ static struct i915_power_well
> > skl_power_wells[] = {
> > .data = SKL_DISP_PW_2,
> > },
> > {
> > + .name = "DC off",
> > + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .ops = &gen9_dc_off_power_well_ops,
> > + .data = SKL_DISP_PW_DC_OFF,
> > + },
> > + {
> > .name = "DDI A/E power well",
> > .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
> > .ops = &skl_power_well_ops,
> > @@ -1769,7 +1814,14 @@ static struct i915_power_well
> > bxt_power_wells[] = {
> > .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> > .ops = &skl_power_well_ops,
> > .data = SKL_DISP_PW_2,
> > - }
> > + },
> > + {
> > + .name = "DC off",
> > + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .ops = &gen9_dc_off_power_well_ops,
> > + .data = SKL_DISP_PW_DC_OFF,
> > + },
> > +
> > };
> >
> > #define set_power_wells(power_domains, __power_wells) ({
> > \
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 09/12] drm/i915: Explain usage of power well IDs vs bit groups
2015-11-11 19:13 ` Imre Deak
@ 2015-11-12 13:15 ` Patrik Jakobsson
0 siblings, 0 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-12 13:15 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Nov 11, 2015 at 09:13:27PM +0200, Imre Deak wrote:
> On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index e6d88f5..31b3a84 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -621,6 +621,7 @@ enum punit_power_well {
> > PUNIT_POWER_WELL_DPIO_RX1 = 11,
> > PUNIT_POWER_WELL_DPIO_CMN_D = 12,
> >
> > + /* Not actual bit groups. Used as IDs for
> > lookup_power_well() */
> > PUNIT_POWER_WELL_ALWAYS_ON,
> > };
> >
> > @@ -633,6 +634,7 @@ enum skl_disp_power_wells {
> > SKL_DISP_PW_1 = 14,
> > SKL_DISP_PW_2,
> >
> > + /* Not actual bit groups. Used as IDs for
> > lookup_power_well() */
>
> It would be good to mention that these IDs are fixed since they are
> also used to index HW flags. With that fixed:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
Good point, will add that.
>
> >
>
> > SKL_DISP_PW_ALWAYS_ON,
> > };
> >
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-12 12:24 ` Patrik Jakobsson
@ 2015-11-12 13:30 ` Imre Deak
2015-11-13 17:53 ` Imre Deak
0 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2015-11-12 13:30 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On to, 2015-11-12 at 13:24 +0100, Patrik Jakobsson wrote:
> On Wed, Nov 11, 2015 at 08:57:19PM +0200, Imre Deak wrote:
> > On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> > > Handle DC off as a power well where enabling the power well will
> > > prevent
> > > the DMC to enter selected DC states (required around modesets and
> > > Aux
> > > A). Disabling the power well will allow DC states again. For now
> > > the
> > > highest DC state is DC6 for Skylake and DC5 for Broxton but will
> > > be
> > > configurable for Skylake in a later patch.
> > >
> > > v2: Check both DC5 and DC6 bits in power well enabled function
> > > (Ville)
> > >
> > > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com
> > > >
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 6 --
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > drivers/gpu/drm/i915/intel_display.c | 6 ++
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 110
> > > +++++++++++++++++++++++---------
> > > 4 files changed, 88 insertions(+), 35 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > b/drivers/gpu/drm/i915/i915_drv.c
> > > index 5a63f9a..0c7f435 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device
> > > *dev)
> > >
> > > static int skl_suspend_complete(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > - if (dev_priv->csr.dmc_payload)
> > > - skl_enable_dc6(dev_priv);
> > > -
> > > return 0;
> > > }
> > >
> > > @@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct
> > > drm_i915_private *dev_priv)
> > >
> > > static int skl_resume_prepare(struct drm_i915_private *dev_priv)
> > > {
> > > - if (dev_priv->csr.dmc_payload)
> > > - skl_disable_dc6(dev_priv);
> > > -
> > > return 0;
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 31b3a84..df445ba 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -636,6 +636,7 @@ enum skl_disp_power_wells {
> > >
> > > /* Not actual bit groups. Used as IDs for
> > > lookup_power_well() */
> > > SKL_DISP_PW_ALWAYS_ON,
> > > + SKL_DISP_PW_DC_OFF,
> >
> > Imo it would be less confusing to call it DC3 power well. Looking
> > at th
> > e DC spec, DC4 is only a transitory state to DC5/6, so what we
> > expect
> > when we disable DC6/5 is DC3 or shallower power states (DC2/1/0).
>
> I've been changing the name quite a few times but settled on "DC off"
> to keep it
> generic. The main mechanism for the power well is to prevent any DC
> states that
> can cause us problems during certain operations (i.e. modeset). The
> DC states we
> need to block could change or be different between platforms. For
> that reason I
> would prefer not to be as specific with the naming.
All the power well names are platform specific so it would be logical
and more meaningful to give this one a platform specific name too. Also
'DC off' is kind of a double negation leading to debug messages like
'enable DC off' which isn't that nice. But now that I think of it my
idea isn't that great either. 'enable DC3' is confusing too, one could
think we enable some power saving state at that point, which is not the
case. So let's keep things as-is for now at least:
Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> >
> > > };
> > >
> > > #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 649ac34..856d801 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -13320,6 +13320,9 @@ static int intel_atomic_commit(struct
> > > drm_device *dev,
> > > to_intel_crtc_state(crtc->state)
> > > ->update_pipe;
> > > unsigned long put_domains = 0;
> > >
> > > + if (modeset)
> > > + intel_display_power_get(dev_priv,
> > > POWER_DOMAIN_MODESET);
> > > +
> > > if (modeset && crtc->state->active) {
> > > update_scanline_offset(to_intel_crtc(crt
> > > c));
> > > dev_priv->display.crtc_enable(crtc);
> > > @@ -13343,6 +13346,9 @@ static int intel_atomic_commit(struct
> > > drm_device *dev,
> > > modeset_put_power_domains(dev_priv,
> > > put_domains);
> > >
> > > intel_post_plane_update(intel_crtc);
> > > +
> > > + if (modeset)
> > > + intel_display_power_put(dev_priv,
> > > POWER_DOMAIN_MODESET);
> > > }
> > >
> > > /* FIXME: add subpixel order */
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index edf753e..95c3fcc 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -49,9 +49,6 @@
> > > * present for a given platform.
> > > */
> > >
> > > -#define GEN9_ENABLE_DC5(dev) 0
> > > -#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
> > > -
> > > #define for_each_power_well(i, power_well, domain_mask,
> > > power_domains) \
> > > for (i = 0;
> > >
> > > \
> > > i < (power_domains)->power_well_count &&
> > > \
> > > @@ -309,9 +306,14 @@ static void hsw_set_power_well(struct
> > > drm_i915_private *dev_priv,
> > > #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> > > BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> > > BIT(POWER_DOMAIN_INIT))
> > > +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > > + BIT(POWER_DOMAIN_MODESET) | \
> > > + BIT(POWER_DOMAIN_AUX_A) | \
> > > + BIT(POWER_DOMAIN_INIT))
> > > #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> > > (POWER_DOMAIN_MASK & ~( \
> > > - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> > > + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > > + SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
> > > BIT(POWER_DOMAIN_INIT))
> > >
> > > #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> > > @@ -339,6 +341,10 @@ static void hsw_set_power_well(struct
> > > drm_i915_private *dev_priv,
> > > BIT(POWER_DOMAIN_AUX_A) | \
> > > BIT(POWER_DOMAIN_PLLS) | \
> > > BIT(POWER_DOMAIN_INIT))
> > > +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > > + BIT(POWER_DOMAIN_MODESET) | \
> > > + BIT(POWER_DOMAIN_AUX_A) | \
> > > + BIT(POWER_DOMAIN_INIT))
> > > #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> > > (POWER_DOMAIN_MASK &
> > > ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS
> > > > \
> > > BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> > > @@ -486,15 +492,6 @@ static void gen9_enable_dc5(struct
> > > drm_i915_private *dev_priv)
> > > gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> > > }
> > >
> > > -static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
> > > -{
> > > - assert_can_disable_dc5(dev_priv);
> > > -
> > > - DRM_DEBUG_KMS("Disabling DC5\n");
> > > -
> > > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > -}
> > > -
> > > static void assert_can_enable_dc6(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > struct drm_device *dev = dev_priv->dev;
> > > @@ -522,6 +519,14 @@ static void assert_can_disable_dc6(struct
> > > drm_i915_private *dev_priv)
> > > "DC6 already programmed to be disabled.\n");
> > > }
> > >
> > > +static void gen9_disable_dc5_dc6(struct drm_i915_private
> > > *dev_priv)
> > > +{
> > > + assert_can_disable_dc5(dev_priv);
> > > + assert_can_disable_dc6(dev_priv);
> > > +
> > > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > +}
> > > +
> > > void skl_enable_dc6(struct drm_i915_private *dev_priv)
> > > {
> > > assert_can_enable_dc6(dev_priv);
> > > @@ -571,6 +576,7 @@ static void skl_set_power_well(struct
> > > drm_i915_private *dev_priv,
> > > case SKL_DISP_PW_DDI_C:
> > > case SKL_DISP_PW_DDI_D:
> > > case SKL_DISP_PW_MISC_IO:
> > > + case SKL_DISP_PW_DC_OFF:
> > > break;
> > > default:
> > > WARN(1, "Unknown power well %lu\n", power_well
> > > ->data);
> > > @@ -589,17 +595,13 @@ static void skl_set_power_well(struct
> > > drm_i915_private *dev_priv,
> > > "Invalid for power well status
> > > to be
> > > enabled, unless done by the BIOS, \
> > > when request is to disable!\n");
> > > if (power_well->data == SKL_DISP_PW_2) {
> > > - if (GEN9_ENABLE_DC5(dev))
> > > - gen9_disable_dc5(dev_pri
> > > v);
> > > - if (SKL_ENABLE_DC6(dev)) {
> > > - /*
> > > - * DDI buffer
> > > programming
> > > unnecessary during driver-load/resume
> > > - * as it's already done
> > > during modeset initialization then.
> > > - * It's also invalid
> > > here as
> > > encoder list is still uninitialized.
> > > - */
> > > - if (!dev_priv
> > > ->power_domains.initializing)
> > > - intel_prepare_dd
> > > i(de
> > > v);
> > > - }
> > > + /*
> > > + * DDI buffer programming
> > > unnecessary during driver-load/resume
> > > + * as it's already done during
> > > modeset initialization then.
> > > + * It's also invalid here as
> > > encoder
> > > list is still uninitialized.
> > > + */
> > > + if (!dev_priv
> > > ->power_domains.initializing)
> > > + intel_prepare_ddi(dev);
> > > }
> > > I915_WRITE(HSW_PWR_WELL_DRIVER, tmp |
> > > req_mask);
> > > }
> > > @@ -617,10 +619,6 @@ static void skl_set_power_well(struct
> > > drm_i915_private *dev_priv,
> > > I915_WRITE(HSW_PWR_WELL_DRIVER, t
> > > mp &
> > > ~req_mask);
> > > POSTING_READ(HSW_PWR_WELL_DRIVER);
> > > DRM_DEBUG_KMS("Disabling %s\n",
> > > power_well
> > > ->name);
> > > -
> > > - if (GEN9_ENABLE_DC5(dev) &&
> > > - power_well->data ==
> > > SKL_DISP_PW_2)
> > > - gen9_enable_dc5(dev_priv
> > > );
> > > }
> > > }
> > >
> > > @@ -695,6 +693,40 @@ static void skl_power_well_disable(struct
> > > drm_i915_private *dev_priv,
> > > skl_set_power_well(dev_priv, power_well, false);
> > > }
> > >
> > > +static bool gen9_dc_off_power_well_enabled(struct
> > > drm_i915_private
> > > *dev_priv,
> > > + struct i915_power_well
> > > *power_well)
> > > +{
> > > + return (I915_READ(DC_STATE_EN) &
> > > DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> > > +}
> > > +
> > > +static void gen9_dc_off_power_well_enable(struct
> > > drm_i915_private
> > > *dev_priv,
> > > + struct i915_power_well
> > > *power_well)
> > > +{
> > > + gen9_disable_dc5_dc6(dev_priv);
> > > +}
> > > +
> > > +static void gen9_dc_off_power_well_disable(struct
> > > drm_i915_private
> > > *dev_priv,
> > > + struct i915_power_well
> > > *power_well)
> > > +{
> > > + if (IS_SKYLAKE(dev_priv))
> > > + skl_enable_dc6(dev_priv);
> > > + else
> > > + gen9_enable_dc5(dev_priv);
> > > +}
> > > +
> > > +static void gen9_dc_off_power_well_sync_hw(struct
> > > drm_i915_private
> > > *dev_priv,
> > > + struct i915_power_well
> > > *power_well)
> > > +{
> > > + if (power_well->count > 0) {
> > > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > + } else {
> > > + if (IS_SKYLAKE(dev_priv))
> > > + gen9_set_dc_state(dev_priv,
> > > DC_STATE_EN_UPTO_DC6);
> > > + else
> > > + gen9_set_dc_state(dev_priv,
> > > DC_STATE_EN_UPTO_DC5);
> > > + }
> > > +}
> > > +
> > > static void i9xx_always_on_power_well_noop(struct
> > > drm_i915_private
> > > *dev_priv,
> > > struct
> > > i915_power_well
> > > *power_well)
> > > {
> > > @@ -1517,6 +1549,13 @@ static const struct i915_power_well_ops
> > > skl_power_well_ops = {
> > > .is_enabled = skl_power_well_enabled,
> > > };
> > >
> > > +static const struct i915_power_well_ops
> > > gen9_dc_off_power_well_ops =
> > > {
> > > + .sync_hw = gen9_dc_off_power_well_sync_hw,
> > > + .enable = gen9_dc_off_power_well_enable,
> > > + .disable = gen9_dc_off_power_well_disable,
> > > + .is_enabled = gen9_dc_off_power_well_enabled,
> > > +};
> > > +
> > > static struct i915_power_well hsw_power_wells[] = {
> > > {
> > > .name = "always-on",
> > > @@ -1697,6 +1736,12 @@ static struct i915_power_well
> > > skl_power_wells[] = {
> > > .data = SKL_DISP_PW_2,
> > > },
> > > {
> > > + .name = "DC off",
> > > + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > > + .ops = &gen9_dc_off_power_well_ops,
> > > + .data = SKL_DISP_PW_DC_OFF,
> > > + },
> > > + {
> > > .name = "DDI A/E power well",
> > > .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
> > > .ops = &skl_power_well_ops,
> > > @@ -1769,7 +1814,14 @@ static struct i915_power_well
> > > bxt_power_wells[] = {
> > > .domains =
> > > BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> > > .ops = &skl_power_well_ops,
> > > .data = SKL_DISP_PW_2,
> > > - }
> > > + },
> > > + {
> > > + .name = "DC off",
> > > + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> > > + .ops = &gen9_dc_off_power_well_ops,
> > > + .data = SKL_DISP_PW_DC_OFF,
> > > + },
> > > +
> > > };
> > >
> > > #define set_power_wells(power_domains, __power_wells) ({
> > > \
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 11/12] drm/i915/gen9: Add boot parameter for disabling DC6
2015-11-12 12:51 ` Patrik Jakobsson
@ 2015-11-12 13:52 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2015-11-12 13:52 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On to, 2015-11-12 at 13:51 +0100, Patrik Jakobsson wrote:
> On Wed, Nov 11, 2015 at 09:04:09PM +0200, Imre Deak wrote:
> > On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> > > v2: Use _unsafe (Jani)
> > >
> > > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com
> > > >
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > drivers/gpu/drm/i915/i915_params.c | 6 ++++++
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
> > > 3 files changed, 9 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index c0252ef..5628c5a 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -2639,6 +2639,7 @@ struct i915_params {
> > > int panel_use_ssc;
> > > int vbt_sdvo_panel_type;
> > > int enable_rc6;
> > > + int enable_dc6;
> > > int enable_fbc;
> > > int enable_ppgtt;
> > > int enable_execlists;
> > > diff --git a/drivers/gpu/drm/i915/i915_params.c
> > > b/drivers/gpu/drm/i915/i915_params.c
> > > index 368df67..6457f3a 100644
> > > --- a/drivers/gpu/drm/i915/i915_params.c
> > > +++ b/drivers/gpu/drm/i915/i915_params.c
> > > @@ -32,6 +32,7 @@ struct i915_params i915 __read_mostly = {
> > > .panel_use_ssc = -1,
> > > .vbt_sdvo_panel_type = -1,
> > > .enable_rc6 = -1,
> > > + .enable_dc6 = 1,
> > > .enable_fbc = -1,
> > > .enable_execlists = -1,
> > > .enable_hangcheck = true,
> > > @@ -79,6 +80,11 @@ MODULE_PARM_DESC(enable_rc6,
> > > "For example, 3 would enable rc6 and deep rc6, and 7
> > > would
> > > enable everything. "
> > > "default: -1 (use per-chip default)");
> > >
> > > +module_param_named_unsafe(enable_dc6, i915.enable_dc6, int,
> > > 0400);
> > > +MODULE_PARM_DESC(enable_dc6,
> > > + "Enable power-saving display C-state 6. "
> > > + "(0 = disable; 1 = enable [default])");
> > > +
> >
> > It would be more generic to have something like enable_dc, -1=per
> > -chip
> > default, 0=disable, 1=up to dc5, 2=up to dc6.
>
> I'm not sure if this parameter is going to stay for long but if it
> does I
> suppose we should have DC9 as well.
Yea, we could extend this in case we make DC9 a power well.
> But do we really need this level of control?
> My intention was to work around the DC6 corner case. Do you think
> we could make good use of a more generic interface?
This is an experimental functionality and have device wide effects (at
least display wide), so I wouldn't be surprised if we can make a good
use of a more fine grained control here.
> Perhaps useful for testing? If so, I
> definitely think we should go with your more generic solution.
> Otherwise I'd
> rather keep it simple. Feel free to override my decision here.
>
> Also, what would 0=disable be? Not starting the DMC at all or DC3/4?
Just not enabling DC5/6 ever in gen9_dc_off_power_well_disable(). The
idea would be to test if some failure is caused by DC5 for example.
> > module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600);
> > > MODULE_PARM_DESC(enable_fbc,
> > > "Enable frame buffer compression for power savings "
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 95c3fcc..62c1273 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -708,7 +708,7 @@ static void
> > > gen9_dc_off_power_well_enable(struct
> > > drm_i915_private *dev_priv,
> > > static void gen9_dc_off_power_well_disable(struct
> > > drm_i915_private
> > > *dev_priv,
> > > struct i915_power_well
> > > *power_well)
> > > {
> > > - if (IS_SKYLAKE(dev_priv))
> > > + if (IS_SKYLAKE(dev_priv) && i915.enable_dc6)
> > > skl_enable_dc6(dev_priv);
> > > else
> > > gen9_enable_dc5(dev_priv);
> > > @@ -720,7 +720,7 @@ static void
> > > gen9_dc_off_power_well_sync_hw(struct
> > > drm_i915_private *dev_priv,
> > > if (power_well->count > 0) {
> > > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > } else {
> > > - if (IS_SKYLAKE(dev_priv))
> > > + if (IS_SKYLAKE(dev_priv) && i915.enable_dc6)
> > > gen9_set_dc_state(dev_priv,
> > > DC_STATE_EN_UPTO_DC6);
> > > else
> > > gen9_set_dc_state(dev_priv,
> > > DC_STATE_EN_UPTO_DC5);
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-12 13:30 ` Imre Deak
@ 2015-11-13 17:53 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2015-11-13 17:53 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On to, 2015-11-12 at 15:30 +0200, Imre Deak wrote:
> On to, 2015-11-12 at 13:24 +0100, Patrik Jakobsson wrote:
> > On Wed, Nov 11, 2015 at 08:57:19PM +0200, Imre Deak wrote:
> > > On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> > > > Handle DC off as a power well where enabling the power well
> > > > will
> > > > prevent
> > > > the DMC to enter selected DC states (required around modesets
> > > > and
> > > > Aux
> > > > A). Disabling the power well will allow DC states again. For
> > > > now
> > > > the
> > > > highest DC state is DC6 for Skylake and DC5 for Broxton but
> > > > will
> > > > be
> > > > configurable for Skylake in a later patch.
> > > >
> > > > v2: Check both DC5 and DC6 bits in power well enabled function
> > > > (Ville)
> > > >
> > > > Signed-off-by: Patrik Jakobsson <
> > > > patrik.jakobsson@linux.intel.com
> > > > >
> > > > ---
> > > > drivers/gpu/drm/i915/i915_drv.c | 6 --
> > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > drivers/gpu/drm/i915/intel_display.c | 6 ++
> > > > drivers/gpu/drm/i915/intel_runtime_pm.c | 110
> > > > +++++++++++++++++++++++---------
> > > > 4 files changed, 88 insertions(+), 35 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > > b/drivers/gpu/drm/i915/i915_drv.c
> > > > index 5a63f9a..0c7f435 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > @@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device
> > > > *dev)
> > > >
> > > > static int skl_suspend_complete(struct drm_i915_private
> > > > *dev_priv)
> > > > {
> > > > - if (dev_priv->csr.dmc_payload)
> > > > - skl_enable_dc6(dev_priv);
> > > > -
> > > > return 0;
> > > > }
> > > >
> > > > @@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct
> > > > drm_i915_private *dev_priv)
> > > >
> > > > static int skl_resume_prepare(struct drm_i915_private
> > > > *dev_priv)
> > > > {
> > > > - if (dev_priv->csr.dmc_payload)
> > > > - skl_disable_dc6(dev_priv);
> > > > -
> > > > return 0;
> > > > }
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 31b3a84..df445ba 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -636,6 +636,7 @@ enum skl_disp_power_wells {
> > > >
> > > > /* Not actual bit groups. Used as IDs for
> > > > lookup_power_well() */
> > > > SKL_DISP_PW_ALWAYS_ON,
> > > > + SKL_DISP_PW_DC_OFF,
> > >
> > > Imo it would be less confusing to call it DC3 power well. Looking
> > > at th
> > > e DC spec, DC4 is only a transitory state to DC5/6, so what we
> > > expect
> > > when we disable DC6/5 is DC3 or shallower power states (DC2/1/0).
> >
> > I've been changing the name quite a few times but settled on "DC
> > off"
> > to keep it
> > generic. The main mechanism for the power well is to prevent any DC
> > states that
> > can cause us problems during certain operations (i.e. modeset). The
> > DC states we
> > need to block could change or be different between platforms. For
> > that reason I
> > would prefer not to be as specific with the naming.
>
> All the power well names are platform specific so it would be logical
> and more meaningful to give this one a platform specific name too.
> Also
> 'DC off' is kind of a double negation leading to debug messages like
> 'enable DC off' which isn't that nice. But now that I think of it my
> idea isn't that great either. 'enable DC3' is confusing too, one
> could
> think we enable some power saving state at that point, which is not
> the
> case. So let's keep things as-is for now at least:
>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
I noticed some issue only now, when testing it more:
> > > };
> > > >
> > > > #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > index 649ac34..856d801 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -13320,6 +13320,9 @@ static int intel_atomic_commit(struct
> > > > drm_device *dev,
> > > > to_intel_crtc_state(crtc->state)
> > > > ->update_pipe;
> > > > unsigned long put_domains = 0;
> > > >
> > > > + if (modeset)
> > > > + intel_display_power_get(dev_priv,
> > > > POWER_DOMAIN_MODESET);
> > > > +
> > > > if (modeset && crtc->state->active) {
> > > > update_scanline_offset(to_intel_crtc(c
> > > > rt
> > > > c));
> > > > dev_priv->display.crtc_enable(crtc);
> > > > @@ -13343,6 +13346,9 @@ static int intel_atomic_commit(struct
> > > > drm_device *dev,
> > > > modeset_put_power_domains(dev_priv,
> > > > put_domains);
> > > >
> > > > intel_post_plane_update(intel_crtc);
> > > > +
> > > > + if (modeset)
> > > > + intel_display_power_put(dev_priv,
> > > > POWER_DOMAIN_MODESET);
> > > > }
> > > >
> > > > /* FIXME: add subpixel order */
> > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > index edf753e..95c3fcc 100644
> > > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > @@ -49,9 +49,6 @@
> > > > * present for a given platform.
> > > > */
> > > >
> > > > -#define GEN9_ENABLE_DC5(dev) 0
> > > > -#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
> > > > -
> > > > #define for_each_power_well(i, power_well, domain_mask,
> > > > power_domains) \
> > > > for (i = 0;
> > > >
> > > > \
> > > > i < (power_domains)->power_well_count &&
> > > > \
> > > > @@ -309,9 +306,14 @@ static void hsw_set_power_well(struct
> > > > drm_i915_private *dev_priv,
> > > > #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> > > > BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> > > > BIT(POWER_DOMAIN_INIT))
> > > > +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > > > + BIT(POWER_DOMAIN_MODESET) | \
> > > > + BIT(POWER_DOMAIN_AUX_A) | \
> > > > + BIT(POWER_DOMAIN_INIT))
This needs SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS as well, so that we
enable/disable DC5/6 whenever we toggle PW_2.
> > > > #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> > > > (POWER_DOMAIN_MASK & ~(
> > > > \
> > > > - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> > > > + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |
> > > > \
> > > > + SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
> > > > BIT(POWER_DOMAIN_INIT))
> > > >
> > > > #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (
> > > > \
> > > > @@ -339,6 +341,10 @@ static void hsw_set_power_well(struct
> > > > drm_i915_private *dev_priv,
> > > > BIT(POWER_DOMAIN_AUX_A) | \
> > > > BIT(POWER_DOMAIN_PLLS) | \
> > > > BIT(POWER_DOMAIN_INIT))
> > > > +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > > > + BIT(POWER_DOMAIN_MODESET) | \
> > > > + BIT(POWER_DOMAIN_AUX_A) | \
> > > > + BIT(POWER_DOMAIN_INIT))
As above, this needs BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS.
> > > > #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> > > > (POWER_DOMAIN_MASK &
> > > > ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS
> > > > > \
> > > > BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> > > > @@ -486,15 +492,6 @@ static void gen9_enable_dc5(struct
> > > > drm_i915_private *dev_priv)
> > > > gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> > > > }
> > > >
> > > > -static void gen9_disable_dc5(struct drm_i915_private
> > > > *dev_priv)
> > > > -{
> > > > - assert_can_disable_dc5(dev_priv);
> > > > -
> > > > - DRM_DEBUG_KMS("Disabling DC5\n");
> > > > -
> > > > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > > -}
> > > > -
> > > > static void assert_can_enable_dc6(struct drm_i915_private
> > > > *dev_priv)
> > > > {
> > > > struct drm_device *dev = dev_priv->dev;
> > > > @@ -522,6 +519,14 @@ static void assert_can_disable_dc6(struct
> > > > drm_i915_private *dev_priv)
> > > > "DC6 already programmed to be disabled.\n");
> > > > }
> > > >
> > > > +static void gen9_disable_dc5_dc6(struct drm_i915_private
> > > > *dev_priv)
> > > > +{
> > > > + assert_can_disable_dc5(dev_priv);
> > > > + assert_can_disable_dc6(dev_priv);
> > > > +
> > > > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > > +}
> > > > +
> > > > void skl_enable_dc6(struct drm_i915_private *dev_priv)
> > > > {
> > > > assert_can_enable_dc6(dev_priv);
> > > > @@ -571,6 +576,7 @@ static void skl_set_power_well(struct
> > > > drm_i915_private *dev_priv,
> > > > case SKL_DISP_PW_DDI_C:
> > > > case SKL_DISP_PW_DDI_D:
> > > > case SKL_DISP_PW_MISC_IO:
> > > > + case SKL_DISP_PW_DC_OFF:
> > > > break;
> > > > default:
> > > > WARN(1, "Unknown power well %lu\n", power_well
> > > > ->data);
> > > > @@ -589,17 +595,13 @@ static void skl_set_power_well(struct
> > > > drm_i915_private *dev_priv,
> > > > "Invalid for power well status
> > > > to be
> > > > enabled, unless done by the BIOS, \
> > > > when request is to
> > > > disable!\n");
> > > > if (power_well->data == SKL_DISP_PW_2)
> > > > {
> > > > - if (GEN9_ENABLE_DC5(dev))
> > > > - gen9_disable_dc5(dev_p
> > > > ri
> > > > v);
> > > > - if (SKL_ENABLE_DC6(dev)) {
> > > > - /*
> > > > - * DDI buffer
> > > > programming
> > > > unnecessary during driver-load/resume
> > > > - * as it's already
> > > > done
> > > > during modeset initialization then.
> > > > - * It's also invalid
> > > > here as
> > > > encoder list is still uninitialized.
> > > > - */
> > > > - if (!dev_priv
> > > > ->power_domains.initializing)
> > > > - intel_prepare_
> > > > dd
> > > > i(de
> > > > v);
> > > > - }
> > > > + /*
> > > > + * DDI buffer programming
> > > > unnecessary during driver-load/resume
> > > > + * as it's already done during
> > > > modeset initialization then.
> > > > + * It's also invalid here as
> > > > encoder
> > > > list is still uninitialized.
> > > > + */
> > > > + if (!dev_priv
> > > > ->power_domains.initializing)
> > > > + intel_prepare_ddi(dev)
> > > > ;
> > > > }
> > > > I915_WRITE(HSW_PWR_WELL_DRIVER, tmp |
> > > > req_mask);
> > > > }
> > > > @@ -617,10 +619,6 @@ static void skl_set_power_well(struct
> > > > drm_i915_private *dev_priv,
> > > > I915_WRITE(HSW_PWR_WELL_DRIVER,
> > > > t
> > > > mp &
> > > > ~req_mask);
> > > > POSTING_READ(HSW_PWR_WELL_DRIVER);
> > > > DRM_DEBUG_KMS("Disabling %s\n",
> > > > power_well
> > > > ->name);
> > > > -
> > > > - if (GEN9_ENABLE_DC5(dev) &&
> > > > - power_well->data ==
> > > > SKL_DISP_PW_2)
> > > > - gen9_enable_dc5(dev_pr
> > > > iv
> > > > );
> > > > }
> > > > }
> > > >
> > > > @@ -695,6 +693,40 @@ static void skl_power_well_disable(struct
> > > > drm_i915_private *dev_priv,
> > > > skl_set_power_well(dev_priv, power_well, false);
> > > > }
> > > >
> > > > +static bool gen9_dc_off_power_well_enabled(struct
> > > > drm_i915_private
> > > > *dev_priv,
> > > > + struct
> > > > i915_power_well
> > > > *power_well)
> > > > +{
> > > > + return (I915_READ(DC_STATE_EN) &
> > > > DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> > > > +}
> > > > +
> > > > +static void gen9_dc_off_power_well_enable(struct
> > > > drm_i915_private
> > > > *dev_priv,
> > > > + struct
> > > > i915_power_well
> > > > *power_well)
> > > > +{
> > > > + gen9_disable_dc5_dc6(dev_priv);
> > > > +}
> > > > +
> > > > +static void gen9_dc_off_power_well_disable(struct
> > > > drm_i915_private
> > > > *dev_priv,
> > > > + struct
> > > > i915_power_well
> > > > *power_well)
> > > > +{
> > > > + if (IS_SKYLAKE(dev_priv))
> > > > + skl_enable_dc6(dev_priv);
> > > > + else
> > > > + gen9_enable_dc5(dev_priv);
> > > > +}
> > > > +
> > > > +static void gen9_dc_off_power_well_sync_hw(struct
> > > > drm_i915_private
> > > > *dev_priv,
> > > > + struct
> > > > i915_power_well
> > > > *power_well)
> > > > +{
> > > > + if (power_well->count > 0) {
> > > > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > > + } else {
> > > > + if (IS_SKYLAKE(dev_priv))
> > > > + gen9_set_dc_state(dev_priv,
> > > > DC_STATE_EN_UPTO_DC6);
> > > > + else
> > > > + gen9_set_dc_state(dev_priv,
> > > > DC_STATE_EN_UPTO_DC5);
> > > > + }
> > > > +}
> > > > +
> > > > static void i9xx_always_on_power_well_noop(struct
> > > > drm_i915_private
> > > > *dev_priv,
> > > > struct
> > > > i915_power_well
> > > > *power_well)
> > > > {
> > > > @@ -1517,6 +1549,13 @@ static const struct i915_power_well_ops
> > > > skl_power_well_ops = {
> > > > .is_enabled = skl_power_well_enabled,
> > > > };
> > > >
> > > > +static const struct i915_power_well_ops
> > > > gen9_dc_off_power_well_ops =
> > > > {
> > > > + .sync_hw = gen9_dc_off_power_well_sync_hw,
> > > > + .enable = gen9_dc_off_power_well_enable,
> > > > + .disable = gen9_dc_off_power_well_disable,
> > > > + .is_enabled = gen9_dc_off_power_well_enabled,
> > > > +};
> > > > +
> > > > static struct i915_power_well hsw_power_wells[] = {
> > > > {
> > > > .name = "always-on",
> > > > @@ -1697,6 +1736,12 @@ static struct i915_power_well
> > > > skl_power_wells[] = {
> > > > .data = SKL_DISP_PW_2,
> > > > },
> > > > {
> > > > + .name = "DC off",
> > > > + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > > > + .ops = &gen9_dc_off_power_well_ops,
> > > > + .data = SKL_DISP_PW_DC_OFF,
> > > > + },
This should be listed right before the PW_2 well, so that the we have
the following sequences:
1. disable DC5/6
2. enable PW_2
1. disable PW_2
2. enable DC5/6
> > > > + {
> > > > .name = "DDI A/E power well",
> > > > .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
> > > > .ops = &skl_power_well_ops,
> > > > @@ -1769,7 +1814,14 @@ static struct i915_power_well
> > > > bxt_power_wells[] = {
> > > > .domains =
> > > > BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> > > > .ops = &skl_power_well_ops,
> > > > .data = SKL_DISP_PW_2,
> > > > - }
> > > > + },
> > > > + {
> > > > + .name = "DC off",
> > > > + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> > > > + .ops = &gen9_dc_off_power_well_ops,
> > > > + .data = SKL_DISP_PW_DC_OFF,
> > > > + },
As above, this should be listed right before the PW_2 well.
> > > > +
> > > > };
> > > >
> > > > #define set_power_wells(power_domains, __power_wells) ({
> > > >
> > > > \
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v2 03/12] drm/i915: Clean up AUX power domain handling
2015-11-09 15:48 ` [PATCH 03/12] drm/i915: Clean up AUX power domain handling Patrik Jakobsson
2015-11-11 18:22 ` Imre Deak
@ 2015-11-16 14:01 ` Patrik Jakobsson
1 sibling, 0 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-16 14:01 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Introduce intel_display_port_aux_power_domain() which simply returns
the appropriate AUX power domain for a specific port, and then replace
the intel_display_port_power_domain() with calls to the new function
in the DP code. As long as we're not actually enabling the port we don't
need the lane power domains, and those are handled now purely from
modeset_update_crtc_power_domains().
My initial motivation for this was to see if I could keep the DPIO power
wells powered down while doing AUX on CHV, but turns out I can't so this
doesn't change anything for CHV at least. But I think it's still a
worthwile change.
v2: Add case for PORT E. Default to POWER_DOMAIN_AUX_D for now. (Ville)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 43 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dp.c | 48 +++++++++++-------------------------
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 59 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d0fec07..cdedaf2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5143,6 +5143,26 @@ static enum intel_display_power_domain port_to_power_domain(enum port port)
}
}
+static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
+{
+ switch (port) {
+ case PORT_A:
+ return POWER_DOMAIN_AUX_A;
+ case PORT_B:
+ return POWER_DOMAIN_AUX_B;
+ case PORT_C:
+ return POWER_DOMAIN_AUX_C;
+ case PORT_D:
+ return POWER_DOMAIN_AUX_D;
+ case PORT_E:
+ /* FIXME: Check VBT for actual wiring of PORT E */
+ return POWER_DOMAIN_AUX_D;
+ default:
+ WARN_ON_ONCE(1);
+ return POWER_DOMAIN_AUX_A;
+ }
+}
+
#define for_each_power_domain(domain, mask) \
for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
if ((1 << (domain)) & (mask))
@@ -5174,6 +5194,29 @@ intel_display_port_power_domain(struct intel_encoder *intel_encoder)
}
}
+enum intel_display_power_domain
+intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
+{
+ struct drm_device *dev = intel_encoder->base.dev;
+ struct intel_digital_port *intel_dig_port;
+
+ switch (intel_encoder->type) {
+ case INTEL_OUTPUT_UNKNOWN:
+ /* Only DDI platforms should ever use this output type */
+ WARN_ON_ONCE(!HAS_DDI(dev));
+ case INTEL_OUTPUT_DISPLAYPORT:
+ case INTEL_OUTPUT_EDP:
+ intel_dig_port = enc_to_dig_port(&intel_encoder->base);
+ return port_to_aux_power_domain(intel_dig_port->port);
+ case INTEL_OUTPUT_DP_MST:
+ intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
+ return port_to_aux_power_domain(intel_dig_port->port);
+ default:
+ WARN_ON_ONCE(1);
+ return POWER_DOMAIN_AUX_A;
+ }
+}
+
static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4655af0..3978540 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -277,7 +277,7 @@ static void pps_lock(struct intel_dp *intel_dp)
* See vlv_power_sequencer_reset() why we need
* a power domain reference here.
*/
- power_domain = intel_display_port_power_domain(encoder);
+ power_domain = intel_display_port_aux_power_domain(encoder);
intel_display_power_get(dev_priv, power_domain);
mutex_lock(&dev_priv->pps_mutex);
@@ -293,7 +293,7 @@ static void pps_unlock(struct intel_dp *intel_dp)
mutex_unlock(&dev_priv->pps_mutex);
- power_domain = intel_display_port_power_domain(encoder);
+ power_domain = intel_display_port_aux_power_domain(encoder);
intel_display_power_put(dev_priv, power_domain);
}
@@ -816,8 +816,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
intel_dp_check_edp(intel_dp);
- intel_aux_display_runtime_get(dev_priv);
-
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
status = I915_READ_NOTRACE(ch_ctl);
@@ -926,7 +924,6 @@ done:
ret = recv_bytes;
out:
pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
- intel_aux_display_runtime_put(dev_priv);
if (vdd)
edp_panel_vdd_off(intel_dp, false);
@@ -1784,7 +1781,7 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
if (edp_have_panel_vdd(intel_dp))
return need_to_disable;
- power_domain = intel_display_port_power_domain(intel_encoder);
+ power_domain = intel_display_port_aux_power_domain(intel_encoder);
intel_display_power_get(dev_priv, power_domain);
DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
@@ -1874,7 +1871,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
if ((pp & POWER_TARGET_ON) == 0)
intel_dp->last_power_cycle = jiffies;
- power_domain = intel_display_port_power_domain(intel_encoder);
+ power_domain = intel_display_port_aux_power_domain(intel_encoder);
intel_display_power_put(dev_priv, power_domain);
}
@@ -2025,7 +2022,7 @@ static void edp_panel_off(struct intel_dp *intel_dp)
wait_panel_off(intel_dp);
/* We got a reference when we enabled the VDD. */
- power_domain = intel_display_port_power_domain(intel_encoder);
+ power_domain = intel_display_port_aux_power_domain(intel_encoder);
intel_display_power_put(dev_priv, power_domain);
}
@@ -4765,26 +4762,6 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
intel_dp->has_audio = false;
}
-static enum intel_display_power_domain
-intel_dp_power_get(struct intel_dp *dp)
-{
- struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
- enum intel_display_power_domain power_domain;
-
- power_domain = intel_display_port_power_domain(encoder);
- intel_display_power_get(to_i915(encoder->base.dev), power_domain);
-
- return power_domain;
-}
-
-static void
-intel_dp_power_put(struct intel_dp *dp,
- enum intel_display_power_domain power_domain)
-{
- struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
- intel_display_power_put(to_i915(encoder->base.dev), power_domain);
-}
-
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
@@ -4808,7 +4785,8 @@ intel_dp_detect(struct drm_connector *connector, bool force)
return connector_status_disconnected;
}
- power_domain = intel_dp_power_get(intel_dp);
+ power_domain = intel_display_port_aux_power_domain(intel_encoder);
+ intel_display_power_get(to_i915(dev), power_domain);
/* Can't disconnect eDP, but you can close the lid... */
if (is_edp(intel_dp))
@@ -4853,7 +4831,7 @@ intel_dp_detect(struct drm_connector *connector, bool force)
}
out:
- intel_dp_power_put(intel_dp, power_domain);
+ intel_display_power_put(to_i915(dev), power_domain);
return status;
}
@@ -4862,6 +4840,7 @@ intel_dp_force(struct drm_connector *connector)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
enum intel_display_power_domain power_domain;
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
@@ -4871,11 +4850,12 @@ intel_dp_force(struct drm_connector *connector)
if (connector->status != connector_status_connected)
return;
- power_domain = intel_dp_power_get(intel_dp);
+ power_domain = intel_display_port_aux_power_domain(intel_encoder);
+ intel_display_power_get(dev_priv, power_domain);
intel_dp_set_edid(intel_dp);
- intel_dp_power_put(intel_dp, power_domain);
+ intel_display_power_put(dev_priv, power_domain);
if (intel_encoder->type != INTEL_OUTPUT_EDP)
intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
@@ -5091,7 +5071,7 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
* indefinitely.
*/
DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
- power_domain = intel_display_port_power_domain(&intel_dig_port->base);
+ power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
intel_display_power_get(dev_priv, power_domain);
edp_panel_vdd_schedule_off(intel_dp);
@@ -5172,7 +5152,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
port_name(intel_dig_port->port),
long_hpd ? "long" : "short");
- power_domain = intel_display_port_power_domain(intel_encoder);
+ power_domain = intel_display_port_aux_power_domain(intel_encoder);
intel_display_power_get(dev_priv, power_domain);
if (long_hpd) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a68b6cd..7d11aa0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1188,6 +1188,8 @@ void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
enum intel_display_power_domain
intel_display_port_power_domain(struct intel_encoder *intel_encoder);
+enum intel_display_power_domain
+intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_state *pipe_config);
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
--
2.5.0
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 09/12] drm/i915: Explain usage of power well IDs vs bit groups
2015-11-09 15:48 ` [PATCH 09/12] drm/i915: Explain usage of power well IDs vs bit groups Patrik Jakobsson
2015-11-11 19:13 ` Imre Deak
@ 2015-11-16 14:01 ` Patrik Jakobsson
1 sibling, 0 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-16 14:01 UTC (permalink / raw)
To: intel-gfx
v2: Add explanation of the fixed power well bits (Imre)
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e6d88f5..0f3849f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -609,6 +609,7 @@
/* See the PUNIT HAS v0.8 for the below bits */
enum punit_power_well {
+ /* These numbers are fixed and must match the position of the pw bits */
PUNIT_POWER_WELL_RENDER = 0,
PUNIT_POWER_WELL_MEDIA = 1,
PUNIT_POWER_WELL_DISP2D = 3,
@@ -621,10 +622,12 @@ enum punit_power_well {
PUNIT_POWER_WELL_DPIO_RX1 = 11,
PUNIT_POWER_WELL_DPIO_CMN_D = 12,
+ /* Not actual bit groups. Used as IDs for lookup_power_well() */
PUNIT_POWER_WELL_ALWAYS_ON,
};
enum skl_disp_power_wells {
+ /* These numbers are fixed and must match the position of the pw bits */
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_DDI_A_E,
SKL_DISP_PW_DDI_B,
@@ -633,6 +636,7 @@ enum skl_disp_power_wells {
SKL_DISP_PW_1 = 14,
SKL_DISP_PW_2,
+ /* Not actual bit groups. Used as IDs for lookup_power_well() */
SKL_DISP_PW_ALWAYS_ON,
};
--
2.5.0
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v3 11/12] drm/i915/gen9: Add boot parameter for disabling DC6
2015-11-09 15:48 ` [PATCH v2 11/12] drm/i915/gen9: Add boot parameter for disabling DC6 Patrik Jakobsson
2015-11-11 19:04 ` Imre Deak
@ 2015-11-16 14:01 ` Patrik Jakobsson
2015-11-16 19:25 ` Imre Deak
1 sibling, 1 reply; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-16 14:01 UTC (permalink / raw)
To: intel-gfx
v2: Use _unsafe (Jani)
v3: Allow specifying specific DC-states instead of just DC6 (Imre)
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_params.c | 6 ++++++
drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +++++++++++---
3 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0252ef..c85c1ec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2639,6 +2639,7 @@ struct i915_params {
int panel_use_ssc;
int vbt_sdvo_panel_type;
int enable_rc6;
+ int enable_dc;
int enable_fbc;
int enable_ppgtt;
int enable_execlists;
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 368df67..ccc15c9 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -32,6 +32,7 @@ struct i915_params i915 __read_mostly = {
.panel_use_ssc = -1,
.vbt_sdvo_panel_type = -1,
.enable_rc6 = -1,
+ .enable_dc = -1,
.enable_fbc = -1,
.enable_execlists = -1,
.enable_hangcheck = true,
@@ -79,6 +80,11 @@ MODULE_PARM_DESC(enable_rc6,
"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
"default: -1 (use per-chip default)");
+module_param_named_unsafe(enable_dc, i915.enable_dc, int, 0400);
+MODULE_PARM_DESC(enable_dc,
+ "Enable power-saving display C-states. "
+ "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
+
module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600);
MODULE_PARM_DESC(enable_fbc,
"Enable frame buffer compression for power savings "
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b6ee48e..4d6f777 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -417,6 +417,11 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
WARN_ON_ONCE(state & ~mask);
+ if (i915.enable_dc == 0)
+ state = DC_STATE_DISABLE;
+ else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5)
+ state = DC_STATE_EN_UPTO_DC5;
+
if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
gen9_set_dc_state_debugmask_memory_up(dev_priv);
@@ -524,7 +529,9 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
{
assert_can_disable_dc5(dev_priv);
- assert_can_disable_dc6(dev_priv);
+
+ if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1)
+ assert_can_disable_dc6(dev_priv);
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
}
@@ -709,7 +716,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- if (IS_SKYLAKE(dev_priv))
+ if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1)
skl_enable_dc6(dev_priv);
else
gen9_enable_dc5(dev_priv);
@@ -721,7 +728,8 @@ static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
if (power_well->count > 0) {
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
} else {
- if (IS_SKYLAKE(dev_priv))
+ if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 &&
+ i915.enable_dc != 1)
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
else
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
--
2.5.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v3 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-09 15:48 ` [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well Patrik Jakobsson
2015-11-11 18:57 ` Imre Deak
2015-11-11 19:23 ` Imre Deak
@ 2015-11-16 14:01 ` Patrik Jakobsson
2015-11-16 14:41 ` Patrik Jakobsson
` (2 more replies)
2 siblings, 3 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-16 14:01 UTC (permalink / raw)
To: intel-gfx
Handle DC off as a power well where enabling the power well will prevent
the DMC to enter selected DC states (required around modesets and Aux
A). Disabling the power well will allow DC states again. For now the
highest DC state is DC6 for Skylake and DC5 for Broxton but will be
configurable for Skylake in a later patch.
v2: Check both DC5 and DC6 bits in power well enabled function (Ville)
v3:
- Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
- Add PW2 dependency to DC_OFF (Imre)
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 6 --
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 6 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 111 +++++++++++++++++++++++---------
4 files changed, 89 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5a63f9a..0c7f435 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
static int skl_suspend_complete(struct drm_i915_private *dev_priv)
{
- if (dev_priv->csr.dmc_payload)
- skl_enable_dc6(dev_priv);
-
return 0;
}
@@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
static int skl_resume_prepare(struct drm_i915_private *dev_priv)
{
- if (dev_priv->csr.dmc_payload)
- skl_disable_dc6(dev_priv);
-
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0f3849f..b6a3525 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -638,6 +638,7 @@ enum skl_disp_power_wells {
/* Not actual bit groups. Used as IDs for lookup_power_well() */
SKL_DISP_PW_ALWAYS_ON,
+ SKL_DISP_PW_DC_OFF,
};
#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 978b1b9..21385a0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13323,6 +13323,9 @@ static int intel_atomic_commit(struct drm_device *dev,
to_intel_crtc_state(crtc->state)->update_pipe;
unsigned long put_domains = 0;
+ if (modeset)
+ intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
+
if (modeset && crtc->state->active) {
update_scanline_offset(to_intel_crtc(crtc));
dev_priv->display.crtc_enable(crtc);
@@ -13346,6 +13349,9 @@ static int intel_atomic_commit(struct drm_device *dev,
modeset_put_power_domains(dev_priv, put_domains);
intel_post_plane_update(intel_crtc);
+
+ if (modeset)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
}
/* FIXME: add subpixel order */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index edf753e..b6ee48e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -49,9 +49,6 @@
* present for a given platform.
*/
-#define GEN9_ENABLE_DC5(dev) 0
-#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
-
#define for_each_power_well(i, power_well, domain_mask, power_domains) \
for (i = 0; \
i < (power_domains)->power_well_count && \
@@ -309,9 +306,15 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
BIT(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT(POWER_DOMAIN_MODESET) | \
+ BIT(POWER_DOMAIN_AUX_A) | \
+ BIT(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
(POWER_DOMAIN_MASK & ~( \
- SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
+ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
BIT(POWER_DOMAIN_INIT))
#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
@@ -339,6 +342,11 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_AUX_A) | \
BIT(POWER_DOMAIN_PLLS) | \
BIT(POWER_DOMAIN_INIT))
+#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT(POWER_DOMAIN_MODESET) | \
+ BIT(POWER_DOMAIN_AUX_A) | \
+ BIT(POWER_DOMAIN_INIT))
#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
(POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
@@ -486,15 +494,6 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
}
-static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
-{
- assert_can_disable_dc5(dev_priv);
-
- DRM_DEBUG_KMS("Disabling DC5\n");
-
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
-}
-
static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
@@ -522,6 +521,14 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
"DC6 already programmed to be disabled.\n");
}
+static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
+{
+ assert_can_disable_dc5(dev_priv);
+ assert_can_disable_dc6(dev_priv);
+
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+}
+
void skl_enable_dc6(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc6(dev_priv);
@@ -589,17 +596,13 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
"Invalid for power well status to be enabled, unless done by the BIOS, \
when request is to disable!\n");
if (power_well->data == SKL_DISP_PW_2) {
- if (GEN9_ENABLE_DC5(dev))
- gen9_disable_dc5(dev_priv);
- if (SKL_ENABLE_DC6(dev)) {
- /*
- * DDI buffer programming unnecessary during driver-load/resume
- * as it's already done during modeset initialization then.
- * It's also invalid here as encoder list is still uninitialized.
- */
- if (!dev_priv->power_domains.initializing)
- intel_prepare_ddi(dev);
- }
+ /*
+ * DDI buffer programming unnecessary during driver-load/resume
+ * as it's already done during modeset initialization then.
+ * It's also invalid here as encoder list is still uninitialized.
+ */
+ if (!dev_priv->power_domains.initializing)
+ intel_prepare_ddi(dev);
}
I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
}
@@ -617,10 +620,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
POSTING_READ(HSW_PWR_WELL_DRIVER);
DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
-
- if (GEN9_ENABLE_DC5(dev) &&
- power_well->data == SKL_DISP_PW_2)
- gen9_enable_dc5(dev_priv);
}
}
@@ -695,6 +694,40 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
skl_set_power_well(dev_priv, power_well, false);
}
+static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
+}
+
+static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ gen9_disable_dc5_dc6(dev_priv);
+}
+
+static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if (IS_SKYLAKE(dev_priv))
+ skl_enable_dc6(dev_priv);
+ else
+ gen9_enable_dc5(dev_priv);
+}
+
+static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if (power_well->count > 0) {
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ } else {
+ if (IS_SKYLAKE(dev_priv))
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
+ else
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
+ }
+}
+
static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -1517,6 +1550,13 @@ static const struct i915_power_well_ops skl_power_well_ops = {
.is_enabled = skl_power_well_enabled,
};
+static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
+ .sync_hw = gen9_dc_off_power_well_sync_hw,
+ .enable = gen9_dc_off_power_well_enable,
+ .disable = gen9_dc_off_power_well_disable,
+ .is_enabled = gen9_dc_off_power_well_enabled,
+};
+
static struct i915_power_well hsw_power_wells[] = {
{
.name = "always-on",
@@ -1691,6 +1731,12 @@ static struct i915_power_well skl_power_wells[] = {
.data = SKL_DISP_PW_MISC_IO,
},
{
+ .name = "DC off",
+ .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .data = SKL_DISP_PW_DC_OFF,
+ },
+ {
.name = "power well 2",
.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &skl_power_well_ops,
@@ -1769,7 +1815,14 @@ static struct i915_power_well bxt_power_wells[] = {
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &skl_power_well_ops,
.data = SKL_DISP_PW_2,
- }
+ },
+ {
+ .name = "DC off",
+ .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .data = SKL_DISP_PW_DC_OFF,
+ },
+
};
#define set_power_wells(power_domains, __power_wells) ({ \
--
2.5.0
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH v3 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-16 14:01 ` [PATCH v3 " Patrik Jakobsson
@ 2015-11-16 14:41 ` Patrik Jakobsson
2015-11-16 15:20 ` [PATCH v4 " Patrik Jakobsson
2015-11-16 19:28 ` [PATCH v3 " Imre Deak
2 siblings, 0 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-16 14:41 UTC (permalink / raw)
To: intel-gfx
On Mon, Nov 16, 2015 at 03:01:07PM +0100, Patrik Jakobsson wrote:
> Handle DC off as a power well where enabling the power well will prevent
> the DMC to enter selected DC states (required around modesets and Aux
> A). Disabling the power well will allow DC states again. For now the
> highest DC state is DC6 for Skylake and DC5 for Broxton but will be
> configurable for Skylake in a later patch.
>
> v2: Check both DC5 and DC6 bits in power well enabled function (Ville)
> v3:
> - Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
> - Add PW2 dependency to DC_OFF (Imre)
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 6 --
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 6 ++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 111 +++++++++++++++++++++++---------
> 4 files changed, 89 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5a63f9a..0c7f435 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
>
> static int skl_suspend_complete(struct drm_i915_private *dev_priv)
> {
> - if (dev_priv->csr.dmc_payload)
> - skl_enable_dc6(dev_priv);
> -
> return 0;
> }
>
> @@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
>
> static int skl_resume_prepare(struct drm_i915_private *dev_priv)
> {
> - if (dev_priv->csr.dmc_payload)
> - skl_disable_dc6(dev_priv);
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0f3849f..b6a3525 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -638,6 +638,7 @@ enum skl_disp_power_wells {
>
> /* Not actual bit groups. Used as IDs for lookup_power_well() */
> SKL_DISP_PW_ALWAYS_ON,
> + SKL_DISP_PW_DC_OFF,
> };
>
> #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 978b1b9..21385a0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13323,6 +13323,9 @@ static int intel_atomic_commit(struct drm_device *dev,
> to_intel_crtc_state(crtc->state)->update_pipe;
> unsigned long put_domains = 0;
>
> + if (modeset)
> + intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
> +
> if (modeset && crtc->state->active) {
> update_scanline_offset(to_intel_crtc(crtc));
> dev_priv->display.crtc_enable(crtc);
> @@ -13346,6 +13349,9 @@ static int intel_atomic_commit(struct drm_device *dev,
> modeset_put_power_domains(dev_priv, put_domains);
>
> intel_post_plane_update(intel_crtc);
> +
> + if (modeset)
> + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
> }
>
> /* FIXME: add subpixel order */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index edf753e..b6ee48e 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -49,9 +49,6 @@
> * present for a given platform.
> */
>
> -#define GEN9_ENABLE_DC5(dev) 0
> -#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
> -
> #define for_each_power_well(i, power_well, domain_mask, power_domains) \
> for (i = 0; \
> i < (power_domains)->power_well_count && \
> @@ -309,9 +306,15 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~( \
> - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> @@ -339,6 +342,11 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_AUX_A) | \
> BIT(POWER_DOMAIN_PLLS) | \
> BIT(POWER_DOMAIN_INIT))
> +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
> BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> @@ -486,15 +494,6 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> }
>
> -static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
> -{
> - assert_can_disable_dc5(dev_priv);
> -
> - DRM_DEBUG_KMS("Disabling DC5\n");
> -
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> -}
> -
> static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> {
> struct drm_device *dev = dev_priv->dev;
> @@ -522,6 +521,14 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
> "DC6 already programmed to be disabled.\n");
> }
>
> +static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
> +{
> + assert_can_disable_dc5(dev_priv);
> + assert_can_disable_dc6(dev_priv);
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +}
> +
> void skl_enable_dc6(struct drm_i915_private *dev_priv)
> {
> assert_can_enable_dc6(dev_priv);
> @@ -589,17 +596,13 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> "Invalid for power well status to be enabled, unless done by the BIOS, \
> when request is to disable!\n");
> if (power_well->data == SKL_DISP_PW_2) {
> - if (GEN9_ENABLE_DC5(dev))
> - gen9_disable_dc5(dev_priv);
> - if (SKL_ENABLE_DC6(dev)) {
> - /*
> - * DDI buffer programming unnecessary during driver-load/resume
> - * as it's already done during modeset initialization then.
> - * It's also invalid here as encoder list is still uninitialized.
> - */
> - if (!dev_priv->power_domains.initializing)
> - intel_prepare_ddi(dev);
> - }
> + /*
> + * DDI buffer programming unnecessary during driver-load/resume
> + * as it's already done during modeset initialization then.
> + * It's also invalid here as encoder list is still uninitialized.
> + */
> + if (!dev_priv->power_domains.initializing)
> + intel_prepare_ddi(dev);
> }
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
> }
> @@ -617,10 +620,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
> POSTING_READ(HSW_PWR_WELL_DRIVER);
> DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
> -
> - if (GEN9_ENABLE_DC5(dev) &&
> - power_well->data == SKL_DISP_PW_2)
> - gen9_enable_dc5(dev_priv);
> }
> }
>
> @@ -695,6 +694,40 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
> skl_set_power_well(dev_priv, power_well, false);
> }
>
> +static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> +}
> +
> +static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + gen9_disable_dc5_dc6(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + if (IS_SKYLAKE(dev_priv))
> + skl_enable_dc6(dev_priv);
> + else
> + gen9_enable_dc5(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + if (power_well->count > 0) {
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + } else {
> + if (IS_SKYLAKE(dev_priv))
> + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
> + else
> + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> + }
> +}
> +
> static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> @@ -1517,6 +1550,13 @@ static const struct i915_power_well_ops skl_power_well_ops = {
> .is_enabled = skl_power_well_enabled,
> };
>
> +static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
> + .sync_hw = gen9_dc_off_power_well_sync_hw,
> + .enable = gen9_dc_off_power_well_enable,
> + .disable = gen9_dc_off_power_well_disable,
> + .is_enabled = gen9_dc_off_power_well_enabled,
> +};
> +
> static struct i915_power_well hsw_power_wells[] = {
> {
> .name = "always-on",
> @@ -1691,6 +1731,12 @@ static struct i915_power_well skl_power_wells[] = {
> .data = SKL_DISP_PW_MISC_IO,
> },
> {
> + .name = "DC off",
> + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .data = SKL_DISP_PW_DC_OFF,
> + },
> + {
> .name = "power well 2",
> .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> @@ -1769,7 +1815,14 @@ static struct i915_power_well bxt_power_wells[] = {
> .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> .data = SKL_DISP_PW_2,
> - }
> + },
> + {
> + .name = "DC off",
> + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .data = SKL_DISP_PW_DC_OFF,
> + },
> +
Just realized that I forgot to move DC off for BXT above PW2. Will resend, sorry
for the noise.
-Patrik
> };
>
> #define set_power_wells(power_domains, __power_wells) ({ \
> --
> 2.5.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v4 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-16 14:01 ` [PATCH v3 " Patrik Jakobsson
2015-11-16 14:41 ` Patrik Jakobsson
@ 2015-11-16 15:20 ` Patrik Jakobsson
2015-11-17 19:21 ` Imre Deak
2015-11-23 22:58 ` Matt Roper
2015-11-16 19:28 ` [PATCH v3 " Imre Deak
2 siblings, 2 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-16 15:20 UTC (permalink / raw)
To: intel-gfx
Handle DC off as a power well where enabling the power well will prevent
the DMC to enter selected DC states (required around modesets and Aux
A). Disabling the power well will allow DC states again. For now the
highest DC state is DC6 for Skylake and DC5 for Broxton but will be
configurable for Skylake in a later patch.
v2: Check both DC5 and DC6 bits in power well enabled function (Ville)
v3:
- Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
- Add PW2 dependency to DC_OFF (Imre)
v4: Put DC_OFF before PW2 in BXT power well array
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 6 --
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 6 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 110 +++++++++++++++++++++++---------
4 files changed, 88 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5a63f9a..0c7f435 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
static int skl_suspend_complete(struct drm_i915_private *dev_priv)
{
- if (dev_priv->csr.dmc_payload)
- skl_enable_dc6(dev_priv);
-
return 0;
}
@@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
static int skl_resume_prepare(struct drm_i915_private *dev_priv)
{
- if (dev_priv->csr.dmc_payload)
- skl_disable_dc6(dev_priv);
-
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0f3849f..b6a3525 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -638,6 +638,7 @@ enum skl_disp_power_wells {
/* Not actual bit groups. Used as IDs for lookup_power_well() */
SKL_DISP_PW_ALWAYS_ON,
+ SKL_DISP_PW_DC_OFF,
};
#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 978b1b9..21385a0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13323,6 +13323,9 @@ static int intel_atomic_commit(struct drm_device *dev,
to_intel_crtc_state(crtc->state)->update_pipe;
unsigned long put_domains = 0;
+ if (modeset)
+ intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
+
if (modeset && crtc->state->active) {
update_scanline_offset(to_intel_crtc(crtc));
dev_priv->display.crtc_enable(crtc);
@@ -13346,6 +13349,9 @@ static int intel_atomic_commit(struct drm_device *dev,
modeset_put_power_domains(dev_priv, put_domains);
intel_post_plane_update(intel_crtc);
+
+ if (modeset)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
}
/* FIXME: add subpixel order */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index edf753e..0ff1646 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -49,9 +49,6 @@
* present for a given platform.
*/
-#define GEN9_ENABLE_DC5(dev) 0
-#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
-
#define for_each_power_well(i, power_well, domain_mask, power_domains) \
for (i = 0; \
i < (power_domains)->power_well_count && \
@@ -309,9 +306,15 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
BIT(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT(POWER_DOMAIN_MODESET) | \
+ BIT(POWER_DOMAIN_AUX_A) | \
+ BIT(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
(POWER_DOMAIN_MASK & ~( \
- SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
+ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
BIT(POWER_DOMAIN_INIT))
#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
@@ -339,6 +342,11 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_AUX_A) | \
BIT(POWER_DOMAIN_PLLS) | \
BIT(POWER_DOMAIN_INIT))
+#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT(POWER_DOMAIN_MODESET) | \
+ BIT(POWER_DOMAIN_AUX_A) | \
+ BIT(POWER_DOMAIN_INIT))
#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
(POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
@@ -486,15 +494,6 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
}
-static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
-{
- assert_can_disable_dc5(dev_priv);
-
- DRM_DEBUG_KMS("Disabling DC5\n");
-
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
-}
-
static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
@@ -522,6 +521,14 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
"DC6 already programmed to be disabled.\n");
}
+static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
+{
+ assert_can_disable_dc5(dev_priv);
+ assert_can_disable_dc6(dev_priv);
+
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+}
+
void skl_enable_dc6(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc6(dev_priv);
@@ -589,17 +596,13 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
"Invalid for power well status to be enabled, unless done by the BIOS, \
when request is to disable!\n");
if (power_well->data == SKL_DISP_PW_2) {
- if (GEN9_ENABLE_DC5(dev))
- gen9_disable_dc5(dev_priv);
- if (SKL_ENABLE_DC6(dev)) {
- /*
- * DDI buffer programming unnecessary during driver-load/resume
- * as it's already done during modeset initialization then.
- * It's also invalid here as encoder list is still uninitialized.
- */
- if (!dev_priv->power_domains.initializing)
- intel_prepare_ddi(dev);
- }
+ /*
+ * DDI buffer programming unnecessary during driver-load/resume
+ * as it's already done during modeset initialization then.
+ * It's also invalid here as encoder list is still uninitialized.
+ */
+ if (!dev_priv->power_domains.initializing)
+ intel_prepare_ddi(dev);
}
I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
}
@@ -617,10 +620,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
POSTING_READ(HSW_PWR_WELL_DRIVER);
DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
-
- if (GEN9_ENABLE_DC5(dev) &&
- power_well->data == SKL_DISP_PW_2)
- gen9_enable_dc5(dev_priv);
}
}
@@ -695,6 +694,40 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
skl_set_power_well(dev_priv, power_well, false);
}
+static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
+}
+
+static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ gen9_disable_dc5_dc6(dev_priv);
+}
+
+static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if (IS_SKYLAKE(dev_priv))
+ skl_enable_dc6(dev_priv);
+ else
+ gen9_enable_dc5(dev_priv);
+}
+
+static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if (power_well->count > 0) {
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ } else {
+ if (IS_SKYLAKE(dev_priv))
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
+ else
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
+ }
+}
+
static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -1517,6 +1550,13 @@ static const struct i915_power_well_ops skl_power_well_ops = {
.is_enabled = skl_power_well_enabled,
};
+static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
+ .sync_hw = gen9_dc_off_power_well_sync_hw,
+ .enable = gen9_dc_off_power_well_enable,
+ .disable = gen9_dc_off_power_well_disable,
+ .is_enabled = gen9_dc_off_power_well_enabled,
+};
+
static struct i915_power_well hsw_power_wells[] = {
{
.name = "always-on",
@@ -1691,6 +1731,12 @@ static struct i915_power_well skl_power_wells[] = {
.data = SKL_DISP_PW_MISC_IO,
},
{
+ .name = "DC off",
+ .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .data = SKL_DISP_PW_DC_OFF,
+ },
+ {
.name = "power well 2",
.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &skl_power_well_ops,
@@ -1765,11 +1811,17 @@ static struct i915_power_well bxt_power_wells[] = {
.data = SKL_DISP_PW_1,
},
{
+ .name = "DC off",
+ .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .data = SKL_DISP_PW_DC_OFF,
+ },
+ {
.name = "power well 2",
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &skl_power_well_ops,
.data = SKL_DISP_PW_2,
- }
+ },
};
#define set_power_wells(power_domains, __power_wells) ({ \
--
2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH v3 11/12] drm/i915/gen9: Add boot parameter for disabling DC6
2015-11-16 14:01 ` [PATCH v3 " Patrik Jakobsson
@ 2015-11-16 19:25 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2015-11-16 19:25 UTC (permalink / raw)
To: Patrik Jakobsson, intel-gfx
On ma, 2015-11-16 at 15:01 +0100, Patrik Jakobsson wrote:
> v2: Use _unsafe (Jani)
> v3: Allow specifying specific DC-states instead of just DC6 (Imre)
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_params.c | 6 ++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +++++++++++---
> 3 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c0252ef..c85c1ec 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2639,6 +2639,7 @@ struct i915_params {
> int panel_use_ssc;
> int vbt_sdvo_panel_type;
> int enable_rc6;
> + int enable_dc;
> int enable_fbc;
> int enable_ppgtt;
> int enable_execlists;
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 368df67..ccc15c9 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -32,6 +32,7 @@ struct i915_params i915 __read_mostly = {
> .panel_use_ssc = -1,
> .vbt_sdvo_panel_type = -1,
> .enable_rc6 = -1,
> + .enable_dc = -1,
> .enable_fbc = -1,
> .enable_execlists = -1,
> .enable_hangcheck = true,
> @@ -79,6 +80,11 @@ MODULE_PARM_DESC(enable_rc6,
> "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
> "default: -1 (use per-chip default)");
>
> +module_param_named_unsafe(enable_dc, i915.enable_dc, int, 0400);
> +MODULE_PARM_DESC(enable_dc,
> + "Enable power-saving display C-states. "
> + "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
> +
> module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600);
> MODULE_PARM_DESC(enable_fbc,
> "Enable frame buffer compression for power savings "
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b6ee48e..4d6f777 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -417,6 +417,11 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
>
> WARN_ON_ONCE(state & ~mask);
>
> + if (i915.enable_dc == 0)
> + state = DC_STATE_DISABLE;
> + else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5)
> + state = DC_STATE_EN_UPTO_DC5;
> +
Ideally we would have a sanitize function for the option and setup a
dev_priv->enable_dc_state there based on the platform and the option
value. Then the check for which state to enable would be simpler and we
could have the check only in the power well enable/disable/sync_hw
hooks, and set the passed in state here unconditionally. But this can
be done as a follow-up, this patch looks ok to me regardless:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
> gen9_set_dc_state_debugmask_memory_up(dev_priv);
>
> @@ -524,7 +529,9 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
> static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
> {
> assert_can_disable_dc5(dev_priv);
> - assert_can_disable_dc6(dev_priv);
> +
> + if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1)
> + assert_can_disable_dc6(dev_priv);
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> }
> @@ -709,7 +716,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - if (IS_SKYLAKE(dev_priv))
> + if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1)
> skl_enable_dc6(dev_priv);
> else
> gen9_enable_dc5(dev_priv);
> @@ -721,7 +728,8 @@ static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
> if (power_well->count > 0) {
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> } else {
> - if (IS_SKYLAKE(dev_priv))
> + if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 &&
> + i915.enable_dc != 1)
> gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
> else
> gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v3 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-16 14:01 ` [PATCH v3 " Patrik Jakobsson
2015-11-16 14:41 ` Patrik Jakobsson
2015-11-16 15:20 ` [PATCH v4 " Patrik Jakobsson
@ 2015-11-16 19:28 ` Imre Deak
2015-11-16 19:46 ` Patrik Jakobsson
2 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2015-11-16 19:28 UTC (permalink / raw)
To: Patrik Jakobsson, intel-gfx
On ma, 2015-11-16 at 15:01 +0100, Patrik Jakobsson wrote:
> Handle DC off as a power well where enabling the power well will prevent
> the DMC to enter selected DC states (required around modesets and Aux
> A). Disabling the power well will allow DC states again. For now the
> highest DC state is DC6 for Skylake and DC5 for Broxton but will be
> configurable for Skylake in a later patch.
>
> v2: Check both DC5 and DC6 bits in power well enabled function (Ville)
> v3:
> - Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
> - Add PW2 dependency to DC_OFF (Imre)
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 6 --
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 6 ++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 111 +++++++++++++++++++++++---------
> 4 files changed, 89 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5a63f9a..0c7f435 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
>
> static int skl_suspend_complete(struct drm_i915_private *dev_priv)
> {
> - if (dev_priv->csr.dmc_payload)
> - skl_enable_dc6(dev_priv);
> -
> return 0;
> }
>
> @@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
>
> static int skl_resume_prepare(struct drm_i915_private *dev_priv)
> {
> - if (dev_priv->csr.dmc_payload)
> - skl_disable_dc6(dev_priv);
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0f3849f..b6a3525 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -638,6 +638,7 @@ enum skl_disp_power_wells {
>
> /* Not actual bit groups. Used as IDs for lookup_power_well() */
> SKL_DISP_PW_ALWAYS_ON,
> + SKL_DISP_PW_DC_OFF,
> };
>
> #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 978b1b9..21385a0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13323,6 +13323,9 @@ static int intel_atomic_commit(struct drm_device *dev,
> to_intel_crtc_state(crtc->state)->update_pipe;
> unsigned long put_domains = 0;
>
> + if (modeset)
> + intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
> +
> if (modeset && crtc->state->active) {
> update_scanline_offset(to_intel_crtc(crtc));
> dev_priv->display.crtc_enable(crtc);
> @@ -13346,6 +13349,9 @@ static int intel_atomic_commit(struct drm_device *dev,
> modeset_put_power_domains(dev_priv, put_domains);
>
> intel_post_plane_update(intel_crtc);
> +
> + if (modeset)
> + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
> }
>
> /* FIXME: add subpixel order */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index edf753e..b6ee48e 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -49,9 +49,6 @@
> * present for a given platform.
> */
>
> -#define GEN9_ENABLE_DC5(dev) 0
> -#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
> -
> #define for_each_power_well(i, power_well, domain_mask, power_domains) \
> for (i = 0; \
> i < (power_domains)->power_well_count && \
> @@ -309,9 +306,15 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~( \
> - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> @@ -339,6 +342,11 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_AUX_A) | \
> BIT(POWER_DOMAIN_PLLS) | \
> BIT(POWER_DOMAIN_INIT))
> +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
> BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> @@ -486,15 +494,6 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> }
>
> -static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
> -{
> - assert_can_disable_dc5(dev_priv);
> -
> - DRM_DEBUG_KMS("Disabling DC5\n");
> -
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> -}
> -
> static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> {
> struct drm_device *dev = dev_priv->dev;
> @@ -522,6 +521,14 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
> "DC6 already programmed to be disabled.\n");
> }
>
> +static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
> +{
> + assert_can_disable_dc5(dev_priv);
> + assert_can_disable_dc6(dev_priv);
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +}
> +
> void skl_enable_dc6(struct drm_i915_private *dev_priv)
> {
> assert_can_enable_dc6(dev_priv);
> @@ -589,17 +596,13 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> "Invalid for power well status to be enabled, unless done by the BIOS, \
> when request is to disable!\n");
> if (power_well->data == SKL_DISP_PW_2) {
> - if (GEN9_ENABLE_DC5(dev))
> - gen9_disable_dc5(dev_priv);
> - if (SKL_ENABLE_DC6(dev)) {
> - /*
> - * DDI buffer programming unnecessary during driver-load/resume
> - * as it's already done during modeset initialization then.
> - * It's also invalid here as encoder list is still uninitialized.
> - */
> - if (!dev_priv->power_domains.initializing)
> - intel_prepare_ddi(dev);
> - }
> + /*
> + * DDI buffer programming unnecessary during driver-load/resume
> + * as it's already done during modeset initialization then.
> + * It's also invalid here as encoder list is still uninitialized.
> + */
> + if (!dev_priv->power_domains.initializing)
> + intel_prepare_ddi(dev);
> }
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
> }
> @@ -617,10 +620,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
> POSTING_READ(HSW_PWR_WELL_DRIVER);
> DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
> -
> - if (GEN9_ENABLE_DC5(dev) &&
> - power_well->data == SKL_DISP_PW_2)
> - gen9_enable_dc5(dev_priv);
> }
> }
>
> @@ -695,6 +694,40 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
> skl_set_power_well(dev_priv, power_well, false);
> }
>
> +static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> +}
> +
> +static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + gen9_disable_dc5_dc6(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + if (IS_SKYLAKE(dev_priv))
> + skl_enable_dc6(dev_priv);
> + else
> + gen9_enable_dc5(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + if (power_well->count > 0) {
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + } else {
> + if (IS_SKYLAKE(dev_priv))
> + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
> + else
> + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> + }
> +}
> +
> static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> @@ -1517,6 +1550,13 @@ static const struct i915_power_well_ops skl_power_well_ops = {
> .is_enabled = skl_power_well_enabled,
> };
>
> +static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
> + .sync_hw = gen9_dc_off_power_well_sync_hw,
> + .enable = gen9_dc_off_power_well_enable,
> + .disable = gen9_dc_off_power_well_disable,
> + .is_enabled = gen9_dc_off_power_well_enabled,
> +};
> +
> static struct i915_power_well hsw_power_wells[] = {
> {
> .name = "always-on",
> @@ -1691,6 +1731,12 @@ static struct i915_power_well skl_power_wells[] = {
> .data = SKL_DISP_PW_MISC_IO,
> },
> {
> + .name = "DC off",
> + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .data = SKL_DISP_PW_DC_OFF,
> + },
> + {
> .name = "power well 2",
> .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> @@ -1769,7 +1815,14 @@ static struct i915_power_well bxt_power_wells[] = {
> .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> .data = SKL_DISP_PW_2,
> - }
> + },
> + {
> + .name = "DC off",
> + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .data = SKL_DISP_PW_DC_OFF,
> + },
> +
You forgot to move this one. With that fixed the patch looks ok and my
R-b holds.
> };
>
> #define set_power_wells(power_domains, __power_wells) ({ \
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v3 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-16 19:28 ` [PATCH v3 " Imre Deak
@ 2015-11-16 19:46 ` Patrik Jakobsson
0 siblings, 0 replies; 47+ messages in thread
From: Patrik Jakobsson @ 2015-11-16 19:46 UTC (permalink / raw)
To: imre.deak; +Cc: Intel Graphics Development
On Mon, Nov 16, 2015 at 8:28 PM, Imre Deak <imre.deak@intel.com> wrote:
> On ma, 2015-11-16 at 15:01 +0100, Patrik Jakobsson wrote:
>> Handle DC off as a power well where enabling the power well will prevent
>> the DMC to enter selected DC states (required around modesets and Aux
>> A). Disabling the power well will allow DC states again. For now the
>> highest DC state is DC6 for Skylake and DC5 for Broxton but will be
>> configurable for Skylake in a later patch.
>>
>> v2: Check both DC5 and DC6 bits in power well enabled function (Ville)
>> v3:
>> - Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
>> - Add PW2 dependency to DC_OFF (Imre)
>>
>> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
>> Reviewed-by: Imre Deak <imre.deak@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.c | 6 --
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_display.c | 6 ++
>> drivers/gpu/drm/i915/intel_runtime_pm.c | 111 +++++++++++++++++++++++---------
>> 4 files changed, 89 insertions(+), 35 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index 5a63f9a..0c7f435 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
>>
>> static int skl_suspend_complete(struct drm_i915_private *dev_priv)
>> {
>> - if (dev_priv->csr.dmc_payload)
>> - skl_enable_dc6(dev_priv);
>> -
>> return 0;
>> }
>>
>> @@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
>>
>> static int skl_resume_prepare(struct drm_i915_private *dev_priv)
>> {
>> - if (dev_priv->csr.dmc_payload)
>> - skl_disable_dc6(dev_priv);
>> -
>> return 0;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 0f3849f..b6a3525 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -638,6 +638,7 @@ enum skl_disp_power_wells {
>>
>> /* Not actual bit groups. Used as IDs for lookup_power_well() */
>> SKL_DISP_PW_ALWAYS_ON,
>> + SKL_DISP_PW_DC_OFF,
>> };
>>
>> #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 978b1b9..21385a0 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -13323,6 +13323,9 @@ static int intel_atomic_commit(struct drm_device *dev,
>> to_intel_crtc_state(crtc->state)->update_pipe;
>> unsigned long put_domains = 0;
>>
>> + if (modeset)
>> + intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
>> +
>> if (modeset && crtc->state->active) {
>> update_scanline_offset(to_intel_crtc(crtc));
>> dev_priv->display.crtc_enable(crtc);
>> @@ -13346,6 +13349,9 @@ static int intel_atomic_commit(struct drm_device *dev,
>> modeset_put_power_domains(dev_priv, put_domains);
>>
>> intel_post_plane_update(intel_crtc);
>> +
>> + if (modeset)
>> + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
>> }
>>
>> /* FIXME: add subpixel order */
>> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> index edf753e..b6ee48e 100644
>> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> @@ -49,9 +49,6 @@
>> * present for a given platform.
>> */
>>
>> -#define GEN9_ENABLE_DC5(dev) 0
>> -#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
>> -
>> #define for_each_power_well(i, power_well, domain_mask, power_domains) \
>> for (i = 0; \
>> i < (power_domains)->power_well_count && \
>> @@ -309,9 +306,15 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>> #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
>> BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
>> BIT(POWER_DOMAIN_INIT))
>> +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
>> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
>> + BIT(POWER_DOMAIN_MODESET) | \
>> + BIT(POWER_DOMAIN_AUX_A) | \
>> + BIT(POWER_DOMAIN_INIT))
>> #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
>> (POWER_DOMAIN_MASK & ~( \
>> - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
>> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
>> + SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
>> BIT(POWER_DOMAIN_INIT))
>>
>> #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
>> @@ -339,6 +342,11 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>> BIT(POWER_DOMAIN_AUX_A) | \
>> BIT(POWER_DOMAIN_PLLS) | \
>> BIT(POWER_DOMAIN_INIT))
>> +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
>> + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
>> + BIT(POWER_DOMAIN_MODESET) | \
>> + BIT(POWER_DOMAIN_AUX_A) | \
>> + BIT(POWER_DOMAIN_INIT))
>> #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
>> (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
>> BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
>> @@ -486,15 +494,6 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
>> gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
>> }
>>
>> -static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
>> -{
>> - assert_can_disable_dc5(dev_priv);
>> -
>> - DRM_DEBUG_KMS("Disabling DC5\n");
>> -
>> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>> -}
>> -
>> static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
>> {
>> struct drm_device *dev = dev_priv->dev;
>> @@ -522,6 +521,14 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
>> "DC6 already programmed to be disabled.\n");
>> }
>>
>> +static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
>> +{
>> + assert_can_disable_dc5(dev_priv);
>> + assert_can_disable_dc6(dev_priv);
>> +
>> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>> +}
>> +
>> void skl_enable_dc6(struct drm_i915_private *dev_priv)
>> {
>> assert_can_enable_dc6(dev_priv);
>> @@ -589,17 +596,13 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>> "Invalid for power well status to be enabled, unless done by the BIOS, \
>> when request is to disable!\n");
>> if (power_well->data == SKL_DISP_PW_2) {
>> - if (GEN9_ENABLE_DC5(dev))
>> - gen9_disable_dc5(dev_priv);
>> - if (SKL_ENABLE_DC6(dev)) {
>> - /*
>> - * DDI buffer programming unnecessary during driver-load/resume
>> - * as it's already done during modeset initialization then.
>> - * It's also invalid here as encoder list is still uninitialized.
>> - */
>> - if (!dev_priv->power_domains.initializing)
>> - intel_prepare_ddi(dev);
>> - }
>> + /*
>> + * DDI buffer programming unnecessary during driver-load/resume
>> + * as it's already done during modeset initialization then.
>> + * It's also invalid here as encoder list is still uninitialized.
>> + */
>> + if (!dev_priv->power_domains.initializing)
>> + intel_prepare_ddi(dev);
>> }
>> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
>> }
>> @@ -617,10 +620,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
>> POSTING_READ(HSW_PWR_WELL_DRIVER);
>> DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
>> -
>> - if (GEN9_ENABLE_DC5(dev) &&
>> - power_well->data == SKL_DISP_PW_2)
>> - gen9_enable_dc5(dev_priv);
>> }
>> }
>>
>> @@ -695,6 +694,40 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
>> skl_set_power_well(dev_priv, power_well, false);
>> }
>>
>> +static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
>> + struct i915_power_well *power_well)
>> +{
>> + return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
>> +}
>> +
>> +static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
>> + struct i915_power_well *power_well)
>> +{
>> + gen9_disable_dc5_dc6(dev_priv);
>> +}
>> +
>> +static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
>> + struct i915_power_well *power_well)
>> +{
>> + if (IS_SKYLAKE(dev_priv))
>> + skl_enable_dc6(dev_priv);
>> + else
>> + gen9_enable_dc5(dev_priv);
>> +}
>> +
>> +static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
>> + struct i915_power_well *power_well)
>> +{
>> + if (power_well->count > 0) {
>> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>> + } else {
>> + if (IS_SKYLAKE(dev_priv))
>> + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
>> + else
>> + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
>> + }
>> +}
>> +
>> static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
>> struct i915_power_well *power_well)
>> {
>> @@ -1517,6 +1550,13 @@ static const struct i915_power_well_ops skl_power_well_ops = {
>> .is_enabled = skl_power_well_enabled,
>> };
>>
>> +static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
>> + .sync_hw = gen9_dc_off_power_well_sync_hw,
>> + .enable = gen9_dc_off_power_well_enable,
>> + .disable = gen9_dc_off_power_well_disable,
>> + .is_enabled = gen9_dc_off_power_well_enabled,
>> +};
>> +
>> static struct i915_power_well hsw_power_wells[] = {
>> {
>> .name = "always-on",
>> @@ -1691,6 +1731,12 @@ static struct i915_power_well skl_power_wells[] = {
>> .data = SKL_DISP_PW_MISC_IO,
>> },
>> {
>> + .name = "DC off",
>> + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
>> + .ops = &gen9_dc_off_power_well_ops,
>> + .data = SKL_DISP_PW_DC_OFF,
>> + },
>> + {
>> .name = "power well 2",
>> .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
>> .ops = &skl_power_well_ops,
>> @@ -1769,7 +1815,14 @@ static struct i915_power_well bxt_power_wells[] = {
>> .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
>> .ops = &skl_power_well_ops,
>> .data = SKL_DISP_PW_2,
>> - }
>> + },
>> + {
>> + .name = "DC off",
>> + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
>> + .ops = &gen9_dc_off_power_well_ops,
>> + .data = SKL_DISP_PW_DC_OFF,
>> + },
>> +
>
> You forgot to move this one. With that fixed the patch looks ok and my
> R-b holds.
Yea sorry about that. There's already a v4 available.
>
>> };
>>
>> #define set_power_wells(power_domains, __power_wells) ({ \
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH 12/12] drm/i915/skl: Remove unused suspend and resume callbacks
2015-11-09 15:48 ` [PATCH 12/12] drm/i915/skl: Remove unused suspend and resume callbacks Patrik Jakobsson
@ 2015-11-17 18:28 ` Imre Deak
0 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2015-11-17 18:28 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 17 -----------------
> 1 file changed, 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 0c7f435..77d183d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -622,7 +622,6 @@ static void intel_suspend_encoders(struct
> drm_i915_private *dev_priv)
> static int intel_suspend_complete(struct drm_i915_private
> *dev_priv);
> static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
> bool rpm_resume);
> -static int skl_resume_prepare(struct drm_i915_private *dev_priv);
> static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
>
>
> @@ -857,8 +856,6 @@ static int i915_drm_resume_early(struct
> drm_device *dev)
>
> if (IS_BROXTON(dev))
> ret = bxt_resume_prepare(dev_priv);
> - else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> - ret = skl_resume_prepare(dev_priv);
> else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> hsw_disable_pc8(dev_priv);
>
> @@ -1070,11 +1067,6 @@ static int i915_pm_resume(struct device *dev)
> return i915_drm_resume(drm_dev);
> }
>
> -static int skl_suspend_complete(struct drm_i915_private *dev_priv)
> -{
> - return 0;
> -}
> -
> static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
> {
> hsw_enable_pc8(dev_priv);
> @@ -1114,11 +1106,6 @@ static int bxt_resume_prepare(struct
> drm_i915_private *dev_priv)
> return 0;
> }
>
> -static int skl_resume_prepare(struct drm_i915_private *dev_priv)
> -{
> - return 0;
> -}
> -
> /*
> * Save all Gunit registers that may be lost after a D3 and a
> subsequent
> * S0i[R123] transition. The list of registers needing a
> save/restore is
> @@ -1582,8 +1569,6 @@ static int intel_runtime_resume(struct device
> *device)
>
> if (IS_BROXTON(dev))
> ret = bxt_resume_prepare(dev_priv);
> - else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> - ret = skl_resume_prepare(dev_priv);
> else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> hsw_disable_pc8(dev_priv);
> else if (IS_VALLEYVIEW(dev_priv))
> @@ -1626,8 +1611,6 @@ static int intel_suspend_complete(struct
> drm_i915_private *dev_priv)
>
> if (IS_BROXTON(dev_priv))
> ret = bxt_suspend_complete(dev_priv);
> - else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> - ret = skl_suspend_complete(dev_priv);
> else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> ret = hsw_suspend_complete(dev_priv);
> else if (IS_VALLEYVIEW(dev_priv))
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-16 15:20 ` [PATCH v4 " Patrik Jakobsson
@ 2015-11-17 19:21 ` Imre Deak
2015-11-23 22:58 ` Matt Roper
1 sibling, 0 replies; 47+ messages in thread
From: Imre Deak @ 2015-11-17 19:21 UTC (permalink / raw)
To: Patrik Jakobsson, intel-gfx
On ma, 2015-11-16 at 16:20 +0100, Patrik Jakobsson wrote:
> Handle DC off as a power well where enabling the power well will
> prevent
> the DMC to enter selected DC states (required around modesets and Aux
> A). Disabling the power well will allow DC states again. For now the
> highest DC state is DC6 for Skylake and DC5 for Broxton but will be
> configurable for Skylake in a later patch.
>
> v2: Check both DC5 and DC6 bits in power well enabled function
> (Ville)
> v3:
> - Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
> - Add PW2 dependency to DC_OFF (Imre)
> v4: Put DC_OFF before PW2 in BXT power well array
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
This has some checkpatch errors, I fixed them up while applying.
> ---
> drivers/gpu/drm/i915/i915_drv.c | 6 --
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 6 ++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 110
> +++++++++++++++++++++++---------
> 4 files changed, 88 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 5a63f9a..0c7f435 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
>
> static int skl_suspend_complete(struct drm_i915_private *dev_priv)
> {
> - if (dev_priv->csr.dmc_payload)
> - skl_enable_dc6(dev_priv);
> -
> return 0;
> }
>
> @@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct
> drm_i915_private *dev_priv)
>
> static int skl_resume_prepare(struct drm_i915_private *dev_priv)
> {
> - if (dev_priv->csr.dmc_payload)
> - skl_disable_dc6(dev_priv);
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 0f3849f..b6a3525 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -638,6 +638,7 @@ enum skl_disp_power_wells {
>
> /* Not actual bit groups. Used as IDs for
> lookup_power_well() */
> SKL_DISP_PW_ALWAYS_ON,
> + SKL_DISP_PW_DC_OFF,
> };
>
> #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 978b1b9..21385a0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13323,6 +13323,9 @@ static int intel_atomic_commit(struct
> drm_device *dev,
> to_intel_crtc_state(crtc->state)-
> >update_pipe;
> unsigned long put_domains = 0;
>
> + if (modeset)
> + intel_display_power_get(dev_priv,
> POWER_DOMAIN_MODESET);
> +
> if (modeset && crtc->state->active) {
> update_scanline_offset(to_intel_crtc(crtc));
> dev_priv->display.crtc_enable(crtc);
> @@ -13346,6 +13349,9 @@ static int intel_atomic_commit(struct
> drm_device *dev,
> modeset_put_power_domains(dev_priv,
> put_domains);
>
> intel_post_plane_update(intel_crtc);
> +
> + if (modeset)
> + intel_display_power_put(dev_priv,
> POWER_DOMAIN_MODESET);
> }
>
> /* FIXME: add subpixel order */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index edf753e..0ff1646 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -49,9 +49,6 @@
> * present for a given platform.
> */
>
> -#define GEN9_ENABLE_DC5(dev) 0
> -#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
> -
> #define for_each_power_well(i, power_well, domain_mask,
> power_domains) \
> for (i = 0;
> \
> i < (power_domains)->power_well_count &&
> \
> @@ -309,9 +306,15 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~( \
> - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> @@ -339,6 +342,11 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_AUX_A) | \
> BIT(POWER_DOMAIN_PLLS) | \
> BIT(POWER_DOMAIN_INIT))
> +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS
> | \
> BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> @@ -486,15 +494,6 @@ static void gen9_enable_dc5(struct
> drm_i915_private *dev_priv)
> gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> }
>
> -static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
> -{
> - assert_can_disable_dc5(dev_priv);
> -
> - DRM_DEBUG_KMS("Disabling DC5\n");
> -
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> -}
> -
> static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> {
> struct drm_device *dev = dev_priv->dev;
> @@ -522,6 +521,14 @@ static void assert_can_disable_dc6(struct
> drm_i915_private *dev_priv)
> "DC6 already programmed to be disabled.\n");
> }
>
> +static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
> +{
> + assert_can_disable_dc5(dev_priv);
> + assert_can_disable_dc6(dev_priv);
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +}
> +
> void skl_enable_dc6(struct drm_i915_private *dev_priv)
> {
> assert_can_enable_dc6(dev_priv);
> @@ -589,17 +596,13 @@ static void skl_set_power_well(struct
> drm_i915_private *dev_priv,
> "Invalid for power well status to be
> enabled, unless done by the BIOS, \
> when request is to disable!\n");
> if (power_well->data == SKL_DISP_PW_2) {
> - if (GEN9_ENABLE_DC5(dev))
> - gen9_disable_dc5(dev_priv);
> - if (SKL_ENABLE_DC6(dev)) {
> - /*
> - * DDI buffer programming
> unnecessary during driver-load/resume
> - * as it's already done
> during modeset initialization then.
> - * It's also invalid here as
> encoder list is still uninitialized.
> - */
> - if (!dev_priv-
> >power_domains.initializing)
> - intel_prepare_ddi(de
> v);
> - }
> + /*
> + * DDI buffer programming
> unnecessary during driver-load/resume
> + * as it's already done during
> modeset initialization then.
> + * It's also invalid here as encoder
> list is still uninitialized.
> + */
> + if (!dev_priv-
> >power_domains.initializing)
> + intel_prepare_ddi(dev);
> }
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp |
> req_mask);
> }
> @@ -617,10 +620,6 @@ static void skl_set_power_well(struct
> drm_i915_private *dev_priv,
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp &
> ~req_mask);
> POSTING_READ(HSW_PWR_WELL_DRIVER);
> DRM_DEBUG_KMS("Disabling %s\n", power_well-
> >name);
> -
> - if (GEN9_ENABLE_DC5(dev) &&
> - power_well->data == SKL_DISP_PW_2)
> - gen9_enable_dc5(dev_priv);
> }
> }
>
> @@ -695,6 +694,40 @@ static void skl_power_well_disable(struct
> drm_i915_private *dev_priv,
> skl_set_power_well(dev_priv, power_well, false);
> }
>
> +static bool gen9_dc_off_power_well_enabled(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + return (I915_READ(DC_STATE_EN) &
> DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> +}
> +
> +static void gen9_dc_off_power_well_enable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + gen9_disable_dc5_dc6(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + if (IS_SKYLAKE(dev_priv))
> + skl_enable_dc6(dev_priv);
> + else
> + gen9_enable_dc5(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + if (power_well->count > 0) {
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + } else {
> + if (IS_SKYLAKE(dev_priv))
> + gen9_set_dc_state(dev_priv,
> DC_STATE_EN_UPTO_DC6);
> + else
> + gen9_set_dc_state(dev_priv,
> DC_STATE_EN_UPTO_DC5);
> + }
> +}
> +
> static void i9xx_always_on_power_well_noop(struct drm_i915_private
> *dev_priv,
> struct i915_power_well
> *power_well)
> {
> @@ -1517,6 +1550,13 @@ static const struct i915_power_well_ops
> skl_power_well_ops = {
> .is_enabled = skl_power_well_enabled,
> };
>
> +static const struct i915_power_well_ops gen9_dc_off_power_well_ops =
> {
> + .sync_hw = gen9_dc_off_power_well_sync_hw,
> + .enable = gen9_dc_off_power_well_enable,
> + .disable = gen9_dc_off_power_well_disable,
> + .is_enabled = gen9_dc_off_power_well_enabled,
> +};
> +
> static struct i915_power_well hsw_power_wells[] = {
> {
> .name = "always-on",
> @@ -1691,6 +1731,12 @@ static struct i915_power_well
> skl_power_wells[] = {
> .data = SKL_DISP_PW_MISC_IO,
> },
> {
> + .name = "DC off",
> + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .data = SKL_DISP_PW_DC_OFF,
> + },
> + {
> .name = "power well 2",
> .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> @@ -1765,11 +1811,17 @@ static struct i915_power_well
> bxt_power_wells[] = {
> .data = SKL_DISP_PW_1,
> },
> {
> + .name = "DC off",
> + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .data = SKL_DISP_PW_DC_OFF,
> + },
> + {
> .name = "power well 2",
> .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> .data = SKL_DISP_PW_2,
> - }
> + },
> };
>
> #define set_power_wells(power_domains, __power_wells) ({
> \
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
` (11 preceding siblings ...)
2015-11-09 15:48 ` [PATCH 12/12] drm/i915/skl: Remove unused suspend and resume callbacks Patrik Jakobsson
@ 2015-11-17 19:54 ` Imre Deak
12 siblings, 0 replies; 47+ messages in thread
From: Imre Deak @ 2015-11-17 19:54 UTC (permalink / raw)
To: Patrik Jakobsson, Ville Syrjälä; +Cc: intel-gfx
On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> This v2 of the series is rebased on top of a new series from Imre [1]
> and contains a few new patches and reordering.
>
> These patches should sit on top of the DMC redesign patches from
> Animesh/Imre [2] which in turn depends on Mika's FW debug patches
> [3].
>
> First couple of patches are from Ville and is included since they
> otherwise might be forgotten. The third from Ville helps with
> handling
> DC off when doing Aux A communication.
I pushed the series to dinq. Thanks for the patches and the review.
--Imre
> [1]
> http://lists.freedesktop.org/archives/intel-gfx/2015-November/079412.
> html
>
> [2]
> http://lists.freedesktop.org/archives/intel-gfx/2015-October/079041.h
> tml
>
> [3]
> http://lists.freedesktop.org/archives/intel-gfx/2015-October/078898.h
> tml
>
> Patrik Jakobsson (9):
> drm/i915: Don't trust CSR program memory contents
> drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6
> drm/i915: Remove distinction between DDI 2 vs 4 lanes
> drm/i915: Add a modeset power domain
> drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()
> drm/i915: Explain usage of power well IDs vs bit groups
> drm/i915/gen9: Turn DC handling into a power well
> drm/i915/gen9: Add boot parameter for disabling DC6
> drm/i915/skl: Remove unused suspend and resume callbacks
>
> Ville Syrjälä (3):
> drm/i915: Clean up AUX power domain handling
> drm/i915: Introduce a gmbus power domain
> drm/i915: Remove DDI power domain exclusion
> SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS
>
> drivers/gpu/drm/i915/i915_debugfs.c | 32 ++--
> drivers/gpu/drm/i915/i915_drv.c | 23 ---
> drivers/gpu/drm/i915/i915_drv.h | 17 +--
> drivers/gpu/drm/i915/i915_params.c | 6 +
> drivers/gpu/drm/i915/i915_reg.h | 3 +
> drivers/gpu/drm/i915/intel_csr.c | 10 +-
> drivers/gpu/drm/i915/intel_display.c | 56 ++++++-
> drivers/gpu/drm/i915/intel_dp.c | 48 ++----
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 8 +-
> drivers/gpu/drm/i915/intel_i2c.c | 6 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 255 ++++++++++++++++----
> ------------
> 12 files changed, 233 insertions(+), 235 deletions(-)
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-16 15:20 ` [PATCH v4 " Patrik Jakobsson
2015-11-17 19:21 ` Imre Deak
@ 2015-11-23 22:58 ` Matt Roper
2015-11-23 23:09 ` Imre Deak
1 sibling, 1 reply; 47+ messages in thread
From: Matt Roper @ 2015-11-23 22:58 UTC (permalink / raw)
To: Patrik Jakobsson; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 11459 bytes --]
On Mon, Nov 16, 2015 at 04:20:01PM +0100, Patrik Jakobsson wrote:
> Handle DC off as a power well where enabling the power well will prevent
> the DMC to enter selected DC states (required around modesets and Aux
> A). Disabling the power well will allow DC states again. For now the
> highest DC state is DC6 for Skylake and DC5 for Broxton but will be
> configurable for Skylake in a later patch.
>
> v2: Check both DC5 and DC6 bits in power well enabled function (Ville)
> v3:
> - Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
> - Add PW2 dependency to DC_OFF (Imre)
> v4: Put DC_OFF before PW2 in BXT power well array
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
I've been seeing a BXT regression on recent di-nightly where DPMS off
causes the entire platform to power down[1] instead of just the display;
my bisect lands on this commit as the culprit. Any idea what the cause
could be? I can reproduce by either letting the system sit idle long
enough at an fb console, or by doing an "xset dpms force off" in X.
Unfortunately I don't have a functioning serial console on this
platform, so I can't get any messages that may show up around the DPMS
operation. I've attached my boot-time dmesg output in case that helps.
Subsequent commits seem to depend on the changes here, so I haven't
reverted this commit directly on di-nightly, but I confirmed that if I
checkout this commit directly I see DPMS problems, whereas its HEAD~1
works as expected.
Matt
[1] My BIOS and/or hardware is a bit flaky so even when operating
"normally" most attempts to reboot/poweroff/S3 suspend all result in the
platform going into some "mostly off" state with an error LED lit and
require a full power cycle to resurrect. That's the same state I wind
up in after DPMS off when this patch is present.
> ---
> drivers/gpu/drm/i915/i915_drv.c | 6 --
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 6 ++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 110 +++++++++++++++++++++++---------
> 4 files changed, 88 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5a63f9a..0c7f435 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
>
> static int skl_suspend_complete(struct drm_i915_private *dev_priv)
> {
> - if (dev_priv->csr.dmc_payload)
> - skl_enable_dc6(dev_priv);
> -
> return 0;
> }
>
> @@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
>
> static int skl_resume_prepare(struct drm_i915_private *dev_priv)
> {
> - if (dev_priv->csr.dmc_payload)
> - skl_disable_dc6(dev_priv);
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0f3849f..b6a3525 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -638,6 +638,7 @@ enum skl_disp_power_wells {
>
> /* Not actual bit groups. Used as IDs for lookup_power_well() */
> SKL_DISP_PW_ALWAYS_ON,
> + SKL_DISP_PW_DC_OFF,
> };
>
> #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 978b1b9..21385a0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13323,6 +13323,9 @@ static int intel_atomic_commit(struct drm_device *dev,
> to_intel_crtc_state(crtc->state)->update_pipe;
> unsigned long put_domains = 0;
>
> + if (modeset)
> + intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
> +
> if (modeset && crtc->state->active) {
> update_scanline_offset(to_intel_crtc(crtc));
> dev_priv->display.crtc_enable(crtc);
> @@ -13346,6 +13349,9 @@ static int intel_atomic_commit(struct drm_device *dev,
> modeset_put_power_domains(dev_priv, put_domains);
>
> intel_post_plane_update(intel_crtc);
> +
> + if (modeset)
> + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
> }
>
> /* FIXME: add subpixel order */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index edf753e..0ff1646 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -49,9 +49,6 @@
> * present for a given platform.
> */
>
> -#define GEN9_ENABLE_DC5(dev) 0
> -#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
> -
> #define for_each_power_well(i, power_well, domain_mask, power_domains) \
> for (i = 0; \
> i < (power_domains)->power_well_count && \
> @@ -309,9 +306,15 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~( \
> - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> @@ -339,6 +342,11 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_AUX_A) | \
> BIT(POWER_DOMAIN_PLLS) | \
> BIT(POWER_DOMAIN_INIT))
> +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
> BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> @@ -486,15 +494,6 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> }
>
> -static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
> -{
> - assert_can_disable_dc5(dev_priv);
> -
> - DRM_DEBUG_KMS("Disabling DC5\n");
> -
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> -}
> -
> static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> {
> struct drm_device *dev = dev_priv->dev;
> @@ -522,6 +521,14 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
> "DC6 already programmed to be disabled.\n");
> }
>
> +static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
> +{
> + assert_can_disable_dc5(dev_priv);
> + assert_can_disable_dc6(dev_priv);
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +}
> +
> void skl_enable_dc6(struct drm_i915_private *dev_priv)
> {
> assert_can_enable_dc6(dev_priv);
> @@ -589,17 +596,13 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> "Invalid for power well status to be enabled, unless done by the BIOS, \
> when request is to disable!\n");
> if (power_well->data == SKL_DISP_PW_2) {
> - if (GEN9_ENABLE_DC5(dev))
> - gen9_disable_dc5(dev_priv);
> - if (SKL_ENABLE_DC6(dev)) {
> - /*
> - * DDI buffer programming unnecessary during driver-load/resume
> - * as it's already done during modeset initialization then.
> - * It's also invalid here as encoder list is still uninitialized.
> - */
> - if (!dev_priv->power_domains.initializing)
> - intel_prepare_ddi(dev);
> - }
> + /*
> + * DDI buffer programming unnecessary during driver-load/resume
> + * as it's already done during modeset initialization then.
> + * It's also invalid here as encoder list is still uninitialized.
> + */
> + if (!dev_priv->power_domains.initializing)
> + intel_prepare_ddi(dev);
> }
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
> }
> @@ -617,10 +620,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
> POSTING_READ(HSW_PWR_WELL_DRIVER);
> DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
> -
> - if (GEN9_ENABLE_DC5(dev) &&
> - power_well->data == SKL_DISP_PW_2)
> - gen9_enable_dc5(dev_priv);
> }
> }
>
> @@ -695,6 +694,40 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
> skl_set_power_well(dev_priv, power_well, false);
> }
>
> +static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> +}
> +
> +static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + gen9_disable_dc5_dc6(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + if (IS_SKYLAKE(dev_priv))
> + skl_enable_dc6(dev_priv);
> + else
> + gen9_enable_dc5(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + if (power_well->count > 0) {
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + } else {
> + if (IS_SKYLAKE(dev_priv))
> + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
> + else
> + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> + }
> +}
> +
> static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> @@ -1517,6 +1550,13 @@ static const struct i915_power_well_ops skl_power_well_ops = {
> .is_enabled = skl_power_well_enabled,
> };
>
> +static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
> + .sync_hw = gen9_dc_off_power_well_sync_hw,
> + .enable = gen9_dc_off_power_well_enable,
> + .disable = gen9_dc_off_power_well_disable,
> + .is_enabled = gen9_dc_off_power_well_enabled,
> +};
> +
> static struct i915_power_well hsw_power_wells[] = {
> {
> .name = "always-on",
> @@ -1691,6 +1731,12 @@ static struct i915_power_well skl_power_wells[] = {
> .data = SKL_DISP_PW_MISC_IO,
> },
> {
> + .name = "DC off",
> + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .data = SKL_DISP_PW_DC_OFF,
> + },
> + {
> .name = "power well 2",
> .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> @@ -1765,11 +1811,17 @@ static struct i915_power_well bxt_power_wells[] = {
> .data = SKL_DISP_PW_1,
> },
> {
> + .name = "DC off",
> + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .data = SKL_DISP_PW_DC_OFF,
> + },
> + {
> .name = "power well 2",
> .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> .data = SKL_DISP_PW_2,
> - }
> + },
> };
>
> #define set_power_wells(power_domains, __power_wells) ({ \
> --
> 2.5.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
[-- Attachment #2: dmesg-boot.txt --]
[-- Type: text/plain, Size: 108294 bytes --]
[ 0.000000] Initializing cgroup subsys cpuset
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Initializing cgroup subsys cpuacct
[ 0.000000] Linux version 4.3.0-rc3mdr+ (mattrope@mdroper-hswdev) (gcc version 4.9.2 (Debian 4.9.2-10) ) #315 SMP PREEMPT Mon Nov 23 12:35:55 PST 2015
[ 0.000000] Command line: gmskernel.efi drm.debug=0xf
[ 0.000000] x86/fpu: xstate_offset[2]: 0000, xstate_sizes[2]: 0000
[ 0.000000] x86/fpu: xstate_offset[3]: 03c0, xstate_sizes[3]: 0040
[ 0.000000] x86/fpu: xstate_offset[4]: 0400, xstate_sizes[4]: 0040
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x01: 'x87 floating point registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x02: 'SSE registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x08: 'MPX bounds registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x10: 'MPX CSR'
[ 0.000000] x86/fpu: Enabled xstate features 0x1b, context size is 0x440 bytes, using 'standard' format.
[ 0.000000] x86/fpu: Using 'eager' FPU context switches.
[ 0.000000] e820: BIOS-provided physical RAM map:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable
[ 0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000059000-0x000000000009dfff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009e000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000000effffff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000f000000-0x0000000012550fff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000012551000-0x000000007764afff] usable
[ 0.000000] BIOS-e820: [mem 0x000000007764b000-0x0000000079b33fff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000079b34000-0x0000000079b93fff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x0000000079b94000-0x0000000079bc3fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x0000000079bc4000-0x0000000079e08fff] usable
[ 0.000000] BIOS-e820: [mem 0x0000000079e09000-0x0000000079e09fff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x0000000079e0a000-0x0000000079e33fff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000079e34000-0x000000007affffff] usable
[ 0.000000] BIOS-e820: [mem 0x000000007b000000-0x000000007fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000e006a000-0x00000000e006afff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fed01000-0x00000000fed01fff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x00000001ffffffff] usable
[ 0.000000] NX (Execute Disable) protection: active
[ 0.000000] efi: EFI v2.40 by EDK II
[ 0.000000] efi: ACPI=0x79bc3000 ACPI 2.0=0x79bc3014 ESRT=0x79ad8000 SMBIOS=0x777f4000
[ 0.000000] efi: requested map not found.
[ 0.000000] esrt: ESRT header is not in the memory map.
[ 0.000000] SMBIOS 3.0 present.
[ 0.000000] DMI: Intel Corp. BROXTON P A0 PLATFORM/NOTEBOOK, BIOS BXTI_IFWI_X64_D_2015_10_29_2010 10/29/2015
[ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
[ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
[ 0.000000] e820: last_pfn = 0x200000 max_arch_pfn = 0x400000000
[ 0.000000] MTRR default type: uncachable
[ 0.000000] MTRR fixed ranges enabled:
[ 0.000000] 00000-6FFFF write-back
[ 0.000000] 70000-7FFFF uncachable
[ 0.000000] 80000-9FFFF write-back
[ 0.000000] A0000-BFFFF uncachable
[ 0.000000] C0000-FFFFF write-protect
[ 0.000000] MTRR variable ranges enabled:
[ 0.000000] 0 base 0000000000 mask 7F80000000 write-back
[ 0.000000] 1 base 007C000000 mask 7FFC000000 uncachable
[ 0.000000] 2 base 007B000000 mask 7FFF000000 uncachable
[ 0.000000] 3 base 0100000000 mask 7F00000000 write-back
[ 0.000000] 4 disabled
[ 0.000000] 5 disabled
[ 0.000000] 6 disabled
[ 0.000000] 7 disabled
[ 0.000000] 8 disabled
[ 0.000000] 9 disabled
[ 0.000000] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WC UC- WT
[ 0.000000] original variable MTRRs
[ 0.000000] reg 0, base: 0GB, range: 2GB, type WB
[ 0.000000] reg 1, base: 1984MB, range: 64MB, type UC
[ 0.000000] reg 2, base: 1968MB, range: 16MB, type UC
[ 0.000000] reg 3, base: 4GB, range: 4GB, type WB
[ 0.000000] total RAM covered: 6064M
[ 0.000000] Found optimal setting for mtrr clean up
[ 0.000000] gran_size: 64K chunk_size: 128M num_reg: 4 lose cover RAM: 0G
[ 0.000000] New variable MTRRs
[ 0.000000] reg 0, base: 0GB, range: 2GB, type WB
[ 0.000000] reg 1, base: 1968MB, range: 16MB, type UC
[ 0.000000] reg 2, base: 1984MB, range: 64MB, type UC
[ 0.000000] reg 3, base: 4GB, range: 4GB, type WB
[ 0.000000] e820: update [mem 0x7b000000-0xffffffff] usable ==> reserved
[ 0.000000] e820: last_pfn = 0x7b000 max_arch_pfn = 0x400000000
[ 0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576
[ 0.000000] Using GB pages for direct mapping
[ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff]
[ 0.000000] [mem 0x00000000-0x000fffff] page 4k
[ 0.000000] BRK [0x01f0d000, 0x01f0dfff] PGTABLE
[ 0.000000] BRK [0x01f0e000, 0x01f0efff] PGTABLE
[ 0.000000] BRK [0x01f0f000, 0x01f0ffff] PGTABLE
[ 0.000000] init_memory_mapping: [mem 0x1ffe00000-0x1ffffffff]
[ 0.000000] [mem 0x1ffe00000-0x1ffffffff] page 1G
[ 0.000000] init_memory_mapping: [mem 0x1e0000000-0x1ffdfffff]
[ 0.000000] [mem 0x1e0000000-0x1ffdfffff] page 1G
[ 0.000000] init_memory_mapping: [mem 0x00100000-0x0effffff]
[ 0.000000] [mem 0x00100000-0x001fffff] page 4k
[ 0.000000] [mem 0x00200000-0x0effffff] page 2M
[ 0.000000] init_memory_mapping: [mem 0x12551000-0x7764afff]
[ 0.000000] [mem 0x12551000-0x125fffff] page 4k
[ 0.000000] [mem 0x12600000-0x775fffff] page 2M
[ 0.000000] [mem 0x77600000-0x7764afff] page 4k
[ 0.000000] BRK [0x01f10000, 0x01f10fff] PGTABLE
[ 0.000000] BRK [0x01f11000, 0x01f11fff] PGTABLE
[ 0.000000] BRK [0x01f12000, 0x01f12fff] PGTABLE
[ 0.000000] init_memory_mapping: [mem 0x79bc4000-0x79e08fff]
[ 0.000000] [mem 0x79bc4000-0x79bfffff] page 4k
[ 0.000000] [mem 0x79c00000-0x79dfffff] page 2M
[ 0.000000] [mem 0x79e00000-0x79e08fff] page 4k
[ 0.000000] init_memory_mapping: [mem 0x79e34000-0x7affffff]
[ 0.000000] [mem 0x79e34000-0x79ffffff] page 4k
[ 0.000000] [mem 0x7a000000-0x7affffff] page 2M
[ 0.000000] init_memory_mapping: [mem 0x100000000-0x1dfffffff]
[ 0.000000] [mem 0x100000000-0x1dfffffff] page 1G
[ 0.000000] ACPI: Early table checksum verification disabled
[ 0.000000] ACPI: RSDP 0x0000000079BC3014 000024 (v02 INTEL )
[ 0.000000] ACPI: XSDT 0x0000000079B9C188 0000DC (v01 INTEL EDK2 00000003 BRXT 01000013)
[ 0.000000] ACPI: FACP 0x0000000079BB8000 00010C (v05 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI BIOS Warning (bug): 32/64X length mismatch in FADT/Pm1aEventBlock: 32/16 (20150818/tbfadt-623)
[ 0.000000] ACPI BIOS Warning (bug): Invalid length for FADT/Pm1aEventBlock: 16, using default 32 (20150818/tbfadt-704)
[ 0.000000] ACPI: DSDT 0x0000000079BAB000 007CBF (v02 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: FACS 0x0000000079B8D000 000040
[ 0.000000] ACPI: SSDT 0x0000000079BC1000 0000B1 (v01 Intel_ ADebTabl 00001000 INTL 20120518)
[ 0.000000] ACPI: OEM0 0x0000000079BBF000 000084 (v05 INTEL BATTERY 00000005 INTL 00000000)
[ 0.000000] ACPI: EM_1 0x0000000079BBE000 000029 (v00 INTEL OEM1 00000005 INTL 0100000D)
[ 0.000000] ACPI: OEM1 0x0000000079BBD000 000040 (v01 INTEL ENRGYMGT 00000005 INTL 0100000D)
[ 0.000000] ACPI: PIDV 0x0000000079BBC000 0000DC (v02 00000002 BRXT 0100000D)
[ 0.000000] ACPI: RSCI 0x0000000079BBB000 000030 (v02 INTEL BOOTSRC 00000001 BRXT 0100000D)
[ 0.000000] ACPI: OEM0 0x0000000079BC0000 000084 (v05 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: DBG2 0x0000000079BBA000 000072 (v00 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: HPET 0x0000000079BB7000 000038 (v01 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: LPIT 0x0000000079BB6000 00005C (v01 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: APIC 0x0000000079BB5000 000084 (v03 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: MCFG 0x0000000079BB4000 00003C (v01 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: NPKT 0x0000000079BB3000 000065 (v01 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: SSDT 0x0000000079BA1000 000B2E (v02 INTEL UsbCTabl 00000003 BRXT 0100000D)
[ 0.000000] ACPI: SSDT 0x0000000079B9F000 00108D (v01 Intel_ Platform 00001000 INTL 20120518)
[ 0.000000] ACPI: SSDT 0x0000000079B9E000 0004DE (v02 PmRef Cpu0Ist 00003000 INTL 20120518)
[ 0.000000] ACPI: SSDT 0x0000000079B9D000 000663 (v02 CpuRef CpuSsdt 00003000 INTL 20120518)
[ 0.000000] ACPI: SSDT 0x0000000079B99000 0027A3 (v02 SaSsdt SaSsdt 00003000 INTL 20120518)
[ 0.000000] ACPI: UEFI 0x0000000079B87000 000042 (v01 INTEL EDK2 00000002 BRXT 01000013)
[ 0.000000] ACPI: FPDT 0x0000000079BC2000 000044 (v01 INTEL EDK2 00000002 BRXT 01000013)
[ 0.000000] ACPI: DMAR 0x0000000079BB9000 0000B0 (v01 INTEL EDK2 00000003 BRXT 0100000D)
[ 0.000000] ACPI: NHLT 0x0000000079BA9000 001CB1 (v00 INTEL EDK2 00000002 BRXT 01000013)
[ 0.000000] ACPI: Local APIC address 0xfee00000
[ 0.000000] [ffffea0000000000-ffffea0006ffffff] PMD -> [ffff8801f9600000-ffff8801fe9fffff] on node 0
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000000001000-0x0000000000ffffff]
[ 0.000000] DMA32 [mem 0x0000000001000000-0x00000000ffffffff]
[ 0.000000] Normal [mem 0x0000000100000000-0x00000001ffffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000000001000-0x0000000000057fff]
[ 0.000000] node 0: [mem 0x0000000000059000-0x000000000009dfff]
[ 0.000000] node 0: [mem 0x0000000000100000-0x000000000effffff]
[ 0.000000] node 0: [mem 0x0000000012551000-0x000000007764afff]
[ 0.000000] node 0: [mem 0x0000000079bc4000-0x0000000079e08fff]
[ 0.000000] node 0: [mem 0x0000000079e34000-0x000000007affffff]
[ 0.000000] node 0: [mem 0x0000000100000000-0x00000001ffffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x00000001ffffffff]
[ 0.000000] On node 0 totalpages: 1528999
[ 0.000000] DMA zone: 56 pages used for memmap
[ 0.000000] DMA zone: 3093 pages reserved
[ 0.000000] DMA zone: 3996 pages, LIFO batch:0
[ 0.000000] DMA32 zone: 6514 pages used for memmap
[ 0.000000] DMA32 zone: 476427 pages, LIFO batch:31
[ 0.000000] Normal zone: 14336 pages used for memmap
[ 0.000000] Normal zone: 1048576 pages, LIFO batch:31
[ 0.000000] Reserving Intel graphics stolen memory at 0x7c000000-0x7fffffff
[ 0.000000] ACPI: PM-Timer IO Port: 0x408
[ 0.000000] ACPI: Local APIC address 0xfee00000
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high level lint[0x1])
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high level lint[0x1])
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high level lint[0x1])
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high level lint[0x1])
[ 0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-119
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
[ 0.000000] ACPI: IRQ0 used by override.
[ 0.000000] ACPI: IRQ9 used by override.
[ 0.000000] Using ACPI (MADT) for SMP configuration information
[ 0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000
[ 0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs
[ 0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff]
[ 0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00058fff]
[ 0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x000fffff]
[ 0.000000] PM: Registered nosave memory: [mem 0x0f000000-0x12550fff]
[ 0.000000] PM: Registered nosave memory: [mem 0x7764b000-0x79b33fff]
[ 0.000000] PM: Registered nosave memory: [mem 0x79b34000-0x79b93fff]
[ 0.000000] PM: Registered nosave memory: [mem 0x79b94000-0x79bc3fff]
[ 0.000000] PM: Registered nosave memory: [mem 0x79e09000-0x79e09fff]
[ 0.000000] PM: Registered nosave memory: [mem 0x79e0a000-0x79e33fff]
[ 0.000000] PM: Registered nosave memory: [mem 0x7b000000-0x7fffffff]
[ 0.000000] PM: Registered nosave memory: [mem 0x80000000-0xe0069fff]
[ 0.000000] PM: Registered nosave memory: [mem 0xe006a000-0xe006afff]
[ 0.000000] PM: Registered nosave memory: [mem 0xe006b000-0xfed00fff]
[ 0.000000] PM: Registered nosave memory: [mem 0xfed01000-0xfed01fff]
[ 0.000000] PM: Registered nosave memory: [mem 0xfed02000-0xffffffff]
[ 0.000000] e820: [mem 0x80000000-0xe0069fff] available for PCI devices
[ 0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns
[ 0.000000] setup_percpu: NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:4 nr_node_ids:1
[ 0.000000] PERCPU: Embedded 33 pages/cpu @ffff8801ffc00000 s94984 r8192 d31992 u524288
[ 0.000000] pcpu-alloc: s94984 r8192 d31992 u524288 alloc=1*2097152
[ 0.000000] pcpu-alloc: [0] 0 1 2 3
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1505000
[ 0.000000] Kernel command line: root=/dev/sda2 console=tty0 console=ttyS1,115200n8 maxcpus=4 noxsave i915.preliminary_hw_support=1 psplash=false 3 gmskernel.efi drm.debug=0xf
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
[ 0.000000] Memory: 5870816K/6115996K available (6968K kernel code, 1106K rwdata, 3480K rodata, 1268K init, 13000K bss, 245180K reserved, 0K cma-reserved)
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] Build-time adjustment of leaf fanout to 64.
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4
[ 0.000000] NR_IRQS:4352 nr_irqs:1024 16
[ 0.000000] Console: colour dummy device 80x25
[ 0.000000] console [tty0] enabled
[ 0.000000] console [ttyS1] enabled
[ 0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[ 0.000000] ... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.000000] ... MAX_LOCK_DEPTH: 48
[ 0.000000] ... MAX_LOCKDEP_KEYS: 8191
[ 0.000000] ... CLASSHASH_SIZE: 4096
[ 0.000000] ... MAX_LOCKDEP_ENTRIES: 32768
[ 0.000000] ... MAX_LOCKDEP_CHAINS: 65536
[ 0.000000] ... CHAINHASH_SIZE: 32768
[ 0.000000] memory used by lock dependency info: 8127 kB
[ 0.000000] per task-struct memory footprint: 1920 bytes
[ 0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 99544814920 ns
[ 0.000000] hpet clockevent registered
[ 0.000000] tsc: Fast TSC calibration using PIT
[ 0.000000] tsc: Detected 4748.619 MHz processor
[ 0.000002] Calibrating delay loop (skipped), value calculated using timer frequency.. 9497.23 BogoMIPS (lpj=4748619)
[ 0.000239] pid_max: default: 32768 minimum: 301
[ 0.000363] ACPI: Core revision 20150818
[ 0.061314] ACPI: 7 ACPI AML tables successfully acquired and loaded
[ 0.062936] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes)
[ 0.063096] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes)
[ 0.063929] Initializing cgroup subsys io
[ 0.064043] Initializing cgroup subsys devices
[ 0.064146] Initializing cgroup subsys freezer
[ 0.064258] Initializing cgroup subsys perf_event
[ 0.064428] CPU: Physical Processor ID: 0
[ 0.064525] CPU: Processor Core ID: 0
[ 0.067617] mce: CPU supports 7 MCE banks
[ 0.067743] CPU0: Thermal monitoring enabled (TM1)
[ 0.067861] process: using mwait in idle threads
[ 0.067962] Last level iTLB entries: 4KB 48, 2MB 0, 4MB 0
[ 0.068086] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0
[ 0.068641] Freeing SMP alternatives memory: 24K (ffffffff81253000 - ffffffff81259000)
[ 0.071841] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[ 0.081994] TSC deadline timer enabled
[ 0.081998] smpboot: CPU0: Intel 06/5c (family: 0x6, model: 0x5c, stepping: 0x8)
[ 0.082199] Performance Events: PEBS fmt3+, generic architected perfmon, full-width counters, Intel PMU driver.
[ 0.082434] ... version: 4
[ 0.082521] ... bit width: 48
[ 0.082610] ... generic registers: 4
[ 0.082697] ... value mask: 0000ffffffffffff
[ 0.082810] ... max period: 0000ffffffffffff
[ 0.082923] ... fixed-purpose events: 3
[ 0.083013] ... event mask: 000000070000000f
[ 0.096280] x86: Booting SMP configuration:
[ 0.096374] .... node #0, CPUs: #1 #2 #3
[ 0.117957] x86: Booted up 1 node, 4 CPUs
[ 0.118055] smpboot: Total of 4 processors activated (37988.95 BogoMIPS)
[ 0.119417] devtmpfs: initialized
[ 0.120404] PM: Registering ACPI NVS region [mem 0x79b34000-0x79b93fff] (393216 bytes)
[ 0.120691] PM: Registering ACPI NVS region [mem 0x79e09000-0x79e09fff] (4096 bytes)
[ 0.121177] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
[ 0.121562] pinctrl core: initialized pinctrl subsystem
[ 0.121803] RTC time: 14:59:37, date: 11/17/15
[ 0.122324] NET: Registered protocol family 16
[ 0.127002] cpuidle: using governor ladder
[ 0.132009] cpuidle: using governor menu
[ 0.132240] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
[ 0.132405] ACPI: bus type PCI registered
[ 0.132845] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000)
[ 0.133049] PCI: not using MMCONFIG
[ 0.133126] PCI: Using configuration type 1 for base access
[ 0.146053] ACPI: Added _OSI(Module Device)
[ 0.146153] ACPI: Added _OSI(Processor Device)
[ 0.146249] ACPI: Added _OSI(3.0 _SCP Extensions)
[ 0.146350] ACPI: Added _OSI(Processor Aggregator Device)
[ 0.157403] ACPI: Executed 3 blocks of module-level executable AML code
[ 0.186112] ACPI: Dynamic OEM Table Load:
[ 0.186223] ACPI: SSDT 0xFFFF8801F8BBB940 00009A (v02 PmRef Cpu0Cst 00003001 INTL 20120518)
[ 0.189704] ACPI: Dynamic OEM Table Load:
[ 0.189814] ACPI: SSDT 0xFFFF8801F9127E00 00015F (v02 PmRef ApIst 00003000 INTL 20120518)
[ 0.192340] ACPI: Dynamic OEM Table Load:
[ 0.192448] ACPI: SSDT 0xFFFF8801F9127C00 000119 (v02 PmRef ApCst 00003000 INTL 20120518)
[ 0.192765] ACPI Error: [\_PR_.CPU4] Namespace lookup failure, AE_NOT_FOUND (20150818/dswload-210)
[ 0.192975] ACPI Exception: AE_NOT_FOUND, During name lookup/catalog (20150818/psobject-227)
[ 0.193183] ACPI Error: Method parse/execution failed [\_PR.CPU1.APCT] (Node ffff8801f8423630), AE_NOT_FOUND (20150818/psparse-542)
[ 0.193466] ACPI Error: Method parse/execution failed [\_PR.CPU1.GCAP] (Node ffff8801f8423658), AE_NOT_FOUND (20150818/psparse-542)
[ 0.193745] ACPI Error: Method parse/execution failed [\_PR.CPU1._PDC] (Node ffff8801f84236a8), AE_NOT_FOUND (20150818/psparse-542)
[ 0.199483] ACPI: Interpreter enabled
[ 0.199576] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20150818/hwxface-580)
[ 0.199786] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20150818/hwxface-580)
[ 0.200158] ACPI: (supports S0 S3 S4 S5)
[ 0.200244] ACPI: Using IOAPIC for interrupt routing
[ 0.200499] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000)
[ 0.203760] PCI: MMCONFIG at [mem 0xe0000000-0xe3ffffff] reserved in ACPI motherboard resources
[ 0.203963] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[ 0.274227] ACPI: Power Resource [FN00] (off)
[ 0.276744] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
[ 0.276887] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
[ 0.283639] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME PCIeCapability]
[ 0.283805] acpi PNP0A08:00: FADT indicates ASPM is unsupported, using BIOS configuration
[ 0.284714] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge
[ 0.285250] PCI host bridge to bus 0000:00
[ 0.285343] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 0.285463] pci_bus 0000:00: root bus resource [io 0x0070-0x0077]
[ 0.285713] pci_bus 0000:00: root bus resource [io 0x0000-0x006f window]
[ 0.285860] pci_bus 0000:00: root bus resource [io 0x0078-0x0cf7 window]
[ 0.286006] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window]
[ 0.286153] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
[ 0.286314] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff window]
[ 0.286476] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000fffff window]
[ 0.286640] pci_bus 0000:00: root bus resource [mem 0x7c000001-0x7fffffff window]
[ 0.286802] pci_bus 0000:00: root bus resource [mem 0x80000000-0xcfffffff window]
[ 0.286980] pci 0000:00:00.0: [8086:5af0] type 00 class 0x060000
[ 0.288593] pci 0000:00:00.1: [8086:5a8c] type 00 class 0x118000
[ 0.288614] pci 0000:00:00.1: reg 0x10: [mem 0xb2d10000-0xb2d17fff 64bit]
[ 0.290057] pci 0000:00:00.2: [8086:5a8e] type 00 class 0x130000
[ 0.290072] pci 0000:00:00.2: reg 0x10: [mem 0xb2a00000-0xb2afffff 64bit]
[ 0.290079] pci 0000:00:00.2: reg 0x18: [mem 0xb2000000-0xb27fffff 64bit]
[ 0.290086] pci 0000:00:00.2: reg 0x20: [mem 0xb2d20000-0xb2d201ff 64bit]
[ 0.291495] pci 0000:00:02.0: [8086:5a84] type 00 class 0x030000
[ 0.291508] pci 0000:00:02.0: reg 0x10: [mem 0xb0000000-0xb0ffffff 64bit]
[ 0.291514] pci 0000:00:02.0: reg 0x18: [mem 0xa0000000-0xafffffff 64bit pref]
[ 0.291518] pci 0000:00:02.0: reg 0x20: [io 0x2000-0x203f]
[ 0.293205] pci 0000:00:03.0: [8086:5a88] type 00 class 0x048000
[ 0.293217] pci 0000:00:03.0: reg 0x10: [mem 0xb1000000-0xb1ffffff 64bit]
[ 0.294804] pci 0000:00:0e.0: [8086:5a98] type 00 class 0x040300
[ 0.294828] pci 0000:00:0e.0: reg 0x10: [mem 0xb2d18000-0xb2d1bfff 64bit]
[ 0.294846] pci 0000:00:0e.0: reg 0x20: [mem 0xb2b00000-0xb2bfffff 64bit]
[ 0.294887] pci 0000:00:0e.0: PME# supported from D0 D3hot D3cold
[ 0.297484] pci 0000:00:0e.0: System wakeup disabled by ACPI
[ 0.298028] pci 0000:00:0f.0: [8086:5a9a] type 00 class 0x078000
[ 0.298054] pci 0000:00:0f.0: reg 0x10: [mem 0xb2d21000-0xb2d21fff 64bit]
[ 0.298114] pci 0000:00:0f.0: PME# supported from D3hot
[ 0.299542] pci 0000:00:0f.1: [8086:5a9c] type 00 class 0x078000
[ 0.299559] pci 0000:00:0f.1: reg 0x10: [mem 0xb2d22000-0xb2d22fff 64bit]
[ 0.299606] pci 0000:00:0f.1: PME# supported from D3hot
[ 0.301126] pci 0000:00:0f.2: [8086:5a9e] type 00 class 0x078000
[ 0.301148] pci 0000:00:0f.2: reg 0x10: [mem 0xb2d23000-0xb2d23fff 64bit]
[ 0.301202] pci 0000:00:0f.2: PME# supported from D3hot
[ 0.302740] pci 0000:00:11.0: [8086:5aa2] type 00 class 0x005007
[ 0.302763] pci 0000:00:11.0: reg 0x10: [mem 0xb2d1c000-0xb2d1dfff 64bit]
[ 0.302773] pci 0000:00:11.0: reg 0x18: [mem 0xb2d24000-0xb2d24fff 64bit]
[ 0.304391] pci 0000:00:12.0: [8086:5ae3] type 00 class 0x010601
[ 0.304408] pci 0000:00:12.0: reg 0x10: [mem 0xb2d1e000-0xb2d1ffff]
[ 0.304414] pci 0000:00:12.0: reg 0x14: [mem 0xb2d3c000-0xb2d3c0ff]
[ 0.304419] pci 0000:00:12.0: reg 0x18: [io 0x2080-0x2087]
[ 0.304424] pci 0000:00:12.0: reg 0x1c: [io 0x2088-0x208b]
[ 0.304429] pci 0000:00:12.0: reg 0x20: [io 0x2060-0x207f]
[ 0.304435] pci 0000:00:12.0: reg 0x24: [mem 0xb2d3a000-0xb2d3a7ff]
[ 0.304467] pci 0000:00:12.0: PME# supported from D3hot
[ 0.306067] pci 0000:00:13.0: [8086:5ada] type 01 class 0x060400
[ 0.306128] pci 0000:00:13.0: PME# supported from D0 D3hot D3cold
[ 0.307346] pci 0000:00:13.0: System wakeup disabled by ACPI
[ 0.307893] pci 0000:00:15.0: [8086:5aa8] type 00 class 0x0c0330
[ 0.307915] pci 0000:00:15.0: reg 0x10: [mem 0xb2d00000-0xb2d0ffff 64bit]
[ 0.307965] pci 0000:00:15.0: PME# supported from D3hot D3cold
[ 0.309220] pci 0000:00:15.0: System wakeup disabled by ACPI
[ 0.309656] pci 0000:00:16.0: [8086:5aac] type 00 class 0x118000
[ 0.309677] pci 0000:00:16.0: reg 0x10: [mem 0xb2d26000-0xb2d26fff 64bit]
[ 0.311255] pci 0000:00:16.1: [8086:5aae] type 00 class 0x118000
[ 0.311277] pci 0000:00:16.1: reg 0x10: [mem 0xb2d27000-0xb2d27fff 64bit]
[ 0.312850] pci 0000:00:16.2: [8086:5ab0] type 00 class 0x118000
[ 0.312872] pci 0000:00:16.2: reg 0x10: [mem 0xb2d28000-0xb2d28fff 64bit]
[ 0.314445] pci 0000:00:16.3: [8086:5ab2] type 00 class 0x118000
[ 0.314467] pci 0000:00:16.3: reg 0x10: [mem 0xb2d29000-0xb2d29fff 64bit]
[ 0.316053] pci 0000:00:17.0: [8086:5ab4] type 00 class 0x118000
[ 0.316074] pci 0000:00:17.0: reg 0x10: [mem 0xb2d2a000-0xb2d2afff 64bit]
[ 0.317537] pci 0000:00:17.1: [8086:5ab6] type 00 class 0x118000
[ 0.317555] pci 0000:00:17.1: reg 0x10: [mem 0xb2d2b000-0xb2d2bfff 64bit]
[ 0.319121] pci 0000:00:17.2: [8086:5ab8] type 00 class 0x118000
[ 0.319143] pci 0000:00:17.2: reg 0x10: [mem 0xb2d2c000-0xb2d2cfff 64bit]
[ 0.320725] pci 0000:00:17.3: [8086:5aba] type 00 class 0x118000
[ 0.320747] pci 0000:00:17.3: reg 0x10: [mem 0xb2d2d000-0xb2d2dfff 64bit]
[ 0.322331] pci 0000:00:18.0: [8086:5abc] type 00 class 0x118000
[ 0.322354] pci 0000:00:18.0: reg 0x10: [mem 0xb2d2e000-0xb2d2efff 64bit]
[ 0.323947] pci 0000:00:18.1: [8086:5abe] type 00 class 0x118000
[ 0.323969] pci 0000:00:18.1: reg 0x10: [mem 0xb2d2f000-0xb2d2ffff 64bit]
[ 0.325444] pci 0000:00:18.2: [8086:5ac0] type 00 class 0x118000
[ 0.325466] pci 0000:00:18.2: reg 0x10: [mem 0xb2d30000-0xb2d30fff 64bit]
[ 0.327047] pci 0000:00:18.3: [8086:5aee] type 00 class 0x118000
[ 0.327068] pci 0000:00:18.3: reg 0x10: [mem 0xb2d31000-0xb2d31fff 64bit]
[ 0.328651] pci 0000:00:19.0: [8086:5ac2] type 00 class 0x118000
[ 0.328674] pci 0000:00:19.0: reg 0x10: [mem 0xb2d32000-0xb2d32fff 64bit]
[ 0.330251] pci 0000:00:19.1: [8086:5ac4] type 00 class 0x118000
[ 0.330273] pci 0000:00:19.1: reg 0x10: [mem 0xb2d33000-0xb2d33fff 64bit]
[ 0.331751] pci 0000:00:19.2: [8086:5ac6] type 00 class 0x118000
[ 0.331772] pci 0000:00:19.2: reg 0x10: [mem 0xb2d34000-0xb2d34fff 64bit]
[ 0.333360] pci 0000:00:1a.0: [8086:5ac8] type 00 class 0x0c8000
[ 0.333379] pci 0000:00:1a.0: reg 0x10: [mem 0xb2d35000-0xb2d35fff 64bit]
[ 0.333388] pci 0000:00:1a.0: reg 0x18: [mem 0xb2d36000-0xb2d36fff 64bit]
[ 0.333431] pci 0000:00:1a.0: PME# supported from D0 D3hot
[ 0.335026] pci 0000:00:1b.0: [8086:5aca] type 00 class 0x080501
[ 0.335046] pci 0000:00:1b.0: reg 0x10: [mem 0xb2d37000-0xb2d37fff 64bit]
[ 0.336808] pci 0000:00:1c.0: [8086:5acc] type 00 class 0x080501
[ 0.336827] pci 0000:00:1c.0: reg 0x10: [mem 0xb2d38000-0xb2d38fff 64bit]
[ 0.338583] pci 0000:00:1e.0: [8086:5ad0] type 00 class 0x080501
[ 0.338602] pci 0000:00:1e.0: reg 0x10: [mem 0xb2d39000-0xb2d39fff 64bit]
[ 0.340181] pci 0000:00:1f.0: [8086:5ae8] type 00 class 0x060100
[ 0.341700] pci 0000:00:1f.1: [8086:5ad4] type 00 class 0x0c0500
[ 0.341723] pci 0000:00:1f.1: reg 0x10: [mem 0xb2d3b000-0xb2d3b0ff 64bit]
[ 0.341751] pci 0000:00:1f.1: reg 0x20: [io 0x2040-0x205f]
[ 0.343468] pci 0000:01:00.0: [8086:157b] type 00 class 0x020000
[ 0.343496] pci 0000:01:00.0: reg 0x10: [mem 0xb2c00000-0xb2c1ffff]
[ 0.343514] pci 0000:01:00.0: reg 0x18: [io 0x1000-0x101f]
[ 0.343523] pci 0000:01:00.0: reg 0x1c: [mem 0xb2c20000-0xb2c23fff]
[ 0.343611] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
[ 0.343759] pci 0000:01:00.0: System wakeup disabled by ACPI
[ 0.346920] pci 0000:00:13.0: PCI bridge to [bus 01]
[ 0.347030] pci 0000:00:13.0: bridge window [io 0x1000-0x1fff]
[ 0.347032] pci 0000:00:13.0: bridge window [mem 0xb2c00000-0xb2cfffff]
[ 0.347041] pci_bus 0000:00: on NUMA node 0
[ 0.351122] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.351781] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.352476] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.353123] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.353776] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.354593] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.355238] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.355881] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
[ 0.361301] ACPI: Enabled 2 GPEs in block 00 to 7F
[ 0.361830] vgaarb: setting as boot device: PCI:0000:00:02.0
[ 0.361952] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
[ 0.362242] vgaarb: loaded
[ 0.362303] vgaarb: bridge control possible 0000:00:02.0
[ 0.362873] SCSI subsystem initialized
[ 0.363101] libata version 3.00 loaded.
[ 0.363315] ACPI: bus type USB registered
[ 0.363534] usbcore: registered new interface driver usbfs
[ 0.363710] usbcore: registered new interface driver hub
[ 0.363884] usbcore: registered new device driver usb
[ 0.364256] media: Linux media interface: v0.10
[ 0.364406] Linux video capture interface: v2.00
[ 0.364546] pps_core: LinuxPPS API ver. 1 registered
[ 0.364653] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.364867] PTP clock support registered
[ 0.365319] wmi: Mapper loaded
[ 0.365391] PCI: Using ACPI for IRQ routing
[ 0.367541] PCI: pci_cache_line_size set to 64 bytes
[ 0.367624] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff]
[ 0.367628] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
[ 0.367631] e820: reserve RAM buffer [mem 0x0f000000-0x0fffffff]
[ 0.367634] e820: reserve RAM buffer [mem 0x7764b000-0x77ffffff]
[ 0.367636] e820: reserve RAM buffer [mem 0x79e09000-0x7bffffff]
[ 0.367639] e820: reserve RAM buffer [mem 0x7b000000-0x7bffffff]
[ 0.368398] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
[ 0.368568] hpet0: 8 comparators, 64-bit 19.200000 MHz counter
[ 0.369243] clocksource: Switched to clocksource hpet
[ 0.388961] pnp: PnP ACPI init
[ 0.389324] pnp 00:00: disabling [io 0x164e-0x164f] because it overlaps 0000:00:13.0 BAR 7 [io 0x1000-0x1fff]
[ 0.389771] system 00:00: [io 0x0680-0x069f] has been reserved
[ 0.389904] system 00:00: [io 0x0400-0x047f] has been reserved
[ 0.390035] system 00:00: [io 0x0500-0x05fe] has been reserved
[ 0.390168] system 00:00: [io 0x0600-0x061f] has been reserved
[ 0.390318] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 0.390556] pnp 00:01: Plug and Play ACPI device, IDs PNP0303 (active)
[ 0.390776] pnp 00:02: Plug and Play ACPI device, IDs PNP0f13 (active)
[ 0.392101] system 00:03: [mem 0xe0000000-0xefffffff] could not be reserved
[ 0.392257] system 00:03: [mem 0xfea00000-0xfeafffff] has been reserved
[ 0.392411] system 00:03: [mem 0xfed01000-0xfed01fff] has been reserved
[ 0.392558] system 00:03: [mem 0xfed03000-0xfed03fff] has been reserved
[ 0.392705] system 00:03: [mem 0xfed06000-0xfed06fff] has been reserved
[ 0.392851] system 00:03: [mem 0xfed08000-0xfed09fff] has been reserved
[ 0.392998] system 00:03: [mem 0xfed80000-0xfedbffff] has been reserved
[ 0.393146] system 00:03: [mem 0xfed1c000-0xfed1cfff] has been reserved
[ 0.393299] system 00:03: [mem 0xfee00000-0xfeefffff] has been reserved
[ 0.393442] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 0.394839] pnp 00:04: Plug and Play ACPI device, IDs PNP0b00 (active)
[ 0.395393] pnp: PnP ACPI: found 5 devices
[ 0.411640] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
[ 0.411856] pci 0000:00:13.0: PCI bridge to [bus 01]
[ 0.411965] pci 0000:00:13.0: bridge window [io 0x1000-0x1fff]
[ 0.412094] pci 0000:00:13.0: bridge window [mem 0xb2c00000-0xb2cfffff]
[ 0.412312] pci_bus 0000:00: resource 4 [io 0x0070-0x0077]
[ 0.412313] pci_bus 0000:00: resource 5 [io 0x0000-0x006f window]
[ 0.412314] pci_bus 0000:00: resource 6 [io 0x0078-0x0cf7 window]
[ 0.412316] pci_bus 0000:00: resource 7 [io 0x0d00-0xffff window]
[ 0.412317] pci_bus 0000:00: resource 8 [mem 0x000a0000-0x000bffff window]
[ 0.412318] pci_bus 0000:00: resource 9 [mem 0x000c0000-0x000dffff window]
[ 0.412319] pci_bus 0000:00: resource 10 [mem 0x000e0000-0x000fffff window]
[ 0.412320] pci_bus 0000:00: resource 11 [mem 0x7c000001-0x7fffffff window]
[ 0.412322] pci_bus 0000:00: resource 12 [mem 0x80000000-0xcfffffff window]
[ 0.412323] pci_bus 0000:01: resource 0 [io 0x1000-0x1fff]
[ 0.412324] pci_bus 0000:01: resource 1 [mem 0xb2c00000-0xb2cfffff]
[ 0.412490] NET: Registered protocol family 2
[ 0.413082] TCP established hash table entries: 65536 (order: 7, 524288 bytes)
[ 0.413325] TCP bind hash table entries: 65536 (order: 10, 4194304 bytes)
[ 0.415402] TCP: Hash tables configured (established 65536 bind 65536)
[ 0.415627] UDP hash table entries: 4096 (order: 7, 655360 bytes)
[ 0.416011] UDP-Lite hash table entries: 4096 (order: 7, 655360 bytes)
[ 0.416702] NET: Registered protocol family 1
[ 0.416829] pci 0000:00:02.0: Video device with shadowed ROM
[ 0.416934] PCI: CLS 64 bytes, default 64
[ 0.417111] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
[ 0.417256] software IO TLB [mem 0x71218000-0x75218000] (64MB) mapped at [ffff880071218000-ffff880075217fff]
[ 0.417740] microcode: CPU0 sig=0x506c8, pf=0x1, revision=0x90081004
[ 0.417898] microcode: CPU1 sig=0x506c8, pf=0x1, revision=0x90081004
[ 0.418066] microcode: CPU2 sig=0x506c8, pf=0x1, revision=0x90081004
[ 0.418221] microcode: CPU3 sig=0x506c8, pf=0x1, revision=0x90081004
[ 0.418542] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
[ 0.421606] futex hash table entries: 1024 (order: 5, 131072 bytes)
[ 0.423807] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.424043] ntfs: driver 2.1.32 [Flags: R/O].
[ 0.426053] NET: Registered protocol family 38
[ 0.426257] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250)
[ 0.426508] io scheduler noop registered
[ 0.426618] io scheduler cfq registered (default)
[ 0.427388] pcieport 0000:00:13.0: Signaling PME through PCIe PME interrupt
[ 0.427549] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
[ 0.427684] pcie_pme 0000:00:13.0:pcie01: service driver pcie_pme loaded
[ 0.427817] efifb: probing for efifb
[ 0.427922] efifb: framebuffer at 0xa0000000, mapped to 0xffffc90000800000, using 8100k, total 8100k
[ 0.428113] efifb: mode is 1920x1080x32, linelength=7680, pages=1
[ 0.428235] efifb: scrolling: redraw
[ 0.428314] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
[ 0.432525] Console: switching to colour frame buffer device 240x67
[ 0.436032] fb0: EFI VGA frame buffer device
[ 0.436166] intel_idle: does not run on family 6 model 92
[ 0.436545] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input0
[ 0.436738] ACPI: Power Button [PWRF]
[ 0.437036] ACPI Error: No handler for Region [ECF2] (ffff8801f92520c8) [EmbeddedControl] (20150818/evregion-163)
[ 0.437293] ACPI Error: Region EmbeddedControl (ID=3) has no handler (20150818/exfldio-297)
[ 0.437503] ACPI Error: Method parse/execution failed [\_TZ.FN00._ON] (Node ffff8801f933ae50), AE_NOT_EXIST (20150818/psparse-542)
[ 0.437809] acpi PNP0C0B:00: Failed to change power state to D0
[ 0.438576] Monitor-Mwait will be used to enter C-1 state
[ 0.438598] Monitor-Mwait will be used to enter C-2 state
[ 0.438613] Monitor-Mwait will be used to enter C-3 state
[ 0.438631] ACPI: acpi_idle registered with cpuidle
[ 0.440569] ACPI Error: No handler for Region [ECF2] (ffff8801f92520c8) [EmbeddedControl] (20150818/evregion-163)
[ 0.440828] ACPI Error: Region EmbeddedControl (ID=3) has no handler (20150818/exfldio-297)
[ 0.441043] ACPI Error: Method parse/execution failed [\_TZ.TZ01._TMP] (Node ffff8801f933ac98), AE_NOT_EXIST (20150818/psparse-542)
[ 0.442307] ACPI Error: No handler for Region [ECF2] (ffff8801f92520c8) [EmbeddedControl] (20150818/evregion-163)
[ 0.442554] ACPI Error: Region EmbeddedControl (ID=3) has no handler (20150818/exfldio-297)
[ 0.442768] ACPI Error: Method parse/execution failed [\_TZ.TZ01._TMP] (Node ffff8801f933ac98), AE_NOT_EXIST (20150818/psparse-542)
[ 0.443342] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 0.445557] Linux agpgart interface v0.103
[ 0.456452] loop: module loaded
[ 0.457406] ahci 0000:00:12.0: version 3.0
[ 0.461010] ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
[ 0.461201] ahci 0000:00:12.0: flags: 64bit ncq sntf pm clo only pmp pio slum part deso sadm sds apst
[ 0.462673] scsi host0: ahci
[ 0.463233] ata1: SATA max UDMA/133 abar m2048@0xb2d3a000 port 0xb2d3a100 irq 121
[ 0.464108] e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
[ 0.464255] e100: Copyright(c) 1999-2006 Intel Corporation
[ 0.464478] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 0.464644] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 0.464855] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
[ 0.464990] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[ 0.465206] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.3.0-k
[ 0.465380] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 0.480992] pps pps0: new PPS source ptp0
[ 0.481098] igb 0000:01:00.0: added PHC on eth0
[ 0.481204] igb 0000:01:00.0: Intel(R) Gigabit Ethernet Network Connection
[ 0.481375] igb 0000:01:00.0: eth0: (PCIe:2.5Gb/s:Width x1) 98:4f:ee:0c:6e:5a
[ 0.481544] igb 0000:01:00.0: eth0: PBA No: FFFFFF-0FF
[ 0.481663] igb 0000:01:00.0: Using MSI-X interrupts. 4 rx queue(s), 4 tx queue(s)
[ 0.481923] igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k
[ 0.482107] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[ 0.482328] ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 4.0.1-k
[ 0.482521] ixgbe: Copyright (c) 1999-2015 Intel Corporation.
[ 0.482742] ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.12.1-k
[ 0.482961] ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.
[ 0.483178] ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI
[ 0.483346] ixgb: Copyright (c) 1999-2008 Intel Corporation.
[ 0.484527] pegasus: v0.9.3 (2013/04/25), Pegasus/Pegasus II USB Ethernet driver
[ 0.485712] usbcore: registered new interface driver pegasus
[ 0.486876] usbcore: registered new interface driver asix
[ 0.487991] usbcore: registered new interface driver ax88179_178a
[ 0.489124] usbcore: registered new interface driver cdc_ether
[ 0.490251] usbcore: registered new interface driver net1080
[ 0.491368] usbcore: registered new interface driver cdc_subset
[ 0.492480] usbcore: registered new interface driver zaurus
[ 0.493611] usbcore: registered new interface driver cdc_ncm
[ 0.495686] xhci_hcd 0000:00:15.0: xHCI Host Controller
[ 0.497032] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 1
[ 0.498237] xhci_hcd 0000:00:15.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00009810
[ 0.499357] xhci_hcd 0000:00:15.0: cache line size of 64 is not supported
[ 0.500309] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[ 0.501386] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 0.502487] usb usb1: Product: xHCI Host Controller
[ 0.503521] usb usb1: Manufacturer: Linux 4.3.0-rc3mdr+ xhci-hcd
[ 0.504610] usb usb1: SerialNumber: 0000:00:15.0
[ 0.506454] hub 1-0:1.0: USB hub found
[ 0.507509] hub 1-0:1.0: 8 ports detected
[ 0.517254] xhci_hcd 0000:00:15.0: xHCI Host Controller
[ 0.518542] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 2
[ 0.519857] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
[ 0.520912] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 0.522061] usb usb2: Product: xHCI Host Controller
[ 0.523071] usb usb2: Manufacturer: Linux 4.3.0-rc3mdr+ xhci-hcd
[ 0.524118] usb usb2: SerialNumber: 0000:00:15.0
[ 0.525919] hub 2-0:1.0: USB hub found
[ 0.526933] hub 2-0:1.0: 7 ports detected
[ 0.530958] usb: failed to peer usb2-port2 and usb1-port1 by location (usb2-port2:none) (usb1-port1:usb2-port1)
[ 0.532079] usb usb2-port2: failed to peer to usb1-port1 (-16)
[ 0.533112] usb: port power management may be unreliable
[ 0.534878] usb: failed to peer usb2-port3 and usb1-port1 by location (usb2-port3:none) (usb1-port1:usb2-port1)
[ 0.536020] usb usb2-port3: failed to peer to usb1-port1 (-16)
[ 0.537783] usb: failed to peer usb2-port4 and usb1-port1 by location (usb2-port4:none) (usb1-port1:usb2-port1)
[ 0.538868] usb usb2-port4: failed to peer to usb1-port1 (-16)
[ 0.540677] usb: failed to peer usb2-port5 and usb1-port1 by location (usb2-port5:none) (usb1-port1:usb2-port1)
[ 0.541929] usb usb2-port5: failed to peer to usb1-port1 (-16)
[ 0.543707] usb: failed to peer usb2-port6 and usb1-port1 by location (usb2-port6:none) (usb1-port1:usb2-port1)
[ 0.544785] usb usb2-port6: failed to peer to usb1-port1 (-16)
[ 0.546565] usb: failed to peer usb2-port7 and usb1-port1 by location (usb2-port7:none) (usb1-port1:usb2-port1)
[ 0.547673] usb usb2-port7: failed to peer to usb1-port1 (-16)
[ 0.547856] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[ 0.550294] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 0.551323] ehci-pci: EHCI PCI platform driver
[ 0.552350] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[ 0.553381] ohci-pci: OHCI PCI platform driver
[ 0.554388] uhci_hcd: USB Universal Host Controller Interface driver
[ 0.555550] usbcore: registered new interface driver usb-storage
[ 0.556577] usbcore: registered new interface driver ums-alauda
[ 0.557604] usbcore: registered new interface driver ums-datafab
[ 0.558618] usbcore: registered new interface driver ums-freecom
[ 0.559619] usbcore: registered new interface driver ums-isd200
[ 0.560591] ata1.00: ATA-7: ST3160815AS, 4.AAB, max UDMA/133
[ 0.560624] usbcore: registered new interface driver ums-jumpshot
[ 0.560657] usbcore: registered new interface driver ums-karma
[ 0.560690] usbcore: registered new interface driver ums-sddr09
[ 0.560727] usbcore: registered new interface driver ums-sddr55
[ 0.560760] usbcore: registered new interface driver ums-usbat
[ 0.560877] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12
[ 0.567235] ata1.00: 312581808 sectors, multi 0: LBA48 NCQ (depth 31/32)
[ 1.082165] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x4472d4952e5, max_idle_ns: 440795209703 ns
[ 1.090965] ata1.00: configured for UDMA/133
[ 1.092403] scsi 0:0:0:0: Direct-Access ATA ST3160815AS B PQ: 0 ANSI: 5
[ 1.094470] sd 0:0:0:0: [sda] 312581808 512-byte logical blocks: (160 GB/149 GiB)
[ 1.095633] sd 0:0:0:0: [sda] Write Protect is off
[ 1.096544] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 1.096613] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 1.122084] usb 1-2: new low-speed USB device number 2 using xhci_hcd
[ 1.167376] usb 1-2: New USB device found, idVendor=03f0, idProduct=0024
[ 1.168334] usb 1-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 1.169303] usb 1-2: Product: HP Basic USB Keyboard
[ 1.170230] usb 1-2: Manufacturer: CHICONY
[ 1.334799] clocksource: timekeeping watchdog: Marking clocksource 'tsc' as unstable because the skew is too large:
[ 1.335876] clocksource: 'hpet' wd_now: 6368cfd wd_last: 5a3c0fe mask: ffffffff
[ 1.336933] clocksource: 'tsc' cs_now: 1f1f86d44e cs_last: 1efbf96c76 mask: ffffffffffffffff
[ 1.604230] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 1.604320] usb 1-2: ep 0x81 - rounding interval to 64 microframes, ep desc says 80 microframes
[ 1.605062] i8042: No controller found
[ 1.605373] mousedev: PS/2 mouse device common for all mice
[ 1.606412] rtc_cmos 00:04: rtc core: registered rtc_cmos as rtc0
[ 1.606453] rtc_cmos 00:04: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
[ 1.606476] i2c /dev entries driver
[ 1.606679] usbcore: registered new interface driver uvcvideo
[ 1.606679] USB Video Class driver (1.1.1)
[ 1.606728] sdhci: Secure Digital Host Controller Interface driver
[ 1.606728] sdhci: Copyright(c) Pierre Ossman
[ 1.607350] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:5aca] (rev 3)
[ 1.608423] sdhci-pci 0000:00:1b.0: No vmmc regulator found
[ 1.608423] sdhci-pci 0000:00:1b.0: No vqmmc regulator found
[ 1.609241] sda: sda1 sda2 sda3
[ 1.610935] sd 0:0:0:0: [sda] Attached SCSI disk
[ 1.611828] mmc0: SDHCI controller on PCI [0000:00:1b.0] using ADMA 64-bit
[ 1.612460] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:5acc] (rev 3)
[ 1.613506] sdhci-pci 0000:00:1c.0: No vmmc regulator found
[ 1.613507] sdhci-pci 0000:00:1c.0: No vqmmc regulator found
[ 1.616912] mmc1: SDHCI controller on PCI [0000:00:1c.0] using ADMA 64-bit
[ 1.617529] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:5ad0] (rev 3)
[ 1.618570] sdhci-pci 0000:00:1e.0: No vmmc regulator found
[ 1.618570] sdhci-pci 0000:00:1e.0: No vqmmc regulator found
[ 1.621784] mmc2: SDHCI controller on PCI [0000:00:1e.0] using ADMA 64-bit
[ 1.621924] usbcore: registered new interface driver ushc
[ 1.623293] hidraw: raw HID events driver (C) Jiri Kosina
[ 1.626022] input: CHICONY HP Basic USB Keyboard as /devices/pci0000:00/0000:00:15.0/usb1/1-2/1-2:1.0/0003:03F0:0024.0001/input/input1
[ 1.633856] usb 1-5: new low-speed USB device number 3 using xhci_hcd
[ 1.639827] hid-generic 0003:03F0:0024.0001: input,hidraw0: USB HID v1.10 Keyboard [CHICONY HP Basic USB Keyboard] on usb-0000:00:15.0-2/input0
[ 1.641098] usbcore: registered new interface driver usbhid
[ 1.642103] usbhid: USB HID core driver
[ 1.643116] nf_conntrack version 0.5.0 (65536 buckets, 262144 max)
[ 1.646282] ip_tables: (C) 2000-2006 Netfilter Core Team
[ 1.647375] Initializing XFRM netlink socket
[ 1.650259] NET: Registered protocol family 10
[ 1.654760] ip6_tables: (C) 2000-2006 Netfilter Core Team
[ 1.655900] NET: Registered protocol family 17
[ 1.657973] SSE version of gcm_enc/dec engaged.
[ 1.668903] usb 1-5: New USB device found, idVendor=413c, idProduct=3200
[ 1.669945] usb 1-5: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 1.669949] mmc1: MAN_BKOPS_EN bit is not set
[ 1.671939] usb 1-5: Product: Dell USB Mouse
[ 1.672907] usb 1-5: Manufacturer: Dell
[ 1.674351] usb 1-5: ep 0x81 - rounding interval to 64 microframes, ep desc says 80 microframes
[ 1.677593] input: Dell Dell USB Mouse as /devices/pci0000:00/0000:00:15.0/usb1/1-5/1-5:1.0/0003:413C:3200.0002/input/input2
[ 1.679417] mmc1: new HS200 MMC card at address 0001
[ 1.679834] hid-generic 0003:413C:3200.0002: input,hidraw1: USB HID v1.10 Mouse [Dell Dell USB Mouse] on usb-0000:00:15.0-5/input0
[ 1.682507] mmcblk0: mmc1:0001 CWBC3R 58.2 GiB
[ 1.684211] mmcblk0boot0: mmc1:0001 CWBC3R partition 1 4.00 MiB
[ 1.685801] mmcblk0boot1: mmc1:0001 CWBC3R partition 2 4.00 MiB
[ 1.687382] mmcblk0rpmb: mmc1:0001 CWBC3R partition 3 4.00 MiB
[ 1.732167] registered taskstats version 1
[ 1.733319] kmemleak: Kernel memory leak detector initialized
[ 1.733325] kmemleak: Automatic memory scanning thread started
[ 1.738518] Magic number: 7:236:991
[ 1.744160] PM: Hibernation image not present or could not be loaded.
[ 1.749580] EXT2-fs (sda2): warning: mounting ext3 filesystem as ext2
[ 1.750842] VFS: Mounted root (ext2 filesystem) readonly on device 8:2.
[ 1.760207] devtmpfs: mounted
[ 1.761562] Freeing unused kernel memory: 1268K (ffffffff81116000 - ffffffff81253000)
[ 1.762695] Write protecting the kernel read-only data: 12288k
[ 1.769089] Freeing unused kernel memory: 1216K (ffff880000ad0000 - ffff880000c00000)
[ 1.771212] Freeing unused kernel memory: 616K (ffff880000f66000 - ffff880001000000)
[ 1.895690] random: nonblocking pool is initialized
[ 2.129091] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[ 2.157716] Adding 7813116k swap on /dev/sda3. Priority:-1 extents:1 across:7813116k
[ 2.352931] udevd[431]: starting version 182
[ 2.696081] [drm] Initialized drm 1.1.0 20060810
[ 3.058980] Setting dangerous option preliminary_hw_support - tainting kernel
[ 3.060576] [drm:drm_pci_init]
[ 3.061104] [drm:drm_get_pci_dev]
[ 3.061284] [drm:drm_minor_register]
[ 3.062284] [drm:drm_minor_register] new minor registered 64
[ 3.062285] [drm:drm_minor_register]
[ 3.063227] [drm:drm_minor_register] new minor registered 128
[ 3.063228] [drm:drm_minor_register]
[ 3.064153] [drm:drm_minor_register] new minor registered 0
[ 3.064165] [drm:i915_dump_device_info] i915 device info: gen=9, pciid=0x5a84 rev=0x03 flags=need_gfx_hws,is_broxton,is_preliminary,has_fbc,has_hotplug,has_ddi,has_fpga_dbg,
[ 3.064194] [drm:intel_detect_pch] No PCH found.
[ 3.064311] [drm] Memory usable by graphics device = 4096M
[ 3.065005] [drm:i915_gem_gtt_init] GMADR size = 256M
[ 3.065006] [drm:i915_gem_gtt_init] GTT stolen size = 64M
[ 3.065006] [drm:i915_gem_gtt_init] ppgtt mode: 3
[ 3.065012] checking generic (a0000000 7e9000) vs hw (a0000000 10000000)
[ 3.065013] fb: switching to inteldrmfb from EFI VGA
[ 3.065723] Console: switching to colour dummy device 80x25
[ 3.066071] [drm] Replacing VGA console driver
[ 3.069198] [drm:intel_opregion_setup] graphic opregion physical addr: 0x79b88018
[ 3.069221] [drm:intel_opregion_setup] Public ACPI methods supported
[ 3.069222] [drm:intel_opregion_setup] ASLE supported
[ 3.070227] [drm:intel_device_info_runtime_init] slice total: 1
[ 3.070229] [drm:intel_device_info_runtime_init] subslice total: 3
[ 3.070229] [drm:intel_device_info_runtime_init] subslice per slice: 3
[ 3.070229] [drm:intel_device_info_runtime_init] EU total: 18
[ 3.070230] [drm:intel_device_info_runtime_init] EU per subslice: 6
[ 3.070230] [drm:intel_device_info_runtime_init] has slice power gating: n
[ 3.070231] [drm:intel_device_info_runtime_init] has subslice power gating: y
[ 3.070231] [drm:intel_device_info_runtime_init] has EU power gating: y
[ 3.070236] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 3.070377] [drm] Driver supports precise vblank timestamp query.
[ 3.070507] [drm:init_vbt_defaults] Set default to SSC at 100000 kHz
[ 3.070508] [drm:validate_vbt] Using VBT from OpRegion: $VBT BROXTON d
[ 3.070509] [drm:parse_general_features] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
[ 3.070510] [drm:parse_general_definitions] crt_ddc_bus_pin: 2
[ 3.070511] [drm:parse_lfp_panel_data] DRRS supported mode is static
[ 3.070516] [drm:parse_lfp_panel_data] Found panel mode in BIOS VBT tables:
[ 3.070517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[ 3.070518] [drm:parse_lfp_panel_data] VBT initial LVDS value 300
[ 3.070518] [drm:parse_lfp_backlight] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255
[ 3.070519] [drm:parse_sdvo_device_mapping] Unsupported child device size for SDVO mapping.
[ 3.070519] [drm:parse_device_mapping] Expected child device config size for VBT version 201 not known; assuming 38
[ 3.070524] [drm:parse_driver_features] DRRS State Enabled:1
[ 3.070525] [drm:parse_ddi_port] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
[ 3.070526] [drm:parse_ddi_port] VBT HDMI level shift for port A: 0
[ 3.070526] [drm:parse_ddi_port] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
[ 3.070527] [drm:parse_ddi_port] VBT HDMI level shift for port B: 0
[ 3.070527] [drm:parse_ddi_port] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
[ 3.070528] [drm:parse_ddi_port] VBT HDMI level shift for port C: 0
[ 3.070763] [drm:intel_dsm_pci_probe] no _DSM method for intel device
[ 3.070786] [drm:i915_gem_init_stolen] Memory reserved for graphics device: 65536K, usable: 64512K
[ 3.070806] [drm:intel_power_well_enable] enabling always-on
[ 3.070807] [drm:intel_power_well_enable] enabling power well 1
[ 3.070808] [drm:intel_power_well_enable] enabling DC off
[ 3.070809] [drm:gen9_set_dc_state] Setting DC state from 00 to 00
[ 3.070810] [drm:intel_power_well_enable] enabling power well 2
[ 3.070813] [drm:gen9_set_dc_state] Setting DC state from 00 to 00
[ 3.070815] [drm:intel_csr_ucode_init] Loading i915/bxt_dmc_ver1.bin
[ 3.070818] [drm:drm_irq_install] irq=128
[ 3.072514] [drm:intel_print_wm_latency] Gen9 Plane WM0 latency 2 (2.0 usec)
[ 3.072515] [drm:intel_print_wm_latency] Gen9 Plane WM1 latency 4 (4.0 usec)
[ 3.072516] [drm:intel_print_wm_latency] Gen9 Plane WM2 latency 17 (17.0 usec)
[ 3.072516] [drm:intel_print_wm_latency] Gen9 Plane WM3 latency 17 (17.0 usec)
[ 3.072517] [drm:intel_print_wm_latency] Gen9 Plane WM4 latency 17 (17.0 usec)
[ 3.072517] [drm:intel_print_wm_latency] Gen9 Plane WM5 latency 17 (17.0 usec)
[ 3.072518] [drm:intel_print_wm_latency] Gen9 Plane WM6 latency 17 (17.0 usec)
[ 3.072518] [drm:intel_print_wm_latency] Gen9 Plane WM7 latency 17 (17.0 usec)
[ 3.072520] [drm:intel_modeset_init] 3 display pipes available.
[ 3.072718] [drm:intel_update_cdclk] Current CD clock rate: 624000 kHz
[ 3.072719] [drm:intel_update_max_cdclk] Max CD clock rate: 624000 kHz
[ 3.072719] [drm:intel_update_max_cdclk] Max dotclock rate: 624000 kHz
[ 3.072721] [drm:broxton_init_cdclk] Display already initialized
[ 3.072752] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
[ 3.073329] [drm:intel_ddi_init] BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing
[ 3.073342] [drm:intel_dp_init_connector] Adding eDP connector on port A
[ 3.073715] [drm:drm_sysfs_connector_add] adding "eDP-1" to sysfs
[ 3.073715] [drm:drm_sysfs_hotplug_event] generating hotplug event
[ 3.073791] [drm:intel_dp_init_panel_power_sequencer] cur t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0
[ 3.073792] [drm:intel_dp_init_panel_power_sequencer] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
[ 3.073792] [drm:intel_dp_init_panel_power_sequencer] panel power up delay 200, power down delay 50, power cycle delay 500
[ 3.073793] [drm:intel_dp_init_panel_power_sequencer] backlight on delay 1, off delay 200
[ 3.073798] [drm:intel_dp_aux_init] registering DPDDC-A bus for card0-eDP-1
[ 3.074917] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
[ 3.074919] [drm:wait_panel_power_cycle] Wait for panel power cycle
[ 3.078972] [drm] Finished loading i915/bxt_dmc_ver1.bin (v1.6)
[ 3.345248] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000002
[ 3.345253] [drm:wait_panel_status] Wait complete
[ 3.345259] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x0000000a
[ 3.345262] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
[ 3.463881] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.466120] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.470093] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.474265] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.475554] [drm] failed to retrieve link info, disabling eDP
[ 3.476299] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
[ 3.476303] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000002
[ 3.476305] [drm:drm_sysfs_connector_remove] removing "eDP-1" from sysfs
[ 3.476540] [drm:intel_dp_init_connector] Adding DP connector on port B
[ 3.477171] [drm:drm_sysfs_connector_add] adding "DP-1" to sysfs
[ 3.477172] [drm:drm_sysfs_hotplug_event] generating hotplug event
[ 3.477305] [drm:intel_dp_aux_init] registering DPDDC-B bus for card0-DP-1
[ 3.479667] [drm:drm_sysfs_connector_add] adding "HDMI-A-1" to sysfs
[ 3.479668] [drm:drm_sysfs_hotplug_event] generating hotplug event
[ 3.479780] [drm:intel_dp_init_connector] Adding DP connector on port C
[ 3.480055] [drm:drm_sysfs_connector_add] adding "DP-2" to sysfs
[ 3.480056] [drm:drm_sysfs_hotplug_event] generating hotplug event
[ 3.480115] [drm:intel_dp_aux_init] registering DPDDC-C bus for card0-DP-2
[ 3.481477] [drm:drm_sysfs_connector_add] adding "HDMI-A-2" to sysfs
[ 3.481478] [drm:drm_sysfs_hotplug_event] generating hotplug event
[ 3.481560] [drm:intel_modeset_readout_hw_state] [CRTC:21] hw state readout: enabled
[ 3.481561] [drm:intel_modeset_readout_hw_state] [CRTC:26] hw state readout: disabled
[ 3.481563] [drm:intel_modeset_readout_hw_state] [CRTC:31] hw state readout: disabled
[ 3.481564] [drm:intel_modeset_readout_hw_state] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
[ 3.481570] [drm:intel_modeset_readout_hw_state] PORT PLL B hw state readout: crtc_mask 0x00000001, on 1
[ 3.481571] [drm:intel_modeset_readout_hw_state] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
[ 3.481574] [drm:intel_modeset_readout_hw_state] [ENCODER:33:TMDS-33] hw state readout: enabled, pipe A
[ 3.481574] [drm:intel_modeset_readout_hw_state] [ENCODER:35:DP MST-35] hw state readout: disabled, pipe A
[ 3.481575] [drm:intel_modeset_readout_hw_state] [ENCODER:36:DP MST-36] hw state readout: disabled, pipe B
[ 3.481576] [drm:intel_modeset_readout_hw_state] [ENCODER:37:DP MST-37] hw state readout: disabled, pipe C
[ 3.481576] [drm:intel_modeset_readout_hw_state] [ENCODER:42:TMDS-42] hw state readout: disabled, pipe A
[ 3.481577] [drm:intel_modeset_readout_hw_state] [ENCODER:44:DP MST-44] hw state readout: disabled, pipe A
[ 3.481577] [drm:intel_modeset_readout_hw_state] [ENCODER:45:DP MST-45] hw state readout: disabled, pipe B
[ 3.481578] [drm:intel_modeset_readout_hw_state] [ENCODER:46:DP MST-46] hw state readout: disabled, pipe C
[ 3.481579] [drm:intel_modeset_readout_hw_state] [CONNECTOR:34:DP-1] hw state readout: disabled
[ 3.481581] [drm:intel_modeset_readout_hw_state] [CONNECTOR:40:HDMI-A-1] hw state readout: enabled
[ 3.481581] [drm:intel_modeset_readout_hw_state] [CONNECTOR:43:DP-2] hw state readout: disabled
[ 3.481582] [drm:intel_modeset_readout_hw_state] [CONNECTOR:47:HDMI-A-2] hw state readout: disabled
[ 3.481618] [drm:drm_calc_timestamping_constants] crtc 21: hwmode: htotal 2200, vtotal 1125, vdisplay 1080
[ 3.481618] [drm:drm_calc_timestamping_constants] crtc 21: clock 148500 kHz framedur 16666666 linedur 14814
[ 3.481637] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,564)@ 13.5051 -> 12.996696 [e 5 us, 0 rep]
[ 3.481641] [drm:intel_dump_pipe_config] [CRTC:21][setup_hw_state] config ffff88007a840400 for pipe A
[ 3.481641] [drm:intel_dump_pipe_config] cpu_transcoder: A
[ 3.481641] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[ 3.481642] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 3.481643] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 3.481643] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[ 3.481644] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[ 3.481644] [drm:intel_dump_pipe_config] requested mode:
[ 3.481645] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
[ 3.481645] [drm:intel_dump_pipe_config] adjusted mode:
[ 3.481646] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
[ 3.481647] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
[ 3.481647] [drm:intel_dump_pipe_config] port clock: 148500
[ 3.481648] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
[ 3.481648] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0
[ 3.481649] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[ 3.481649] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x07800438, enabled
[ 3.481650] [drm:intel_dump_pipe_config] ips: 0
[ 3.481650] [drm:intel_dump_pipe_config] double wide: 0
[ 3.481651] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6667, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
[ 3.481652] [drm:intel_dump_pipe_config] planes on this crtc
[ 3.481652] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 disabled, scaler_id = -1
[ 3.481653] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = -1
[ 3.481654] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = -1
[ 3.481654] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.2 idx: 3 disabled, scaler_id = -1
[ 3.481655] [drm:intel_dump_pipe_config] [CRTC:26][setup_hw_state] config ffff8801f64b9000 for pipe B
[ 3.481656] [drm:intel_dump_pipe_config] cpu_transcoder: B
[ 3.481656] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
[ 3.481657] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 3.481657] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 3.481658] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[ 3.481658] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[ 3.481659] [drm:intel_dump_pipe_config] requested mode:
[ 3.481659] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[ 3.481660] [drm:intel_dump_pipe_config] adjusted mode:
[ 3.481660] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[ 3.481661] [drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
[ 3.481662] [drm:intel_dump_pipe_config] port clock: 0
[ 3.481662] [drm:intel_dump_pipe_config] pipe src size: 0x0
[ 3.481662] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
[ 3.481663] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[ 3.481663] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[ 3.481664] [drm:intel_dump_pipe_config] ips: 0
[ 3.481664] [drm:intel_dump_pipe_config] double wide: 0
[ 3.481665] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
[ 3.481665] [drm:intel_dump_pipe_config] planes on this crtc
[ 3.481666] [drm:intel_dump_pipe_config] STANDARD PLANE:24 plane: 1.0 idx: 4 disabled, scaler_id = -1
[ 3.481667] [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 1.2 idx: 5 disabled, scaler_id = -1
[ 3.481667] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 1.1 idx: 6 disabled, scaler_id = -1
[ 3.481668] [drm:intel_dump_pipe_config] STANDARD PLANE:28 plane: 1.2 idx: 7 disabled, scaler_id = -1
[ 3.481669] [drm:intel_dump_pipe_config] [CRTC:31][setup_hw_state] config ffff8801f40e4000 for pipe C
[ 3.481669] [drm:intel_dump_pipe_config] cpu_transcoder: C
[ 3.481670] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
[ 3.481670] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 3.481671] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 3.481672] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[ 3.481672] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[ 3.481672] [drm:intel_dump_pipe_config] requested mode:
[ 3.481673] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[ 3.481673] [drm:intel_dump_pipe_config] adjusted mode:
[ 3.481674] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[ 3.481675] [drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
[ 3.481675] [drm:intel_dump_pipe_config] port clock: 0
[ 3.481676] [drm:intel_dump_pipe_config] pipe src size: 0x0
[ 3.481676] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
[ 3.481677] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[ 3.481677] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[ 3.481678] [drm:intel_dump_pipe_config] ips: 0
[ 3.481678] [drm:intel_dump_pipe_config] double wide: 0
[ 3.481679] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
[ 3.481679] [drm:intel_dump_pipe_config] planes on this crtc
[ 3.481680] [drm:intel_dump_pipe_config] STANDARD PLANE:29 plane: 2.0 idx: 8 disabled, scaler_id = -1
[ 3.481681] [drm:intel_dump_pipe_config] CURSOR PLANE:30 plane: 2.3 idx: 9 disabled, scaler_id = -1
[ 3.481681] [drm:intel_dump_pipe_config] STANDARD PLANE:32 plane: 2.1 idx: 10 disabled, scaler_id = -1
[ 3.481699] [drm:intel_power_well_disable] disabling always-on
[ 3.481707] [drm:skylake_get_initial_plane_config] pipe A with fb: size=1920x1080@32, offset=0, pitch 7680, size 0x7e9000
[ 3.481708] [drm:i915_gem_object_create_stolen_for_preallocated] creating preallocated stolen object: stolen_offset=0, gtt_offset=0, size=7e9000
[ 3.481731] [drm:i915_pages_create_for_stolen] offset=0x0, size=8294400
[ 3.481757] [drm:intel_alloc_initial_plane_obj] initial plane fb obj ffff8801f41e8dc0
[ 3.481758] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (1)
[ 3.481763] [drm:i915_gem_setup_global_gtt] reserving preallocated space: 0 + 7e9000
[ 3.481764] [drm:i915_gem_setup_global_gtt] clearing unused GTT space: [7e9000, fffff000]
[ 3.526880] [drm:i915_gem_context_init] LR context support initialized
[ 3.526921] [drm:intel_init_pipe_control] render ring pipe control offset: 0x007ea000
[ 3.526977] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
[ 3.526986] [drm:i915_pages_create_for_stolen] offset=0x7e9000, size=16384
[ 3.527084] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
[ 3.527094] [drm:i915_pages_create_for_stolen] offset=0x7ed000, size=16384
[ 3.527165] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
[ 3.527174] [drm:i915_pages_create_for_stolen] offset=0x7f1000, size=16384
[ 3.527245] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
[ 3.527254] [drm:i915_pages_create_for_stolen] offset=0x7f5000, size=16384
[ 3.527314] [drm:gen8_init_common_ring] Execlists enabled for render ring
[ 3.527320] [drm:gen8_init_common_ring] Execlists enabled for bsd ring
[ 3.527323] [drm:gen8_init_common_ring] Execlists enabled for blitter ring
[ 3.527326] [drm:gen8_init_common_ring] Execlists enabled for video enhancement ring
[ 3.527451] [drm:intel_update_cdclk] Current CD clock rate: 624000 kHz
[ 3.527652] [drm:intel_fbdev_init_bios] found possible fb from plane A
[ 3.527652] [drm:intel_fbdev_init_bios] pipe B not active or no fb, skipping
[ 3.527653] [drm:intel_fbdev_init_bios] pipe C not active or no fb, skipping
[ 3.527653] [drm:intel_fbdev_init_bios] checking plane A for BIOS fb
[ 3.527654] [drm:intel_fbdev_init_bios] pipe A area: 1920x1080, bpp: 32, size: 8294400
[ 3.527655] [drm:intel_fbdev_init_bios] fb big enough for plane A (8294400 >= 8294400)
[ 3.527655] [drm:intel_fbdev_init_bios] pipe B not active, skipping
[ 3.527656] [drm:intel_fbdev_init_bios] pipe C not active, skipping
[ 3.527656] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (2)
[ 3.527657] [drm:intel_fbdev_init_bios] using BIOS fb for initial console
[ 3.527708] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:DP-1]
[ 3.527709] [drm:intel_dp_detect] [CONNECTOR:34:DP-1]
[ 3.529888] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.531542] [drm:intel_didl_outputs] More than 15 outputs detected via ACPI
[ 3.532044] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.535378] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.539428] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.541201] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:DP-1] status updated from 3 to 2
[ 3.541203] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:DP-1] disconnected
[ 3.541204] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1]
[ 3.541205] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
[ 3.556518] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no)
[ 3.562893] acpi device:4c: registered as cooling_device1
[ 3.563678] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input3
[ 3.564606] [drm] Initialized i915 1.6.0 20151023 for 0000:00:02.0 on minor 0
[ 3.589047] [drm] GMBUS [i915 gmbus dpb] timed out, falling back to bit banging on pin 1
[ 3.645002] [drm:drm_detect_monitor_audio] Monitor has basic audio support
[ 3.645003] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] status updated from 3 to 1
[ 3.645124] [drm:drm_edid_to_eld] ELD monitor VE248
[ 3.645125] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
[ 3.645126] [drm:drm_edid_to_eld] ELD size 28, SAD count 1
[ 3.645138] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] probed modes :
[ 3.645139] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[ 3.645140] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
[ 3.645140] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
[ 3.645141] [drm:drm_mode_debug_printmodeline] Modeline 56:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
[ 3.645142] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
[ 3.645143] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
[ 3.645143] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
[ 3.645144] [drm:drm_mode_debug_printmodeline] Modeline 61:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
[ 3.645145] [drm:drm_mode_debug_printmodeline] Modeline 62:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
[ 3.645146] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
[ 3.645146] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
[ 3.645147] [drm:drm_mode_debug_printmodeline] Modeline 60:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
[ 3.645148] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
[ 3.645149] [drm:drm_mode_debug_printmodeline] Modeline 53:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
[ 3.645149] [drm:drm_mode_debug_printmodeline] Modeline 57:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
[ 3.645150] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
[ 3.645151] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
[ 3.645152] [drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
[ 3.645153] [drm:drm_mode_debug_printmodeline] Modeline 71:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[ 3.645154] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
[ 3.645154] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
[ 3.645155] [drm:drm_mode_debug_printmodeline] Modeline 74:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
[ 3.645156] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
[ 3.645157] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
[ 3.645157] [drm:drm_mode_debug_printmodeline] Modeline 63:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
[ 3.645158] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
[ 3.645159] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
[ 3.645160] [drm:drm_mode_debug_printmodeline] Modeline 90:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
[ 3.645161] [drm:drm_mode_debug_printmodeline] Modeline 55:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
[ 3.645161] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
[ 3.645162] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
[ 3.645163] [drm:drm_mode_debug_printmodeline] Modeline 67:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
[ 3.645164] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
[ 3.645164] [drm:drm_mode_debug_printmodeline] Modeline 82:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
[ 3.645165] [drm:drm_mode_debug_printmodeline] Modeline 69:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[ 3.645166] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:DP-2]
[ 3.645167] [drm:intel_dp_detect] [CONNECTOR:43:DP-2]
[ 3.645169] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:DP-2] status updated from 3 to 2
[ 3.645169] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:DP-2] disconnected
[ 3.645170] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2]
[ 3.645171] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-2]
[ 3.665207] [drm:intel_hdmi_detect] Live status not up!
[ 3.665208] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2] status updated from 3 to 2
[ 3.665209] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2] disconnected
[ 3.665211] [drm:drm_setup_crtcs]
[ 3.665218] [drm:drm_enable_connectors] connector 34 enabled? no
[ 3.665218] [drm:drm_enable_connectors] connector 40 enabled? yes
[ 3.665219] [drm:drm_enable_connectors] connector 43 enabled? no
[ 3.665219] [drm:drm_enable_connectors] connector 47 enabled? no
[ 3.665221] [drm:drm_sysfs_hotplug_event] generating hotplug event
[ 3.665222] [drm:intel_fb_initial_config] connector DP-1 not enabled, skipping
[ 3.665223] [drm:intel_fb_initial_config] looking for cmdline mode on connector HDMI-A-1
[ 3.665224] [drm:intel_fb_initial_config] looking for preferred mode on connector HDMI-A-1 0
[ 3.665225] [drm:intel_fb_initial_config] connector HDMI-A-1 on pipe A [CRTC:21]: 1920x1080
[ 3.665226] [drm:intel_fb_initial_config] connector DP-2 not enabled, skipping
[ 3.665226] [drm:intel_fb_initial_config] connector HDMI-A-2 not enabled, skipping
[ 3.665228] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 21 (0,0)
[ 3.665231] [drm:intelfb_create] re-using BIOS fb
[ 3.665249] [drm:drm_fb_helper_hotplug_event]
[ 3.665251] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:DP-1]
[ 3.665251] [drm:intel_dp_detect] [CONNECTOR:34:DP-1]
[ 3.665252] ------------[ cut here ]------------
[ 3.665258] [drm:intelfb_create] allocated 1920x1080 fb: 0x00000000, bo ffff8801f41e8dc0
[ 3.665363] WARNING: CPU: 1 PID: 68 at /home/mattrope/work/kernel/gms/drivers/gpu/drm/i915/intel_display.c:5228 intel_display_port_aux_power_domain+0xb9/0xd0 [i915]()
[ 3.665663] WARN_ON_ONCE(1)
[ 3.665665] Modules linked in: i915 drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm video
[ 3.665666] CPU: 1 PID: 68 Comm: kworker/1:2 Tainted: G U 4.3.0-rc3mdr+ #315
[ 3.665666] Hardware name: Intel Corp. BROXTON P A0 PLATFORM/NOTEBOOK, BIOS BXTI_IFWI_X64_D_2015_10_29_2010 10/29/2015
[ 3.665669] Workqueue: events output_poll_execute [drm_kms_helper]
[ 3.665669] fbcon: inteldrmfb (fb0) is primary device
[ 3.665671] ffffffffa018af30 ffff88007a9ffb58 ffffffff806d5209 ffff88007a9ffba0
[ 3.665671] ffff88007a9ffb90 ffffffff8046c141 0000000000000015 ffff8801f40e1800
[ 3.665672] ffff8801f6677000 ffff8801f6677000 ffff8801f6e080d8 ffff88007a9ffbf0
[ 3.665672] Call Trace:
[ 3.665674] [<ffffffff806d5209>] dump_stack+0x4b/0x72
[ 3.665675] [<ffffffff8046c141>] warn_slowpath_common+0x81/0xc0
[ 3.665675] [<ffffffff8046c1c7>] warn_slowpath_fmt+0x47/0x50
[ 3.665684] [<ffffffffa011d769>] intel_display_port_aux_power_domain+0xb9/0xd0 [i915]
[ 3.665694] [<ffffffffa0145988>] intel_dp_detect+0x88/0x4a0 [i915]
[ 3.665696] [<ffffffffa0078bb1>] drm_helper_probe_single_connector_modes_merge_bits+0x2a1/0x4d0 [drm_kms_helper]
[ 3.665697] [<ffffffffa0078dee>] drm_helper_probe_single_connector_modes+0xe/0x10 [drm_kms_helper]
[ 3.665699] [<ffffffffa0082f48>] drm_fb_helper_probe_connector_modes.isra.3+0x48/0x70 [drm_kms_helper]
[ 3.665700] [<ffffffffa00842ce>] drm_fb_helper_hotplug_event+0x6e/0xf0 [drm_kms_helper]
[ 3.665709] [<ffffffffa0132c09>] intel_fbdev_output_poll_changed+0x19/0x20 [i915]
[ 3.665711] [<ffffffffa0078612>] drm_kms_helper_hotplug_event+0x22/0x30 [drm_kms_helper]
[ 3.665712] [<ffffffffa00787f6>] output_poll_execute+0x196/0x1e0 [drm_kms_helper]
[ 3.665713] [<ffffffff80483672>] process_one_work+0x1c2/0x510
[ 3.665713] [<ffffffff804835e3>] ? process_one_work+0x133/0x510
[ 3.665714] [<ffffffff80483a24>] worker_thread+0x64/0x470
[ 3.665714] [<ffffffff804839c0>] ? process_one_work+0x510/0x510
[ 3.665715] [<ffffffff804839c0>] ? process_one_work+0x510/0x510
[ 3.665715] [<ffffffff804893b5>] kthread+0x105/0x120
[ 3.665716] [<ffffffff804892b0>] ? kthread_create_on_node+0x1f0/0x1f0
[ 3.665717] [<ffffffff80acb8df>] ret_from_fork+0x3f/0x70
[ 3.665717] [<ffffffff804892b0>] ? kthread_create_on_node+0x1f0/0x1f0
[ 3.665718] ---[ end trace 0e0f25523c9bb5b2 ]---
[ 3.667876] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.670064] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.673810] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.677616] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.679057] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:DP-1] disconnected
[ 3.679061] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1]
[ 3.679065] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
[ 3.754045] [drm:drm_detect_monitor_audio] Monitor has basic audio support
[ 3.754063] [drm:drm_property_unreference_blob] ffff8801f69af200: blob ID: 50 (1)
[ 3.754673] [drm:drm_edid_to_eld] ELD monitor VE248
[ 3.754676] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
[ 3.754678] [drm:drm_edid_to_eld] ELD size 28, SAD count 1
[ 3.754793] [drm:drm_mode_debug_printmodeline] Modeline 61:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
[ 3.754794] [drm:drm_mode_prune_invalid] Not using 1600x1200 mode: VIRTUAL_Y
[ 3.754803] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] probed modes :
[ 3.754807] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[ 3.754810] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
[ 3.754813] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
[ 3.754815] [drm:drm_mode_debug_printmodeline] Modeline 56:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
[ 3.754818] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
[ 3.754821] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
[ 3.754824] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
[ 3.754827] [drm:drm_mode_debug_printmodeline] Modeline 62:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
[ 3.754830] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
[ 3.754833] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
[ 3.754836] [drm:drm_mode_debug_printmodeline] Modeline 60:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
[ 3.754839] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
[ 3.754841] [drm:drm_mode_debug_printmodeline] Modeline 53:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
[ 3.754844] [drm:drm_mode_debug_printmodeline] Modeline 57:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
[ 3.754847] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
[ 3.754850] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
[ 3.754853] [drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
[ 3.754856] [drm:drm_mode_debug_printmodeline] Modeline 71:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[ 3.754859] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
[ 3.754862] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
[ 3.754864] [drm:drm_mode_debug_printmodeline] Modeline 74:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
[ 3.754867] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
[ 3.754870] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
[ 3.754890] [drm:drm_mode_debug_printmodeline] Modeline 63:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
[ 3.754893] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
[ 3.754895] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
[ 3.754898] [drm:drm_mode_debug_printmodeline] Modeline 90:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
[ 3.754901] [drm:drm_mode_debug_printmodeline] Modeline 55:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
[ 3.754904] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
[ 3.754907] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
[ 3.754910] [drm:drm_mode_debug_printmodeline] Modeline 67:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
[ 3.754913] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
[ 3.754915] [drm:drm_mode_debug_printmodeline] Modeline 82:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
[ 3.754918] [drm:drm_mode_debug_printmodeline] Modeline 69:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[ 3.754920] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:DP-2]
[ 3.754922] [drm:intel_dp_detect] [CONNECTOR:43:DP-2]
[ 3.754926] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:DP-2] disconnected
[ 3.754928] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2]
[ 3.754929] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-2]
[ 3.774971] [drm:intel_hdmi_detect] Live status not up!
[ 3.774971] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2] disconnected
[ 3.775083] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (3)
[ 3.775097] [drm:drm_property_reference_blob] ffff8801f6e4ec40: blob ID: 48 (1)
[ 3.775213] [drm:drm_property_unreference_blob] ffff8801f6e4ec40: blob ID: 48 (2)
[ 3.775230] [drm:drm_framebuffer_unreference] ffff8801f6e4ed00: FB ID: 49 (4)
[ 3.775231] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (3)
[ 3.775331] [drm:connected_sink_compute_bpp] [CONNECTOR:40:HDMI-A-1] checking for sink bpp constrains
[ 3.775333] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
[ 3.775336] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
[ 3.775337] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
[ 3.775338] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
[ 3.775341] [drm:intel_pipe_config_compare] mismatch in has_infoframe (expected 0, found 1)
[ 3.775342] [drm:intel_pipe_config_compare] mismatch in has_audio (expected 0, found 1)
[ 3.775346] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff88007ab0c800 for pipe A
[ 3.775347] [drm:intel_dump_pipe_config] cpu_transcoder: A
[ 3.775348] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[ 3.775350] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 3.775351] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 3.775353] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[ 3.775354] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
[ 3.775355] [drm:intel_dump_pipe_config] requested mode:
[ 3.775357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[ 3.775358] [drm:intel_dump_pipe_config] adjusted mode:
[ 3.775360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
[ 3.775362] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
[ 3.775363] [drm:intel_dump_pipe_config] port clock: 148500
[ 3.775364] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
[ 3.775366] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0
[ 3.775367] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[ 3.775368] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[ 3.775369] [drm:intel_dump_pipe_config] ips: 0
[ 3.775370] [drm:intel_dump_pipe_config] double wide: 0
[ 3.775373] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6667, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
[ 3.775374] [drm:intel_dump_pipe_config] planes on this crtc
[ 3.775377] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
[ 3.775379] [drm:intel_dump_pipe_config] FB:49, fb = 1920x1080 format = 0x34325258
[ 3.775379] [drm:intel_dump_pipe_config] scaler:-1 src (0, 0) 0x0 dst (0, 0) 0x0
[ 3.775381] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = -1
[ 3.775382] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = -1
[ 3.775384] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.2 idx: 3 disabled, scaler_id = -1
[ 3.775389] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:18] scaler_user index 0.0
[ 3.775397] [drm:intel_get_shared_dpll] CRTC:21 using pre-allocated PORT PLL B
[ 3.775398] [drm:intel_get_shared_dpll] using PORT PLL B for pipe A
[ 3.775399] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:21] scaler_user index 0.31
[ 3.775401] [drm:skl_update_scaler] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
[ 3.775538] [drm:set_no_fbc_reason] Disabling FBC: disabled per chip default
[ 3.775549] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,641)@ 14.175543 -> 14.166047 [e 7 us, 0 rep]
[ 3.775552] [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=1, diff=70, hw=3352 hw_last=3282
[ 3.775577] [drm:intel_disable_pipe] disabling pipe A
[ 3.777330] [drm:intel_disable_shared_dpll] disable PORT PLL B (active 1, on? 1) for crtc 21
[ 3.777350] [drm:intel_disable_shared_dpll] disabling PORT PLL B
[ 3.777355] [drm:drm_calc_timestamping_constants] crtc 21: hwmode: htotal 2200, vtotal 1125, vdisplay 1080
[ 3.777357] [drm:drm_calc_timestamping_constants] crtc 21: clock 148500 kHz framedur 16666666 linedur 14814
[ 3.779240] [drm:intel_update_cdclk] Current CD clock rate: 288000 kHz
[ 3.779243] [drm:intel_power_well_enable] enabling always-on
[ 3.779245] [drm:intel_enable_shared_dpll] enable PORT PLL B (active 0, on? 0) for crtc 21
[ 3.779246] [drm:intel_enable_shared_dpll] enabling PORT PLL B
[ 3.779315] [drm:skylake_pfit_enable] for crtc_state = ffff88007ab0c800
[ 3.779434] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
[ 3.779438] [drm:intel_enable_pipe] enabling pipe A
[ 3.779448] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x7 p(0,-45)@ 14.191071 -> 14.191738 [e 6 us, 0 rep]
[ 3.779451] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:40:HDMI-A-1], [ENCODER:33:TMDS-33]
[ 3.779452] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 28 bytes ELD
[ 3.779480] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 148500 (0x00090000)
[ 3.779486] [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[ 3.779492] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x7 p(0,-35)@ 14.191249 -> 14.191767 [e 6 us, 0 rep]
[ 3.779494] [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=72, diff=0, hw=3353 hw_last=3353
[ 3.779496] [drm:vblank_disable_fn] disabling vblank on crtc 0
[ 3.779502] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x7 p(0,-32)@ 14.191291 -> 14.191765 [e 6 us, 0 rep]
[ 3.779504] [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=72, diff=0, hw=3353 hw_last=3353
[ 3.779514] [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[ 3.779520] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x7 p(0,-28)@ 14.191360 -> 14.191775 [e 5 us, 0 rep]
[ 3.779521] [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=72, diff=0, hw=3353 hw_last=3353
[ 3.783684] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x7 p(0,-37)@ 14.207930 -> 14.208478 [e 7 us, 0 rep]
[ 3.783688] [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=72, diff=1, hw=3354 hw_last=3353
[ 3.783703] [drm:vblank_disable_fn] disabling vblank on crtc 0
[ 3.783712] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x7 p(0,-29)@ 14.208052 -> 14.208482 [e 6 us, 0 rep]
[ 3.783715] [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=73, diff=0, hw=3354 hw_last=3354
[ 3.783759] [drm:intel_power_well_disable] disabling always-on
[ 3.783772] [drm:intel_connector_check_state] [CONNECTOR:40:HDMI-A-1]
[ 3.783777] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
[ 3.783778] [drm:check_encoder_state] [ENCODER:35:DP MST-35]
[ 3.783780] [drm:check_encoder_state] [ENCODER:36:DP MST-36]
[ 3.783781] [drm:check_encoder_state] [ENCODER:37:DP MST-37]
[ 3.783782] [drm:check_encoder_state] [ENCODER:42:TMDS-42]
[ 3.783785] [drm:check_encoder_state] [ENCODER:44:DP MST-44]
[ 3.783786] [drm:check_encoder_state] [ENCODER:45:DP MST-45]
[ 3.783787] [drm:check_encoder_state] [ENCODER:46:DP MST-46]
[ 3.783789] [drm:drm_property_unreference_blob] ffff8801f6e4ec40: blob ID: 48 (1)
[ 3.783796] [drm:check_crtc_state] [CRTC:21]
[ 3.783831] [drm:check_shared_dpll_state] PORT PLL A
[ 3.783833] [drm:check_shared_dpll_state] PORT PLL B
[ 3.783853] [drm:check_shared_dpll_state] PORT PLL C
[ 3.783868] [drm:drm_framebuffer_unreference] ffff8801f6e4ed00: FB ID: 49 (4)
[ 3.783902] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (3)
[ 3.783904] [drm:drm_framebuffer_unreference] ffff8801f6e4ed00: FB ID: 49 (4)
[ 3.783920] Console: switching to colour frame buffer device 240x67
[ 3.783936] [drm:drm_setup_crtcs]
[ 3.783970] [drm:drm_enable_connectors] connector 34 enabled? no
[ 3.783972] [drm:drm_enable_connectors] connector 40 enabled? yes
[ 3.783973] [drm:drm_enable_connectors] connector 43 enabled? no
[ 3.783974] [drm:drm_enable_connectors] connector 47 enabled? no
[ 3.783986] [drm:intel_fb_initial_config] connector DP-1 not enabled, skipping
[ 3.783987] [drm:intel_fb_initial_config] looking for cmdline mode on connector HDMI-A-1
[ 3.783989] [drm:intel_fb_initial_config] looking for preferred mode on connector HDMI-A-1 0
[ 3.783991] [drm:intel_fb_initial_config] connector HDMI-A-1 on pipe A [CRTC:21]: 1920x1080
[ 3.783992] [drm:intel_fb_initial_config] connector DP-2 not enabled, skipping
[ 3.783993] [drm:intel_fb_initial_config] connector HDMI-A-2 not enabled, skipping
[ 3.783997] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 21 (0,0)
[ 3.784127] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (3)
[ 3.784139] [drm:drm_property_reference_blob] ffff88007aadc640: blob ID: 50 (1)
[ 3.784233] [drm:drm_property_unreference_blob] ffff88007aadc640: blob ID: 50 (2)
[ 3.784246] [drm:drm_framebuffer_unreference] ffff8801f6e4ed00: FB ID: 49 (4)
[ 3.784248] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (3)
[ 3.784289] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:18] scaler_user index 0.0
[ 3.784306] [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[ 3.784314] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,133)@ 14.210448 -> 14.208478 [e 6 us, 0 rep]
[ 3.784317] [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=73, diff=0, hw=3354 hw_last=3354
[ 3.784320] [drm:vblank_disable_fn] disabling vblank on crtc 0
[ 3.784329] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,137)@ 14.210509 -> 14.208479 [e 6 us, 0 rep]
[ 3.784331] [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=73, diff=0, hw=3354 hw_last=3354
[ 3.784360] [drm:drm_property_unreference_blob] ffff88007aadc640: blob ID: 50 (1)
[ 3.784372] [drm:drm_framebuffer_unreference] ffff8801f6e4ed00: FB ID: 49 (4)
[ 3.784404] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (3)
[ 3.784405] [drm:drm_framebuffer_unreference] ffff8801f6e4ed00: FB ID: 49 (4)
[ 3.784418] [drm:drm_sysfs_hotplug_event] generating hotplug event
[ 3.784517] [drm:drm_property_reference_blob] ffff8801f6e4e940: blob ID: 61 (1)
[ 3.784531] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (3)
[ 3.784533] [drm:drm_property_unreference_blob] ffff8801f6e4e940: blob ID: 61 (2)
[ 3.784549] [drm:drm_framebuffer_unreference] ffff8801f6e4ed00: FB ID: 49 (4)
[ 3.784550] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (3)
[ 3.784657] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:18] scaler_user index 0.0
[ 3.784672] [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[ 3.784680] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,231)@ 14.211906 -> 14.208483 [e 6 us, 0 rep]
[ 3.784683] [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=73, diff=0, hw=3354 hw_last=3354
[ 3.784686] [drm:vblank_disable_fn] disabling vblank on crtc 0
[ 3.784694] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,235)@ 14.211964 -> 14.208482 [e 6 us, 0 rep]
[ 3.784696] [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=73, diff=0, hw=3354 hw_last=3354
[ 3.784722] [drm:drm_property_unreference_blob] ffff8801f6e4e940: blob ID: 61 (1)
[ 3.784733] [drm:drm_framebuffer_unreference] ffff8801f6e4ed00: FB ID: 49 (4)
[ 3.784765] [drm:drm_fb_helper_hotplug_event]
[ 3.784767] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:DP-1]
[ 3.784781] [drm:intel_dp_detect] [CONNECTOR:34:DP-1]
[ 3.786981] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.789184] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.792504] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.796605] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x7d40001f
[ 3.798169] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:DP-1] disconnected
[ 3.798170] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1]
[ 3.798172] [drm:intel_hdmi_detect] [CONNECTOR:40:HDMI-A-1]
[ 3.873890] [drm:drm_detect_monitor_audio] Monitor has basic audio support
[ 3.873906] [drm:drm_property_unreference_blob] ffff8801f6400600: blob ID: 78 (1)
[ 3.874505] [drm:drm_edid_to_eld] ELD monitor VE248
[ 3.874507] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
[ 3.874509] [drm:drm_edid_to_eld] ELD size 28, SAD count 1
[ 3.874619] [drm:drm_mode_debug_printmodeline] Modeline 96:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
[ 3.874620] [drm:drm_mode_prune_invalid] Not using 1600x1200 mode: VIRTUAL_Y
[ 3.874628] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:HDMI-A-1] probed modes :
[ 3.874631] [drm:drm_mode_debug_printmodeline] Modeline 51:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[ 3.874634] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
[ 3.874637] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
[ 3.874640] [drm:drm_mode_debug_printmodeline] Modeline 56:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
[ 3.874643] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
[ 3.874646] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
[ 3.874649] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
[ 3.874652] [drm:drm_mode_debug_printmodeline] Modeline 62:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
[ 3.874655] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
[ 3.874658] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
[ 3.874660] [drm:drm_mode_debug_printmodeline] Modeline 60:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
[ 3.874664] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
[ 3.874667] [drm:drm_mode_debug_printmodeline] Modeline 53:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
[ 3.874669] [drm:drm_mode_debug_printmodeline] Modeline 57:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
[ 3.874672] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
[ 3.874675] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
[ 3.874678] [drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
[ 3.874681] [drm:drm_mode_debug_printmodeline] Modeline 71:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[ 3.874684] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
[ 3.874687] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
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[ 3.874695] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
[ 3.874698] [drm:drm_mode_debug_printmodeline] Modeline 63:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
[ 3.874701] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
[ 3.874704] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
[ 3.874707] [drm:drm_mode_debug_printmodeline] Modeline 90:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
[ 3.874710] [drm:drm_mode_debug_printmodeline] Modeline 55:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
[ 3.874712] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
[ 3.874715] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
[ 3.874718] [drm:drm_mode_debug_printmodeline] Modeline 67:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
[ 3.874721] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
[ 3.874724] [drm:drm_mode_debug_printmodeline] Modeline 82:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
[ 3.874726] [drm:drm_mode_debug_printmodeline] Modeline 69:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[ 3.874728] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:DP-2]
[ 3.874730] [drm:intel_dp_detect] [CONNECTOR:43:DP-2]
[ 3.874734] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:DP-2] disconnected
[ 3.874735] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2]
[ 3.874736] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-2]
[ 3.894779] [drm:intel_hdmi_detect] Live status not up!
[ 3.894780] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2] disconnected
[ 3.894799] [drm:drm_setup_crtcs]
[ 3.894830] [drm:drm_enable_connectors] connector 34 enabled? no
[ 3.894831] [drm:drm_enable_connectors] connector 40 enabled? yes
[ 3.894833] [drm:drm_enable_connectors] connector 43 enabled? no
[ 3.894834] [drm:drm_enable_connectors] connector 47 enabled? no
[ 3.894845] [drm:intel_fb_initial_config] connector DP-1 not enabled, skipping
[ 3.894847] [drm:intel_fb_initial_config] looking for cmdline mode on connector HDMI-A-1
[ 3.894848] [drm:intel_fb_initial_config] looking for preferred mode on connector HDMI-A-1 0
[ 3.894850] [drm:intel_fb_initial_config] connector HDMI-A-1 on pipe A [CRTC:21]: 1920x1080
[ 3.894851] [drm:intel_fb_initial_config] connector DP-2 not enabled, skipping
[ 3.894852] [drm:intel_fb_initial_config] connector HDMI-A-2 not enabled, skipping
[ 3.894856] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 21 (0,0)
[ 3.895111] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (3)
[ 3.895122] [drm:drm_property_reference_blob] ffff8801f5409b80: blob ID: 50 (1)
[ 3.895213] [drm:drm_property_unreference_blob] ffff8801f5409b80: blob ID: 50 (2)
[ 3.895226] [drm:drm_framebuffer_unreference] ffff8801f6e4ed00: FB ID: 49 (4)
[ 3.895228] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (3)
[ 3.895267] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:18] scaler_user index 0.0
[ 3.895280] [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
[ 3.895288] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,646)@ 14.652399 -> 14.642829 [e 6 us, 0 rep]
[ 3.895291] [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=73, diff=26, hw=3380 hw_last=3354
[ 3.895294] [drm:vblank_disable_fn] disabling vblank on crtc 0
[ 3.895302] [drm:drm_calc_vbltimestamp_from_scanoutpos] crtc 0 : v 0x5 p(0,650)@ 14.652458 -> 14.642829 [e 6 us, 0 rep]
[ 3.895305] [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=99, diff=0, hw=3380 hw_last=3380
[ 3.895331] [drm:drm_property_unreference_blob] ffff8801f5409b80: blob ID: 50 (1)
[ 3.895343] [drm:drm_framebuffer_unreference] ffff8801f6e4ed00: FB ID: 49 (4)
[ 3.895372] [drm:drm_framebuffer_reference] ffff8801f6e4ed00: FB ID: 49 (3)
[ 3.895373] [drm:drm_framebuffer_unreference] ffff8801f6e4ed00: FB ID: 49 (4)
[ 3.904523] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
[ 3.909734] [drm] RC6 on
[ 3.927792] EXT2-fs (sda2): warning: mounting unchecked fs, running e2fsck is recommended
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-23 22:58 ` Matt Roper
@ 2015-11-23 23:09 ` Imre Deak
2015-11-24 12:24 ` Daniel Vetter
0 siblings, 1 reply; 47+ messages in thread
From: Imre Deak @ 2015-11-23 23:09 UTC (permalink / raw)
To: Matt Roper, Patrik Jakobsson; +Cc: intel-gfx
On Mon, 2015-11-23 at 14:58 -0800, Matt Roper wrote:
> On Mon, Nov 16, 2015 at 04:20:01PM +0100, Patrik Jakobsson wrote:
> > Handle DC off as a power well where enabling the power well will
> > prevent
> > the DMC to enter selected DC states (required around modesets and
> > Aux
> > A). Disabling the power well will allow DC states again. For now
> > the
> > highest DC state is DC6 for Skylake and DC5 for Broxton but will be
> > configurable for Skylake in a later patch.
> >
> > v2: Check both DC5 and DC6 bits in power well enabled function
> > (Ville)
> > v3:
> > - Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
> > - Add PW2 dependency to DC_OFF (Imre)
> > v4: Put DC_OFF before PW2 in BXT power well array
> >
> > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> I've been seeing a BXT regression on recent di-nightly where DPMS off
> causes the entire platform to power down[1] instead of just the
> display;
> my bisect lands on this commit as the culprit. Any idea what the
> cause
> could be? I can reproduce by either letting the system sit idle long
> enough at an fb console, or by doing an "xset dpms force off" in X.
> Unfortunately I don't have a functioning serial console on this
> platform, so I can't get any messages that may show up around the
> DPMS
> operation. I've attached my boot-time dmesg output in case that
> helps.
>
> Subsequent commits seem to depend on the changes here, so I haven't
> reverted this commit directly on di-nightly, but I confirmed that if
> I
> checkout this commit directly I see DPMS problems, whereas its HEAD~1
> works as expected.
The power well support on BXT is not stable atm, we need to apply at
least a similar set of fixes as we did for SKL. So for now I would
suggest disabling it, by booting with i915.disable_power_well=0 until
things are fixed. This should've been made the default option earlier,
I forgot about this. I will follow up with the patch to that extent.
Thanks for the report,
Imre
> Matt
>
>
> [1] My BIOS and/or hardware is a bit flaky so even when operating
> "normally" most attempts to reboot/poweroff/S3 suspend all result in
> the
> platform going into some "mostly off" state with an error LED lit and
> require a full power cycle to resurrect. That's the same state I
> wind
> up in after DPMS off when this patch is present.
>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 6 --
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_display.c | 6 ++
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 110
> > +++++++++++++++++++++++---------
> > 4 files changed, 88 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 5a63f9a..0c7f435 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1072,9 +1072,6 @@ static int i915_pm_resume(struct device *dev)
> >
> > static int skl_suspend_complete(struct drm_i915_private *dev_priv)
> > {
> > - if (dev_priv->csr.dmc_payload)
> > - skl_enable_dc6(dev_priv);
> > -
> > return 0;
> > }
> >
> > @@ -1119,9 +1116,6 @@ static int bxt_resume_prepare(struct
> > drm_i915_private *dev_priv)
> >
> > static int skl_resume_prepare(struct drm_i915_private *dev_priv)
> > {
> > - if (dev_priv->csr.dmc_payload)
> > - skl_disable_dc6(dev_priv);
> > -
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 0f3849f..b6a3525 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -638,6 +638,7 @@ enum skl_disp_power_wells {
> >
> > /* Not actual bit groups. Used as IDs for
> > lookup_power_well() */
> > SKL_DISP_PW_ALWAYS_ON,
> > + SKL_DISP_PW_DC_OFF,
> > };
> >
> > #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 978b1b9..21385a0 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -13323,6 +13323,9 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> > to_intel_crtc_state(crtc->state)-
> > >update_pipe;
> > unsigned long put_domains = 0;
> >
> > + if (modeset)
> > + intel_display_power_get(dev_priv,
> > POWER_DOMAIN_MODESET);
> > +
> > if (modeset && crtc->state->active) {
> > update_scanline_offset(to_intel_crtc(crtc)
> > );
> > dev_priv->display.crtc_enable(crtc);
> > @@ -13346,6 +13349,9 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> > modeset_put_power_domains(dev_priv,
> > put_domains);
> >
> > intel_post_plane_update(intel_crtc);
> > +
> > + if (modeset)
> > + intel_display_power_put(dev_priv,
> > POWER_DOMAIN_MODESET);
> > }
> >
> > /* FIXME: add subpixel order */
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index edf753e..0ff1646 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -49,9 +49,6 @@
> > * present for a given platform.
> > */
> >
> > -#define GEN9_ENABLE_DC5(dev) 0
> > -#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
> > -
> > #define for_each_power_well(i, power_well, domain_mask,
> > power_domains) \
> > for (i = 0;
> > \
> > i < (power_domains)->power_well_count &&
> > \
> > @@ -309,9 +306,15 @@ static void hsw_set_power_well(struct
> > drm_i915_private *dev_priv,
> > #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> > BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> > BIT(POWER_DOMAIN_INIT))
> > +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > + BIT(POWER_DOMAIN_MODESET) | \
> > + BIT(POWER_DOMAIN_AUX_A) | \
> > + BIT(POWER_DOMAIN_INIT))
> > #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> > (POWER_DOMAIN_MASK & ~( \
> > - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> > + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > + SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
> > BIT(POWER_DOMAIN_INIT))
> >
> > #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> > @@ -339,6 +342,11 @@ static void hsw_set_power_well(struct
> > drm_i915_private *dev_priv,
> > BIT(POWER_DOMAIN_AUX_A) | \
> > BIT(POWER_DOMAIN_PLLS) | \
> > BIT(POWER_DOMAIN_INIT))
> > +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > + BIT(POWER_DOMAIN_MODESET) | \
> > + BIT(POWER_DOMAIN_AUX_A) | \
> > + BIT(POWER_DOMAIN_INIT))
> > #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> > (POWER_DOMAIN_MASK &
> > ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
> > BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
> > @@ -486,15 +494,6 @@ static void gen9_enable_dc5(struct
> > drm_i915_private *dev_priv)
> > gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> > }
> >
> > -static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
> > -{
> > - assert_can_disable_dc5(dev_priv);
> > -
> > - DRM_DEBUG_KMS("Disabling DC5\n");
> > -
> > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > -}
> > -
> > static void assert_can_enable_dc6(struct drm_i915_private
> > *dev_priv)
> > {
> > struct drm_device *dev = dev_priv->dev;
> > @@ -522,6 +521,14 @@ static void assert_can_disable_dc6(struct
> > drm_i915_private *dev_priv)
> > "DC6 already programmed to be disabled.\n");
> > }
> >
> > +static void gen9_disable_dc5_dc6(struct drm_i915_private
> > *dev_priv)
> > +{
> > + assert_can_disable_dc5(dev_priv);
> > + assert_can_disable_dc6(dev_priv);
> > +
> > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > +}
> > +
> > void skl_enable_dc6(struct drm_i915_private *dev_priv)
> > {
> > assert_can_enable_dc6(dev_priv);
> > @@ -589,17 +596,13 @@ static void skl_set_power_well(struct
> > drm_i915_private *dev_priv,
> > "Invalid for power well status to
> > be enabled, unless done by the BIOS, \
> > when request is to disable!\n");
> > if (power_well->data == SKL_DISP_PW_2) {
> > - if (GEN9_ENABLE_DC5(dev))
> > - gen9_disable_dc5(dev_priv)
> > ;
> > - if (SKL_ENABLE_DC6(dev)) {
> > - /*
> > - * DDI buffer programming
> > unnecessary during driver-load/resume
> > - * as it's already done
> > during modeset initialization then.
> > - * It's also invalid here
> > as encoder list is still uninitialized.
> > - */
> > - if (!dev_priv-
> > >power_domains.initializing)
> > - intel_prepare_ddi(
> > dev);
> > - }
> > + /*
> > + * DDI buffer programming
> > unnecessary during driver-load/resume
> > + * as it's already done during
> > modeset initialization then.
> > + * It's also invalid here as
> > encoder list is still uninitialized.
> > + */
> > + if (!dev_priv-
> > >power_domains.initializing)
> > + intel_prepare_ddi(dev);
> > }
> > I915_WRITE(HSW_PWR_WELL_DRIVER, tmp |
> > req_mask);
> > }
> > @@ -617,10 +620,6 @@ static void skl_set_power_well(struct
> > drm_i915_private *dev_priv,
> > I915_WRITE(HSW_PWR_WELL_DRIVER, tmp
> > & ~req_mask);
> > POSTING_READ(HSW_PWR_WELL_DRIVER);
> > DRM_DEBUG_KMS("Disabling %s\n",
> > power_well->name);
> > -
> > - if (GEN9_ENABLE_DC5(dev) &&
> > - power_well->data == SKL_DISP_PW_2)
> > - gen9_enable_dc5(dev_priv);
> > }
> > }
> >
> > @@ -695,6 +694,40 @@ static void skl_power_well_disable(struct
> > drm_i915_private *dev_priv,
> > skl_set_power_well(dev_priv, power_well, false);
> > }
> >
> > +static bool gen9_dc_off_power_well_enabled(struct drm_i915_private
> > *dev_priv,
> > + struct i915_power_well
> > *power_well)
> > +{
> > + return (I915_READ(DC_STATE_EN) &
> > DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> > +}
> > +
> > +static void gen9_dc_off_power_well_enable(struct drm_i915_private
> > *dev_priv,
> > + struct i915_power_well
> > *power_well)
> > +{
> > + gen9_disable_dc5_dc6(dev_priv);
> > +}
> > +
> > +static void gen9_dc_off_power_well_disable(struct drm_i915_private
> > *dev_priv,
> > + struct i915_power_well
> > *power_well)
> > +{
> > + if (IS_SKYLAKE(dev_priv))
> > + skl_enable_dc6(dev_priv);
> > + else
> > + gen9_enable_dc5(dev_priv);
> > +}
> > +
> > +static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private
> > *dev_priv,
> > + struct i915_power_well
> > *power_well)
> > +{
> > + if (power_well->count > 0) {
> > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > + } else {
> > + if (IS_SKYLAKE(dev_priv))
> > + gen9_set_dc_state(dev_priv,
> > DC_STATE_EN_UPTO_DC6);
> > + else
> > + gen9_set_dc_state(dev_priv,
> > DC_STATE_EN_UPTO_DC5);
> > + }
> > +}
> > +
> > static void i9xx_always_on_power_well_noop(struct drm_i915_private
> > *dev_priv,
> > struct i915_power_well
> > *power_well)
> > {
> > @@ -1517,6 +1550,13 @@ static const struct i915_power_well_ops
> > skl_power_well_ops = {
> > .is_enabled = skl_power_well_enabled,
> > };
> >
> > +static const struct i915_power_well_ops gen9_dc_off_power_well_ops
> > = {
> > + .sync_hw = gen9_dc_off_power_well_sync_hw,
> > + .enable = gen9_dc_off_power_well_enable,
> > + .disable = gen9_dc_off_power_well_disable,
> > + .is_enabled = gen9_dc_off_power_well_enabled,
> > +};
> > +
> > static struct i915_power_well hsw_power_wells[] = {
> > {
> > .name = "always-on",
> > @@ -1691,6 +1731,12 @@ static struct i915_power_well
> > skl_power_wells[] = {
> > .data = SKL_DISP_PW_MISC_IO,
> > },
> > {
> > + .name = "DC off",
> > + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .ops = &gen9_dc_off_power_well_ops,
> > + .data = SKL_DISP_PW_DC_OFF,
> > + },
> > + {
> > .name = "power well 2",
> > .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> > .ops = &skl_power_well_ops,
> > @@ -1765,11 +1811,17 @@ static struct i915_power_well
> > bxt_power_wells[] = {
> > .data = SKL_DISP_PW_1,
> > },
> > {
> > + .name = "DC off",
> > + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .ops = &gen9_dc_off_power_well_ops,
> > + .data = SKL_DISP_PW_DC_OFF,
> > + },
> > + {
> > .name = "power well 2",
> > .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> > .ops = &skl_power_well_ops,
> > .data = SKL_DISP_PW_2,
> > - }
> > + },
> > };
> >
> > #define set_power_wells(power_domains, __power_wells) ({
> > \
> > --
> > 2.5.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v4 10/12] drm/i915/gen9: Turn DC handling into a power well
2015-11-23 23:09 ` Imre Deak
@ 2015-11-24 12:24 ` Daniel Vetter
0 siblings, 0 replies; 47+ messages in thread
From: Daniel Vetter @ 2015-11-24 12:24 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Nov 24, 2015 at 01:09:03AM +0200, Imre Deak wrote:
> On Mon, 2015-11-23 at 14:58 -0800, Matt Roper wrote:
> > On Mon, Nov 16, 2015 at 04:20:01PM +0100, Patrik Jakobsson wrote:
> > > Handle DC off as a power well where enabling the power well will
> > > prevent
> > > the DMC to enter selected DC states (required around modesets and
> > > Aux
> > > A). Disabling the power well will allow DC states again. For now
> > > the
> > > highest DC state is DC6 for Skylake and DC5 for Broxton but will be
> > > configurable for Skylake in a later patch.
> > >
> > > v2: Check both DC5 and DC6 bits in power well enabled function
> > > (Ville)
> > > v3:
> > > - Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
> > > - Add PW2 dependency to DC_OFF (Imre)
> > > v4: Put DC_OFF before PW2 in BXT power well array
> > >
> > > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > > Reviewed-by: Imre Deak <imre.deak@intel.com>
> >
> > I've been seeing a BXT regression on recent di-nightly where DPMS off
> > causes the entire platform to power down[1] instead of just the
> > display;
> > my bisect lands on this commit as the culprit. Any idea what the
> > cause
> > could be? I can reproduce by either letting the system sit idle long
> > enough at an fb console, or by doing an "xset dpms force off" in X.
> > Unfortunately I don't have a functioning serial console on this
> > platform, so I can't get any messages that may show up around the
> > DPMS
> > operation. I've attached my boot-time dmesg output in case that
> > helps.
> >
> > Subsequent commits seem to depend on the changes here, so I haven't
> > reverted this commit directly on di-nightly, but I confirmed that if
> > I
> > checkout this commit directly I see DPMS problems, whereas its HEAD~1
> > works as expected.
>
> The power well support on BXT is not stable atm, we need to apply at
> least a similar set of fixes as we did for SKL. So for now I would
> suggest disabling it, by booting with i915.disable_power_well=0 until
> things are fixed. This should've been made the default option earlier,
> I forgot about this. I will follow up with the patch to that extent.
I guess we should pull in that patch asap. Other problem is that current
igt tests aren't too good at obeying the dsi encoder/pipe restrictions, so
atm pm_rpm just skips. That needs to be fixed too.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2015-11-24 12:25 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-11-09 15:48 [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 01/12] drm/i915: Don't trust CSR program memory contents Patrik Jakobsson
2015-11-11 19:05 ` Imre Deak
2015-11-09 15:48 ` [PATCH 02/12] drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6 Patrik Jakobsson
2015-11-11 19:08 ` Imre Deak
2015-11-09 15:48 ` [PATCH 03/12] drm/i915: Clean up AUX power domain handling Patrik Jakobsson
2015-11-11 18:22 ` Imre Deak
2015-11-11 18:37 ` Ville Syrjälä
2015-11-12 9:02 ` Patrik Jakobsson
2015-11-12 10:15 ` Ville Syrjälä
2015-11-16 14:01 ` [PATCH v2 " Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 04/12] drm/i915: Introduce a gmbus power domain Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 05/12] drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 06/12] drm/i915: Remove distinction between DDI 2 vs 4 lanes Patrik Jakobsson
2015-11-11 19:10 ` Imre Deak
2015-11-09 15:48 ` [PATCH 07/12] drm/i915: Add a modeset power domain Patrik Jakobsson
2015-11-11 19:11 ` Imre Deak
2015-11-09 15:48 ` [PATCH 08/12] drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5() Patrik Jakobsson
2015-11-09 15:48 ` [PATCH 09/12] drm/i915: Explain usage of power well IDs vs bit groups Patrik Jakobsson
2015-11-11 19:13 ` Imre Deak
2015-11-12 13:15 ` Patrik Jakobsson
2015-11-16 14:01 ` [PATCH v2 " Patrik Jakobsson
2015-11-09 15:48 ` [PATCH v2 10/12] drm/i915/gen9: Turn DC handling into a power well Patrik Jakobsson
2015-11-11 18:57 ` Imre Deak
2015-11-12 12:24 ` Patrik Jakobsson
2015-11-12 13:30 ` Imre Deak
2015-11-13 17:53 ` Imre Deak
2015-11-11 19:23 ` Imre Deak
2015-11-12 12:55 ` Patrik Jakobsson
2015-11-16 14:01 ` [PATCH v3 " Patrik Jakobsson
2015-11-16 14:41 ` Patrik Jakobsson
2015-11-16 15:20 ` [PATCH v4 " Patrik Jakobsson
2015-11-17 19:21 ` Imre Deak
2015-11-23 22:58 ` Matt Roper
2015-11-23 23:09 ` Imre Deak
2015-11-24 12:24 ` Daniel Vetter
2015-11-16 19:28 ` [PATCH v3 " Imre Deak
2015-11-16 19:46 ` Patrik Jakobsson
2015-11-09 15:48 ` [PATCH v2 11/12] drm/i915/gen9: Add boot parameter for disabling DC6 Patrik Jakobsson
2015-11-11 19:04 ` Imre Deak
2015-11-12 12:51 ` Patrik Jakobsson
2015-11-12 13:52 ` Imre Deak
2015-11-16 14:01 ` [PATCH v3 " Patrik Jakobsson
2015-11-16 19:25 ` Imre Deak
2015-11-09 15:48 ` [PATCH 12/12] drm/i915/skl: Remove unused suspend and resume callbacks Patrik Jakobsson
2015-11-17 18:28 ` Imre Deak
2015-11-17 19:54 ` [PATCH v2 00/12] Skylake DMC/DC-state fixes and redesign Imre Deak
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