From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37608) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZyKfH-0004yI-Ax for qemu-devel@nongnu.org; Mon, 16 Nov 2015 09:21:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZyKfG-00082d-G5 for qemu-devel@nongnu.org; Mon, 16 Nov 2015 09:21:51 -0500 From: Peter Maydell Date: Mon, 16 Nov 2015 14:05:18 +0000 Message-Id: <1447682723-3977-15-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1447682723-3977-1-git-send-email-peter.maydell@linaro.org> References: <1447682723-3977-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 14/19] target-arm: Implement asidx_from_attrs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, qemu-arm@nongnu.org, Paolo Bonzini , "Edgar E. Iglesias" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Andreas=20F=C3=A4rber?= Implement the asidx_from_attrs CPU method to return the Secure or NonSecure address space as appropriate. (The function is inline so we can use it directly in target-arm code to be added in later patches.) Signed-off-by: Peter Maydell --- target-arm/cpu.c | 1 + target-arm/cpu.h | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 690d984..32d0b5c 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -1450,6 +1450,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) #else cc->do_interrupt = arm_cpu_do_interrupt; cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; + cc->asidx_from_attrs = arm_asidx_from_attrs; cc->vmsd = &vmstate_arm_cpu; cc->virtio_is_big_endian = arm_cpu_is_big_endian; #endif diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 9108b5b..ee873b7 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1997,4 +1997,12 @@ enum { QEMU_PSCI_CONDUIT_HVC = 2, }; +#ifndef CONFIG_USER_ONLY +/* Return the address space index to use for a memory access */ +static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) +{ + return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; +} +#endif + #endif -- 1.9.1