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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: patches@linaro.org, qemu-arm@nongnu.org,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Andreas Färber" <afaerber@suse.de>
Subject: [Qemu-devel] [PATCH v2 19/19] HACK: rearrange the virt memory map to suit OP-TEE
Date: Mon, 16 Nov 2015 14:05:23 +0000	[thread overview]
Message-ID: <1447682723-3977-20-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1447682723-3977-1-git-send-email-peter.maydell@linaro.org>

The current OP-TEE codebase expects the secure UART to
be at 0x09010000 and irq 2 (it is based on an old
non-upstream patch to add a second uart, and upstream
used that memory map area for something else). When
the TZ support is upstream in QEMU we can move OP-TEE
on to a proper upstream QEMU and update it to use the
new UART location, but for now this hack patch allows
running a more-or-less unmodified OP-TEE.

Put the secure UART at the address and irq where OP-TEE
expects it, moving some other devices down to make space.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 623e835..ced42be 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -118,9 +118,9 @@ static const MemMapEntry a15memmap[] = {
     /* This redistributor space allows up to 2*64kB*123 CPUs */
     [VIRT_GIC_REDIST] =         { 0x080A0000, 0x00F60000 },
     [VIRT_UART] =               { 0x09000000, 0x00001000 },
-    [VIRT_RTC] =                { 0x09010000, 0x00001000 },
-    [VIRT_FW_CFG] =             { 0x09020000, 0x00000018 },
-    [VIRT_SECURE_UART] =        { 0x09030000, 0x00001000 },
+    [VIRT_RTC] =                { 0x09020000, 0x00001000 },
+    [VIRT_FW_CFG] =             { 0x09030000, 0x00000018 },
+    [VIRT_SECURE_UART] =        { 0x09010000, 0x00001000 },
     [VIRT_MMIO] =               { 0x0a000000, 0x00000200 },
     /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
     [VIRT_PLATFORM_BUS] =       { 0x0c000000, 0x02000000 },
@@ -134,9 +134,9 @@ static const MemMapEntry a15memmap[] = {
 
 static const int a15irqmap[] = {
     [VIRT_UART] = 1,
-    [VIRT_RTC] = 2,
-    [VIRT_PCIE] = 3, /* ... to 6 */
-    [VIRT_SECURE_UART] = 7,
+    [VIRT_RTC] = 3,
+    [VIRT_PCIE] = 4, /* ... to 7 */
+    [VIRT_SECURE_UART] = 2,
     [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
     [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
     [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
-- 
1.9.1

  parent reply	other threads:[~2015-11-16 14:21 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-16 14:05 [Qemu-devel] [PATCH v2 00/19] Add support for multiple address spaces per CPU and use it for ARM TrustZone Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 01/19] exec.c: Don't set cpu->as until cpu_address_space_init Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 02/19] exec.c: Allow target CPUs to define multiple AddressSpaces Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 03/19] exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 04/19] include/qom/cpu.h: Add new get_phys_page_attrs_debug method Peter Maydell
2015-11-16 14:07   ` Andreas Färber
2015-11-16 14:22     ` Andreas Färber
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 05/19] include/qom/cpu.h: Add new asidx_from_attrs method Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 06/19] cputlb.c: Use correct address space when looking up MemoryRegionSection Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 07/19] exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 08/19] exec.c: Add cpu_get_address_space() Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 09/19] exec.c: Use cpu_get_phys_page_attrs_debug Peter Maydell
2016-01-11 13:47   ` Paolo Bonzini
2016-01-11 14:18     ` Peter Maydell
2016-01-11 14:59       ` Paolo Bonzini
2016-01-11 15:04         ` Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 10/19] exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 11/19] memory: Add address_space_init_shareable() Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 12/19] qom/cpu: Add MemoryRegion property Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 13/19] target-arm: Add QOM property for Secure memory region Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 14/19] target-arm: Implement asidx_from_attrs Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 15/19] target-arm: Implement cpu_get_phys_page_attrs_debug Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 16/19] target-arm: Support multiple address spaces in page table walks Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 17/19] hw/arm/virt: Wire up memory region to CPUs explicitly Peter Maydell
2015-11-16 14:05 ` [Qemu-devel] [PATCH v2 18/19] [RFC] hw/arm/virt: add secure memory region and UART Peter Maydell
2015-12-08 16:55   ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2015-11-16 14:05 ` Peter Maydell [this message]
2015-12-15 16:26 ` [Qemu-devel] [PATCH v2 00/19] Add support for multiple address spaces per CPU and use it for ARM TrustZone Peter Maydell
2016-01-11 13:04   ` Peter Maydell
2016-01-12 13:56     ` Edgar E. Iglesias

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