From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37784) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZyKfS-000515-PU for qemu-devel@nongnu.org; Mon, 16 Nov 2015 09:22:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZyKfR-00085v-S6 for qemu-devel@nongnu.org; Mon, 16 Nov 2015 09:22:02 -0500 From: Peter Maydell Date: Mon, 16 Nov 2015 14:05:09 +0000 Message-Id: <1447682723-3977-6-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1447682723-3977-1-git-send-email-peter.maydell@linaro.org> References: <1447682723-3977-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 05/19] include/qom/cpu.h: Add new asidx_from_attrs method List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, qemu-arm@nongnu.org, Paolo Bonzini , "Edgar E. Iglesias" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Andreas=20F=C3=A4rber?= Add a new method to CPUClass which the memory system core can use to obtain the correct address space index to use for a memory access with a given set of transaction attributes, together with the wrapper function cpu_asidx_from_attrs() which implements the default behaviour ("always use asidx 0") for CPU classes which don't provide the method. Signed-off-by: Peter Maydell --- include/qom/cpu.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 58605a5..ed23246 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -102,6 +102,8 @@ struct TranslationBlock; * associated memory transaction attributes to use for the access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_page_debug. + * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for + * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @debug_excp_handler: Callback for handling debug exceptions. @@ -158,6 +160,7 @@ typedef struct CPUClass { hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); + int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); void (*debug_excp_handler)(CPUState *cpu); @@ -492,6 +495,23 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); } + +/** cpu_asidx_from_attrs: + * @cpu: CPU + * @attrs: memory transaction attributes + * + * Returns the address space index specifying the CPU AddressSpace + * to use for a memory access with the given transaction attributes. + */ +static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + if (cc->asidx_from_attrs) { + return cc->asidx_from_attrs(cpu, attrs); + } + return 0; +} #endif /** -- 1.9.1