From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754575AbbK3QYA (ORCPT ); Mon, 30 Nov 2015 11:24:00 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:22335 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752473AbbK3QX6 (ORCPT ); Mon, 30 Nov 2015 11:23:58 -0500 From: Paul Burton To: CC: Paul Burton , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Michal Simek , "Jiang Liu" , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , , Russell Joyce , , Thomas Gleixner , Arnd Bergmann , Subject: [PATCH 07/28] PCI: xilinx: always clear interrupt decode register Date: Mon, 30 Nov 2015 16:21:32 +0000 Message-ID: <1448900513-20856-8-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1448900513-20856-1-git-send-email-paul.burton@imgtec.com> References: <1448900513-20856-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.100.200.236] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If an MSI or INTx interrupt is incorrectly triggered with an empty FIFO then xilinx_pcie_intr_handler will print a warning & skip further processing. However it did not clear the interrupt in the decode register, so the same INTX or MSI interrupt would trigger again immediately even though the FIFO is still empty. Clear the interrupt in the decode register to avoid that situation. Signed-off-by: Paul Burton --- drivers/pci/host/pcie-xilinx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index c6fe273..3058a57 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -444,7 +444,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) /* Check whether interrupt valid */ if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { dev_warn(port->dev, "RP Intr FIFO1 read error\n"); - return IRQ_HANDLED; + goto out; } if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { @@ -490,6 +490,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) if (status & XILINX_PCIE_INTR_MST_ERRP) dev_warn(port->dev, "Master error poison\n"); +out: /* Clear the Interrupt Decode register */ pcie_write(port, status, XILINX_PCIE_REG_IDR); -- 2.6.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailapp01.imgtec.com ([195.59.15.196]:21940 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27008047AbbK3QYCOGyRv (ORCPT ); Mon, 30 Nov 2015 17:24:02 +0100 From: Paul Burton Subject: [PATCH 07/28] PCI: xilinx: always clear interrupt decode register Date: Mon, 30 Nov 2015 16:21:32 +0000 Message-ID: <1448900513-20856-8-git-send-email-paul.burton@imgtec.com> In-Reply-To: <1448900513-20856-1-git-send-email-paul.burton@imgtec.com> References: <1448900513-20856-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: linux-mips@linux-mips.org Cc: Paul Burton , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Michal Simek , Jiang Liu , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, Russell Joyce , linux-kernel@vger.kernel.org, Thomas Gleixner , Arnd Bergmann , linux-arm-kernel@lists.infradead.org Message-ID: <20151130162132.AxEGLr6JRMU9iykW5LTx9W6nAg92orzgHCyPSggkZZA@z> If an MSI or INTx interrupt is incorrectly triggered with an empty FIFO then xilinx_pcie_intr_handler will print a warning & skip further processing. However it did not clear the interrupt in the decode register, so the same INTX or MSI interrupt would trigger again immediately even though the FIFO is still empty. Clear the interrupt in the decode register to avoid that situation. Signed-off-by: Paul Burton --- drivers/pci/host/pcie-xilinx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index c6fe273..3058a57 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -444,7 +444,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) /* Check whether interrupt valid */ if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { dev_warn(port->dev, "RP Intr FIFO1 read error\n"); - return IRQ_HANDLED; + goto out; } if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { @@ -490,6 +490,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) if (status & XILINX_PCIE_INTR_MST_ERRP) dev_warn(port->dev, "Master error poison\n"); +out: /* Clear the Interrupt Decode register */ pcie_write(port, status, XILINX_PCIE_REG_IDR); -- 2.6.2 From mboxrd@z Thu Jan 1 00:00:00 1970 From: paul.burton@imgtec.com (Paul Burton) Date: Mon, 30 Nov 2015 16:21:32 +0000 Subject: [PATCH 07/28] PCI: xilinx: always clear interrupt decode register In-Reply-To: <1448900513-20856-1-git-send-email-paul.burton@imgtec.com> References: <1448900513-20856-1-git-send-email-paul.burton@imgtec.com> Message-ID: <1448900513-20856-8-git-send-email-paul.burton@imgtec.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org If an MSI or INTx interrupt is incorrectly triggered with an empty FIFO then xilinx_pcie_intr_handler will print a warning & skip further processing. However it did not clear the interrupt in the decode register, so the same INTX or MSI interrupt would trigger again immediately even though the FIFO is still empty. Clear the interrupt in the decode register to avoid that situation. Signed-off-by: Paul Burton --- drivers/pci/host/pcie-xilinx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index c6fe273..3058a57 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -444,7 +444,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) /* Check whether interrupt valid */ if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { dev_warn(port->dev, "RP Intr FIFO1 read error\n"); - return IRQ_HANDLED; + goto out; } if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { @@ -490,6 +490,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) if (status & XILINX_PCIE_INTR_MST_ERRP) dev_warn(port->dev, "Master error poison\n"); +out: /* Clear the Interrupt Decode register */ pcie_write(port, status, XILINX_PCIE_REG_IDR); -- 2.6.2