From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753561AbbLIEJ4 (ORCPT ); Tue, 8 Dec 2015 23:09:56 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:59296 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753070AbbLIEIb (ORCPT ); Tue, 8 Dec 2015 23:08:31 -0500 X-AuditID: cbfee68e-f793c6d00000136c-cb-5667a9314612 From: Chanwoo Choi To: myungjoo.ham@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 15/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210 Date: Wed, 09 Dec 2015 13:08:07 +0900 Message-id: <1449634091-1842-16-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1449634091-1842-1-git-send-email-cw00.choi@samsung.com> References: <1449634091-1842-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLIsWRmVeSWpSXmKPExsWyRsSkWNdwZXqYwY8nqhbXvzxntZh/5Byr Rf+bhawW516tZLR4/cLQov/xa2aLs01v2C0u75rDZvG59wijxYzz+5gs1m28xW5x+zKvxdLr F5ksbjeuYLOYMH0ti0Xr3iPsFm2rP7A6CHqsmbeG0aOluYfN43JfL5PHzll32T1WLv/C5rFp VSebx79j7B59W1YxenzeJBfAGcVlk5Kak1mWWqRvl8CVMeHiD8aChWoVyydcZWpg/CHbxcjJ ISFgIrH2yG52CFtM4sK99WwgtpDACkaJnlvhXYwcYDVf5ol3MXIBhWcxSpztesYO4XwBch4c ZgVpYBPQktj/4gZYs4iAu8TXe7vZQIqYBb4wSbRO/s4MkhAW8JM4svYSO8hUFgFViYmr00HC vAKuEmenroc6Qk7iw55HYDYnUPzK9neMEAe5SBx72sQEMlNCoJFD4uKEuWAJFgEBiW+TD7FA XCorsekAM8QcSYmDK26wTGAUXsDIsIpRNLUguaA4Kb3ISK84Mbe4NC9dLzk/dxMjMNZO/3vW t4Px5gHrQ4wCHIxKPLwXXNLDhFgTy4orcw8xmgJtmMgsJZqcD4zovJJ4Q2MzIwtTE1NjI3NL MyVx3gSpn8FCAumJJanZqakFqUXxRaU5qcWHGJk4OKUaGGMum539yfysizkh5O6JBTXn3i1S Vfi3+vDRV7keak0ztk8IdHA+ovaxbpoh8/0nWrozaqd5rU+qYitbbfzk+CFOibP6/8SEL26O Pbtks1IixypZ/fLd9971ndU0tS56f0zse2aJucuuFuNfBZsjsy/vnrnmSFOWyovEZ5ErTs3y 3ff/tte95t1KLMUZiYZazEXFiQCKaWeEsAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNIsWRmVeSWpSXmKPExsVy+t9jQV3DlelhBhOWy1lc//Kc1WL+kXOs Fv1vFrJanHu1ktHi9QtDi/7Hr5ktzja9Ybe4vGsOm8Xn3iOMFjPO72OyWLfxFrvF7cu8Fkuv X2SyuN24gs1iwvS1LBate4+wW7St/sDqIOixZt4aRo+W5h42j8t9vUweO2fdZfdYufwLm8em VZ1sHv+OsXv0bVnF6PF5k1wAZ1QDo01GamJKapFCal5yfkpmXrqtkndwvHO8qZmBoa6hpYW5 kkJeYm6qrZKLT4CuW2YO0CtKCmWJOaVAoYDE4mIlfTtME0JD3HQtYBojdH1DguB6jAzQQMIa xowJF38wFixUq1g+4SpTA+MP2S5GDg4JAROJL/PEuxg5gUwxiQv31rN1MXJxCAnMYpQ42/WM HcL5AuQ8OMwKUsUmoCWx/8UNNhBbRMBd4uu93WAdzAJfmCRaJ39nBkkIC/hJHFl7iR1kA4uA qsTE1ekgYV4BV4mzU9ezQ2yTk/iw5xGYzQkUv7L9HSOILSTgInHsaRPTBEbeBYwMqxglUguS C4qT0nON8lLL9YoTc4tL89L1kvNzNzGCI/qZ9A7Gw7vcDzEKcDAq8fBecEkPE2JNLCuuzD3E KMHBrCTCq1ULFOJNSaysSi3Kjy8qzUktPsRoCnTXRGYp0eR8YLLJK4k3NDYxM7I0Mje0MDI2 VxLn3XcpMkxIID2xJDU7NbUgtQimj4mDU6qB0U3q82eLiQlLmj7NfGjF5afHcsm3e6vS7aLd n3SWTZnCyprm1CJ+mFlDRo+7/PHVl9Y3L3Lv0Px2XZxxyUqtyzciWDr/f+h2SFlYzlsr9DPP PUj/ssX6mOiv815OCLmy7SeHedUlh+VGwquqU8P3R9ue/VXAnTkv6HJE3rYYcWEPTVNXaQFl JZbijERDLeai4kQAUiTYr/4CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has one power line for all buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - DMC/ACP clock for DMC (Dynamic Memory Controller) - ACLK200 clock for LCD0 - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD0/LCD1 - ACLK133 clock for FSYS/GPS - GDL/GDR clock for LEFTBUS/RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi --- arch/arm/boot/dts/exynos4210.dtsi | 172 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 172 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 3e5ba665d200..658c5a1fe03c 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -257,6 +257,178 @@ power-domains = <&pd_lcd1>; #iommu-cells = <0>; }; + + bus_dmc: bus_dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_acp: bus_acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + }; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; + + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1025000>; + }; + opp01 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1050000>; + }; + opp02 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1150000>; + }; + }; + + bus_acp_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1025000>; + }; + opp01 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <1050000>; + }; + opp02 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1150000>; + }; + }; + + bus_peri_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <5000000>; + opp-microvolt = <1025000>; + }; + opp01 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1050000>; + }; + }; + + bus_fsys_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <10000000>; + opp-microvolt = <1025000>; + }; + opp01 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1050000>; + }; + }; + + bus_display_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1025000>; + }; + opp01 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1050000>; + }; + opp02 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <1150000>; + }; + }; + + bus_leftbus_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1025000>; + }; + opp01 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <1050000>; + }; + opp02 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1150000>; + }; + }; }; &gic { -- 1.9.1