From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55679) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8Ohm-0005ij-AV for qemu-devel@nongnu.org; Mon, 14 Dec 2015 03:42:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a8Ohl-0001w3-1g for qemu-devel@nongnu.org; Mon, 14 Dec 2015 03:42:02 -0500 Received: from mail-wm0-x229.google.com ([2a00:1450:400c:c09::229]:38327) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8Ohk-0001vy-PK for qemu-devel@nongnu.org; Mon, 14 Dec 2015 03:42:00 -0500 Received: by wmpp66 with SMTP id p66so50475593wmp.1 for ; Mon, 14 Dec 2015 00:42:00 -0800 (PST) From: Alvise Rigo Date: Mon, 14 Dec 2015 09:41:36 +0100 Message-Id: <1450082498-27109-13-git-send-email-a.rigo@virtualopensystems.com> In-Reply-To: <1450082498-27109-1-git-send-email-a.rigo@virtualopensystems.com> References: <1450082498-27109-1-git-send-email-a.rigo@virtualopensystems.com> Subject: [Qemu-devel] [RFC v6 12/14] softmmu: Simplify helper_*_st_name, wrap RAM code List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, mttcg@listserver.greensocs.com Cc: claudio.fontana@huawei.com, pbonzini@redhat.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, alex.bennee@linaro.org, rth@twiddle.net Attempting to simplify the helper_*_st_name, wrap the code relative to a RAM access into an inline function. Suggested-by: Jani Kokkonen Suggested-by: Claudio Fontana Signed-off-by: Alvise Rigo --- softmmu_template.h | 110 +++++++++++++++++++++++++++++++++-------------------- 1 file changed, 68 insertions(+), 42 deletions(-) diff --git a/softmmu_template.h b/softmmu_template.h index 2ebf527..262c95f 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -416,13 +416,46 @@ static inline void glue(helper_le_st_name, _do_mmio_access)(CPUArchState *env, glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr); } +static inline void glue(helper_le_st_name, _do_ram_access)(CPUArchState *env, + DATA_TYPE val, + target_ulong addr, + TCGMemOpIdx oi, + unsigned mmu_idx, + int index, + uintptr_t retaddr) +{ + uintptr_t haddr; + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (DATA_SIZE > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 + >= TARGET_PAGE_SIZE)) { + glue(helper_le_st_name, _do_unl_access)(env, val, addr, oi, mmu_idx, + retaddr); + return; + } + + /* Handle aligned access or unaligned access in the same page. */ + if ((addr & (DATA_SIZE - 1)) != 0 + && (get_memop(oi) & MO_AMASK) == MO_ALIGN) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + haddr = addr + env->tlb_table[mmu_idx][index].addend; +#if DATA_SIZE == 1 + glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val); +#else + glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val); +#endif +} + void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) { unsigned mmu_idx = get_mmuidx(oi); int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; - uintptr_t haddr; /* Adjust the given return address. */ retaddr -= GETPC_ADJ; @@ -484,28 +517,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, } } - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >= TARGET_PAGE_SIZE)) { - glue(helper_le_st_name, _do_unl_access)(env, val, addr, oi, mmu_idx, - retaddr); - return; - } - - /* Handle aligned access or unaligned access in the same page. */ - if ((addr & (DATA_SIZE - 1)) != 0 - && (get_memop(oi) & MO_AMASK) == MO_ALIGN) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - haddr = addr + env->tlb_table[mmu_idx][index].addend; -#if DATA_SIZE == 1 - glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val); -#else - glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val); -#endif + glue(helper_le_st_name, _do_ram_access)(env, val, addr, oi, mmu_idx, index, + retaddr); } #if DATA_SIZE > 1 @@ -555,13 +568,42 @@ static inline void glue(helper_be_st_name, _do_mmio_access)(CPUArchState *env, glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr); } +static inline void glue(helper_be_st_name, _do_ram_access)(CPUArchState *env, + DATA_TYPE val, + target_ulong addr, + TCGMemOpIdx oi, + unsigned mmu_idx, + int index, + uintptr_t retaddr) +{ + uintptr_t haddr; + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (DATA_SIZE > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 + >= TARGET_PAGE_SIZE)) { + glue(helper_be_st_name, _do_unl_access)(env, val, addr, oi, mmu_idx, + retaddr); + return; + } + + /* Handle aligned access or unaligned access in the same page. */ + if ((addr & (DATA_SIZE - 1)) != 0 + && (get_memop(oi) & MO_AMASK) == MO_ALIGN) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + haddr = addr + env->tlb_table[mmu_idx][index].addend; + glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val); +} + void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) { unsigned mmu_idx = get_mmuidx(oi); int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; - uintptr_t haddr; /* Adjust the given return address. */ retaddr -= GETPC_ADJ; @@ -623,24 +665,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, } } - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >= TARGET_PAGE_SIZE)) { - glue(helper_be_st_name, _do_unl_access)(env, val, addr, oi, mmu_idx, - retaddr); - return; - } - - /* Handle aligned access or unaligned access in the same page. */ - if ((addr & (DATA_SIZE - 1)) != 0 - && (get_memop(oi) & MO_AMASK) == MO_ALIGN) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - haddr = addr + env->tlb_table[mmu_idx][index].addend; - glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val); + glue(helper_be_st_name, _do_ram_access)(env, val, addr, oi, mmu_idx, index, + retaddr); } #endif /* DATA_SIZE > 1 */ -- 2.6.4