From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: [PATCH] xen/arm: vgic: Clarify some comments after 5d495f4 Date: Thu, 17 Dec 2015 17:29:10 +0000 Message-ID: <1450373350-9085-1-git-send-email-julien.grall@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1a9cOF-0000cD-OZ for xen-devel@lists.xenproject.org; Thu, 17 Dec 2015 17:30:55 +0000 List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xenproject.org Cc: Julien Grall , ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Ian pointed out that the definition of "offset" and "appropriate boundary" in the comments added by "xen/arm: vgic: Optimize the way to store the target vCPU in the rank" were not cleared. Clarify them by explicitly mentionning the offset is in byte and the appropriate boundary is ITARGET/IROUTER Signed-off-by: Julien Grall --- xen/arch/arm/vgic-v2.c | 4 ++-- xen/arch/arm/vgic-v3.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index 07316e8..032b964 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -65,7 +65,7 @@ void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize, * Fetch an ITARGETSR register based on the offset from ITARGETSR0. Only * one vCPU will be listed for a given vIRQ. * - * Note the offset will be aligned to the appropriate boundary. + * Note the byte offset will be aligned to an ITARGETSR boundary. */ static uint32_t vgic_fetch_itargetsr(struct vgic_irq_rank *rank, unsigned int offset) @@ -88,7 +88,7 @@ static uint32_t vgic_fetch_itargetsr(struct vgic_irq_rank *rank, * Store an ITARGETSR register in a convenient way and migrate the vIRQ * if necessary. This function only deals with ITARGETSR8 and onwards. * - * Note the offset will be aligned to the appropriate boundary. + * Note the byte offset will be aligned to an ITARGETSR boundary. */ static void vgic_store_itargetsr(struct domain *d, struct vgic_irq_rank *rank, unsigned int offset, uint32_t itargetsr) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index f01bbd9..6ab8002 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -94,7 +94,7 @@ static struct vcpu *vgic_v3_irouter_to_vcpu(struct domain *d, uint64_t irouter) * Fetch an IROUTER register based on the offset from IROUTER0. Only one * vCPU will be listed for a given vIRQ. * - * Note the offset will be aligned to the appropriate boundary. + * Note the byte offset will be aligned to an IROUTER boundary. */ static uint64_t vgic_fetch_irouter(struct vgic_irq_rank *rank, unsigned int offset) -- 2.1.4