From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: [PULL 17/45] target-i386/kvm: Hyper-V SynIC timers MSR's support Date: Thu, 17 Dec 2015 18:46:13 +0100 Message-ID: <1450374401-31352-18-git-send-email-pbonzini@redhat.com> References: <1450374401-31352-1-git-send-email-pbonzini@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Andrey Smetanin , Richard Henderson , Eduardo Habkost , =?UTF-8?q?Andreas=20F=C3=83=C2=A4rber?= , Marcelo Tosatti , "Denis V. Lunev" , Roman Kagan , kvm@vger.kernel.org To: qemu-devel@nongnu.org Return-path: Received: from mx1.redhat.com ([209.132.183.28]:51190 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752232AbbLQRrT (ORCPT ); Thu, 17 Dec 2015 12:47:19 -0500 In-Reply-To: <1450374401-31352-1-git-send-email-pbonzini@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: =46rom: Andrey Smetanin Hyper-V SynIC timers are host timers that are configurable by guest through corresponding MSR's (HV_X64_MSR_STIMER*). Guest setup and use fired by host events(SynIC interrupt and appropriate timer expiration message) as guest clock events. The state of Hyper-V SynIC timers are stored in corresponding MSR's. This patch seria implements such MSR's support and migration. Signed-off-by: Andrey Smetanin CC: Paolo Bonzini CC: Richard Henderson CC: Eduardo Habkost CC: "Andreas F=C3=83=C2=A4rber" CC: Marcelo Tosatti CC: Denis V. Lunev CC: Roman Kagan CC: kvm@vger.kernel.org Message-Id: <1448464885-8300-3-git-send-email-asmetanin@virtuozzo.com> Signed-off-by: Paolo Bonzini --- target-i386/cpu-qom.h | 1 + target-i386/cpu.c | 1 + target-i386/cpu.h | 2 ++ target-i386/kvm.c | 50 +++++++++++++++++++++++++++++++++++++++++++= ++++++- target-i386/machine.c | 29 +++++++++++++++++++++++++++++ 5 files changed, 82 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index 7ea5b34..5f9d960 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -95,6 +95,7 @@ typedef struct X86CPU { bool hyperv_vpindex; bool hyperv_runtime; bool hyperv_synic; + bool hyperv_stimer; bool check_cpuid; bool enforce_cpuid; bool expose_kvm; diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 2fdd855..92f7cc1 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -3147,6 +3147,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false), DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false), DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false), + DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false), DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 1168ddf..595891e 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -925,6 +925,8 @@ typedef struct CPUX86State { uint64_t msr_hv_synic_evt_page; uint64_t msr_hv_synic_msg_page; uint64_t msr_hv_synic_sint[HV_SYNIC_SINT_COUNT]; + uint64_t msr_hv_stimer_config[HV_SYNIC_STIMER_COUNT]; + uint64_t msr_hv_stimer_count[HV_SYNIC_STIMER_COUNT]; =20 /* exception/interrupt handling */ int error_code; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index d1c2c81..7692b59 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -90,6 +90,7 @@ static bool has_msr_hv_reset; static bool has_msr_hv_vpindex; static bool has_msr_hv_runtime; static bool has_msr_hv_synic; +static bool has_msr_hv_stimer; static bool has_msr_mtrr; static bool has_msr_xss; =20 @@ -526,7 +527,8 @@ static bool hyperv_enabled(X86CPU *cpu) cpu->hyperv_reset || cpu->hyperv_vpindex || cpu->hyperv_runtime || - cpu->hyperv_synic); + cpu->hyperv_synic || + cpu->hyperv_stimer); } =20 static Error *invtsc_mig_blocker; @@ -630,6 +632,13 @@ int kvm_arch_init_vcpu(CPUState *cs) env->msr_hv_synic_sint[sint] =3D HV_SYNIC_SINT_MASKED; } } + if (cpu->hyperv_stimer) { + if (!has_msr_hv_stimer) { + fprintf(stderr, "Hyper-V timers aren't supported by ke= rnel\n"); + return -ENOSYS; + } + c->eax |=3D HV_X64_MSR_SYNTIMER_AVAILABLE; + } c =3D &cpuid_data.entries[cpuid_i++]; c->function =3D HYPERV_CPUID_ENLIGHTMENT_INFO; if (cpu->hyperv_relaxed_timing) { @@ -980,6 +989,10 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_hv_synic =3D true; continue; } + if (kvm_msr_list->indices[i] =3D=3D HV_X64_MSR_STIMER0= _CONFIG) { + has_msr_hv_stimer =3D true; + continue; + } } } =20 @@ -1558,6 +1571,19 @@ static int kvm_put_msrs(X86CPU *cpu, int level) env->msr_hv_synic_sint[j]); } } + if (has_msr_hv_stimer) { + int j; + + for (j =3D 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j= ++) { + kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_CONFI= G + j*2, + env->msr_hv_stimer_config[j]); + } + + for (j =3D 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j+= +) { + kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_COUNT= + j*2, + env->msr_hv_stimer_count[j]); + } + } if (has_msr_mtrr) { kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_d= eftype); kvm_msr_entry_set(&msrs[n++], @@ -1937,6 +1963,14 @@ static int kvm_get_msrs(X86CPU *cpu) msrs[n++].index =3D msr; } } + if (has_msr_hv_stimer) { + uint32_t msr; + + for (msr =3D HV_X64_MSR_STIMER0_CONFIG; msr <=3D HV_X64_MSR_ST= IMER3_COUNT; + msr++) { + msrs[n++].index =3D msr; + } + } if (has_msr_mtrr) { msrs[n++].index =3D MSR_MTRRdefType; msrs[n++].index =3D MSR_MTRRfix64K_00000; @@ -2108,6 +2142,20 @@ static int kvm_get_msrs(X86CPU *cpu) case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15: env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] =3D msrs[= i].data; break; + case HV_X64_MSR_STIMER0_CONFIG: + case HV_X64_MSR_STIMER1_CONFIG: + case HV_X64_MSR_STIMER2_CONFIG: + case HV_X64_MSR_STIMER3_CONFIG: + env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONF= IG)/2] =3D + msrs[i].data; + break; + case HV_X64_MSR_STIMER0_COUNT: + case HV_X64_MSR_STIMER1_COUNT: + case HV_X64_MSR_STIMER2_COUNT: + case HV_X64_MSR_STIMER3_COUNT: + env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT= )/2] =3D + msrs[i].data; + break; case MSR_MTRRdefType: env->mtrr_deftype =3D msrs[i].data; break; diff --git a/target-i386/machine.c b/target-i386/machine.c index d41e286..6126d96 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -746,6 +746,34 @@ static const VMStateDescription vmstate_msr_hyperv= _synic =3D { } }; =20 +static bool hyperv_stimer_enable_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + int i; + + for (i =3D 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) { + if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i= ]) { + return true; + } + } + return false; +} + +static const VMStateDescription vmstate_msr_hyperv_stimer =3D { + .name =3D "cpu/msr_hyperv_stimer", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D hyperv_stimer_enable_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config, + X86CPU, HV_SYNIC_STIMER_COUNT), + VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count, + X86CPU, HV_SYNIC_STIMER_COUNT), + VMSTATE_END_OF_LIST() + } +}; + static bool avx512_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -930,6 +958,7 @@ VMStateDescription vmstate_x86_cpu =3D { &vmstate_msr_hyperv_crash, &vmstate_msr_hyperv_runtime, &vmstate_msr_hyperv_synic, + &vmstate_msr_hyperv_stimer, &vmstate_avx512, &vmstate_xss, NULL --=20 2.5.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9ce9-0001Ae-OJ for qemu-devel@nongnu.org; Thu, 17 Dec 2015 12:47:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a9ce8-0006sr-DR for qemu-devel@nongnu.org; Thu, 17 Dec 2015 12:47:21 -0500 Received: from mx1.redhat.com ([209.132.183.28]:43952) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9ce8-0006sn-5f for qemu-devel@nongnu.org; Thu, 17 Dec 2015 12:47:20 -0500 From: Paolo Bonzini Date: Thu, 17 Dec 2015 18:46:13 +0100 Message-Id: <1450374401-31352-18-git-send-email-pbonzini@redhat.com> In-Reply-To: <1450374401-31352-1-git-send-email-pbonzini@redhat.com> References: <1450374401-31352-1-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 17/45] target-i386/kvm: Hyper-V SynIC timers MSR's support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Eduardo Habkost , kvm@vger.kernel.org, Marcelo Tosatti , Roman Kagan , Andrey Smetanin , "Denis V. Lunev" , =?UTF-8?q?Andreas=20F=C3=83=C2=A4rber?= , Richard Henderson From: Andrey Smetanin Hyper-V SynIC timers are host timers that are configurable by guest through corresponding MSR's (HV_X64_MSR_STIMER*). Guest setup and use fired by host events(SynIC interrupt and appropriate timer expiration message) as guest clock events. The state of Hyper-V SynIC timers are stored in corresponding MSR's. This patch seria implements such MSR's support and migration. Signed-off-by: Andrey Smetanin CC: Paolo Bonzini CC: Richard Henderson CC: Eduardo Habkost CC: "Andreas F=C3=83=C2=A4rber" CC: Marcelo Tosatti CC: Denis V. Lunev CC: Roman Kagan CC: kvm@vger.kernel.org Message-Id: <1448464885-8300-3-git-send-email-asmetanin@virtuozzo.com> Signed-off-by: Paolo Bonzini --- target-i386/cpu-qom.h | 1 + target-i386/cpu.c | 1 + target-i386/cpu.h | 2 ++ target-i386/kvm.c | 50 +++++++++++++++++++++++++++++++++++++++++++++= ++++- target-i386/machine.c | 29 +++++++++++++++++++++++++++++ 5 files changed, 82 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index 7ea5b34..5f9d960 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -95,6 +95,7 @@ typedef struct X86CPU { bool hyperv_vpindex; bool hyperv_runtime; bool hyperv_synic; + bool hyperv_stimer; bool check_cpuid; bool enforce_cpuid; bool expose_kvm; diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 2fdd855..92f7cc1 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -3147,6 +3147,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false), DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false), DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false), + DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false), DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 1168ddf..595891e 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -925,6 +925,8 @@ typedef struct CPUX86State { uint64_t msr_hv_synic_evt_page; uint64_t msr_hv_synic_msg_page; uint64_t msr_hv_synic_sint[HV_SYNIC_SINT_COUNT]; + uint64_t msr_hv_stimer_config[HV_SYNIC_STIMER_COUNT]; + uint64_t msr_hv_stimer_count[HV_SYNIC_STIMER_COUNT]; =20 /* exception/interrupt handling */ int error_code; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index d1c2c81..7692b59 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -90,6 +90,7 @@ static bool has_msr_hv_reset; static bool has_msr_hv_vpindex; static bool has_msr_hv_runtime; static bool has_msr_hv_synic; +static bool has_msr_hv_stimer; static bool has_msr_mtrr; static bool has_msr_xss; =20 @@ -526,7 +527,8 @@ static bool hyperv_enabled(X86CPU *cpu) cpu->hyperv_reset || cpu->hyperv_vpindex || cpu->hyperv_runtime || - cpu->hyperv_synic); + cpu->hyperv_synic || + cpu->hyperv_stimer); } =20 static Error *invtsc_mig_blocker; @@ -630,6 +632,13 @@ int kvm_arch_init_vcpu(CPUState *cs) env->msr_hv_synic_sint[sint] =3D HV_SYNIC_SINT_MASKED; } } + if (cpu->hyperv_stimer) { + if (!has_msr_hv_stimer) { + fprintf(stderr, "Hyper-V timers aren't supported by kern= el\n"); + return -ENOSYS; + } + c->eax |=3D HV_X64_MSR_SYNTIMER_AVAILABLE; + } c =3D &cpuid_data.entries[cpuid_i++]; c->function =3D HYPERV_CPUID_ENLIGHTMENT_INFO; if (cpu->hyperv_relaxed_timing) { @@ -980,6 +989,10 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_hv_synic =3D true; continue; } + if (kvm_msr_list->indices[i] =3D=3D HV_X64_MSR_STIMER0_C= ONFIG) { + has_msr_hv_stimer =3D true; + continue; + } } } =20 @@ -1558,6 +1571,19 @@ static int kvm_put_msrs(X86CPU *cpu, int level) env->msr_hv_synic_sint[j]); } } + if (has_msr_hv_stimer) { + int j; + + for (j =3D 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++= ) { + kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_CONFIG = + j*2, + env->msr_hv_stimer_config[j]); + } + + for (j =3D 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++)= { + kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_COUNT += j*2, + env->msr_hv_stimer_count[j]); + } + } if (has_msr_mtrr) { kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_def= type); kvm_msr_entry_set(&msrs[n++], @@ -1937,6 +1963,14 @@ static int kvm_get_msrs(X86CPU *cpu) msrs[n++].index =3D msr; } } + if (has_msr_hv_stimer) { + uint32_t msr; + + for (msr =3D HV_X64_MSR_STIMER0_CONFIG; msr <=3D HV_X64_MSR_STIM= ER3_COUNT; + msr++) { + msrs[n++].index =3D msr; + } + } if (has_msr_mtrr) { msrs[n++].index =3D MSR_MTRRdefType; msrs[n++].index =3D MSR_MTRRfix64K_00000; @@ -2108,6 +2142,20 @@ static int kvm_get_msrs(X86CPU *cpu) case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15: env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] =3D msrs[i]= .data; break; + case HV_X64_MSR_STIMER0_CONFIG: + case HV_X64_MSR_STIMER1_CONFIG: + case HV_X64_MSR_STIMER2_CONFIG: + case HV_X64_MSR_STIMER3_CONFIG: + env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG= )/2] =3D + msrs[i].data; + break; + case HV_X64_MSR_STIMER0_COUNT: + case HV_X64_MSR_STIMER1_COUNT: + case HV_X64_MSR_STIMER2_COUNT: + case HV_X64_MSR_STIMER3_COUNT: + env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/= 2] =3D + msrs[i].data; + break; case MSR_MTRRdefType: env->mtrr_deftype =3D msrs[i].data; break; diff --git a/target-i386/machine.c b/target-i386/machine.c index d41e286..6126d96 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -746,6 +746,34 @@ static const VMStateDescription vmstate_msr_hyperv_s= ynic =3D { } }; =20 +static bool hyperv_stimer_enable_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + int i; + + for (i =3D 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) { + if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i])= { + return true; + } + } + return false; +} + +static const VMStateDescription vmstate_msr_hyperv_stimer =3D { + .name =3D "cpu/msr_hyperv_stimer", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D hyperv_stimer_enable_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config, + X86CPU, HV_SYNIC_STIMER_COUNT), + VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count, + X86CPU, HV_SYNIC_STIMER_COUNT), + VMSTATE_END_OF_LIST() + } +}; + static bool avx512_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -930,6 +958,7 @@ VMStateDescription vmstate_x86_cpu =3D { &vmstate_msr_hyperv_crash, &vmstate_msr_hyperv_runtime, &vmstate_msr_hyperv_synic, + &vmstate_msr_hyperv_stimer, &vmstate_avx512, &vmstate_xss, NULL --=20 2.5.0