From mboxrd@z Thu Jan 1 00:00:00 1970 From: James Hogan Subject: [PATCH v4 2/7] mips/kvm: Implement PRid CP0 register Date: Fri, 18 Dec 2015 10:45:59 +0000 Message-ID: <1450435564-30720-3-git-send-email-james.hogan@imgtec.com> References: <1450435564-30720-1-git-send-email-james.hogan@imgtec.com> Mime-Version: 1.0 Content-Type: text/plain Cc: , Leon Alrae , Aurelien Jarno , James Hogan To: , Paolo Bonzini Return-path: Received: from mailapp01.imgtec.com ([195.59.15.196]:51699 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751194AbbLRKqV (ORCPT ); Fri, 18 Dec 2015 05:46:21 -0500 In-Reply-To: <1450435564-30720-1-git-send-email-james.hogan@imgtec.com> Sender: kvm-owner@vger.kernel.org List-ID: Implement saving and restoring to KVM state of the Processor ID (PRid) CP0 register. This allows QEMU to control the PRid exposed to the guest instead of using the default set by KVM. Signed-off-by: James Hogan Reviewed-by: Leon Alrae Cc: Paolo Bonzini Cc: Aurelien Jarno --- target-mips/kvm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target-mips/kvm.c b/target-mips/kvm.c index 5cd65ad201ca..41abc8709d96 100644 --- a/target-mips/kvm.c +++ b/target-mips/kvm.c @@ -228,6 +228,7 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) +#define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, @@ -520,6 +521,11 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err); ret = err; } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, &env->CP0_ErrorEPC); if (err < 0) { @@ -606,6 +612,11 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, &env->CP0_ErrorEPC); if (err < 0) { -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52419) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9sYL-00072p-K2 for qemu-devel@nongnu.org; Fri, 18 Dec 2015 05:46:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a9sYI-0008NF-Kv for qemu-devel@nongnu.org; Fri, 18 Dec 2015 05:46:25 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:11036) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9sYI-0008Lf-G8 for qemu-devel@nongnu.org; Fri, 18 Dec 2015 05:46:22 -0500 From: James Hogan Date: Fri, 18 Dec 2015 10:45:59 +0000 Message-ID: <1450435564-30720-3-git-send-email-james.hogan@imgtec.com> In-Reply-To: <1450435564-30720-1-git-send-email-james.hogan@imgtec.com> References: <1450435564-30720-1-git-send-email-james.hogan@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v4 2/7] mips/kvm: Implement PRid CP0 register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Paolo Bonzini Cc: James Hogan , Leon Alrae , Aurelien Jarno , kvm@vger.kernel.org Implement saving and restoring to KVM state of the Processor ID (PRid) CP0 register. This allows QEMU to control the PRid exposed to the guest instead of using the default set by KVM. Signed-off-by: James Hogan Reviewed-by: Leon Alrae Cc: Paolo Bonzini Cc: Aurelien Jarno --- target-mips/kvm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target-mips/kvm.c b/target-mips/kvm.c index 5cd65ad201ca..41abc8709d96 100644 --- a/target-mips/kvm.c +++ b/target-mips/kvm.c @@ -228,6 +228,7 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) +#define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, @@ -520,6 +521,11 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err); ret = err; } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, &env->CP0_ErrorEPC); if (err < 0) { @@ -606,6 +612,11 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, &env->CP0_ErrorEPC); if (err < 0) { -- 2.4.10